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Giáo trình ngôn ngữ mô tả phần cứng PDF
Giáo trình ngôn ngữ mô tả phần cứng PDF
Gio trnh
2012
Li ni u
Ngy nay, khi mch thit k vi hng triu cng logic c tch hp
trong mt con Chip th vic thit k mch v i dy kt ni bng tay tr nn
bt kh thi, chnh t l do mt khi nim ngn ng c mc tru tng
cao dng m t thit k phn cng c ra i, chnh l Verilog.
Cng vi s ra i ca ngn ng m t phn cng Verilog l hng lot cc
cng c EDA (Electronic Design Automation) v CAD (Computer Aided
Design) gip cho nhng k s thit k phn cng to nn nhng con
Chip c tch hp rt cao, tc siu vit v chc nng a dng.
Gio trnh Ngn ng m t phn cng Verilog nhm gip sinh vin
trang b kin thc v thit k vi mch. Gio trnh tp trung vo mng thit
k cc mch s vi mch t hp v mch tun t. Gio trnh cng gii thiu
v cc bc cn thc hin trong qu trnh thit k vi mch t vic m t
thit k, kim tra, phn tch cho n tng hp phn cng ca thit k.
Gio trnh Ngn ng m t phn cng Verilog dng cho sinh vin
chuyn ngnh K thut my tnh v sinh vin cc khi in t. tip nhn
kin thc d dng, sinh vin cn trang b trc kin thc v thit k s v
h thng s.
Gio trnh ny c bin dch v tng hp t kinh nghim nghin cu
ging dy ca tc gi v ba ngun ti liu chnh: IEEE Standard for Verilog
Hardware Description Language, 2006; Verilog Digital System Design,
Second Edition, McGraw-Hill; The Complete Verilog Book, Vivek
Sagdeo, Sun Micro System, Inc.
Nhm cung cp mt lung kin thc mch lc, gio trnh c chia ra
lm 9 chng:
Chng 1: Dn nhp thit k h thng s vi Verilog. Chng ny s
gii thiu lch s pht trin ca ngn ng m t phn cng Verilog, bn
cnh mt qui trnh thit k vi mch s dng ngn ng m t phn cng
Verilog cng c trnh by c th y.
Chng 2: Trnh by cc t kha c s dng trong mi trng m t
thit k bi Verilog.
Chng 3: Trnh by cc loi d liu c s dng trong thit k mch
bi Verilog, gm hai loi d liu chnh l loi d liu net v loi d liu
bin.
Chng 4: Trnh by cc ton t cng nh cc dng biu thc c h
tr bi Verilog.
Chng 5: Gii thiu cu trc ca mt thit k, phng thc s dng
thit k con.
Chng 6: Trnh by phng php thit k s dng m hnh cu trc,
trong phng thc ny, module thit k c xy dng bng cch gi cc
module thit k nh hn v kt ni chng li.
Chng 7: Trnh by phng thc thit k s dng m hnh RTL bi
php gn ni tip v m hnh hnh vi s dng ngn ng c tnh tru tng
cao tng t nh ngn ng lp trnh. Phn thit k my trng thi s dng
m hnh hnh vi cng c nu ra trong chng ny.
Chng 8: Trnh by phng php thit k v s dng tc v v hm.
Chng 9: Gii thiu cc phng php kim tra chc nng ca thit k.
Do thi gian cng nh khi lng trnh by gio trnh khng cho php
tc gi i su hn v mi kha cnh ca thit k vi mch nh phn tch nh
thi, tng hp phn cng. c c nhng kin thc ny c gi c th
tham kho trong cc ti liu tham kho m gio trnh ny cung cp.
Mc d nhm tc gi c gng bin son k lng tuy nhin cng
kh trnh khi nhng thiu st. Nhm tc gi mong nhn c nhng ng
gp mang tnh xy dng t qu c gi nhm chnh sa gio trnh hon
thin hn.
Chng 1. Dn nhp thit k h thng s vi Verilog
Chng 1. Dn nhp thit k h thng s vi Verilog
1
Chng 1. Dn nhp thit k h thng s vi Verilog
Verilog khin n tr thnh mt ngn ng c nhiu k s thit k phn
cng la chn.
2
Chng 1. Dn nhp thit k h thng s vi Verilog
phn cng thc s c to ra, mt qu trnh m phng khc (hu tng hp
(postsynthesis)) phi c thc hin. Vic m phng ny, ta c th s dng
testbench tng t testbench s dng trong m phng tin tng hp
(presynthesis). Bng phng php ny, m hnh thit k mc hnh vi
v m hnh phn cng ca thit k c kim tra vi cng d liu ng vo.
S khc nhau gia m phng tin tng hp v hu tng hp l mc
chi tit c th t c t mi loi m phng.
3
Chng 1. Dn nhp thit k h thng s vi Verilog
Nhng phn tip theo s m t t m v mi khi trong Hnh 1.1
5
Chng 1. Dn nhp thit k h thng s vi Verilog
1.1.3 nh gi thit k
1.1.3.1 M phng
Cng c m
Sng tn hiu ng vo
phng
To bng 2 cch Bo co kt qu
- V sng dng text
- Testbench PASS/FAIL
in
Hnh 1.2 Hai cch khc nhau nh ngha d liu kim tra ng vo
Testbench M t thit k
`timescale 1ns/100ps module DFF (clk, din, qout);
module testbench(); input clk, din;
reg clk; output reg qout;
wire din, qout; always @(posedge clk) begin
always #10 clk = ~clk; qout = din;
DFF i1 (clk, din, qout); end
endmodule endmodule
SIMULATOR
10ns
clk
din
qout
8
Chng 1. Dn nhp thit k h thng s vi Verilog
1.1.3.2 K thut chn kim tra (assertion)
10
Chng 1. Dn nhp thit k h thng s vi Verilog
phn cng bao gm nhng mc m t khc nhau ca Verilog, v kt qu
ng ra ca n l mt phn cng chi tit cho thit b phn cng mc ch
nh FPLD hay sn xut chip ASIC.
Tng hp
Phn tch Sp xp cell v i
- a v biu thc Boolean
- To ra mt d dy kt ni
- Ti u logic
liu thit k c nh - Ti u din tch
-To ra phn cng c kt
dng ng nht - Ti u kt ni
ni bi cc linh kin c bn
2.1ns
Phn tch timing
- Ch ra thi gian tr hon
trn tng path ca mch
1.1.4.4 Binding
1.1.4.5 Sp xp cell v i dy kt ni
Bc sp xp v i dy kt ni s quyt nh vic t v tr ca cc
linh kin trn thit b phn cng mc ch. Vic kt ni cc ng vo v ng
ra ca nhng linh kin ny dng h thng dy lin kt v vng chuyn
mch trn thit b phn cng mc ch c quyt nh bi bc sp xp
v i dy lin kt ny. Kt qu ng ra ca bc ny c a ti thit b
phn cng mc ch, nh np ln FPLD, hay dng sn xut ASIC.
Mt v d minh ha v qu trnh tng hp c ch ra trn Hnh 1.5.
Trong hnh ny, mch m c dng chy m phng trong hnh 1.3
12
Chng 1. Dn nhp thit k h thng s vi Verilog
c tng hp. Ngoi vic m t phn cng thit k dng Verilog, cng c
tng hp i hi nhng thng tin m t thit b phn cng ch tin hnh
qu trnh tng hp ca mnh. Kt qu ng ra ca cng c tng hp l danh
sch cc cng v flip-flop c sn trong thit b phn cng ch v h thng
dy kt ni gia chng. Hnh 1.5 cng ch ra mt kt qu ng ra mang tnh
trc quan m c to ra t ng bng cng c tng hp ca Altera
Quartus II.
M t thit k
module DFF (clk, din, qout);
input clk, din;
output reg qout;
always @(posedge clk) begin
qout = din;
end
endmodule
din
qout
clk
Quan st trn Hnh 1.1, bc phn tch thi gian l mt phn trong
qu trnh bin dch, hoc trong mt s cng c th bc phn tch thi gian
ny c thc hin sau qu trnh bin dch. Bc ny s to ra kh nng
xu nht v tr hon , tc xung clock, tr hon t cng ny n
cng khc, cng nh thi gian cho vic thit lp v gi tn hiu. Kt qu
ca bc phn tch thi gian c th hin di dng bng hoc biu .
Ngi thit k s dng nhng thng tin ny xc nh tc xung clock,
hay ni cch khc l xc nh tc hot ng ca mch thit k.
14
Chng 1. Dn nhp thit k h thng s vi Verilog
1.1.7 To linh kin phn cng
15
Chng 1. Dn nhp thit k h thng s vi Verilog
Vo nm 1987, VHDL tr thnh mt chun ngn ng m t phn
cng ca IEEE. Bi do s h tr ca B quc phng (DoD), VHDL c
s dng nhiu trong nhng d n ln ca chnh ph M. Trong n lc ph
bin Verilog, vo nm 1990, OVI (Open Verilog International) c thnh
lp v Verilog chim u th trong lnh vc cng nghip. iu ny to ra
mt s quan tm kh ln t ngi dng v cc nh cung cp EDA
(Electronic Design Automation) ti Verilog.
Vo nm 1993, nhng n lc nhm chun ha ngn ng Verilog
c bt u. Verilog tr thnh chun IEEE, IEEE Std 1364-1995, vo
nm 1995. Vi nhng cng c m phng, cng c tng hp, cng c phn
tch thi gian, v nhng cng c thit k da trn Verilog c sn, chun
Verilog IEEE ny nhanh chng c chp nhn su rng trong cng ng
thit k in t.
Mt phin bn mi ca Verilog c chp nhn bi IEEE vo nm
2001. Phin bn mi ny c xem nh chun Verilog-2001 v c dng
bi hu ht ngi s dng v ngi pht trin cng c. Nhng c im
mi trong phin bn mi l n cho php bn ngoi c kh nng c v
ghi d liu, qun l th vin, xy dng cu hnh thit k, h tr nhng cu
trc c mc tru tng cao hn, nhng cu trc m t s lp li, cng
nh thm mt s c tnh vo phin bn ny. Qu trnh ci tin chun ny
vn ang c tip tc vi s ti tr ca IEEE.
1.2.2.2 Mc cng
17
Chng 1. Dn nhp thit k h thng s vi Verilog
truy vn li thng tin v nh thi trong m t tin thit k ban u. Hn
na, tin ch ny cng cho php ngi vit m hnh ha tinh chnh hnh vi
nh thi ca m hnh da trn hin thc phn cng.
1.2.2.4 M t Bus
1.2.2.5 Mc hnh vi
18
Chng 1. Dn nhp thit k h thng s vi Verilog
dng v m phng. Verilog cho php vic truy xut c v ghi ngu nhin
n cc tp tin.
1.2.2.7 PLI
19
Chng 1. Dn nhp thit k h thng s vi Verilog
Hin nay c rt nhiu cng c v mi trng da trn Verilog cung
cp kh nng chy m phng, kim tra thit k v tng hp thit k. Mi
trng m phng cung cp nhng chng trnh giao din ha cho bc
thit k trc layout (front-end) v nhng cng c to dng sng v cng
c hin th. Nhng cng c tng hp da trn nn tng ca Verilog v khi
tng hp mt thit k th thit b phn cng ch nh FPGA hoc ASIC cn
phi c xc nh trc.
1.3 Tng kt
1.4 Bi tp
20
Chng 1. Dn nhp thit k h thng s vi Verilog
3. Nu s khc bit gia ngn ng m t phn cng ni chung (ngn
ng Verilog HDL ni ring) v ngn ng lp trnh ni chung (ngn
ng C ni ring).
4. Tm hiu s khc bit gia hai loi ngn ng m t phn cng
Verilog HDL v VHDL.
5. Qu trnh tng hp (synthesis) l g?
6. Verilog HDL c th c s dng m t mch tng t (analog)
trong phn cng khng ?
7. Tm kim 3 cng c m phng Verilog HDL h tr min ph.
8. Tm kim 3 ti liu h tr vic hc v nghin cu Verilog HDL.
9. Tm kim 3 website h tr vic hc v nghin cu Verilog HDL.
10.Tm kim cc cng ty thit k chip Vit Nam ang s dng Verilog
HDL trong vic thit k.
11.Tm hiu v s dng thnh tho hai cng c m phng QuartusII v
ModelSim.
21
Chng 2. Qui c v t kha
Chng 2. Qui c v t kha
2.2 Ch thch
2.3 Ton t
22
Chng 2. Qui c v t kha
2.4 S hc
23
Chng 2. Qui c v t kha
5be // khng hp l ( s thp lc phn i hi h)
24
Chng 2. Qui c v t kha
Nhng s thp phn n gin khng km theo rng bit v nh
dng c s c th c xem nh l nhng s nguyn c du, trong khi
nhng s c m t bi nh dng c s c th c xem nh nhng s
nguyn c du khi thnh phn ch nh s c km thm vo hoc n s
c xem nh nhng s nguyn khng du khi ch c thnh phn nh
dng c s c s dng. Thnh phn ch nh s c du s khng nh
hng n mu bit c m t m n ch nh hng trong qu trnh bin
dch.
Ton t cng hay tr ng trc hng s rng l mt ton t n
cng hay tr. Hai ton t ny nu c t nm gia thnh phn nh dng
c s v s l khng ng c php.
Nhng s m c biu din di dng b hai.
Cc gi tr s c bit x v z:
-Mt s x dng biu din mt gi tr khng xc nh trong nhng
hng s thp lc phn, hng s bt phn v hng s nh phn.
-Mt s z dng biu din mt s c gi tr tng tr cao.
Mt s x c th c thit lp trn 4 bit biu din mt s thp lc
phn, trn 3 bit biu din mt s bt phn, trn 1 bit biu din mt s
nh phn c gi tr khng xc nh. Tng t, mt s z c th c thit lp
25
Chng 2. Qui c v t kha
trn 4 bit biu din mt s thp lc phn, trn 3 bit biu din mt s
bt phn, trn 1 bit biu din mt s nh phn c gi tr tng tr cao.
V d 2.7
2.5
0.9
1543.34592
3.2E23 or 3.2e23
5.6e-3
0.9e-0
45E13
43E-6
354.156_972_e-19 (du gch di c b qua)
2.4.3 S o
28
Chng 2. Qui c v t kha
Hai s thc 48.8 v 48.5 u tr thnh 49 khi c bin i sang s
nguyn, v s 48.3 s tr thnh 48.
Bin i s thc -5.5 sang s nguyn s c -6, bin i s 5.5 sang
s nguyn s c 6.
2.5 Chui
V d 2.8
lu tr mt chui 12 k t Verilog HDL! i hi mt reg c
rng 8*12, hoc 96 bit
reg [8*12:1] stringvar;
initial begin
stringvar = Verilog HDL!;
end
29
Chng 2. Qui c v t kha
2.5.2 X l chui
30
Chng 2. Qui c v t kha
K t u tin ca mt nh danh khng th l mt k s hay $; n c
th l mt k t hoc mt du gch di. nh danh s l khc nhau gia
ch thng v ch hoa nh trong ngn ng lp trnh C.
V d 2.9
kiemtra_e
net_m
fault_result
string_ab
_wire1
n$983
2.6.1 nh danh vi k t \
V d 2.10
\netc+num
\-signal
31
Chng 2. Qui c v t kha
\***fault-result***
\wirea/\wireb
\{m,n}
\i*(k+l)
V d 2.11
$time tr v thi gian chy m phng hin ti
$display tng t nh hm printf trong C
$stop ngng chy m phng
$finish hon thnh chy m phng
$monitor gim st chy m phng
32
Chng 2. Qui c v t kha
2.7 Bi tp
33
Chng 3. Loi d liu trong Verilog
Chng 3. Loi d liu trong Verilog
34
Chng 3. Loi d liu trong Verilog
ngha c 32 bit. Gi tr time c 64 bit. Thc s bit c hai loi
sau:
4 gi tr trng thi (0,1,x,z); c bit nh l gi tr
logic.
128 loi trng thi (4 trng thi v 64 mnh (8 cho
mnh 0 v 8 cho mnh 1)
Loi floating point (s thc)
Chui k t
Gi tr tr hon Nhng gi tr ny c th l single, double,
triplet hay n-tuple ch tr hon cnh ln, cnh xung
hoc s chuyn i khc ca tn hiu.
Gi tr chuyn trng thi (01) chuyn trng thi t 0 sang
1. Gi tr ny c th c trong nhng linh kin c bn do ngi
dng nh ngha hoc trong nhng khi m t (specify blocks)
Nhng gi tr c iu kin/Boole true/false hoc 0/1
units (ch dng cho timescale) femtoseconds (Fs) n
seconds (s)
Nhng loi d liu khc nhau trong Verilog c khai bo bng pht
biu khai bo d liu. Nhng pht biu ny xut hin trong nhng nh
ngha module trc khi s dng v mt s trong chng c th c khai
bo bn trong nhng khi tun t c t tn. Thm vo , nhng loi
gi tr c th phn bit vi nhng loi ca d liu khc, nhng c tnh
phn cng ca wires so vi registers cng c phn bit nh l nhng
khai bo net so vi khai bo reg trong Verilog. T driving ngha l iu
35
Chng 3. Loi d liu trong Verilog
khin c dng trong nhng m t phn cng m t cch thc mt gi
tr c gn n mt phn t. Nets v regs l hai phn t d liu chnh
trong Verilog. Nets c iu khin mt cch ni tip t nhng php gn
ni tip (continuous assignments) hoc t nhng phn t cu trc nh
module ports, gates, transistors hoc nhng phn t c bn do ngi dng
t nh ngha. Regs c iu khin mt cch cht ch t nhng khi hnh
vi (behavioural blocks). Nets thng thng c thc thi nh l wires trong
phn cng v regs th c th l wires hoc phn t tm hoc flip-flops
(registers).
Nhng loi d liu khc nhau trong Verilog c khai bo nh l
mt trong nhng loi sau:
parameter: Loi ny l nhng biu thc gi tr hng s c
phn tch sau qu trnh bin dch v cho php modules c
gn tham s.
input, output, inout : Nhng loi d liu ny nh ngha chiu
v rng ca mt port.
net: y l loi d liu dng cho vic kt ni hoc wire trong
phn cng vi s phn tch khc nhau.
reg: y l loi d liu tru tng ging nh l mt thanh ghi
(register) v c iu khin theo hnh vi.
time: y l loi d liu lu tr khong thi gian nh tr
hon v thi gian m phng.
integer: y l loi d liu s nguyn.
real: y l loi d liu floating point hay s thc
event: y l d liu ch ra rng mt c hiu c bt tch
cc.
Nhng loi d liu ny tt c c th c khai bo mc module.
Nhng m t khc trong Verilog vi nhng kh nng to lp mc ch bao
36
Chng 3. Loi d liu trong Verilog
gm nhng tc v, nhng hm v nhng khi begin-end c t tn. Nets
c iu khin khng theo hnh vi (non-behaviorally) nn do n khng
th c khai bo cho nhng mc ch khc. Tt c nhng loi d liu
khc c th c th hin trong nhng tc v v trong nhng khi begin-
end.
V d 3.1
input a, b;
reg [15:0] c;
time tg;
37
Chng 3. Loi d liu trong Verilog
Nhng loi net khc nhau c nh ngha trong Verilog c m t
bn di v trong Bng 3.1 s tm tt s phn gii logic ca chng. S
phn gii logic l mt qui nh gii quyt xung t xy ra khi c nhiu
mc logic iu khin mt net.
Wire: mt net vi gi tr 0,1,x v s phn gii logic c da
trn s tng ng.
Wand: mt net vi gi tr 0,1,x v s phn gii logic c da
trn nguyn tc ca php wired and
Wor: mt net vi gi tr 0,1,x v s phn gii logic c da
trn wired or
Tri: mt net vi gi tr 0,1,x,z v s phn gii logic c da
trn nguyn tc ca bus tri-state
Tri0: mt net vi gi tr 0,1,x,z v s phn gii logic c da
trn nguyn tc ca bus tri-state v mt gi tr mc nh l 0
khi khng c iu khin
Tri1: mt net vi gi tr 0,1,x,z v s phn gii logic c da
trn nguyn tc ca bus tri-state v mt gi tr mc nh l 1
khi khng c iu khin
Trior: mt net vi gi tr 0,1,x,z v s phn gii logic c
da trn nguyn tc ca tri-state cho gi tr z-non-z s dng
hm or ca gi tr non-z
Triand: mt net vi gi tr 0,1,x,z v s phn gii logic c
da trn nguyn tc ca tri-state cho gi tr z-non-z s dng
hm and ca gi tr non-z
Trireg: mt net vi gi tr 0,1,x,z v s phn gii logic c
da trn nguyn tc ca tri-state cng vi gi tr lu tr in
tch (gi tr trc c dng phn gii gi tr mi)
Supply0, supply1 (gnd v vdd)
38
Chng 3. Loi d liu trong Verilog
Bng 3.1 S phn gii ca cc loi net
tri/wire 0 1 X Z triand/wand 0 1 X Z
0 0 X X 0 0 0 0 0 0
1 X 1 X 1 1 0 1 X 1
X X X X X X 0 X X X
Z 0 1 X X Z 0 1 X Z
trior/wor 0 1 X Z tri0 0 1 X Z
0 0 1 X 0 0 0 0 0 0
1 1 1 1 1 1 X 1 X 1
X X 1 X X X X X X X
Z 0 1 X Z Z 0 1 X 0
trireg 0 1 X Z tri1 0 1 X Z
0 0 1 X 0 0 0 X X 0
1 1 1 1 1 1 X 1 X 1
X X 1 X X X X X X X
Z 0 1 X P Z 0 1 X 1
39
Chng 3. Loi d liu trong Verilog
V d 3.2
wire a1;
wire [2:0] b2;
tri abc
V d 3.3
module tri_kiemtra (out, m, n,p);
input [1:0] select ,m ,n, p;
output out;
tri out;
assign out = m ; to kt ni cho net tri
assign out = n;
assign out = p;
endmodule
module mnp (m, n, p, select)
output m, n, p;
input [1:0] select;
40
Chng 3. Loi d liu trong Verilog
always @(select) begin
m = 1bz; // thit lp tt c cc bin c gi tr Z
n = 1bz;
p = 1bz;
case (select) // ch thit lp mt bin non-Z
2b00: m = 1b1;
2b01: n = 1b0;
2b10: p = 1b1;
endcase
end
endmodule
module top_tri_test ( out, m, n, p, select);
input [1:0] select;
input m, n, p;
output out;
tri out;
mnp (m, n, p, select);
tri_test (out, m, n, p);
endmodule
Wired nets bao gm nhng loi d liu wor, wand, trior v triand.
Chng c dng m hnh gi tr logic ca net. Nhng wired net trn c
bng s tht khc nhau phn gii nhng xung t nu xy ra khi c
nhiu cng linh kin cng iu khin mt net.
41
Chng 3. Loi d liu trong Verilog
3.4.3.1 Wand/triand nets
V d 3.4
module wand_test (out, b1,b2);
input b1, b2;
output out;
wand out;
assign out = b1;
assign out = b2;
endmodule
3.4.3.2 Wor/Trior
V d 3.5
module wor_test(a1,a2);
input a1, a2;
42
Chng 3. Loi d liu trong Verilog
ouput out;
wor out;
assign out = a1;
assign out = a2;
endmodule
V d 3.6
module kiemtra;
43
Chng 3. Loi d liu trong Verilog
reg c0, c1, i1, i2;
tri d0, d1, d2;
trireg d;
and(d0, il, i2);
nmos nl (d1, d0, c0);
nmos n2(d, d1, c1);
initial
begin
$monitor(time = %d d = %d c0=%d c1=%d d0=%d d1=%d
i1=%d i2=%d, $time, d, c0, c1, d0, d1, i1, i2);
#1
i1 = 1;
i2 = l;
c0 = l;
c1 = 1;
#5
c0 = 0;
end
endmodule
Simulation result:
time = 0 d= x c0=x c1=x d0=x d1=x i1=x i2=x
time = 1 d= 1 c1=1 c1=1 d0=1 d1=1 i1=1 i2=1
time = 6 d= 1 c0=0 c1=1 d0=1 d1=0 i1=1 i2=1
V d 3.7
supply0 gnd;
supply1 power;
45
Chng 3. Loi d liu trong Verilog
tham s, biu thc ca chng hay c th l nhng biu thc ng dng
nhng bin s khc. tr hon c th l rise, fall, hay hold (thi gian thay
i n z) v mi loi tr hon ny c th c ba gi tr - minimum, typical
v maximum. S m t tr hon rise, fall, v hold c phn bit bi
du phy (,) v s m t min-typ-max c phn bit bi du hai chm (:).
tr hon rise bao gm thi gian tr hon khi gi tr tn hiu thay i t 0
ln 1, 0 n x v t x n 1. tr hon fall bao gm thi gian tr hon khi
gi tr tn hiu thay i t 1 xung 0, 1 n x v t x n 0. tr hon
hold bao gm thi gian tr hon khi gi tr tn hiu thay i t 0 ln z, 1 n
z v t x n z. Khi nim tr hon ny cng c dng cho vic nh
ngha tr hon ca cng, transistor, linh kin c bn do ngi dng t
nh ngha v nhng m t hnh vi.
V d 3.8
tri #9 t1, t2;
wire #(10,9,8) a1, a2;
wand #(10:8:6, 9:8:6) a3;
V d 3.9
wire a1, a2;
tri[7:0] t1, t2;
trireg large trg1, trg2;
triand [31:0] #(10:5) gate1;
46
Chng 3. Loi d liu trong Verilog
Trong v d trn, dng u tin vi t kha wire khai bo a1 v a2
l wire n ( scalar wire hay single bit). Dng th hai khai bo hai vector
wire 8 bit t1 v t2 c loi d liu l tri. Dng k tip khai bo net c kh
nng lu gi in dung trg1 v trg2 vi ln in dung l large. Dng
cui cng khai bo mt net c rng 32 bit c loi d liu l triand vi
tr hon l ti thiu (minimum) v trung bnh (typical).
V d 3.10
reg reg1, reg2;
reg [63:0] data1, data2, data3;
V d 3.11
input m;
input [2:0] n;
V d 3.12
output a;
output [2:0] b;
reg [2:0] b;
48
Chng 3. Loi d liu trong Verilog
inout: ta c th khai bo port hai chiu (bidirectional) vi pht biu
inout. Mt port inout c loi d liu l wire v c iu khin bi c php
ca wire. Ta phi khai bo port inout trc khi n c s dng.
V d 3.13
inout a:
inout [2:0] b;
V d 3.14
module fulladder(cout, sum, in1, in2, in3);
input in1, in2, in3; // khai bo 3 ng vo
output cout, sum; //khai bo 2 ng ra
wire in1, in2, in3; //khai bo kiu d liu
reg cout, sum; //khai bo kiu d liu
endmodule
49
Chng 3. Loi d liu trong Verilog
phi l nhng biu thc c gi tr hng khc 0. Nhng biu thc c gi tr
hng ch c th to nn bi nhng hng s, nhng tham s ca Verilog v
cc ton t. Khng c gii hn trong vic nh ngha rng ti a ca mt
bit-vector trong Verilog, tuy nhin vic gii hn ny c th s ph thuc
vo cng c m phng, tng hp, hoc nhng cng c khc.
V d 3.15
wire [63:0] bus;
V d 3.16
wire vectored [31:0] bus1;
wire scalared [31:0] bus2;
50
Chng 3. Loi d liu trong Verilog
reg [7:0] areg
51
Chng 3. Loi d liu trong Verilog
52
Chng 3. Loi d liu trong Verilog
3.8.2 Integer
3.8.3 Time
V d 3.20
time t1, t2;
54
Chng 3. Loi d liu trong Verilog
> >= < <= Relational
! && || Logical
== != Logical equality
?: Conditional
V d 3.21
real float;
realtime rtime;
55
Chng 3. Loi d liu trong Verilog
3.9 Khai bo tham s
3.9.2.1 Parameter
V d 3.22
parameter msb = 1; // nh ngha tham s msb c gi tr hng s l 1
parameter e = 43, f =789; // nh ngha hai hng s
parameter r = 46.7; // khai bo r l mt hng s thc
56
Chng 3. Loi d liu trong Verilog
parameter byte_size = 9,
byte_mask = byte_size - 6;
parameter average_delay = (r + f) / 2;
parameter signed [3:0] mux_selector = 0;
parameter real r1 = 3.6e19;
parameter p1 = 13'h7e;
parameter [31:0] dec_const = 1'b1; // gi tr c i sang 32 bit
parameter newconst = 3'h4; // ng l tham s ny c rng [2:0]
parameter newconst = 4; // ng l tham s ny c rng ti thiu
l 32 bit.
V d 3.23
module top;
reg clk;
58
Chng 3. Loi d liu trong Verilog
reg [0:4] in1;
reg [0:9] in2;
wire [0:4] o1;
wire [0:9] o2;
vdff m1 (o1, in1, clk);
vdff m2 (o2, in2, clk);
endmodule
module vdff (out, in, clk);
parameter size = 1, delay = 1;
input [0:size-1] in;
input clk;
output [0:size-1] out;
reg [0:size-1] out;
always @(posedge clk)
# delay out = in;
endmodule
module annotate;
defparam
top.m1.size = 5,
top.m1.delay = 10,
top.m2.size = 10,
top.m2.delay = 20;
endmodule
60
Chng 3. Loi d liu trong Verilog
phi gn gi tr cho tt c cc tham s nhng dng gi tr mc nh (cng
c gi tr nh c gn trong khai bo tham s trong nh ngha module)
cho cc tham s m khng cn c gi tr mi.
Xt V d 3.24, trong v d ny nhng tham s bn trong instance
ca nhng module mod_a, mod_c, v mod_d c thay i trong khi gi
instance.
V d 3.24
module tb1;
wire [9:0] out_a, out_d;
wire [4:0] out_b, out_c;
reg [9:0] in_a, in_d;
reg [4:0] in_b, in_c;
reg clk;
// To testbench clock v stimulus.
// Bn instance ca module vdff vi php gn gi tr tham s theo th
t danh sch tham s
// mod_a c hai gi tr tham s mi size=10 v delay=15
// mod_b c gi tr tham s mc nh l (size=5, delay=1)
// mod_c c mt gi tr tham s mc nh l size=5 v mt gi tr
mi l delay=12
// thay i gi tr ca tham s delay, ta cng cn phi m t gi
tr mc nh ca tham s size
// mod_d c mt gi tr tham s mi l size=10, v gi tr tham s
delay vn gi gi tr mc nh ca n.
vdff #(10,15) mod_a (.out(out_a), .in(in_a), .clk(clk));
vdff mod_b (.out(out_b), .in(in_b), .clk(clk));
vdff #( 5,12) mod_c (.out(out_c), .in(in_c), .clk(clk));
61
Chng 3. Loi d liu trong Verilog
vdff #(10) mod_d (.out(out_d), .in(in_d), .clk(clk));
endmodule
module vdff (out, in, clk);
parameter size=5, delay=1;
output [size-1:0] out;
input [size-1:0] in;
input clk;
reg [size-1:0] out;
always @(posedge clk)
#delay out = in;
endmodule
V d 3.25
module my_mem (addr, data);
parameter addr_width = 16;
localparam mem_size = 1 << addr_width;
parameter data_width = 8;
...
endmodule
module top;
...
62
Chng 3. Loi d liu trong Verilog
my_mem #(12, 16) m(addr,data);
endmodule
2. Php gn gi tr tham s bi tn
Php gn gi tr tham s bi tn bao gm tn tng minh ca tham
s v gi tr mi ca n. Tn ca tham s s l tn c m t trong
instance ca module.
Ta khng cn thit gn nhng gi tr n tt c cc tham s bn trong
module khi s dng phng php ny. Ch nhng tham s no m c
gn gi tr mi th mi cn c ch ra.
Biu thc tham s c th l mt la chn vic gi instance ca
module c th ghi li vic hin din ca mt tham s m khng cn bt k
mt php gn n n. Nhng du ng m ngoc c i hi, v trong
trng hp ny tham s s gi gi tr mc nh ca n. Khi mt tham s
c gn mt gi tr, th mt php gn khc n tn tham s ny l khng
c php.
Xt V d 3.26, trong v d ny c nhng tham s ca mod_a v ch
mt tham s ca mod_c v mod_d b thay i trong khi gi instance ca
module.
V d 3.26
module tb2;
wire [9:0] out_a, out_d;
wire [4:0] out_b, out_c;
reg [9:0] in_a, in_d;
reg [4:0] in_b, in_c;
reg clk;
// Code to testbench clock & stimulus ...
63
Chng 3. Loi d liu trong Verilog
// Bn instance ca moduel vdff vi gi tr tham s c gn bi tn
// mod_a c gi tr tham s mi l size=10 v delay=15
// mod_b c gi tr tham s mc nh l (size=5, delay=1)
// mod_c c mt gi tr tham s mc nh l size=5 v c mt gi tr
tham s mi l delay=12
// mod_d c mt gi tr tham s mi l size=10.
// cn tham s delay vn gi gi tr mc nh
vdff #(.size(10),.delay(15)) mod_a (.out(out_a),.in(in_a),.clk(clk));
vdff mod_b (.out(out_b),.in(in_b),.clk(clk));
vdff #(.delay(12)) mod_c (.out(out_c),.in(in_c),.clk(clk));
vdff #(.delay( ),.size(10) ) mod_d (.out(out_d),.in(in_d),.clk(clk));
endmodule
module vdff (out, in, clk);
parameter size=5, delay=1;
output [size-1:0] out;
input [size-1:0] in;
input clk;
reg [size-1:0] out;
always @(posedge clk)
#delay out = in;
endmodule
V d 3.28
// instance mod_a khng hp l do c s pha trn gia cc php gn
tham s
vdff #(10, .delay(15)) mod_a (.out(out_a), .in(in_a), .clk(clk));
V d 3.29
parameter
word_size = 32,
memory_size = word_size * 4096;
V d 3.30
localparam thamso1;
localparam signed [3:0] thamso2;
localparam time t1;
localparam integer int2;
localparam var = 5*6;
66
Chng 3. Loi d liu trong Verilog
3.9.3 Tham s c t (specify parameter)
V d 3.31
specify
specparam tRise_clk_q = 150, tFall_clk_q = 200;
specparam tRise_control = 40, tFall_control = 50;
endspecify
Nhng dng gia nhng t kha specify v endspecify l khai
bo bn tham s c t. Dng u tin khai bo hai tham s c t
68
Chng 3. Loi d liu trong Verilog
tRise_clk_q v tFall_clk_q vi gi tr tng ng l 150 v 200. Dng th
hai khai bo hai tham s c t tRise_control v tFall_control vi gi tr
tng ng l 40 v 50.
V d 3.32
module RAM16GEN (output [7:0] DOUT, input [7:0] DIN,
input [5:0] ADR,
input WE, CE);
specparam dhold = 1.0;
specparam ddly = 1.0;
parameter width = 1;
parameter regsize = dhold + 1.0; // Khng hp l - khng th
gn tham s c t (specparam) n mt tham s (parameter)
endmodule
3.10 Bi tp
69
Chng 3. Loi d liu trong Verilog
6. C my loi tham s module ? Nu s khc bit gia hai khai bo
parameter v localparameter trong tham s module ?
70
Chng 4. Biu thc
Chng 4. Biu thc
71
Chng 4. Biu thc
Hng s (bao gm c s thc) hoc chui.
Tham bin (bao gm c tham bin ni v tham bin ch nh).
Bit-select v part-select ca tham bin (khng bao gm s
thc).
Net.
Bit-select v part-select ca net.
Bin reg, integer, hoc time.
Bit-select v part-select ca bin reg, integer, hoc time.
Bin real hoc realtime.
Mng cc phn t.
Bit-select v part-select ca mng cc phn t.
Mt hm gi do ngi dng nh ngha hoc hm gi h thng
m n tr v bt k gi tr no bn trn.
4.2 Ton t
73
Chng 4. Biu thc
Bng 4.3 Danh sch ton t khng c php s dng i vi ton t s thc
{} {{}} Ton t ghp ni, thay th
% Ton t chia ly phn d
=== !== Ton t bng
~ , &, |, ^, ^~, ~^ Ton t bitwwise
^, ^~, ~^, &, ~&, |, ~| Ton t gim
<< >> <<< >>> Ton t dch
74
Chng 4. Biu thc
75
Chng 4. Biu thc
tr. Mt s nguyn khng u c c s s c nh gi nh l mt gi tr
khng du.
V d 4.1 ch ra 4 cch vit biu thc -12 chia 3. Ch rng c
hia gi tr-12 v d12 c nh gi l ging nhau v 2 thnh phn
bit, nhng trong biu thc d12 khng cn c nh danh nh l mt s
ph nh c du.
V d 4.1
integer IntA;
IntA = -12 / 3;// kt qu l -4.
IntA = -'d 12 / 3;// kt qu l 1431655761.
IntA = -'sd 12 / 3;// kt qu l -4.
IntA = -4'sd 12 / 3; // -4'sd12 l mt s m 4-bit l 1100, vi -4. -(-4)
= 4.
// kt qu l 1.
V d 4.2
Reg regA, regB, regC, result;
Result = regA&(regB|regC)
Nu gi tr ca regA l 0 th kt qu ca biu thc c th c pht
hin l 0 m khng cn tnh ton gi tr ca biu thc con regB|regC.
76
Chng 4. Biu thc
4.2.5 Ton t s hc
78
Chng 4. Biu thc
2**3 8 2*2*2
2**0 1 Bt k s no ly tha 0 cng bng 1
2.0**-3sb1 0.5 2.0 l s thc, nn kt qu cng l s thc
2**-3sb1 0 2**-1=1/2, c phn nguyn l s 0
0**-1 bx 0 ly tha s m l mt s khng xc nh
9**0.5 3.0 Kt qu l mt s thc
9.0**(1/2) 1.0 kt qu l 0
-3.0**2.0 9.0
79
Chng 4. Biu thc
reg c du C du, b 2
integer C du, b 2
time Khng du
real, realtime C du, du chm ng
V d 4.3
integer intA;
reg [15:0] regA;
reg signed [15:0] regS;
intA = -4'd12;
regA = intA / 3; // kt qu ca biu thc l -4,
// intA l d liu loi integer, regA bng 65532
regA = -4'd12; // regA bng 65524
intA = regA / 3; // Kt qu ca biu thc 21841,
// regA l d liu loi reg
intA = -4'd12 / 3; // kt qu ca biu thc l 1431655761.
// -4'd12 thc t l mt d liu loi reg 32-bit
regA = -12 / 3; // kt qu ca biu thc l -4,
//-12 thc t l mt d liu loi integer.
regS = -12 / 3; // kt qu ca biu thc l -4. regS l mt reg c
du
regS = -4'sd12 / 3; // kt qu ca biu thc l 1. -4'sd12 l 4.
// Theo lut chia s nguyn ly phn d 4/3==1.
80
Chng 4. Biu thc
4.2.7 Ton t quan h
81
Chng 4. Biu thc
V d 4.4
V d sau s minh ha vi thc thi cc lut v u tin
a<foo - 1// biu thc ny ging vi biu thc a<(foo - 1)
Nhng . . .
foo-(1<a)// biu thc ny khng ging vi biu thc foo-1<a
Khi foo-(1<a) c tnh ton, biu thc quan h s c tnh ton
u tin, v sau hoc l 0, hoc l 1 s c tr bi foo. Khi foo-1<a
c tnh ton th gi tr ca ton hng foo s tr i 1 sau em so snh
vi a.
V d 4.5
V d 1 nu reg alpha gi gi tr integer 237 v beta gi gi tr l 0,
th v d cho php thc thi nh m t:
regA=alpha && beta //regA c ci t l 0
regB =alpha || beta //regB c ci t l 1
V d 2- Biu thc cho php thc thi mt ton t logic v ba biu
thc con m khng cn bt k du ngoc n no
a < size -1 && b != c && index != lastone
Tuy nhin, n khuyn khch s dng du ngoc n vo mt mc
ch thc t s lm cho biu r rng hn v u tin, nh cch vit trong
v d di y.
83
Chng 4. Biu thc
(a < size -1) && (b != c) && (index != lastone)
V d 3 Thng thng s dng ton t ! trong mt cu trc nh
sau:
if(!inword)
Trong mt vi trng hp, cu trc trn lm cho ngi c chng
trnh kh hiu hn cu trc: if ( inword ==0)
Ton t thao tc trn bit s thc thi thao tc trn tng bit ca ton
hng, y l ton t kt hp tng bit trn mi ton hng vi bit tng ng
trn ton hng kia tnh ton ra 1 bit kt qu. Cc bng t 4-12 n 14-16
s cho thy kt qu mi php ton c th trn bit.
84
Chng 4. Biu thc
^ 0 1 x z
0 0 1 x x
1 1 0 x x
X x x x x
Z x x x x
Khi cc ton hng khng bng nhau v chiu di, th ton hng ngn
hn s thm s 0 vo v tr bit c ngha nht (MSB).
86
Chng 4. Biu thc
Bng 4.20 cho thy kt qu ca vic p dng ton t gim trn cc
ton hng khc nhau.
y l hai loi ton t dch, ton t dch logic << v >>, v ton t
dch s hc <<< v >>>. Ton t dch tri << v <<< s dch ton hng bn
tri ca chng sang tri mt s v tr bit c a ra trong ton hng bn
phi. Trong c hai trng hp, bit v tr trng s c in vo bng s 0.
Ton t dch phi, >> v >>>, s dc ton hng bn tri ca chng sang
phi mt s v tr bit c a ra trong ton hng bn phi. Trong ton t
dch phi logic s in vo v tr bit trng l s 0. Trong ton t dch phi
ton hc s in vo v tr bit trng s 0 nu kt qu l loi khng du v n
s in vo v tr bit trng gi tr bit c ngha nht ca ton hng bn tri
nu kt qu l loi c du. Nt ton hng bn phi c dng gi tr x hoc z,
th kt qu s khng xc nh (x). Ton hng bn phi lun lun c xem
nh l mt s khng du v khng c nh hng n du ca kt qu. Du
ca kt qu c xc nh bng ton hng bn tri v s d ca biu thc
nh m t trong 4.6.1.
87
Chng 4. Biu thc
V d 4.6
V d 1- Trong v d ny, thanh ghi result c gn gi tr nh phn
0100, do dch gi tr nh phn 0001 sang tri hai v tr v in s 0 vo
v tr trng
module shift;
reg [3:0] start, result;
initial begin
start = 1;
result = (start << 2);
end
endmodule
V d 2- Trong v d ny, thanh ghi result c gn gi tr nh phn
1110, l do dch gi tr nh phn 1000 sang phi hai v tr v in bit
du vo v tr trng.
module ashift;
reg signed [3:0] start, result;
initial begin
start = 4'b1000;
result = (start >>> 2);
end
endmodule
88
Chng 4. Biu thc
C php 4-1
conditional_expression ::=
expression1 ? { attribute_instance } expression2 : expression3
expression1 ::=
expression
expression2 ::=
expression
expression3 ::=
expression
89
Chng 4. Biu thc
z x x x x
V d 4.7
Theo v d ny s c 3 trng thi bus u ra minh ho vic s dng
ton t iu kin thng thng.
wire [15:0]busa=drive_busa?data:16'bz;
Bus data s c li vo busa khi bit drive_busa l 1. Nu bit drive_busa
khng xc nh, th mt gi tr khng xc nh s c li vo busa, ni
cch khc busa khng xc nh.
V d 4.8
V d ny s ghp ni bn biu thc:
{a, b[3:0], w, 3b101}
N c c lng cho php trong v d:
{a, b[3], b[2], b[1], b[0], w, 1b1, 1b0, 1b1}
V d 4.9
parameter P = 32; // Hp l cho tt c P t 1 ti 32
assign b[31:0] = { {32-P{1b1}}, a[P-1:0] } ;
// Khng hp l cho P=32 bi v s 0 nhn bn xut hin mt mnh
trong ton t kt ni.
assign c[31:0] = { {{32-P{1b1}}}, a[P-1:0] }
// Khng hp l cho P=32
initial
$displayb({32-P{1b1}}, a[P-1:0]);
Khi mt biu thc nhn bn c tnh ton, ton hng s tnh ton
mt cch chnh xc thm ch nu ton t nhn bn l s 0. V d:
Result = {4{func(w)}}
S tnh ton nh l :
91
Chng 4. Biu thc
Y = func(w)
Result = {y, y, y, y}
Bit-select trch ra mt bit ring bit t bin vector net, vector reg,
integer, hoc time, hoc parameter. Cc bit c th c nh a ch bng
mt biu thc. Nu mt bit-select nm ngoi gii hng hoc bit-select l x
hoc z, th gi tr tr v c tham s l x. Mt bit-select hoc part-select
ca mt gi tr v hng, hoc ca mt bin hoc tham s thuc loi real
hoc realtime s khng hp l.
92
Chng 4. Biu thc
Mt s bit lin k nhau trong mt bin vector net, vector reg, integer,
hoc time, hoc tham s c th nh a ch v c gi l mt part-select.
C hai loi part-select, part-select hng s v part-select ch s. Part-select
hng s ca mt vector net hoc reg c a ra theo c php bn di:
Vect [msb_expr: lsb_expr]
C msb_expr v lsb_expr s l biu thc s nguyn khng i. Biu
thc u c a ch c ngha hn biu thc th hai
Part-select ch s ca mt bin vector net, vector reg, integer hoc
time, hoc tham s c a ra theo c php bn di:
reg [15:0] big_vect;
reg [0:15] little_vect;
big_vect[lsb_base_expr +: width_expr]
little_vect[msb_base_expr +: width_expr]
big_vect[msb_base_expr -: width_expr]
little_vect[lsb_base_expr -: width_expr]
Trong msb_base_expr v lsb_base_expr l hai biu thc s
nguyn, v width_expr l mt biu thc s nguyn dng khng i.
Lsb_base_expr v msb_base_expr c th thay i trong thi gian chy.
Trong hai v d u bit c chn bt u t base v tng dn phm vi bit.
Hai v d th hai bit c chn bng u t v tr base v gim dn phm vi
bit.
Mt part-select ca bt k loi no c phm vi a ch nm ngoi
vng a ch ca net, bin reg, integer, time hoc parameter hoc part-
select m c gi tr x hoc z th chng s c gi tr x khi c v s khng
nh hng n d liu lu tr khi ghi. Part-select nm ngoi phm vi cc
b ny s tr v gi tr x cho cc bit nm ngoi phm vi khi c v ch nh
hng n cc bit trong phm vi khi ghi.
93
Chng 4. Biu thc
V d 4.10
reg [31: 0] big_vect;
reg [0 :31] little_vect;
reg [63: 0] dword;
integer sel;
big_vect[ 0 +: 8] // == big_vect[ 7 : 0]
big_vect[15 -: 8] // == big_vect[15 : 8]
little_vect[ 0 +: 8] // == little_vect[0 : 7]
little_vect[15 -: 8] // == little_vect[8 :15]
dword[8*sel +: 8] // bin part-select vi rng c nh
V d 4.11
Trong v d tip theo s khai bo mt b nh 1024 t 8 bit:
reg [7:0] men_name[0:1023];
C php cho a ch b nh s bao gm tn vng nh v biu thc
a ch, theo nh dng sau:
men_name[addr_expr];
Trong addr_expr l mt biu thc nguyn bt k; v vy mt b
nh gin tip c th ch ra nh l mt biu thc n.V d tip theo minh
ha cho b nh gin tip:
men_name[men_name[3]];
94
Chng 4. Biu thc
Trong V d 4.11, t nh a ch men_name[3] s dng lm biu
thc cho vic truy cp b nh ti a ch men_name[men_name[3]]. Cng
ging nh ton t bit-select, a ch trong vng khai bo b nh mi l biu
thc a ch c nh hng. Nu ch s nm bn ngoi vng gin hn a ch
b nh hoc nu bt k bit no trong a ch l z hoc x th gi tr tham
chiu s l x.
V d 4.12
V d tip theo khai bo mt mng hai chiu [256:256] phn t 8 bit
v mt mng ba chiu [256:256:8] cc phn t mt bit:
reg [7:0] twod_array[0:255][0:255];
wire threed_ array[0:255][0:255][0:7];
C php sau truy xut n mng bao gm tn ca b nh hoc mng
v biu thc s nguyn cho mi chiu ca mng:
twod_array[addr_expr][addr_expr]
threed_array[addr_expr][addr_expr][addr_expr]
Nh cc v d trc, addr_expr l mt biu thc s nguyn bt k.
Trong mng hai chiu twod_array truy cp n vector 8 bit, trong khi mng
ba chiu threed_array truy xut n cc bit n trong mng ba chiu.
biu din bit-select hoc part-seclect ca phn t mng, t mong
mun s c chn u tin bng cch cung cp a ch cho mi chiu.
Mt la chn bit-select v part-select s nh a ch ging nh l bit-select
v part-select net v reg.
V d 4.13
twod_array[14][1][3:0] // Truy xut 4 bit thp ca t
twod_array[1][3][6] // Truy xut bit th 6 ca t
twod_array[1][3][sel] // S dng bin bit-select
threed_array[14][1][3:0] // Khng hp l
95
Chng 4. Biu thc
4.3.3 Chui
V d 4.14
Theo v d ny, ta khai bo mt bin chui c ln cha 14
k t v gn cho n mt gi tr. V d s thao tc trn chui s dng ton t
ghp ni.
module string_test;
reg [8*14:1]stringvar;
initial begin
stringvar="Helloworld";
$display("%s is stored as %h", stringvar, stringvar);
stringvar={stringvar,"!!!"};
$display("%s is stored as %h", stringvar, stringvar);
end
endmodule
Kt qu m phng cho on chng trnh trn:
Hello world is stored as 00000048656c6c6f20776f726c64
Hello world!!! is stored as 48656c6c6f20776f726c64212121
96
Chng 4. Biu thc
4.3.3.1 Ton t chui
V d 4.15
reg [8*10:1]s1,s2;
initial begin
s1="Hello";
s2="world!";
if ({s1,s2}=="Helloworld!")
$display("stringsareequal");
end
C php 4-2
constant_expression ::=
98
Chng 4. Biu thc
constant_primary
| unary_operator { attribute_instance } constant_primary
| constant_expression binary_operator { attribute_instance }
constant_expression
| constant_expression ? { attribute_instance } constant_expression
constant_expression
constant_mintypmax_expression ::=
constant_expression
| constant_expression : constant_expression : constant_expression
expression ::=
primary
| unary_operator { attribute_instance } primary
| expression binary_operator { attribute_instance } expression
| conditional_expression
mintypmax_expression ::=
expression
| expression : expression : expression
constant_primary ::= (From A.8.4)
number
| parameter_identifier [ [ constant_range_expression ] ]
| specparam_identifier [ [ constant_range_expression ] ]
|constant_concatenation
| constant_multiple_concatenation
| constant_function_call
| constant_system_function_call
| ( constant_mintypmax_expression )
| string
primary ::=
99
Chng 4. Biu thc
number
| hierarchical_identifier [ { [ expression ] } [ range_expression ] ]
| concatenation
| multiple_concatenation
| function_call
| system_function_call
| ( mintypmax_expression )
| string
V d 4.16
V d 1 - V d ny cho thy biu thc nh ngha b ba duy nht ca
gi tr tr hon. Trong biu thc:
(a:b:c)+(d:e:f)
Gi tr nh nht l tng ca a+d, gi tr trung bnh l tng ca b+e,
gi tr ln nht l tng ca c+f.
V d 2 v d tip theo th hin mt biu thc in hnh s dng
gi tr theo nh dng min:typ:max.
val-(32'd50:32'd75:32'd100)
100
Chng 4. Biu thc
4.5 Biu thc di bit
Kim sot s lng bit c s dng trong vic tnh ton cc biu
thc l rt quan trng nu ph hp vi kt qu t c. Mt vi tnh hun
c gii php n gin; v d, nu mt bit v ton t c quy nh trn hai
thanh ghi 16 bit, th kt qu s l mt gi tr 16 bit. Tuy nhin, trong mt
vi tnh hun, n khng r rn l c bao nhiu bit c s dng trong vic
tnh ton biu thc hoc kch c ca kt qu l bao nhiu.
V d, thc hin tnh ton php cng s hc ca hai thanh ghi 16
bit cn s dng 16 bit, hoc cn s dng 17 bit c th cha c bit trn?
Cu tr li ph thuc vo loi thit b c m hnh v cch m thit b
iu khin nh bit trn. Verilog HDL s dng di bit ca ton hng
pht hin c bao nhiu bit c s dng trong qu trnh tnh ton biu thc.
Cc lut v di bit c a ra 4.5.1. Trong trng hp ton t cng,
di bit ca ton hng ln hn s c s dng cho bin bn tri php
gn.
V d 4.17
reg [15:0] a, b; // thanh ghi 16 bit
reg [15:0] sumA; // thanh ghi 16 bit
reg [16:0] sumB; // thanh ghi 17 bit
sumA = a + b; // biu thc tnh ton s dng 16 bit
sumB = a + b; // biu thc tnh ton s dng 17 bit
101
Chng 4. Biu thc
S lng bit ca mt biu thc (cn gi l kch c ca biu thc) s
c xc nh bng ton hng c gi trong biu thc v ni dung ca
biu thc a ra.
Mt biu thc t xc nh l biu thc m di bit ca n c xc
nh duy nht bi t biu thc , v d, biu thc th hin gi tr tr hon.
Mt biu thc xc nh ton b l biu thc m di bit ca n
c xc nh bng di bit ca biu thc v mt phn ca biu thc
c lin quan khc. V d, kch c bit ca biu thc bn phi ca php gn
ph thuc vo t n v kch c ca biu thc bn tri.
Bng 4.22 th hin cch cc biu thc thng thng xc nh di
bit ca kt qu biu thc. Trong Bng 4.22, i, j v k l cc ton hng ca
biu thc, v L(i) th hin di bit ca ton hng i.
Ton hng nhn c th thc hin m khng mt bt k bit trn no
bng cch gn kt qu rng cha n.
op j, vi op l : + - ~ L(i)
i op j, vi op l: === 1bit Ton hng c kch
!== == != > >= < <= thc l:max (L(i),L(j))
i op j, vi op l: && || 1bit Tt c cc ton hng t
102
Chng 4. Biu thc
xc nh
op j, vi op l: & ~& 1bit Tt c cc ton hng t
| ~| ^ ~^ ^~ ! xc nh
i op j, vi op l: >> L(i) j t xc nh
<< ** >>> <<<
i?j:k max(L(j),L(k) i t xc nh
{i,...,j} L(i)+..+L(j) Tt c cc ton hng t
xc nh
{i{j,..,k}} i * (L(j)+..+L(k)) Tt c cc ton hng t
xc nh
103
Chng 4. Biu thc
tm thi l mt gi tr 16 bit, v vy bit nh b mt trc khi thc thi vic
tnh ton ton t dch phi mt bit.
Gii php l p buc biu thc (a + b) thc hin tnh ton s dng t
nht 17bit. V d thm vo ton t cng mt s integer c gi tr 0, biu
thc s tnh ton ng v n thc thi s dng kch c bit ca integer. Theo
v d bn di th s to ra kt qu ng vi mc ch
Answer = (a + b + 0) >> 1; // s thc thi ng
Trong v d tip theo:
V d 4.19
module bitlength();
reg [3:0] a,b,c;
reg [4:0] d;
initial begin
a = 9;
b = 8;
c = 1;
$display("answer = %b", c ? (a&b) : d);
end
endmodule
Cu lnh $display s hin th
Answer = 01000
Bng cch t n, biu thc a&b c chiu di l 4 bit, nhng bi v trong ni
dung ca biu thc iu kin, n s s dng di bit ln nht, v vy nn
biu thc a&b s c di l 5, l di ca d.
.
V d 4.20
104
Chng 4. Biu thc
reg [3:0] a;
reg [5:0] b;
reg [15:0] c;
initial begin
a = 4'hF;
b = 6'hA;
$display("a*b=%h", a*b); // Kch thc ca biu thc t
xc nh
c = {a**b}; // biu thc a**b l t xc nh
// trong ton t kt ni {}
$display("a**b=%h", c);
c = a**b; // Kch thc ca biu thc xc nh bi c
$display("c=%h", c);
end
Kt qu m phng ca v d ny:
a*b=16 // 'h96 b ct b cn 'h16 v kch thc ca biu thc l 6
a**b=1 // kch thc ca biu thc 4 bit (kch thc ca a)
c=ac61 // kch thc ca biu thc 16 bit (kch thc ca c)
105
Chng 4. Biu thc
$signed tr v mt gi tr c du
$unsigned tr v mt gi tr khng du
V d 4.21
reg [7:0] regA, regB;
reg signed [7:0] regS;
regA = $unsigned(-4); // regA = 8'b11111100
regB = $unsigned(-4'sd4); // regB = 8'b00001100
regS = $signed (4'b1100); // regS = -4
108
Chng 4. Biu thc
4.7 Nhng php gn v php rt gn
V d 4.22
V d 1:
reg [5:0] a;
reg signed [4:0] b;
initial begin
a = 8'hff; // sau khi gn, a = 6'h3f
b = 8'hff; // sau khi gn, b = 5'h1f
end
V d 2:
reg [0:5] a;
reg signed [0:4] b, c;
initial begin
a = 8'sh8f; // sau khi gn, a = 6'h0f
b = 8'sh8f; // sau khi gn, b = 5'h0f
c = -113; // sau khi gn, c = 15
// 1000_1111 = (-'h71 = -113) b ct ngn cn ('h0F = 15)
end
109
Chng 4. Biu thc
V d 3:
reg [7:0] a;
reg signed [7:0] b;
reg signed [5:0] c, d;
initial begin
a = 8'hff;
c = a; // sau khi gn, c = 6'h3f
b = -113;
d = b; // sau khi gn, d = 6'h0f
end
4.8 Bi tp
6. Cc bc nh gi tr ca mt biu thc?
a = 255; b = 255; c = a + b;
110
Chng 4. Biu thc
c = 9'b0 + a + b;
d={a,b};
c = &b;
111
Chng 5. Cu trc phn cp v module
Chng 5. Cu trc phn cp v module
5.2 Module
C php 5-1
module_declaration ::=
{attribute_instance} module_keyword module_identifier [
module_parameter_port_list ]
list_of_ports ; { module_item }
endmodule
|{ attribute_instance } module_keyword module_identifier [
module_parameter_port_list ]
[ list_of_port_declarations ] ; { non_port_module_item }
endmodule
module_keyword ::= module | macromodule
module_parameter_port_list ::= (From A.1.3
# ( parameter_declaration { , parameter_declaration } )
list_of_ports ::= ( port { , port } )
list_of_port_declarations ::= ( port_declaration { , port_declaration } ) | ( )
port ::= [ port_expression ] | . port_identifier ( [ port_expression ] )
port_expression ::= port_reference | { port_reference { , port_reference } }
port_reference ::= port_identifier [ [ constant_range_expression ] ]
port_declaration ::= {attribute_instance} inout_declaration
| {attribute_instance} input_declaration
| {attribute_instance} output_declaration
module_item ::= (From A.1.4)
port_declaration ;
| non_port_module_item
module_or_generate_item ::=
{ attribute_instance } module_or_generate_item_declaration
| { attribute_instance } local_parameter_declaration ;
113
Chng 5. Cu trc phn cp v module
| { attribute_instance } parameter_override
| { attribute_instance } continuous_assign
| { attribute_instance } gate_instantiation
| { attribute_instance } udp_instantiation
| { attribute_instance } module_instantiation
| { attribute_instance } initial_construct
| { attribute_instance } always_construct
| { attribute_instance } loop_generate_construct
| { attribute_instance } conditional_generate_construct
module_or_generate_item_declaration ::=
net_declaration
| reg_declaration
| integer_declaration
| real_declaration
| time_declaration
| realtime_declaration
| event_declaration
| genvar_declaration
| task_declaration
| function_declaration
non_port_module_item ::=
module_or_generate_item
|generate_region
| specify_block
| { attribute_instance } parameter_declaration ;
| { attribute_instance } specparam_declaration
parameter_override ::= defparam list_of_defparam_assignments ;
114
Chng 5. Cu trc phn cp v module
Khai bo hm v tc v
Khai bo kt thc module (endmodule)
C php 5-2
module_instantiation ::= (From A.4.1)
module_identifier [ parameter_value_assignment ]
module_instance { , module_instance } ;
parameter_value_assignment ::=
# ( list_of_parameter_assignments )
115
Chng 5. Cu trc phn cp v module
list_of_parameter_assignments ::=
ordered_parameter_assignment { , ordered_parameter_assignment }
| named_parameter_assignment { , named_parameter_assignment }
ordered_parameter_assignment ::=
expression
named_parameter_assignment ::=
. parameter_identifier ( [ mintypmax_expression ] )
module_instance ::=
name_of_module_instance ( [ list_of_port_connections ] )
name_of_module_instance ::=
module_instance_identifier [ range ]
list_of_port_connections ::=
ordered_port_connection { , ordered_port_connection }
| named_port_connection { , named_port_connection }
ordered_port_connection ::=
{ attribute_instance } [ expression ]
named_port_connection ::=
{ attribute_instance } . port_identifier ( [ expression ] )
V d 5.2
V d 1: V d ny minh ha mt mch ( module cp thp) c
iu khin bi mt dng sng n gin (module cp cao hn) ni m
mch c ci t bn trong module dng sng:
//module cp thp: module m t mt mch flip-flop nand
module ffnand (q, qbar, preset, clear);
output q, qbar;//khai bo 2 net u ra cho mch
input preset, clear;// khai bo 2 net u vo cho mch
// khai bo cng nand 2 u vo v cc kt ni vi chng
nand g1 (q, qbar, preset),
g2 (qbar, q, clear);
endmodule
// module cp cao:
// dng sng m t cho flip-flop nand
module ffnand_wave;
wire out1, out2;//u ra t mch
reg in1, in2;//bin iu khin mch
parameter d = 10;
// th hin ca mch ffnand, tn l "ff",
// v c t u ra ca cc kt ni IO bn trong
ffnand ff(out1, out2, in1, in2);
// nh ngh dng sng m phng mch
117
Chng 5. Cu trc phn cp v module
initial begin
#d in1 = 0; in2 = 1;
#d in1 = 1;
#d in2 = 0;
#d in2 = 1;
end
endmodule
V d 2: V d ny to ra 2 th hin ca module flip-flop ffnand c
nh ngha trong v d 1. N kt ni ch vi u ra q vo mt th hin v
ch mt u ra qbar vo mt th hin khc.
// dng sng m t kim tra
// nand flip-flop, khng c cng u ra
module ffnand_wave;
reg in1,in2;//bin iu khin mch
parameter d=10;
// to hai bn sao ca mch ff nand
// ff1 c qbar khng kt ni, ff2 c q khng kt ni
ffnand ff1(out1,,in1,in2),
ff2(.qbar(out2), .clear(in2), .preset(in1), .q());
// ff3(.q(out3),.clear(in1),,,); is illegal
// nh ngh dng sng m phng mch
initial begin
#din1=0;in2=1;
#din1=1;
#din2=0;
#din2=1;
end
118
Chng 5. Cu trc phn cp v module
endmodule
C php 5-3
list_of_ports ::= (From A.1.3)
( port { , port } )
list_of_port_declarations ::=
( port_declaration { , port_declaration } )
|()
port ::=
[ port_expression ]
| . port_identifier ( [ port_expression ] )
port_expression ::=
port_reference
| { port_reference { , port_reference } }
port_reference ::=
port_identifier [ [ constant_range_expression ] ]
port_declaration ::=
{attribute_instance} inout_declaration
| {attribute_instance} input_declaration
| {attribute_instance} output_declaration
119
Chng 5. Cu trc phn cp v module
5.2.4.2 Lit k port
Cng tham kho cho mi cng trong danh sch cc cng bn trn
ca mi khai bo module c th l 1 trong s:
Mt nh danh n gin hoc nh danh b b qua.
Mt bit-select ca mt vector khai bo trong module
Mt part- select ca mt vector khai bo trong module
Mt ton t kt ni ca bt k phn no trong 3 phn trn.
Biu thc cng l ty chn bi v cng c th c nh ngha m
khng cn bt k kt ni no trong module. Khi mt cng c nh
ngha, th khng c cng no khc c nh ngha cng tn.
C hai loi cng module, loi u tin ch l cng biu thc, l loi
cng ngm. Loi th hai l loi cng trc tip. iu r rng chi tit cng
nh danh s dng kt ni vi cng ca module th hin bng tn v cng
biu thc bao gm khai bo cc nh danh bn trong module nh miu t
trong phn 5.2.4.3. Tn cng kt ni s khng s dng cho cng ngm nh
nu cng biu thc khng l mt nh danh n gin hoc l nh danh b
b qua, m s s dng tn cng.
Mi cng nh danh trong mt cng biu thc trong danh sch ca cc cng trong
khai bo module cng s khai bo trong thn ca module nh mt trong cc khai
bo: input, output hoc inout (cng hai chiu). c th thm vo khai bo cc
loi d liu khc cho cc cng t th v d reg hoc wire.C php cho vic khai
bo cng a ra trong
120
Chng 5. Cu trc phn cp v module
C php 5-4:
C php 5-4
inout_declaration ::=
inout [ net_type ] [ signed ] [ range ] list_of_port_identifiers
input_declaration ::=
input [ net_type ] [ signed ] [ range ] list_of_port_identifiers
output_declaration ::=
output [ net_type ] [ signed ] [ range ]
list_of_port_identifiers
| output reg [ signed ] [ range ]
list_of_variable_port_identifiers
| output output_variable_type
list_of_variable_port_identifiers
list_of_port_identifiers ::= (From A.2.3)
port_identifier { , port_identifier }
121
Chng 5. Cu trc phn cp v module
5.2.4.4 Lit k khai bo port
V d 5.3
Trong v d sau, module tn Test c a ra trong v d trc c
khai bo li nh sau:
module test (
input [7:0] a,
input signed [7:0] b, c, d,//nhiu cng cng chia s mt
thuc tnh khai bo
output [7:0] e,// mi thuc tnh phi c 1 khai bo.
output reg signed [7:0] f, g,
output signed [7:0] h) ;
// Khng hp l nu c bt k khai bo cng no trong phn
thn module
endmodule
122
Chng 5. Cu trc phn cp v module
Cc loi cng tham chiu ca khai bo cng module s khng hon
thnh s dng cch thc danh sch khai bo cng ca khai bo module.
Cng nh khai bo cng s dng trong danh sch khai bo cng s ch nh
danh n gin hoc nh danh trng. Chng s khng c bit-select, part-
select hoc ton t kt ni (nh trong v d complex_ports) hoc khng c
cc cng phn chia ( trong v d split_ports), hoc khng c tn cng ( nh
trong v d same_port).
Thit k t do c th s dng ln ln cc c php trong khai bo
module, v vy vic m t thc thi trng hp t bit bn trn c th thc
hin s dng c php danh sch cng.
V d 5.4
123
Chng 5. Cu trc phn cp v module
module topmod;
wire [4:0] v;
wire a,b,c,w;
modB b1 (v[0], v[3], w, v[4]);
endmodule
module modB (wa, wb, c, d);
inout wa, wb;
input c, d;
tranif1 g1 (wa, wb, cinvert);
not #(2, 6)n1 (cinvert, int);
and #(6, 5)g2 (int, c, d);
endmodule
V d 5.5
V d 1: Trong v d ny, ci t module kt ni ti tn hiu topA v
topB ti cng In1 v Out nh ngha trong module ALPHA. C mt cng
cung cp bi module ALPHA khng c s dng, tn l In2.C th c
cc cng khng c s dng c cp trong ci t ny.
ALPHA instance1 (.Out(topB),.In1(topA),.In2());
V d 2:
V d ny nh ngha module modB v topmod, v sau topmod
ci t modB s dng kt ni cng theo tn.
module topmod;
wire [4:0] v;
wire a,b,c,w;
modB b1 (.wb(v[3]),.wa(v[0]),.d(v[4]),.c(w));
endmodule
module modB(wa, wb, c, d);
inout wa, wb;
input c, d;
tranif1 g1(wa, wb, cinvert);
not #(6, 2)n1(cinvert, int);
and #(5, 6)g2(int, c, d);
125
Chng 5. Cu trc phn cp v module
endmodule
Bi v kt ni l theo tn nn th t ca cc cng khai bo c th o
v tr.
Nhiu kt ni cng ca th hin module l khng cho php, v d bn
di l khng hp l
V d 3: v d cho thy kt ni cng khng hp l
module test;
a ia (.i (a), .i (b), // khng hp l khi kt ni u ra 2 ln.
.o (c), .o (d), // khng hp l khi kt ni u vo 2 ln.
.e (e), .e (f)); // khng hp l khi kt ni u vo ra 2 ln.
endmodule
V d 5.6
module driver (net_r);
output net_r;
real r;
wire [64:1] net_r = $realtobits(r);
endmodule
module receiver (net_r);
input net_r;
wire [64:1] net_r;
real r;
126
Chng 5. Cu trc phn cp v module
initial assign r = $bitstoreal(net_r);
endmodule
Lut 3:
Nu net hai bn ca cng l loi net uwire, mt cnh bo s xy ra
n net khng gp li vo trong mt net n nh m t trong phn 5.2.4.10
5.3 Bi tp
4. Cc cch kt ni port?
130
Chng 5. Cu trc phn cp v module
5. Nhng quy lut khi kt ni port?
131
Chng 6. M hnh thit k cu trc (Structural model)
Chng 6. M hnh thit k cu trc (Structural model)
132
Chng 6. M hnh thit k cu trc (Structural model)
tr hon c cnh ln v cnh xung. Nu khng c c t tr hon th s
khng c tr hon thng qua cng.
Su cng logic ny c mt u ra v mt hoc nhiu u vo. Tham
s u tin trong danh sch cc tham s s kt ni vi u ra ca cng
logic, cc tham s khc kt ni ti u vo:
Bng s tht ca cc cng ny th hin kt qu ca cng 2 gi tr u
vo:
or 0 1 x z xor 0 1 x z
0 0 1 x x 0 0 1 x x
1 1 1 1 1 1 1 0 x x
x x 1 x x x x x x x
z x 1 x x z x x x x
nor 0 1 x z xnor 0 1 x z
0 1 0 x x 0 1 0 x x
1 0 0 0 0 1 0 1 x x
x x 0 x x x x x x x
z x 0 x x z x x x x
133
Chng 6. M hnh thit k cu trc (Structural model)
Cc phin bn ca su cng logic ny c nhiu hn 2 u vo s m
rng t nhin theo bng trn, nhng s lng u vo nh hng ti tr
hon truyn.
V d 6.1
V d ny khai bo mt cng and 2 u vo:
and a1 (out, in1, in2);
Trong u vo l in1, in2. u ra l out, th hin tn l a1.
134
Chng 6. M hnh thit k cu trc (Structural model)
1 1 1 1
x x x x
x x x x
V d 6.2
135
Chng 6. M hnh thit k cu trc (Structural model)
bao gm hai k hiu biu din cho kt qu khng st nh. K hiu L s ch
ra mt kt qu c gi tr 0 hoc z. Gi tr H ch ra kt qu c gi tr 1 hoc
z. Tr hon trn s chuyn tip ti H hoc L s xem nh ging vi tr hon
chuyn tip ti gi tr x. Bn cng logic ny s c mt u ra v mt u
vo d liu, mt u vo iu khin. Tham s th nht trong danh sch
tham s kt ni vi u ra, tham s th hai kt ni vi u vo, tham s th
ba kt ni vi u vo iu khin.
V d 6.3
V d sau khai bo mt th hin ca cng bufif1:
bufif1 bf1 (outw, inw, controlw);
Trong u ra l outw, u vo l inw, u vo iu khin l
controlw, th hin tn l bf1
136
Chng 6. M hnh thit k cu trc (Structural model)
6.2.4 Cng tc MOS
137
Chng 6. M hnh thit k cu trc (Structural model)
no cho mt trong hai gi tr. Bng logic cho cc cng ny bao gm hai k
hiu biu din cho kt qu khng st nh. K hiu L s ch ra mt kt qu
c gi tr 0 hoc z. Gi tr H ch ra kt qu c gi tr 1 hoc z. Tr hon trn
s chuyn tip ti H hoc L s xem nh ging vi tr hon chuyn tip ti
gi tr x.
Bn cng logic ny s c mt u ra v mt u vo d liu, mt u
vo iu khin. Tham s th nht trong danh sch tham s kt ni vi u
ra, tham s th hai kt ni vi u vo, tham s th ba kt ni vi u vo
iu khin.
Cng tt nmos v pmos s cho qua tn hiu t u vo v thng ti
u ra ca chng vi mt thay i v mnh tn hin tron mt trng
hp, tho lun 7.11. Cng tt rnmos v rpmos s gim mnh tnh hin
truyn qua chng, tho lun trong phn 7.12.
V d 6.4
V d ny khai bo mt cng tc pmos:
pmos p1 (out, data, control);
Trong u ra l out, u vo l data, u iu khin l control v
tn th hin l p1.
138
Chng 6. M hnh thit k cu trc (Structural model)
6.2.5 Cng tc truyn hai chiu
139
Chng 6. M hnh thit k cu trc (Structural model)
Thit b tran, tranif0 v tranif1cho qua tn hiu vi thay i v
mnh ch trong trng hp m t phn 6.11. Thit b rtran, rtranif1,
rtranif0 s lm gim mnh ca tn hiu qua chng theo lut tho lun
trong phn 6.12
V d 6.5
V d sau m t khai bo mt th hin tranif1:
tranif1 t1 (inout1,inout2,control);
Thit b u cui hai chiu l inout1 v inout2, u vo iu khin l
control, tn th hin l t1.
V d 6.6
S tng ng mt cng cmos ghp i t mt cng cmos v mt
cng pmos c a ra trong v d sau:
cmos (w, datain, ncontrol, pcontrol);
tng ng vi
nmos (w, datain, ncontrol);
pmos (w, datain, pcontrol);
141
Chng 6. M hnh thit k cu trc (Structural model)
6.2.7 Ngun pullup v pulldown
V d 6.7
V d khai bo hai th hin ngun pullup:
pullup (strong1) p1 (neta), p2 (netb);
Trong v d ny, th hin p1 iu khin neta v th hin p2 iu
khin netb vi mnh strong
143
Chng 6. M hnh thit k cu trc (Structural model)
large1 4
pull1 5
strong1 6
supply1 7
144
Chng 6. M hnh thit k cu trc (Structural model)
6.2.9 mnh v gi tr ca nhng tn hiu kt hp
145
Chng 6. M hnh thit k cu trc (Structural model)
146
Chng 6. M hnh thit k cu trc (Structural model)
V d:
Trong Hnh 6.4 ch ra mt t hp ca tn hiu weak vi gi tr 1 v
tn hiu weak vi gi tr 0 cho ra mt tn hiu c mnh weak v c gi
tr l x.
Hnh 6.4 Hai tn hiu c mnh bng nhau cng iu khin mt net
147
Chng 6. M hnh thit k cu trc (Structural model)
u ra ca bufif1 trong Hnh 6.6l mt strong H, dy gi tr u ra
c m t trong Hnh 6.7.
strength0 strength1
7 6 5 4 3 2 1 0 0 1 2 3 4 5 6 7
Su0 St0 Pu0 La0 We0 Me0 Sm0 HiZ0 HiZ1 Sm1 Me1 We1 La1 Pu1 St1 Su1
148
Chng 6. M hnh thit k cu trc (Structural model)
Kt qu l mt gi tr x bi v phm vi ca n gm gi tr 1 v 0. S
3 5, i trc gi tr x, l t hp ca hai s. S th nht l s 3, tng ng
vi mc strength0 cao nht cho kt qu. S th hai l 5, tng ng vi
cp strength1 cao nht cho kt qu.
Mng chuyn mch c th to ra mt phm vi mnh ca cc gi
tr ging nhau, nh l tnh hiu ca mt cu hnh t cao xung thp nh
Hnh 6.11.
149
Chng 6. M hnh thit k cu trc (Structural model)
strength0 strength1
150
Chng 6. M hnh thit k cu trc (Structural model)
7 6 5 4 3 2 1 0 0 1 2 3 4 5 6 7
Su0 St0 Pu0 La0 We0 Me0 Sm0 HiZ0 HiZ1 Sm1 Me1 We1 La1 Pu1 St1 Su1
Khi tn hiu ca cu hnh t cao xung thp trong Hnh 6.11 t hp,
kt qu l mt gi tr khng xc nh vi phm vi (56x) xc nh bi gi tr
u v cui l hai tn hiu trong Hnh 6.14.
strength0 strength1
7 6 5 4 3 2 1 0 0 1 2 3 4 5 6 7
Su0 St0 Pu0 La0 We0 Me0 Sm0 HiZ0 HiZ1 Sm1 Me1 We1 La1 Pu1 St1 Su1
151
Chng 6. M hnh thit k cu trc (Structural model)
Cng logic to ra kt qu vi mnh khng r rng cng ging nh
iu khin ba trng thi. Nh trong trng hp trong Hnh 6.16. Cng
andN1 khai bo vi mnh highz0, v N2 khai bo vi mnh weak0.
152
Chng 6. M hnh thit k cu trc (Structural model)
strength0 strength1
7 6 5 4 3 2 1 0 0 1 2 3 4 5 6 7
Su0 St0 Pu0 La0 We0 Me0 Sm0 HiZ0 HiZ1 Sm1 Me1 We1 La1 Pu1 St1 Su1
strength0 strength1
7 6 5 4 3 2 1 0 0 1 2 3 4 5 6 7
Su0 St0 Pu0 La0 We0 Me0 Sm0 HiZ0 HiZ1 Sm1 Me1 We1 La1 Pu1 St1 Su1
154
Chng 6. M hnh thit k cu trc (Structural model)
7 6 5 4 3 2 1 0 0 1 2 3 4 5 6 7
Su0 St0 Pu0 La0 We0 Me0 Sm0 HiZ0 HiZ1 Sm1 Me1 We1 La1 Pu1 St1 Su1
strength0 strength1
7 6 5 4 3 2 1 0 0 1 2 3 4 5 6 7
Su0 St0 Pu0 La0 We0 Me0 Sm0 HiZ0 HiZ1 Sm1 Me1 We1 La1 Pu1 St1 Su1
strength0 strength1
7 6 5 4 3 2 1 0 0 1 2 3 4 5 6 7
Su0 St0 Pu0 La0 We0 Me0 Sm0 HiZ0 HiZ1 Sm1 Me1 We1 La1 Pu1 St1 Su1
155
Chng 6. M hnh thit k cu trc (Structural model)
7 6 5 4 3 2 1 0 0 1 2 3 4 5 6 7
Su0 St0 Pu0 La0 We0 Me0 Sm0 HiZ0 HiZ1 Sm1 Me1 We1 La1 Pu1 St1 Su1
strength0 strength1
7 6 5 4 3 2 1 0 0 1 2 3 4 5 6 7
Su0 St0 Pu0 La0 We0 Me0 Sm0 HiZ0 HiZ1 Sm1 Me1 We1 La1 Pu1 St1 Su1
strength0 strength1
7 6 5 4 3 2 1 0 0 1 2 3 4 5 6 7
Su0 St0 Pu0 La0 We0 Me0 Sm0 HiZ0 HiZ1 Sm1 Me1 We1 La1 Pu1 St1 Su1
156
Chng 6. M hnh thit k cu trc (Structural model)
T hp ca hai tn hiu bn trn cho ra tn hiu kt qu bn di:
strength0 strength1
7 6 5 4 3 2 1 0 0 1 2 3 4 5 6 7
Su0 St0 Pu0 La0 We0 Me0 Sm0 HiZ0 HiZ1 Sm1 Me1 We1 La1 Pu1 St1 Su1
Cc loi net triand, wand, trior v wor s gii quyt xung t khi c
nhiu iu khin c cng mt mnh. Loi net s gii quyt gi tr tn
hiu bng cch xem tn hiu nh u vo ca hm logic.
V d:
Xem xt t hp ca hai tn hiu c mnh r rng trong Hnh 6.24.
strength0 strength1
7 6 5 4 3 2 1 0 0 1 2 3 4 5 6 7
Su0 St0 Pu0 La0 We0 Me0 Sm0 HiZ0 HiZ1 Sm1 Me1 We1 La1 Pu1 St1 Su1
strength0 strength1
7 6 5 4 3 2 1 0 0 1 2 3 4 5 6 7
Su0 St0 Pu0 La0 We0 Me0 Sm0 HiZ0 HiZ1 Sm1 Me1 We1 La1 Pu1 St1 Su1
Signal1
strength0 strength1
7 6 5 4 3 2 1 0 0 1 2 3 4 5 6 7
Su0 St0 Pu0 La0 We0 Me0 Sm0 HiZ0 HiZ1 Sm1 Me1 We1 La1 Pu1 St1 Su1
Signal2
Kt qu ca tn hiu:
strength0 strength1
7 6 5 4 3 2 1 0 0 1 2 3 4 5 6 7
Su0 St0 Pu0 La0 We0 Me0 Sm0 HiZ0 HiZ1 Sm1 Me1 We1 La1 Pu1 St1 Su1
158
Chng 6. M hnh thit k cu trc (Structural model)
Signal1 Signal2 Kt qu
mnh Gi tr mnh Gi tr mnh Gi tr
5 0 5 1 5 1
6 0 5 1 6 0
Kt qu ca tn hiu:
strength0 strength1
7 6 5 4 3 2 1 0 0 1 2 3 4 5 6 7
Su0 St0 Pu0 La0 We0 Me0 Sm0 HiZ0 HiZ1 Sm1 Me1 We1 La1 Pu1 St1 Su1
159
Chng 6. M hnh thit k cu trc (Structural model)
Pulldrive Weak drive
Largecapacitor Mediumcapacitor
Weak drive Mediumcapacitor
Mediumcapacitor Smallcapacitor
Smallcapacitor Smallcapacitor
Highimpedance Highimpedance
160
Chng 6. M hnh thit k cu trc (Structural model)
6.2.12.3 mnh ca net supply0, supply1
V d 6.8
V d 1: V d ny c t mt, hai v ba tr hon:
and #(10) a1 (out, in1, in2);// ch c mt tr hon
and #(10,12) a2 (out, in1, in2);// tr hon cnh ln v cnh xung
bufif0 #(10,12,11) b3 (out, in, ctrl);// tr hon cnh ln, cnh xung,
v tt
162
Chng 6. M hnh thit k cu trc (Structural model)
V d 2: V d ny c t mt module mch lt n gin vi ba
trng thi u ra, ni tr hon ring c a ra cho tng cng. Tr hon
truyn t u vo ti u ra ca mt module s c tch ly, v n ph
thuc vo phn tn hiu i qua mng.
module tri_latch (qout, nqout, clock, data, enable);
output qout, nqout;
input clock, data, enable;
tri qout, nqout;
not #5 n1 (ndata,data);
nand #(3,5) n2 (wa,data,clock),
n3 (wb,ndata,clock);
nand #(12,15) n4 (q,nq,wa),
n5 (nq,q,wb);
bufif1 #(3,7,13) q_drive(qout,q,enable),
nq_drive(nqout,nq,enable);
endmodule
C php cho tr hon trn mt cng nguyn thy (bao gm UPD), net
v lnh gn lin tc s cho php ba gi tr tr hon cho cnh ln, cnh
xung v tc. Gi tr ti a, trung bnh v ti thiu ca mi gi tr tr hon
s c t nh l cc biu thc cch nhau bi du hai chm (:). Chng khng
yu cu qua h (v d: min<=typ<=max) gia cc biu thc tr hon ti
thiu, trung bnh v ti a. c th l ba biu thc bt k.
V d 6.9
module iobuf (io1, io2, dir);
...
bufif0 #(5:7:9, 8:10:12, 15:18:21) b1 (io1, io2, dir);
bufif1 #(6:8:10, 5:7:9, 13:17:19) b2 (io2, io1, dir);
...
endmodule
C php tr hon iu khin trong lnh th tc (9.7) cng cho php
cc gi tr ti thiu, trung bnh v ti a. l cc c t bi cc biu thc
ngn cch bi du hai chm (:). V d 6.10 minh ho l thuyt ny:
V d 6.10
parameter min_hi = 97, typ_hi = 100, max_hi = 107;
reg clk;
always begin
#(95:100:105) clk = 1;
#(min_hi:typ_hi:max_hi) clk = 0;
end
164
Chng 6. M hnh thit k cu trc (Structural model)
Mt net trireg khng cn c t tr hon tc v net trireg khng bao
gi thc hin chuyn tip ti trng thi logic z. Khi iu khin ca mt net
trireg thc hin chuyn tip t trng thi logic 1, 0, hoc x ti tc, net
trireg s nh li trng thi logic 1, 0 hoc x trc khi m iu khin cn
m. Gi tr z s khng truyn t iu khin ca mt net trireg ti mt trireg.
Mt net trireg c th ch gi mt trng thi logic x khi x l trng thi logic
khi u ca net trireg hoc khi net trireg b p buc sang trng thi z khi
s dng cu lnh force ( trong phn 9.3.2).
Mt c t tr hon cho phn r in tch mt hnh mt nt lu tr
np khng l l tng, v d mt nt lu tr np s np dng r ra ngoi
thng qua thit b xung quanh v cc kt ni.
Cc qu trnh phn r in tch v c t tr hon cho phn r in
tch c m t trong phn 6.2.15.1 v 6.2.15.2.
165
Chng 6. M hnh thit k cu trc (Structural model)
6.2.15.2 c t tr hon ca thi gian phn r in tch
V d 6.11
V d 1:
V d sau m t mt c t ca thi gian phn r in tch trong mt
khai bo net trireg:
trireg (large) #(0,0,50) cap1;
V d ny khai bo mt net trireg tn cap1. Net trireg ny lu tr
mt in tch large. c t tr hon cho cnh tng l 0, cho tr hon cnh
gim l 0, v thi gian phn r in tch l 50 n v thi gian.
V d 2:
V d tip theo trnh din mt file ngun m t bao gm mt khai
bo net trireg vi mt c t thi gian phn r in tch. Hnh 6-26 th hin
thi s mch ca ngun m t:
module capacitor;
reg data, gate;
// khai bo trireg vi thi gian phn r in tch l 50 n v.
trireg (large) #(0,0,50) cap1;
nmos nmos1 (cap1, data, gate); // nmos iu khin trireg
initial begin
$monitor("%0d data=%v gate=%v cap1=%v", $time,
166
Chng 6. M hnh thit k cu trc (Structural model)
data, gate, cap1);
data = 1;
// Cht iu khin u vo bng cng tc nmos
gate = 1;
#10 gate = 0;
#30 gate = 1;
#10 gate = 0;
#100 $finish;
end
endmodule
C php 6-1
udp_declaration ::=
{ attribute_instance } primitive udp_identifier ( udp_port_list ) ;
udp_port_declaration { udp_port_declaration }
udp_body
endprimitive
| { attribute_instance } primitive udp_identifier (
udp_declaration_port_list ) ;
udp_body
168
Chng 6. M hnh thit k cu trc (Structural model)
endprimitive
udp_port_list ::= (From A.5.2)
output_port_identifier , input_port_identifier{, input_port_identifier}
udp_declaration_port_list ::=
udp_output_declaration, udp_input_declaration{,
dp_input_declaration }
udp_port_declaration ::=
udp_output_declaration ;
| udp_input_declaration ;
| udp_reg_declaration ;
udp_output_declaration ::=
{ attribute_instance } output port_identifier
| { attribute_instance } output reg port_identifier [ =
constant_expression ]
udp_input_declaration ::=
{ attribute_instance } input list_of_port_identifiers
udp_reg_declaration ::=
{ attribute_instance } reg variable_identifier
udp_body ::= (From A.5.3)
combinational_body | sequential_body
combinational_body ::=
table combinational_entry { combinational_entry } endtable
combinational_entry ::=
level_input_list : output_symbol ;
sequential_body ::=
[ udp_initial_statement ] table sequential_entry { sequential_entry }
endtable
udp_initial_statement ::=
initial output_port_identifier = init_val ;
init_val ::= 1'b0 | 1'b1 | 1'bx | 1'bX | 1'B0 | 1'B1 | 1'Bx | 1'BX | 1 | 0
sequential_entry ::=
seq_input_list : current_state : next_state ;
seq_input_list ::=
level_input_list | edge_input_list
level_input_list ::=
level_symbol { level_symbol }
edge_input_list ::=
{ level_symbol } edge_indicator { level_symbol }
edge_indicator ::=
( level_symbol level_symbol ) | edge_symbol
current_state ::= level_symbol
169
Chng 6. M hnh thit k cu trc (Structural model)
next_state ::=output_symbol | -
output_symbol ::= 0 | 1 | x | X
level_symbol ::= 0 | 1 | x | X | ? | b | B
edge_symbol ::= r | R | f | F | p | P | n | N | *
170
Chng 6. M hnh thit k cu trc (Structural model)
UDPs tun t bao gm khai bo mt reg cho cng u ra thm vo
khai bo u ra, khi khai bo UDP s dng cch khai bo th nht ca tiu
UDP hoc nh phn khai bo u ra. UDPs t hp khng bao gm khai
bo reg. Gi tr ban u ca u ra c th c t bi cu ln initial trong
UDP tun t (6.3.1.3)
Qu trnh thc thi c th gii hn s u vo ca UDP, nh chng
cho php t nht 9 u vo cho UDP tun t v 10 u vo cho UDP t hp.
171
Chng 6. M hnh thit k cu trc (Structural model)
UDPs t hp c mt trng trn u vo v mt trng cho u ra.
Trng u vo ngn cch vi u ra bi u hai chm (:). Mi dng nh
ngha u ra cho mt t hp t bit cc gi tr u vo.
UDPs tun t c thm vo mt trng gia trng u vo v u ra.
l trng th hin trng thi hin ti ca UDP v tng ng vi gi tr
u ra hin ti. N gii hn bi du hai chm (:). Mi dng nh ngha u
ra da trn trng thi hin ti, t hp chi tit ca cc gi tr u vo, v mt
chuyn tip gi tr hin ti ti u vo. Mt dng nh m t bn di l
khng hp l:
(01) (10) 0 : 0 : 1 ;
Nu tt c cc gi tr u vo l x, th trng thi u ra s l x.
Khng cn thit c t r rng mi t hp u vo c th. Khi tt
c t hp cc gi tr u vo l khng c t r rng kt qu mc nh cho
u ra l x.
Khng hp l nu t hp ca u vo ging nhau, bao gm c cnh
c t cho u vo khc.
172
Chng 6. M hnh thit k cu trc (Structural model)
K hiu Gii thch Ghi ch
0 Logic 0
1 Logic 1
x Khng xc nh Cho php trong cc trng u vo v
u ra ca tt c UDPs v trng trng
thi hin ti trong UDPs tun t
? Lp li cc gi tr 0,1 Khng cho php trong trng u ra
v x
b Lp li cc gi tr 0,1 Cho php trong cc trng u vo ca
tt c UDPs v trng trng thi hin ti
trong UDPs tun t. Khng cho php
trong trng u ra
- Khng thay i Ch cho php trong trng u ra ca
UDPs tun t.
(vw) Gi tr thay i t v v v w c th l mt gi tr bt k trong
ti w 0, 1, x, ?, b v ch cho php trong
trng u vo.
* Nh (??) Bt k thay i no trong u vo
r Nh (01) Cnh tng ca u vo
f Nh (10) Cnh gim ca u vo
p Lp li cc gi tr Cnh dng ca in th u vo
(01), (0x) v (x1)
n Lp li cc gi tr Cnh m ca in th u vo
(01), (0x) v (x0)
173
Chng 6. M hnh thit k cu trc (Structural model)
6.3.2 UDP t hp
V d 6.12
primitive multiplexer (mux, control, dataA, dataB);
output mux;
input control, dataA, dataB;
table
// bng iu khin mux dataA dataB
01 0 : 1 ;
01 1 : 1 ;
01 x : 1 ;
00 0 : 0 ;
00 1 : 0 ;
00 x : 0 ;
10 1 : 1 ;
11 1 : 1 ;
174
Chng 6. M hnh thit k cu trc (Structural model)
1x 1 : 1 ;
10 0 : 0 ;
11 0 : 0 ;
1x 0 : 0 ;
x0 0 : 0 ;
x1 1 : 1 ;
endtable
endprimitive
V d 6.13
primitive multiplexer (mux, control, dataA, dataB);
output mux;
input control, dataA, dataB;
table
//bng iu khin mux dataA dataB
01?:1 ;// ? = 0 1 x
00?:0 ;
1?1:1 ;
1?0:0 ;
175
Chng 6. M hnh thit k cu trc (Structural model)
x00:0 ;
x11:1 ;
endtable
endprimitive
V d 6.14
primitive latch (q, clock, data);
output q; reg q;
input clock, data;
table
// clock data q q+
01 : ? : 1 ;
00 : ? : 0 ;
1? : ? : - ;// - = khng thay i
endtable
endprimitive
176
Chng 6. M hnh thit k cu trc (Structural model)
cho trng thi hiu ti, c thm vo phn cch vi u vo v u ra
bng du hai chm.
V d 6.15
primitive d_edge_ff (q, clock, data);
output q; reg q;
input clock, data;
table
// clock dataqq+
// u ra thu c trn cnh tng ca clock
(01) 0:?:0;
177
Chng 6. M hnh thit k cu trc (Structural model)
(01) 1:?:1;
(0?) 1:1:1;
(0?) 0:0:0;
// b qua cnh m ca lock
(?0) ?:?:-;
// b qua s thay i d liu khi clock khng thay i
?(??):?:-;
endtable
endprimitive
V d 6.16
primitive jk_edge_ff (q, clock, j, k, preset, clear);
output q; reg q;
input clock, j, k, preset, clear;
178
Chng 6. M hnh thit k cu trc (Structural model)
table
// clockjkpcstate output/next state
???01: ? : 1 ; // preset logic
???*1: 1 : 1 ;
???10: ? : 0 ; // clear logic
???1*: 0 : 0 ;
r0000: 0 : 1 ; // normal clockingcases
r0011: ? : - ;
r0111: ? : 0 ;
r1011: ? : 1 ;
r1111: 0 : 1 ;
r1111: 1 : 0 ;
f????: ? : - ;
b*???: ? : - ; // chuyn tip j v k
b?*??: ? : - ;
endtable
endprimitive
179
Chng 6. M hnh thit k cu trc (Structural model)
u ra. Hai mu cui cng ch ra chuyn tip trong u vo j v k khng
thay i u ra khi ng h n nh mc thp hoc cao.
C php 6-2
udp_instantiation ::=
udp_identifier [ drive_strength ] [ delay2 ]
udp_instance { , udp_instance } ;
udp_instance ::=
[ name_of_udp_instance ] ( output_terminal , input_terminal
{ , input_terminal } )
name_of_udp_instance ::=
udp_instance_identifier [ range ]
V d 6.17
module flip;
reg clock, data;
parameter p1 = 10;
parameter p2 = 33;
parameter p3 = 12;
180
Chng 6. M hnh thit k cu trc (Structural model)
d_edge_ff #p3 d_inst (q, clock, data);
initial begin
data = 1;
clock = 1;
#(20 * p1) $finish;
end
always #p1 clock = ~clock;
always #p2 data = ~data;
endmodule
trc
6.4.1 M t mch t hp
182
Chng 6. M hnh thit k cu trc (Structural model)
V d 6.21 M t mch encoder8-3
module encoder8_3( A , D );
output[2:0] A;
input[7:0] D;
or( A[0], D[1], D[3], D[5], D[7] );
or( A[1], D[2], D[3], D[6], D[7] );
or( A[2], D[4], D[5], D[6], D[7] );
endmodule
184
Chng 6. M hnh thit k cu trc (Structural model)
endmodule
V d 6.28 M t b m 4 bit
6.5 Bi tp
186
Chng 6. M hnh thit k cu trc (Structural model)
5. Nu cc t t tr hon cng v net?
187
Chng 7. M hnh thit k hnh vi (Behavioral model)
Chng 7. M hnh thit k hnh vi (Behavioral model)
188
Chng 7. M hnh thit k hnh vi (Behavioral model)
logic iu khin net. Hay ni cch khc, php gn ni tip iu khin net
theo nh cch m cc cng linh kin iu khin net, trong biu thc bn
phi php gn c th c xem nh l mt mch t hp iu khin net
mt cch lin tc.
V d 7.1
assign m = 1b1;
assign a = b & c;
assign #10 a = 1bz;
V d 7.2
wire (strong1, pull0) mynet = enable ; //khai bo v gn
wire a = b & c; //khai bo v gn
189
Chng 7. M hnh thit k hnh vi (Behavioral model)
thc pha phi ca php gn thay i th ton b gi tr cc net bn tri
php gn s cp nht ngay li gi tr. Nu gi tr mi khc vi gi tr trc
th gi tr mi s c gn vo net bn tri php gn.
V d 7.3
wire a; //khai bo
parameter Zee = 1'bz;
assign a = Zee; //gn 1
assign a = b & c; //gn 2
Nhng dng hp l ca biu thc bn tri ca php gn ni tip phi
l loi d liu net:
Net (c th l net n scalar hoc mt mng cc net net
vector)
Bit bt k c chn trong net vector
Mt phn cc bit bt k c chn trong net vector
Mt phn cc bit bt k c ch s (index) c chn trong net
vector.
Biu thc ni {} gia cc biu thc hp l trn.
V d 7.4
module adder (sum_out, carry_out, carry_in, ina, inb);
output [3:0] sum_out;
output carry_out;
input [3:0] ina, inb;
input carry_in;
wire carry_out, carry_in;
wire [3:0] sum_out, ina, inb;
assign {carry_out, sum_out} = ina + inb + carry_in;
endmodule
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Chng 7. M hnh thit k hnh vi (Behavioral model)
Trong v d trn, php gn ni tip c s dng m hnh mt
mch cng 4 bit c nh. y ta khng th dng php gn ni tip khi
khai bo net bi v ta s dng cc net ny trong php ni {} pha bn tri
php gn.
V d 7.5
module select_bus(busout, bus0, bus1, bus2, bus3, enable, s);
parameter n = 16;
parameter Zee = 16'bz;
output [1:n] busout;
input [1:n] bus0, bus1, bus2, bus3;
input enable;
input [1:2] s;
tri [1:n] data; // khai bo net
// khai bo net vi php gn ni tip
tri [1:n] busout = enable ? data : Zee;
// pht biu vi 4 php gn ni tip
assign
data = (s == 0) ? bus0 : Zee,
data = (s == 1) ? bus1 : Zee,
data = (s == 2) ? bus2 : Zee,
data = (s == 3) ? bus3 : Zee;
endmodule
191
Chng 7. M hnh thit k hnh vi (Behavioral model)
7.2.4 To tr hon (delay) cho php gn
192
Chng 7. M hnh thit k hnh vi (Behavioral model)
C php ny c gi l m t tr hon ca net, c ngha l bt k
s thay i gi tr no t biu thc bn phi php gn m c cung cp
n wireA u s b tr hon trong 10 n v thi gian trc khi php gn
c hiu lc. Nh vy trong v d trn, c hai php gn u i 10 n v
thi gian sau th gi tr bn phi php gn mi c cp nht cho net
wireA.
Cn i vi php gn ni tip c m t ngay trong khai bo net th
tr hon l mt phn ca php gn ni tip ch khng phi l tr hon
ca net, do n s khng phi l tr hon ca cc php gn khc trn
net . Hn na, nu bn tri php gn l mt mng cc net (vector net) th
thi gian tr hon ln, thi gian tr hon xung s khng c cung cp n
nhng bit ring l nu php gn nm ngay trong phn khai bo net.
wire #10 wireA = 1bz;
Trong trng hp m mt ton hng bn phi php gn thay i
trc khi s thay i ca gi tr trc c thi gian truyn n net
bn tri php gn th nhng bc sau s din ra.
Gi tr ca biu thc bn phi php gn c tnh.
Nu gi tr c tnh khc vi gi tr ang truyn n net
bn tri php gn th gi tr ang truyn ny s hy.
Nu gi tr c tnh bng vi gi tr ang truyn n net
bn tri php gn th gi tr ang truyn vn c tip tc.
(procedural assignment)
V d 7.6
module behave;
reg [1:0] a, b;
initial begin
a = b1;
b = b0;
end
always begin
#50 a = ~a;
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Chng 7. M hnh thit k hnh vi (Behavioral model)
end
always begin
#100 b = ~b;
end
endmodule
V d 7.7
V d a: Khai bo mt bin thanh ghi 4 bit v gn gi tr gi tr cho
n l 4.
reg[3:0] a = 4h4;
Php gn khai bo bin trn tng ng vi :
198
Chng 7. M hnh thit k hnh vi (Behavioral model)
reg[3:0] a;
initial a = 4h4;
V d b: Php gn sau l khng c php
reg[3:0] array [3:0] = 0;
V d c: Khai bo hai bin c kiu d liu bin l integer, bin u
c gn gi tr 0.
integer i =0, j;
V d d: Khai bo hai bin c kiu d liu bin l s thc real, gn
gi tr ln lt l 2.5 v 3,000,000.
real r1 = 2.5, n300k = 3E6;
V d e: Khai bo mt bin c kiu d liu bin l time, mt c kiu
d liu bin l realtime vi gi tr khi to
time t1 = 25;
realtime rt1 = 2.5;
V d 7.8
rega = 0;
rega[3] = 1; // gn ti a bit
rega[3:5] = 7; // gn ti mt phn ca mng
mema[address] = 8hff; // php gn n mt phn t nh.
{carry, acc} = rega + regb; // gn n mt php ni (concatenation)
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Chng 7. M hnh thit k hnh vi (Behavioral model)
reg f;
always @(sel or b or c)
if (sel == 1)
f= b;
else
f = c;
endmodule
V d 7.10
module mux (f, g, a, b, c);
output f, g;
input a, b, c;
reg f;
always @(a or b or c)
if (a == 1)
f= b;
else
g = c;
endmodule
201
Chng 7. M hnh thit k hnh vi (Behavioral model)
Trong V d 7.10, iu kin 1 c p ng tuy nhin iu kin 2
khng c p ng, trong lung iu khin u tin (a==1) ch c output f
c gn, vy output g khng c gi tr xc nh, tip n lung iu khin
k tip (a==0) ch c output g c gn, vy output f khng c gi tr xc
nh. Nh vy y khng th l mt m t thit k cho mch t hp bi v
trong mch t hp khi tn hiu input xc nh th tt c cc gi tr output
cng phi xc nh.
Trong V d 7.11:
203
Chng 7. M hnh thit k hnh vi (Behavioral model)
Bc 1: Trnh m phng xc nh cc gi tr ca biu thc bn phi
ca tt c cc php gn qui trnh h trong khi sequential block (begin-end)
v ch chun b thc thi php gn gi tr va xc nh khi c cnh ln xung
clock. Nh vy ti bc ny a vn mang gi tr 0, b vn mang gi tr 1.
Bc 2: Ti cnh ln xung clock, trnh m phng s gn cc gi tr
c xc nh sn trong bc 1 vo bn tri cc php gn mt cch
ng thi. Nh vy, sau bc ny, a c gn gi tr mi t b c sn trc
l 1 cn b c gn gi tr mi t a c sn trc l 0.
V d 7.12 So snh php gn qui trnh kn v qui trnh h trong vic khi to gi
tr.
//non_block1.v
module non_block1;
reg a, b, c, d, e, f;
//php gn kn
initial begin
a = #10 1; // a s c gn = 1 ti t = 10
b = #2 0; // b s c gn = 0 ti t = 12
c = #4 1; // c s c gn = 1 ti t = 16
end
//php gn h
initial begin
d <= #10 1; // d s c gn = 1 ti t = 10
e <= #2 0; // e s c gn = 0 ti t = 2
f <= #4 1; // f s c gn = 1 ti t = 4
end
endmodule
204
Chng 7. M hnh thit k hnh vi (Behavioral model)
Ta thy rng, khi s dng php gn qui trnh h, do tt c php gn
ch c thc thi ng thi ti bc 2 do th t ca cc php gn qui
trnh h khng quan trong.
V d 7.13 So snh php gn qui trnh kn v qui trnh h trong m t mch tun
t.
V d 3: Blocking assignments
rega
always @(posedge clk) begin D-FF
rega = data ;
regb = rega ; data regb
end D-FF
clk
Blocking assignments
always @(posedge clk) begin
rega
regb = rega ;
data regb
rega = data ; D-FF D-FF
clk
end
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Chng 7. M hnh thit k hnh vi (Behavioral model)
Non-blocking assignments
always @(posedge clk) begin rega
regb <= rega ; data regb
rega <= data ; D-FF D-FF
clk
end
Trong php gn qui trinh h, th th t gia cc php gn s khng
nh hng n kt qu synthesis ca phn cng to ra, do trong php gn
qui trinh h cc php gn c thc thi mt cch ng thi.
V d 7.14
//non_block1.v
module non_block1;
reg a, b;
initial begin
a = 0;
b = 1;
a <= b;
b <= a;
end
initial begin
$monitor ($time, ,"a = %b b = %b", a, b);
#100 $finish;
end
endmodule
Gi tr cui cng ca php gn : a = 1; b =0
206
Chng 7. M hnh thit k hnh vi (Behavioral model)
7.3.3.1 Mch tun t vi php gn qui trnh h
in A B C
D-FF D-FF D-FF
clk
207
Chng 7. M hnh thit k hnh vi (Behavioral model)
module fsm (Q1, Q2, in, clock);
output Q1, Q2;
input clock, in;
reg Q1, Q2;
always @posedge clock) begin
Q1 <= in & Q0;
Q0 <= in | Q1;
end
endmodule
C php
conditional_statement ::=
if ( expression ) statement_or_null [ else statement_or_null ]
statement_or_null ::= statement | ;
208
Chng 7. M hnh thit k hnh vi (Behavioral model)
V d 7.17 Ba pht biu s m t cng mt logic
if (expression)
if (expression !=0)
if (expression == 1)
Bi v phn else trong pht biu if-else l ty chn, c th c hoc
khng nu khng cn thit nn c th gy hiu lm khi phn else b b i
trong cc pht biu m cc mnh if lin tip nhau. khng b bi ri
trong suy ngh ta cn nh rng phn else lun l mt phn ca mnh if
gn nht vi n. Ta xem xt 3 v d sau:
V d 7.18
if (index > 0)
if (rega > regb)
result = rega;
else
result = regb;
V d 7.19
if (index > 0)
if (rega > regb)
result = rega;
else
result = regb;
209
Chng 7. M hnh thit k hnh vi (Behavioral model)
Vi cch m t r rng nh trn th s hn ch c nhng hiu lm
trong thit k.
kim sot cht ch hn, khi m t ta nn thm begin-end block
vo pht biu if-else.
V d 7.20
if (index > 0)
begin
if (rega > regb)
result = rega;
end
else result = regb;
C php
if_else_if_statement ::=
if (expression) statement_or_null
{ else if (expression) statement_or_null }
else statement
210
Chng 7. M hnh thit k hnh vi (Behavioral model)
n s thot ra khi chui pht biu. Mi pht biu c th l mt pht
biu n hay mt khi cc pht biu nm trong begin-end block.
Phn pht biu else cui cng trong cu trc if-else-if s c thc
thi khi m khng c iu kin no p ng c cc iu kin trn n.
Phn else thng c s dng to ra cc gi tr mc nh, hoc dng
trong qu trnh kim tra li.
Trong m t thit k sau s dng pht biu if-else kim tra bin
index a ra quyt nh xem mt trong ba bin thanh ghi modify_segn
c phi c cng vo a ch nh hay khng, v vic tng ny phi c
cng vo bin thanh ghi index. Mi dng u tin khai bo bin thanh ghi
v cc tham s.
V d 7.21
// khai bo kiu d liu bin v khai bo tham s
reg [31:0] instruction, segment_area[255:0];
reg [7:0] index;
reg [5:0] modify_seg1, modify_seg2, modify_seg3;
parameter segment1 = 0, inc_seg1 = 1, segment2 = 20, inc_seg2 =
2, segment3 = 64, inc_seg3 = 4, data = 128;
// kim tra ch s bin
if (index < segment2) begin
instruction = segment_area [index + modify_seg1];
index = index + inc_seg1;
end
else if (index < segment3) begin
instruction = segment_area [index + modify_seg2];
index = index + inc_seg2;
end
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Chng 7. M hnh thit k hnh vi (Behavioral model)
else if (index < data) begin
instruction = segment_area [index + modify_seg3];
index = index + inc_seg3;
end
else
instruction = segment_area [index];
Pht biu case l pht biu to ra nhiu s la chn, n kim tra xem
mt biu thc c ph hp vi mt biu thc khc hay khng. C php ca
pht biu case nh sau:
C php
case_statement ::=
| case ( expression ) case_item { case_item } endcase
| casez ( expression ) case_item { case_item } endcase
| casex ( expression ) case_item { case_item } endcase
case_item ::=
expression { , expression } : statement_or_null
| default [ : ] statement_or_null
V d 7.22
reg [15:0] rega;
reg [9:0] result;
212
Chng 7. M hnh thit k hnh vi (Behavioral model)
case (rega)
16d0: result = 10b0111111111;
16d1: result = 10b1011111111;
16d2: result = 10b1101111111;
16d3: result = 10b1110111111;
16d4: result = 10b1111011111;
16d5: result = 10b1111101111;
16d6: result = 10b1111110111;
16d7: result = 10b1111111011;
16d8: result = 10b1111111101;
16d9: result = 10b1111111110;
default result = bx;
endcase
Nhng biu thc trong case item s c tnh ton v so snh theo
th t m chng c cho. Theo th t t trn xung, nu mt trong cc
biu thc trong case item ph hp vi biu thc trong du ngoc n () ca
case th pht biu m kt hp vi case item s c thc thi. Nu tt c
cc so snh u khng ng th pht biu m kt hp vi default item s
c thc thi. Nu default item khng c m t trong pht biu case v
tt c cc so snh u khng ng th khng c bt k pht biu no c
thc thi.
Khc c php, pht biu case khc vi cu trc if-else-if hai im
quan trng sau:
Biu thc c iu kin trong if-else-if ph bin hn vic so
snh biu thc vi nhiu biu thc khc trong pht biu case.
Pht biu case cung cp mt kt qu r rng khi biu thc c
gi tr l x hoc z.
213
Chng 7. M hnh thit k hnh vi (Behavioral model)
Trong vic so snh biu thc ca pht biu case, vic so snh ch
thnh cng khi mi bit ging nhau chnh xc mt cch tng ng theo cc
gi tr 0, 1, x, v z. Kt qu l, s cn trng khi m t thit k s dng pht
biu case l cn thit. di bit ca tt c cc biu thc s phi bng nhau
vic so snh bit-wise gia cc bit c th c thc hin. di ca tt
c biu thc trong case item cng nh biu thc trong () ca case phi bng
vi di ln nht ca biu thc ca case v case item.
Ch : di mc nh ca x v z bng vi di mc nh ca mt
s nguyn (integer).
L do ca vic cung cp kh nng so snh biu thc ca case l
gip x l nhng gi tr x v z, iu ny cung cp mt c ch pht hin
ra nhng gi tr ny v c th kim sot c thit k khi s xut hin ca
chng.
V d sau minh ha vic s dng pht biu case x l nhng gi tr
x v z mt cch thch hp.
V d 7.23
case (select[1:2])
2b00: result = 0;
2b01: result = flaga;
2b0x,
2b0z: result = flaga ? bx : 0;
2b10: result = flagb;
2bx0,
2bz0: result = flagb ? bx : 0;
default result = bx;
endcase
214
Chng 7. M hnh thit k hnh vi (Behavioral model)
Trong V d 7.23, trong case item th 3, nu select[1] l 0 v flaga l
0 th select[2] c l x hoc z th result s l 0.
Trong V d 7.24 s minh ha mt cch khc s dng pht biu
case pht hin x v z
V d 7.24
case (sig)
1bz: $display("signal is floating");
1bx: $display("signal is unknown");
default: $display("signal is %b", sig);
endcase
Hai loi khc ca pht biu case c cung cp cho php x l nhng
iu kin dont care trong vic so snh case. Mt l x l gi tr tng
tr cao (z) nh l dont care, hai l x l nhng gi tr tng tr cao (z)
v gi tr khng xc nh (x) nh l dont care.
Nhng gi tr dont care (gi tr z cho casez, z v x cho casex)
trong bt k bit no ca biu thc trong case hay trong case item s u
c xem nh nhng iu kin dont care trong sut qu trnh so snh,
v v tr ca bit s khng c xem xt. Nhng iu kin dont care
trong biu thc case c th c iu khin mt cch linh ng, bit no nn
c so snh ti thi im no.
C php ca s hc cho php s dng du chm hi (?) thay th
cho z trong nhng pht biu case. iu ny cung cp mt nh dng thun
tin cho vic m t nhng bit dont care trong pht biu case.
V d 7.25 dng pht biu casez. N minh ha mt mch gii m
lnh, nhng gi tr c trng s ln nht chn tc v (task) no cn
215
Chng 7. M hnh thit k hnh vi (Behavioral model)
c gi. Nu bit c trng s ln nht ca ir l 1 th tc v instruction1
c gi m khng cn quan tm n gi tr ca cc bit khc trong ir.
V d 7.25
reg [7:0] ir;
casez (ir)
8b1???????: instruction1(ir);
8b01??????: instruction2(ir);
8b00010???: instruction3(ir);
8b000001??: instruction4(ir);
endcase
V d 7.26
reg [7:0] r, mask;
mask = 8bx0x0x0x0;
casex (r ^ mask)
8b001100xx: stat1;
8b1100xx00: stat2;
8b00xx0011: stat3;
8bxx010100: stat4;
endcase
216
Chng 7. M hnh thit k hnh vi (Behavioral model)
7.5.2 Pht biu case vi biu thc hng s
V d 7.28
reg [2:0] encode ;
case (0)
encode[2] : $display(Select Line 2) ;
encode[1] : $display(Select Line 1) ;
encode[0] : $display(Select Line 0) ;
default $display(Error: One of the bits expected ON);
endcase
C php
looping_statements ::=
forever statement
218
Chng 7. M hnh thit k hnh vi (Behavioral model)
| repeat ( expression ) statement
| while ( expression ) statement
| for ( reg_assignment ; expression ; reg_assignment )
statement
V d 7.29 Pht biu repeat mch nhn s dng ton t add v shift.
parameter size = 8, longsize = 16;
reg [size:1] opa, opb;
reg [longsize:1] result;
begin : mult
reg [longsize:1] shift_opa, shift_opb;
shift_opa = opa;
shift_opb = opb;
result = 0;
repeat (size) begin
if (shift_opb[1])
result = result + shift_opa;
shift_opa = shift_opa << 1;
shift_opb = shift_opb >> 1;
end
end
221
Chng 7. M hnh thit k hnh vi (Behavioral model)
7.7 iu khin nh thi (procedural timing controls)
V d 7.34
#150 regm = regn;
@(posedge clock) regm = regn;
@(a, b, c) y = (a & b) | (b & c) | (a & c);
222
Chng 7. M hnh thit k hnh vi (Behavioral model)
V d 7.35
V d 1: Thc thi php gn sau 10 n v thi gian
# 10 rega = regb;
V d 2: Biu thc tr hon
#d rega = regb; // d c nh ngha nh l mt tham s
#((d+e)/2) rega = regb;// tr hon l gi tr trung bnh ca d v e
#regr regr = regr + 1; // tr hon l gi tr trong regr
223
Chng 7. M hnh thit k hnh vi (Behavioral model)
To 0 1 x z
From
0 No edge posedge posedge posedge
1 negedge No edge negedge negedge
x negedge posedge No edge No edge
z negedge posedge No edge No edge
224
Chng 7. M hnh thit k hnh vi (Behavioral model)
V d 7.37
`timescale 1ns/100ps
module maj3 (input a, b, c, output reg y);
always
@(a, b, c) // tng ng vi @(a or b or c)
begin
y = (a & b) | (b &c) | (a & c);
end
endmodule
V d trn c th c m t gn hn nh sau:
module maj3 (input a, b, c, output reg y);
always @(a, b, c) begin // tng ng vi @(a or b or c)
y = (a & b) | (b &c) | (a & c);
end
endmodule
V d 7.38
`timescale 1ns/100ps
module maj3 (input a, b, c, output reg y);
always
@(a, b, c)
y = (a & b) | (b & c) | (a & c);
// c th vit nh sau: @(a, b, c) y = (a & b) | (b & c) | (a & c);
endmodule
225
Chng 7. M hnh thit k hnh vi (Behavioral model)
Trong V d 7.38, iu khin s kin c t trc pht biu
hnh thnh mt pht biu qui trnh bng cch b i du chm phy. iu
ny c ngha du chm phy sau @(a, b, c) c th c hoc khng. Khi hai
pht biu trn c ghp li th ch mt pht biu c thc thi.
Vic thc thi mt pht biu qui trnh c th c tr hon cho n khi
mt iu kin tr thnh ng (true). iu ny t c bng s dng pht
biu wait, y l mt dng c bit ca iu khin s kin. Mc nh ca
pht biu wait l tch cc mc, iu ny tri ngc vi pht biu iu
khin s kin l tch cc cnh.
Pht biu wait s tnh gi tr ca iu kin, nu gi tr sai (false),
nhng pht biu qui trnh theo sau n s b ng li khng thc thi cho n
khi gi tr tr thnh ng (true) th mi thc thi nhng pht biu qui
trnh v thot ra khi pht biu wait tip tc cc pht biu k tip,
iu ny i lp vi hot ng ca pht biu vng lp while, trong pht
biu vng lp while, gi tr ca iu kin nu ng (true) th nhng pht
biu qui trnh theo sau n s thc thi lp li lin tc trong vng lp cho n
khi gi tr ca iu kin tr thnh sai (false) th thot ra khi vng lp while
tip tc cc pht biu k tip. C php ca nhng pht biu wait c
m t nh sau:
C php
wait_statement::=
wait (expression) statement_or_null
V d 7.39
begin
226
Chng 7. M hnh thit k hnh vi (Behavioral model)
wait (!enable) #10 a = b;
#10 c = d;
end
V d 7.40
always
begin
wait (var1 ==1);
a = b;
end
V d 7.41
always
begin
@var
wait (var1 ==1);
a = b;
end
V d trn m t mt thit k thc hin chc nng khi var chuyn
trng thi ln 1 th a s cp nht gi tr t b. Tng t nh m t sau:
227
Chng 7. M hnh thit k hnh vi (Behavioral model)
always @var1
if (var1 ==1)
a = b;
Trong khai bo qui trnh, Verilog HDL c h tr vic pht biu khi.
Pht biu khi l vic nhm hai hay nhiu pht biu cng vi nhau
chng c th hot ng theo cng c php nh l mt pht biu n. C hai
loi khi trong Verilog HDL.
Khi tun t, hay cn c gi l khi begin-end
Khi song song, hay cn c gi l khi fork-join
Khi tun t c gii hn bi hai t kha begin v end. Nhng pht
biu qui trnh trong khi tun t s c thc thi mt cch tun t theo th
t c cho.
Khi song song c gii hn bi hai t kha fork v join. Nhng
pht biu qui trnh trong khi song song s c thc thi mt cch ng
thi
228
Chng 7. M hnh thit k hnh vi (Behavioral model)
V d 7.42
begin
areg = breg;
creg = areg; // creg lu tr gi tr ca breg
end
229
Chng 7. M hnh thit k hnh vi (Behavioral model)
Gi tr tr hon ca mi pht biu l thi gian m phng c
tnh t khi lung iu khin bc vo khi fork-join cho n
pht biu .
iu khin tr hon c s dng cung cp thi gian tun
t cho cc php gn.
iu khin s thot ra khi khi khi pht biu c th t cui
cng theo thi gian (gi tr tr hon ln nht) c thc thi.
Nhng iu khin nh thi trong khi fork-join khng phi theo th
t tun t theo thi gian.
V d 7.45 s m t dng sng ging nh trong v d trn nhng
dng khi song song thay v dng khi tun t. Dng sng c to ra trn
mt thanh ghi s ging nhau trong c hai trng hp.
V d 7.45
fork
#50 r = h35;
#200 r = hF7; // khng cn theo th t
#100 r = hE2;
#250 -> end_wave; // iu khin thot ra
#150 r = h00;
join
7.8.3 Tn khi
230
Chng 7. M hnh thit k hnh vi (Behavioral model)
N cho php khi c tham chiu trong nhng pht biu
chng hn nh pht biu disable.
Tt c cc thanh ghi l tnh, ngha l mt v tr duy nht tn ti trong
tt c cc thanh ghi v ri khi hoc tin vo khi s khng nh hng n
gi tr cha trong n.
Tn khi s l tn nh dng duy nht cho tt c cc thanh ghi ti bt
k thi im m phng no.
231
Chng 7. M hnh thit k hnh vi (Behavioral model)
7.9.1 Cu trc initial
V d 7.47
initial begin
inputs = b000000; //khi to ti thi im zero
#10 inputs = b011001; // 10 n v thi gian u
#10 inputs = b011011; // 10 n v thi gian th hai
#10 inputs = b011000; // 10 n v thi gian th ba
#10 inputs = b001000; // 10 n v thi gian cui
end
233
Chng 7. M hnh thit k hnh vi (Behavioral model)
ng vo h thng. H thng my trng thi hu hn Moore c m t nh
hnh
next current di
inputs
comb. state memory state comb. outputs :
circuit elements circuit
234
Chng 7. M hnh thit k hnh vi (Behavioral model)
V d 7.48 m t code Verilog cho h thng ny. Chng ta s dng
mt khai bo parameter gn gi tr n cc my trng thi. My trng
thi ca ta c bn trng thi do cn s dng 2 bit khai bo trng thi.
0
reset
0 1
1
got1
1
got101 0
0 1 0 0
0 got10
0
235
Chng 7. M hnh thit k hnh vi (Behavioral model)
parameter got10 = 2'b10;
parameter got101 = 2'b11;
//Mch t hp ca trng thi k tip
always @(state or dataIn)
case (state)
reset:
if (dataIn)
next_state = got1;
else
next_state = reset;
got1:
if (dataIn)
next_state = got1;
else
next_state = got10;
got10:
if (dataIn)
next_state = got101;
else
next_state = reset;
got101:
if (dataIn)
next_state = got1;
else
next_state = got10;
default:
next_state = reset;
236
Chng 7. M hnh thit k hnh vi (Behavioral model)
endcase // case(state)
//Mch chuyn trng thi
always @(posedge clock)
if (reset == 1)
state <= reset;
else
state <= next_state;
//Mch t hp ng ra
assign found = (state == got101) ? 1: 0;
endmodule
reset
dataIn
D-FF
found
D-FF
clock
Hnh 7.4 Mch pht hin chui 101 sau tng hp s dng FSM Moore
237
Chng 7. M hnh thit k hnh vi (Behavioral model)
7.10.2 My trng thi Mealy
next current
inputs
inputs
comb. state memory state comb. outputs
circuit elements circuit
238
Chng 7. M hnh thit k hnh vi (Behavioral model)
V d 7.49 m t code Verilog cho h thng trn. Chng ta s dng
mt khai bo parameter gn gi tr n cc my trng thi. My trng
thi ca ta c ba trng thi nn cn s dng 2 bit khai bo trng thi.
0/0
reset
1/0
1/0
got1
0/0
0/0
got10 1/1
Hnh 7.6 Lu my trng thi hu hn Mealy c chc nng d tm chui 101 lin
tc.
V d 7.49
module Mealy101Detector (dataIn, found, clock, reset);
//Khai bo cng ng vo, ng ra
input dataIn;
input clock;
input reset;
output found;
//Khai bo bin d liu ni
reg [1:0] state;
reg [1:0] next_state;
//Khai bo trng thi
parameter reset = 2'b00;
parameter got1 = 2'b01;
parameter got10 = 2'b10;
239
Chng 7. M hnh thit k hnh vi (Behavioral model)
//Khai bo mch t hp trng thi k tip
always @(state or dataIn)
case (state)
reset:
if (dataIn)
next_state = got1;
else
next_state = reset;
got1:
if (dataIn)
next_state = got1;
else
next_state = got10;
got10:
if (dataIn)
next_state = got1;
else
next_state = reset;
default:
next_state = reset;
endcase // case(state)
//Mch chuyn trng thi
always @(posedge clock)
if (reset == 1)
state <= reset;
else
state <= next_state;
240
Chng 7. M hnh thit k hnh vi (Behavioral model)
//Mch t hp ng ra
assign found = (state == got10 && dataIn == 1) ? 1: 0;
endmodule // Mealy101
D-FF
clock
Hnh 7.7 Mch pht hin chui 101 sau tng hp s dng FSM Mealy
7.11 Bi tp
242
Chng 7. M hnh thit k hnh vi (Behavioral model)
a = #delay1 b;
initial
c = #delay2 d;
initial
begin
e <= #delay3 f;
k <= #delay4 g;
end
14.on code sau thc hin chc nng g? Vit li on m t li s
dng php gn kn
always @(posedge clock) begin
a <= b;
b <= a;
end
15.on code sau thc hin chc nng g? Vit li on m t li s
dng php gn kn
always @(posedge clock)
#0 a <= b + c;
always @(posedge clock)
b <= a;
16.V dng sng ca tn hiu d trn ton b thi gian m phng
`timescale 1ns/100ps
module test;
reg b,c,d;
initial begin
b=1b1;
c=1b0;
#10 b=1b0;
end
243
Chng 7. M hnh thit k hnh vi (Behavioral model)
initial d = #25(b|c);
endmodule
17.V dng sng ca a, b v c trong 100ns u tin ca qu trnh m
phng.
module test;
wire a, b;
reg c;
assign #60 a = 1 ;
initial begin
#20 c = b;
#20 c = a;
#20;
end
endmodule
18.Kim tra xem on m t sau c thc hin chc nng tm gi tr ln
nht c khng?
reg [3:0] mx;
reg [3:0] lst [0:3];
always @ (lst[0] or lst[1] or lst[2] or lst[3]) begin
mx <= 4b0000;
if ( lst[0] >= mx ) mx <= lst[0];
if ( lst[0] >= mx ) mx <= lst[1];
if ( lst[0] >= mx ) mx <= lst[2];
if ( lst[0] >= mx ) mx <= lst[3];
end
19.Kim tra xem hai on m t thit k sau c cng chc nng hay
khng?
M t 1:
244
Chng 7. M hnh thit k hnh vi (Behavioral model)
module addr_dcd (addr_in, decoded_addr);
parameter ADDRESS = 8;
parameter RAMSIZE = 256;
input [ADDRESS 1 : 0] addr_in;
output [RAMSIZE - 1 : 0] decoded_addr;
integer i;
reg [RAMSIZE 1 : 0] decoded_addr;
always @ (addr_in) begin
for( i=0; i < RAMSIZE ; i=i+1)
decoded_addr[ i ] = (addr_in == i);
end
endmodule
M t 2:
module addr_dcd (addr_in, decoded_addr);
parameter ADDRESS = 8;
parameter RAMSIZE = 256;
input [ADDRESS 1 : 0] addr_in;
output [RAMSIZE - 1 : 0] decoded_addr;
integer i;
reg [RAMSIZE 1 : 0] decoded_addr;
always @ (addr_in) begin
for( i=0; i < RAMSIZE ; i=i+1)
decoded_addr[ i ] <= (addr_in == i);
end
endmodule
245
Chng 8. Tc v (task) v hm (function)
Chng 8. Tc v (task) v hm (function)
246
Chng 8. Tc v (task) v hm (function)
Mc ch ca mt function l p ng gi tr u vo bng cch tr
v mt gi tr n. Mt task c th h tr nhiu mc ch v c th tnh
ton nhiu gi tr kt qu. Tuy nhin, ch c i s u ra hoc u vo ra
thng qua gi tr kt qu t vic gi mt task. Mt function c s dng
nh l mt ton hng ca mt biu thc. Gi tr ca ton hng l gi tr tr
v ca hm.
V d:
Hoc l task hoc l function nh ngha chuyn i byte trong
mt t 16 bit. Task c th tr v mt gi tr t chuyn i trong i s
u ra; v vy chng trnh c th gi task switch_bytes nh sau:
switch_bytes (old_word, new_word);
Task switch_bytes s ly cc byte trong old_word, o ngc cc
byte v t cc byte o ngc trong new_word.
Function o ngc t s tr v t o ngc nh l mt gi tr
tr v ca function. V vy c th gi function switch_bytes nh sau:
new_word = switch_bytes (old_word);
247
Chng 8. Tc v (task) v hm (function)
8.2.1 Khai bo tc v
C php 8-1
task_declaration ::=
task [ automatic ] task_identifier ;
{ task_item_declaration }
statement_or_null
endtask
| task [ automatic ] task_identifier ( [ task_port_list ] ) ;
{ block_item_declaration }
statement_or_null
endtask
task_item_declaration ::=
block_item_declaration
| { attribute_instance } tf_ input_declaration ;
| { attribute_instance } tf_output_declaration ;
| { attribute_instance } tf_inout_declaration ;
task_port_list ::=
task_port_item { , task_port_item }
task_port_item ::=
{ attribute_instance } tf_input_declaration
| { attribute_instance } tf_output_declaration
| { attribute_instance } tf_inout_declaration
tf_input_declaration ::=
input [ reg ] [ signed ] [ range ] list_of_port_identifiers
| input task_port_type list_of_port_identifiers
tf_output_declaration ::=
248
Chng 8. Tc v (task) v hm (function)
output [ reg ] [ signed ] [ range ] list_of_port_identifiers
| output task_port_type list_of_port_identifiers
tf_inout_declaration ::=
inout [ reg ] [ signed ] [ range ] list_of_port_identifiers
| inout task_port_type list_of_port_identifiers
task_port_type ::=
integer | real | realtime | time
block_item_declaration ::=
{ attribute_instance } reg [ signed ] [ range ]
list_of_block_variable_identifiers ;
| { attribute_instance } integer list_of_block_variable_identifiers ;
| { attribute_instance } time list_of_block_variable_identifiers ;
| { attribute_instance } real list_of_block_real_identifiers ;
| { attribute_instance } realtime list_of_block_real_identifiers ;
| { attribute_instance } event_declaration
| { attribute_instance } local_parameter_declaration ;
| { attribute_instance } parameter_declaration ;
list_of_block_variable_identifiers ::=
block_variable_type { , block_variable_type }
list_of_block_real_identifiers ::=
block_real_type { , block_real_type }
block_variable_type ::=
variable_identifier { dimension }
block_real_type ::=
real_identifier { dimension }
249
Chng 8. Tc v (task) v hm (function)
C php th nht s bt u vi t kha task, theo sau l t kha ty
chn automatic, theo sau l tn task v tip theo l du chm phy (;), v
kt thc vi t kha endtask. T kha automatic khai bo mt task t ng
lm vo, vi tt c cc task c khai bo phn b ng cho mi mc task
hin ti. Khai bo cc yu ca task bao gm:
i s u vo
i s u ra.
i s u vo ra.
Tt c cc kiu d liu c th khai bo trong mt khi th tc.
C php th hai bt u vi t kha task, theo sau l tn ca task v
danh sch cc cng ca task nm trong du ngoc n. Danh sch cc cng
ca task c th khng c hoc c nhiu cc cng ngn cch nhau bi u
phy. V c mt du chm phy sau du ngoc n. Tip theo l phn thn
ca task v kt thc bng t kha endtask.
Trong c hai c php, khai bo cc cng ging vi c php c
nh ngha bi tf_input_declaration, tf_output_declaration,
tf_inout_declaration c m t trong C php 8-1bn trn.
Task m khng cha t kha ty chn automatic l mt task tnh, vi
tt c cc mc khai bo s c phn b c nh. Nhng mc ny s chia
s c chia s thng qua tt c cc s dng ca task thc thi hin ti. Task
bao gm t kha automatic s l mt task ng. Tt c cc mc khai bo
trong task ng s c phn b ng trong mi ln task c gi. Cc
mc ca task ng khng th truy cp theo cu trc phn cp. Task ng c
th c gi s dng thng qua tn phn cp.
250
Chng 8. Tc v (task) v hm (function)
8.2.2 Kch hot tc v v truyn i s
C php 8-2
task_enable ::=
hierarchical_task_identifier [ ( expression { , expression } ) ] ;
251
Chng 8. Tc v (task) v hm (function)
task. Vic thc thi s tr v gi tr t task thng qua cc gi tr t cc i s
loi output hoc inout ca task tng ng vi bin trong cu lnh kch hot
task. Tt c cc i s trong task s thng qua cc gi tr hn l tham chiu
(l mt con tr n gi tr).
V d 8.1 m t cu trc c bn ca nh ngha mt task vi nm i
s:
V d 8.1
task my_task;
input a, b;
inout c;
output d, e;
begin
. . . // cc cu lnh thc thi nhim v ca task.
...
c = foo1; // gn trng thi ban u cho thanh ghi kt qu.
d = foo2;
e = foo3;
end
endtask
Hoc s dng hnh thc th 2 ca khai bo task, task c th nh
ngha nh sau:
task my_task (input a, b, inout c, output d, e);
begin
. . . // cc cu lnh thc thi nhim v ca task.
...
c = foo1; // gn trng thi ban u cho thanh ghi kt qu.
d = foo2;
252
Chng 8. Tc v (task) v hm (function)
e = foo3;
end
endtask
Cu lnh sau cho php kch hot task:
my_task (v, w, x, y, z);
Cc i s trong cu lnh kch hot task (v, w, x, y, v z) tng ng
vi cc i s (a, b, c, d, v e) trong nh ngha task. Trong thi gian kch
hot task, cc i s input v inout (a, b, v c) nhn cc gi tr thng qua
cc i s v, w, v x. Nh vy vic thc thi li gi kch hot task s tng
ng thc hin lnh gn sau:
a = v;
b = w;
c = x;
Tip theo trong tin trnh ca task, theo nh ngha ca my_task s
t gi tr kt qu tnh ton vo c, d, v e. Khi task hon thnh, lnh gn sau
s tr v gi tr tnh ton ti li gi thc thi task:
x = c;
y = d;
z = e;
V d 8.2
module traffic_lights;
reg clock, red, amber, green;
parameter on = 1, off = 0, red_tics = 350,
amber_tics = 30, green_tics = 200;
253
Chng 8. Tc v (task) v hm (function)
// trng thi ban u.
initial red = off;
initial amber = off;
initial green = off;
always begin // iu khin n tun t.
red = on; // bt n
light(red, red_tics); // i
green = on; // bt n xanh
light(green, green_tics); // i.
amber = on; // bt n vng
light(amber, amber_tics); // i
end
// task s i 'tics' trong cnh ln ca clock trc khi tc tn hiu
n
task light;
output color;
input [31:0] tics;
begin
repeat (tics) @ (posedge clock);
color = off; // tt n.
end
endtask
always begin // to dng sng cho ng h.
#100 clock = 0;
#100 clock = 1;
end
endmodule
254
Chng 8. Tc v (task) v hm (function)
8.2.3 S dng b nh tc v v s kch hot ng thi
8.3 Hm v vic gi hm
Mc ch ca mt function l tr v mt gi tr c s dng
trong mt biu thc. Phn tip theo ca chng ny s m t cc nh
ngha v s dng function.
8.3.1 Khai bo hm
C php 8-3
function_declaration ::=
function [ automatic ] [ function_range_or_type ]
255
Chng 8. Tc v (task) v hm (function)
function_identifier ;
function_item_declaration { function_item_declaration }
function_statement
endfunction
| function [ automatic ] [ function_range_or_type ]
function_identifier ( function_port_list ) ;
{ block_item_declaration }
function_statement
endfunction
function_item_declaration ::=
block_item_declaration
| { attribute_instance } tf_input_declaration ;
function_port_list ::=
{ attribute_instance } tf_input_declaration
{ , { attribute_instance }tf_input_declaration }
tf_input_declaration ::=
input [ reg ] [ signed ] [ range ] list_of_port_identifiers
| input task_port_type list_of_port_identifiers
function_range_or_type ::=
[ signed ] [ range ]
| integer
| real
| realtime
| time
block_item_declaration ::= (From A.2.8)
{ attribute_instance } reg [ signed ] [ range ]
list_of_block_variable_identifiers ;
256
Chng 8. Tc v (task) v hm (function)
| { attribute_instance } integer list_of_block_variable_identifiers ;
| { attribute_instance } time list_of_block_variable_identifiers ;
| { attribute_instance } real list_of_block_real_identifiers ;
| { attribute_instance } realtime list_of_block_real_identifiers ;
| { attribute_instance } event_declaration
| { attribute_instance } local_parameter_declaration ;
| { attribute_instance } parameter_declaration ;
list_of_block_variable_identifiers ::=
block_variable_type { , block_variable_type }
list_of_block_real_identifiers ::=
block_real_type { , block_real_type }
block_variable_type ::=
variable_identifier { dimension }
block_real_type ::=
real_identifier { dimension }
V d 8.3
function [7:0] getbyte;
input [15:0] address;
begin
// chng trnh ly byte t word
...
getbyte = result_expression;
end
endfunction
Hoc s dng cch th hai nh ngha function, function getbyte
c th c nh ngha nh sau:
258
Chng 8. Tc v (task) v hm (function)
function [7:0] getbyte (input [15:0] address);
begin
// chng trnh ly byte t word
...
getbyte = result_expression;
end
endfunction
8.3.2 Tr v mt gi tr t hm
8.3.3 Vic gi hm
259
Chng 8. Tc v (task) v hm (function)
C php 8-4.
C php 8-4
function_call ::=
hierarchical_function_identifier{ attribute_instance } (
expression { , expression } )
260
Chng 8. Tc v (task) v hm (function)
V d 8.4
module tryfact;
// nh ngha hm
function automatic integer factorial;
input [31:0] operand;
integer i;
if (operand >= 2)
factorial = factorial (operand - 1) * operand;
else
factorial = 1;
endfunction
// kim tra hm
integer result;
integer n;
initial begin
for (n = 0; n <= 7; n = n+1) begin
result = factorial(n);
$display("%0d factorial=%0d", n, result);
end
end
endmodule
Kt qu ca vic m phng:
0 factorial=1
1 factorial=1
2 factorial=2
3 factorial=6
4 factorial=24
5 factorial=120
261
Chng 8. Tc v (task) v hm (function)
6 factorial=720
7 factorial=5040
V d 8.5
module ram_model (address, write, chip_select, data);
parameter data_width = 8;
parameter ram_depth = 256;
localparam addr_width = clogb2(ram_depth);
input [addr_width - 1:0] address;
input write, chip_select;
inout [data_width - 1:0] data;
//nh ngha hm clogb2
function integer clogb2;
input [31:0] value;
begin
value = value - 1;
for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1)
value = value >> 1;
end
endfunction
reg [data_width - 1:0] data_store[0:ram_depth - 1];
//phn cn li ca ram_model
263
Chng 8. Tc v (task) v hm (function)
Th hin ca ram_model ny vi tham s c gn nh bn di:
ram_model #(32,421) ram_a0(a_addr,a_wr,a_cs,a_data);
8.4 Bi tp
264
Chng 9. Kim tra thit k
265
Chng 9. Kim tra thit k
phn cui s tho lun v k thut chn kim tra thit k nhm to gii
php tt nht cho vic thit k module.
9.1 Testbench
266
Chng 9. Kim tra thit k
V d 9.1
module alu_4bit (a, b, f, oe, y, p, ov, a_gt_b, a_eq_b, a_lt_b);
input [3:0] a, b;
input [1:0] f;
input oe;
output [3:0] y;
output p, ov, a_gt_b, a_eq_b, a_lt_b;
// . . .
endmodule
Module c cc u vo a, b v u vo chc nng f, u ra y v cc
u ra km theo p, ov, a_gt_b, a_eq_b, a_lt_b.
Mt testbenches cho alu_4bit c nh ngha nh sau:
V d 9.2
module test_alu_4bit;
reg [3:0] a=4b1011, b=4b0110;
reg [1:0] f=2b00;
reg oe=1;
wire [3:0] y;
wire p, ov, a_gt_b, a_eq_b, a_lt_b;
alu_4bit cut( a, b, f, oe, y, p, ov, a_gt_b, a_eq_b,
a_lt_b );
initial begin
#20 b=4b1011;
#20 b=4b1110;
267
Chng 9. Kim tra thit k
#20 b=4b1110;
#80 oe=1b0;
#20 $finish;
end
always #23 f = f + 1;
endmodule
268
Chng 9. Kim tra thit k
V d 9.3
module #(parameter [3:0] poly=0) misr (input clk, rst,
input [3:0] d_in, outputreg [3:0] d_out );
always @( posedge clk )
if( rst )
d_out =4b0000;
else
d_out = d_in ^ ({4{d_out[0]}} & poly) ^
{1b0,d_out[3:1]};
endmodule
269
Chng 9. Kim tra thit k
V d 9.4
module test_misr;
reg clk=0, rst=0;
reg [3:0] d_in;
wire [3:0] d_out;
misr #(4b1100) MUT ( clk, rst, d_in, d_out );
initial begin
#13 rst=1b1;
#19 d_in=4b1000;
#31 rst=0b0;
#330 $finish;
end
always #37 d_in = d_in + 3;
always #11 clk = ~clk;
endmodule
V d 9.5
module moore_detector (input x, rst, clk, output z );
parameter [1:0] a=0, b=1, c=2, d=3;
reg [1:0] current;
always @( posedge clk )
if ( rst ) current = a;
else case ( current )
a : current = x ? b : a ;
b : current = x ? b : c ;
c : current = x ? d : a ;
d : current = x ? b : c ;
default : current = a ;
endcase
assign z = (current==d) ? 1b1 : 1b0;
271
Chng 9. Kim tra thit k
endmodule
V d 9.6
module test_moore_detector;
reg x, reset, clock;
wire z;
moore_detector MUT ( x, reset, clock, z );
initial begin
clock=1b0; x=1b0; reset=1b1;
end
initial #24 reset=1b0;
always #5 clock=~clock;
always #7 x=~x;
endmodule
272
Chng 9. Kim tra thit k
V d 9.7
module test_moore_detector;
reg x=0, reset=1, clock=0;
wire z;
moore_detector MUT ( x, reset, clock, z );
initial #24 reset=1b0;
always #5 clock=~clock;
always #7 x=~x;
initial #189 $stop;
endmodule
V d 9.8
module test_moore_detector;
reg x=0, reset=1, clock=0;
wire z;
moore_detector MUT ( x, reset, clock, z );
initial begin
#24 reset=1b0;
#165 $finish;
end
always #5 clock=~clock;
always #7 x=~x;
endmodule
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Chng 9. Kim tra thit k
V d 9.9
module test_moore_detector;
reg x=0, reset=1, clock=0;
wire z;
moore_detector MUT ( x, reset, clock, z );
initial #24 reset=1b0;
initial repeat(13) #5 clock=~clock;
initial repeat(10) #7 x=$random;
endmodule
275
Chng 9. Kim tra thit k
V d 9.10
module test_moore_detector;
reg x=0, reset=1, clock=0;
wire z;
moore_detector MUT ( x, reset, clock, z );
initial #24 reset=0;
initial repeat(13) #5 clock=~clock;
initial forever @(posedge clock) #3 x=$random;
endmodule
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Chng 9. Kim tra thit k
9.2.5 Tng tc testbench
V d 9.11
module moore_detector (input x, start, rst, clk, output z );
parameter a=0, b=1, c=2, d=3, e=4;
reg [2:0] current;
always @( posedge clk )
if ( rst ) current <= a;
else if ( ~start ) current <= a;
else case ( current )
a : current <= x ? b : a ;
b : current <= x ? c : a ;
c : current <= x ? c : d ;
d : current <= x ? e : a ;
e : current <= x ? c : a ;
default: current <= a;
endcase
assign z = (current==e);
endmodule
Testbench cho my trng thi l mt testbench tng tc mt.
module test_moore_detector;
reg x=0, start, reset=1, clock=0;
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Chng 9. Kim tra thit k
wire z;
moore_detector MUT ( x, start, reset, clock, z );
initial begin
#24 reset=1b0; start=1b1;
wait(z==1b1);
#11 start=1b0;
#13 start=1b1;
repeat(3) begin
#11 start=1b0;
#13 start=1b1;
wait(z==1b1);
end
#50 $stop;
end
always #5 clock=~clock;
always #7 x=$random;
endmodule
V d 9.12
module test_moore_detector;
reg x, start, reset, clock;
wire z;
reg [3:0] t;
moore_detector MUT ( x, start, reset, clock, z );
initial begin:running
clock <= 1b0; x <= 1b0;
reset <= 1b1; reset <= #7 1b0;
start <= 1b0; start <= #17 1b1;
repeat (13) begin
@( posedge clock );
@( negedge clock );
end
start=1b0;
#5;
$finish;
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Chng 9. Kim tra thit k
end
always #5 clock=~clock;
always begin
t = $random;
#(t) x=$random;
end
endmodule
Trong phn trc tho lun cc k thut kim tra kim tra mt
thit k Verilog. Trong phn ny s bn ti mt vi phng thc to d
liu kim tra v p dng kim tra, v h tr mt vi cch xem xt v
kim tra kt qu kim tra. To cc kch thch v phn tch p ng ca mt
thit k i hi mt phn n lc ng k ca ngi thit kt phn cng.
Tm hiu cc k thut kim tra ng l tt, nhng thit k t ng lm cc
th tc ny s rt hu dng cho cc k s.
Hnh thc kim tra thit k l mt cch t ng thit k kim tra
bng cch loi b testbenches v cc vn lin quan n vic to d liu
v quan st cc p ng ca mch. Trong hnh thc kim tra thit k, ngi
280
Chng 9. Kim tra thit k
thit k s thit k mt thuc tnh kim tra thit k ca anh ta. Cng c
kim tra thit k hnh thc khng thc hin m phng, nhng a ra cu tr
li c/khng c cho mi thuc tnh ca thit k ang c kim tra. Mc
d phng php kim tra thit k gip tm ra nhiu li thit k nhng hu
nh nhiu thit k vn cn pht trin testbench v m phng xc nhn
chng trnh Verilog ca h thc hin ng chc nng mong i. Ni cch
khc, tt c cc cu tr li l c cho tt c cc thuc tnh kim tra bi
cng c kim tra thit k hnh thc l cha . Thay v b qua vic to d
liu v quan st p ng, mt bc theo hng t ng ha thit k xc
nhn l gim hoc b qua cc n lc cn thit cho phn tch kt qu p
ng. K thut chn kim tra thit k c s dng theo hng ny, n
s thm gim st thit k ci thin kh nng quan st p ng. Trong khi
thit k ang c m phng vi d liu testbench, trnh quan st c
chn vo i din cho mt s thuc tnh ca thit k lin tc kim tra c
ng vi thit k hnh vi bng cc xc minh nhng thuc tnh . Nu d
liu m phng dn n iu kin ch ra mt trnh gim st chn vo l
khng ph hp vi hnh vi thit k, trnh gim st s cnh bo ti ngi
thit k vn .
Nh cp, chng ta vn phi pht trin mt testbench v thit
k cn thn cc u vo kim tra cho thit k cn kim tra l cn thit cho
k thut chn kim tra thit k. Nhng trong nhiu trng hp, k thut
chn t ng kim tra chc chn s kin xy ra trong thit k l ng
nh mong i. iu ny c ngha lm gim s cn thit cho vic x l
mt danh sch di cc u ra v dng sng.
281
Chng 9. Kim tra thit k
282
Chng 9. Kim tra thit k
9.4.1 Li ch ca k thut chn kim tra.
assert_even_parity
assert_frame
assert_implication
assert_never
assert_next
assert_no_transition
assert_odd_parity
assert_one_hot
assert_quiescent_state
Mt assertion c t trong chng trnh ging nh mt th hin ca
module. Cu trc sau m t mt khai bo th hin module assertion.
C php 9-1
assert_name
#(static_parameters)
instance_name
(dynamic_arguments);
N bt u vi tn ca module assertion, theo sau l cc tham s tnh
(satatic_parameters) nh l kch thc ca vector hoc cc ty chn. Sau
l tn duy nht bt k ca th hin, v phn cui cng l mt trnh gim
st chn vo bao gm cc tham chiu, gim st tn hiu v cc i s ng
khc. Cc i s ng ny l cc cng ca module v cng c xem nh
l cc cng ca assertion module.
C php 9-2
284
Chng 9. Kim tra thit k
assert_always
#( severity_level, property_type,
msg, coverage_level )
instance_name ( clk, reset_n, test_expr )
Lnh ny s lin tc chn kim tra test_expr chc chn n lun
lun ng trn mi cnh ca clock. Nu biu thc kim tra sai, mt thng
ip tng ng s c hin th.
V d 9.13
module BCD_Counter (input rst, clk, outputreg [3:0] cnt);
always @(posedge clk)
begin
if (rst || cnt >= 10) cnt = 0;
else cnt = cnt + 1;
end
assert_always #(1, 0, Err: Non BCD Count, 0)
AA1 (clk, 1b1, (cnt >= 0) && (cnt <= 9));
endmodule
Testbench kim tra module:
module BCD_Counter_Tester;
reg r, c;
wire [3:0] count;
BCD_Counter UUT (r, c, count);
initial begin
r = 0; c = 0;
end
285
Chng 9. Kim tra thit k
C php 9-3
assert_change
#( severity_level, width, num_cks,
action_on_new_start, property_type,
msg, coverage_level )
instance_name ( clk, reset_n, start_event,
test_expr )
C php 9-4
assert_one_hot
#( severity_level, width, property_type,
msg, coverage_level )
instance_name ( clk, reset_n, test_expr )
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Chng 9. Kim tra thit k
C php 9-5
assert_cycle_sequence
#( severity_level, num_cks, necessary_condition,
property_type,
msg, coverage_level )
instance_name ( clk, reset_n, event_sequence )
C php 9-6
assert_next
#( severity_level, num_cks, check_overlapping,
check_missing_start, property_type,
msg, coverage_level )
instance_name ( clk, reset_n, start_event,
test_expr )
9.5 Bi tp
287
Chng 9. Kim tra thit k
288
Chng 9. Kim tra thit k
289
Ngn ng m t phn cng Verilog
PH LC
Chng 1. Dn nhp thit k h thng s vi Verilog ..... 1
1.1 Qui trnh thit k s ............................................................. 2
1.1.1 Dn nhp thit k ....................................................... 4
1.1.2 Testbench trong Verilog ............................................ 5
1.1.3 nh gi thit k ........................................................ 6
1.1.4 Bin dch v tng hp thit k ................................. 10
1.1.5 M phng sau khi tng hp thit k ........................ 13
1.1.6 Phn tch thi gian ................................................... 14
1.1.7 To linh kin phn cng........................................... 15
1.2 Ngn ng phn cng Verilog (Verilog HDL) .................. 15
1.2.1 Qu trnh pht trin Verilog ..................................... 15
1.2.2 Nhng c tnh ca Verilog ..................................... 16
1.2.3 Ngn ng Verilog .................................................... 19
1.3 Tng kt............................................................................. 20
1.4 Bi tp................................................................................ 20
Chng 2. Qui c v t kha ........................................ 22
2.1 Khong trng ..................................................................... 22
2.2 Ch thch ........................................................................... 22
2.3 Ton t .............................................................................. 22
2.4 S hc ................................................................................ 23
2.4.1 Hng s nguyn ........................................................ 23
290
Ngn ng m t phn cng Verilog
298
Ngn ng m t phn cng Verilog
299