Title (en)

Power-reduced preliminary decoded bits in viterbi decoder

Title (de)
Leistungsreduzierte vorlufig dekodierte Bits in Viterbi Dekodierer

Title (fr)
Bit provisionelle puissance reduite dans un dcodeur de Viterbi

Publication
EP 2339757 A1 20110629 (EN)

Application
EP 10196104 A 20101221

Priority
US 64788509 A 20091228

Abstract (en)
Various embodiments relate to a storage unit and a related method in a Viterbi decoder for decoding a binary convolutional code with power
efficiency. A storage unit for storing survivor paths may use a register exchange method to append additional information received from an add-
compare-select unit onto the end of the survivor path. An exemplary method produces a prediction path after a specified depth in the survivor path
processing history and subtracts the prediction path from the survivor path. This may cause a majority of bits that comprise the survivor path to be
converted to a low-energy bit, such as a logical "0". During subsequent copies of a differential survivor path using the register exchange method,
less energy is consumed when copying the entire survivor path, as a majority of the bits in the survivor paths are a logical "0".

Inventor
HEKSTRA ANDRIES PIETER (NL)
TANG WEIHUA (NL)

Applicant
NXP BV (NL)

IPC 8 full level (invention and additional information)

H03M 13/41 (2006.01)

CPC (invention and additional information)

H03M 13/4184(2013.01)

Citation (applicant)
None

Citation (search report)

[IA]TODD K. MOON: "Error Correction Coding: Mathematical Methods and Algorithms", 2005, JOHN WILEY & SONS, INC,
XP002618913
[A]CYPHER R ET AL: "GENERALIZED TRACE-BACK TECHNIQUES FOR SURVIVOR MEMORY MANAGEMENT IN
THE VITERBI ALGORITHM*", JOURNAL OF VLSI SIGNAL PROCESSING SYSTEMS FOR SIGNAL, IMAGE, AND VIDEO
TECHNOLOGY, vol. 5, no. 1, 1 January 1993 (1993-01-01), SPRINGER, NEW YORK, NY, US, pages 85 - 94, XP000364288,
ISSN: 0922-5773, DOI: 10.1007/BF01880274
[A]STEINERT M ET AL: "Power consumption optimization for low latency Viterbi decoder", PROCEEDINGS OF THE
INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, 2004. ISCAS '04., vol. 2, 23 May 2004 (2004-05-23), pages 377 -
380, XP010720184, ISBN: 978-0-7803-8251-0

Cited by
CN102662631A

Designated contracting state (EPC)

AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR

Designated extension state (EPC)

BA ME

EPO simple patent family

EP 2339757 A1 20110629; US 2011161787 A1 20110630; US 8566683 B2 20131022

INPADOC legal status

2016-01-13 [17Q] FIRST EXAMINATION REPORT
- Effective date : 20151209

2012-02-08 [17P] REQUEST FOR EXAMINATION FILED

- Effective date : 20111229

2011-06-29 [AK] DESIGNATED CONTRACTING STATES:

- Kind Code of Ref Document : A1
- Designated State(s) : AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL
PT RO RS SE SI SK SM TR

2011-06-29 [AX] REQUEST FOR EXTENSION OF THE EUROPEAN PATENT TO

- Countries : BA ME