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6562211 digital logic design 2
6562211
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6562211 digital logic design 3
4 (Karnaughs Map)
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6562211 digital logic design 4
4
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6562211 digital logic design 5
: (K-map)
(product term)
2
A=1 A
A=0 A A
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6562211 digital logic design 7
(Sum term)
2) POS : Product Of Sum
2
3
(sum term)
A B C
A B
A 0 0 A+B A 0 0 0 A +B +C
B Q B Q 0 0 1 A +B +C
0 1 A+B
C
1 0 A+B 0 1 0 A +B +C
1 1 A+B 0 1 1 A +B +C
1 0 0 A +B +C
1 0 1 A +B +C
1 1 0 A +B +C
1 1 1 A +B +C
(sum term)
2
A=0 A
A=1 A A
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6562211 digital logic design 8
K-map (SOP 2 )
2
K-map
2
= 22 = 4 () A B 0 1
Dec. A B AB AB
A 0 0 1
B Q 0 0 0 AB AB AB
1 2 3
1 0 1 AB
AB A, B
2 1 0
A, B
3 1 1 AB product term)
A=0 B=0
AB
(product term)
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6562211 digital logic design 9
K-map (SOP 3 )
3
K-map
3
= 23 = 8 ()
A BC 00 01 11 10
Dec. A B C
ABC ABC ABC ABC
0 0 0 0 A B C 0 0 1 3 2
A
B Q 1 0 0 1 A B C ABC ABC ABC ABC
1 4 5 7 6
C 2 0 1 0 A B C
A=0 B=0 C=0
3 0 1 1 A B C
A B C
A, B,C
4 1 0 0 A B C
5 1 0 1 A B C
6 1 1 0 A B C
7 1 1 1 A B C
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6562211 digital logic design 10
K-map (SOP 4 )
4
Dec. A B C D K-map
4
0 0 0 0 0 A B CD
1 0 0 0 1 A B CD
0 0 1 0 A B CD AB CD 00 01 11 10
2
= 24 = 16 3 0 0 1 1 A B CD ABCD ABCD ABCD ABCD
()
00 0 1 3 2
4 0 1 0 0 A B CD
ABCD ABCD ABCD ABCD
5 0 1 0 1 A B CD 01 4 5 7 6
A 6 0 1 1 0 A B CD ABCD ABCD ABCD ABCD
B Q 7 0 1 1 1 A B CD 11 12 13 15 14
C 8 1 0 0 0 A B CD ABCD ABCD ABCD ABCD
D 10 8 9 11 10
9 1 0 0 1 A B CD
10 1 0 1 0 A B CD
A, B,C,D
11 1 0 1 1 A B CD
12 1 1 0 0 A B CD
A=0 B=0 C=0 D=0 13 1 1 0 1 A B CD
14 1 1 1 0 A B CD
A B C D 15 1 1 1 1 A B CD
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6562211 digital logic design 11
K-map
2 A B C D
3
= 22 = 4 = 2 = 8
3
A A
Q Q
B B
C
A B A B C
AB CD 00 01 11 10
A B 0 1 00 0 1 3 2
A BC 00 01 11 10 01 4 5 7 6
0 0 1
1 2 3 0 0 1 3 2 11 12 13 15 14
1 4 5 7 6 10 8 9 11 10
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6562211 digital logic design 12
Minimum SOP
K-map
2
A B 0 1 A B A B A B
0 1 0 1 0 1
0 0 1 0 0 1 0 0 1 0 0 1
1 2 3 1 2 3 1 2 3 1 2 3
K-map 2
A B 0 1 A B 0 1
0 0 1 0 0 1
1 2 3 1 2 3
K-map
2 4 8
K-map
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6562211 digital logic design 13
Minimum SOP
K-map
3
A BC 00 01 11 10 A BC 00 01 11 10 A BC 00 01 11 10
0 0 1 3 2 0 0 1 3 2 0 0 1 3 2
1 4 5 7 6 1 4 5 7 6 1 4 5 7 6
2
4
4
K-map 3
A BC 00 11 10 A BC 00 11
01 01 10
0 0 1 3 2 0 0 1 3 2
1 4 5 7 6 1 4 5 7 6
K-map
2 4 8
K-map
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6562211 digital logic design 14
Minimum SOP
K-map
4
AB CD AB CD
AB CD00 01 11 10 00 01 11 10 00 01 11 10
00 0 1 3 2 00 0 1 3 2 00 0 1 3 2
01 4 5 7 6 01 4 5 7 6 01 4 5 7 6
11 12 13 15 14 11 12 13 15 14 11 12 13 15 14
10 8 9 11 10 10 8 9 11 10 10 8 9 11 10
4
4
8
AB CD AB CD
AB CD00 01 11 10 00 01 11 10 00 01 11 10
00 0 1 3 2 00 0 1 3 2 00 0 1 3 2
01 4 5 7 6 01 4 5 7 6 01 4 5 7 6
11 12 13 15 14 11 12 13 15 14 11 12 13 15 14
10 8 9 11 10 10 8 9 11 10 10 8 9 11 10
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2
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6562211 digital logic design 15
K-map
(SOP)
: 2
: 1
K-map
A, B
K-map
input output A+B
Dec. A B Q(A,B) A B
A 0 1
Q
B 0 0 0 AB 0 AB AB
1 0 1 AB 1 0 1
0 0 1 B
2 1 0 AB 1 A AB AB
1 1
3 1 1 AB 1 1 2 3
A=0 B=0 AB+AB=A(B+B) =A1=A
AB
AB+AB=B(A+A) =B1=B
(SOP)
Q(A,B) = (AB) + (AB) + (AB)
Q(A,B) = (AB) + (AB) +(AB)
K-map
Q(A,B) = (A+B)
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6562211 digital logic design 16
2
(POS)
: 2
: 1 K-map
A, B
K-map
input output AB
Dec. A B Q(A,B) A B
A 0 1
Q
B 0 0 0 A+B 1 A A+B A+B
1 0 1 A+B 0 1 0 B
0 0 1
2 1 0 A+B 0 A+B A+B
3 1 1 A+B 0 0 2 0 3
1
A=0 B=0
(A+B)(A+B)=B+(AA) =B+(0)=B
(POS)
Q(A,B) = (AB)
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6562211 digital logic design 17
3
(SOP)
: 3
: 1
A=0 B=0 C=0
A B C
K-map K-map
AB 00 0
AB 01 1
AB 10 2
AB 11 3
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6562211 digital logic design 20
: 7
(SOP) :2 : 7
0-1-2-3
00-01-10-11
A a input output
B
A b Dec. A B a b c d e f g
B 0 0 0 AB 1 1 1 1 1 1 0
A c
B 1 0 1 AB 0 1 1 0 0 0 0
A d 1 1 0 1 0 1
2 1 0 AB 1
B
A e 3 1 1 AB 1 1 1 1 0 0 1
B
f K-map a
A
2
B
A g A+B
B A B 0 1
AB+AB=A(B+B) =A1=A AB AB
1 0
AB+AB=B(A+A) =B1=B 0 0 1 B
AB AB
1 1
a = A+B 1 2 3
A
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6562211 digital logic design 21
: 7
(SOP) :2 : 7
0-1-2-3
00-01-10-11
A a input output
B
A b Dec. A B a b c d e f g
B
A c 0 0 0 AB 1 1 1 1 1 1 0
B
A d 1 0 1 AB 0 1 1 0 0 0 0
B 2 1 0 AB 1 1 0 1 1 0 1
A e
B 3 1 1 AB 1 1 1 1 0 0 1
A f
B K-map
a
A g
2
d
B A+B a
AB+AB=A(B+B) =A1=A A B 0 1
AB AB
AB+AB=B(A+A) =B1=B
1 0
1
a = A+B 0 0
AB AB
B
1 1
d = A+B 1 2 3
A
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6562211 digital logic design 22
: 7
(SOP) :2 : 7
0-1-2-3
00-01-10-11
A a input output
B
A b Dec. A B a b c d e f g
B
A 0 0 0 AB 1 1 1 1 1 1 0
c
B 1 0 1 AB 0 1 1 0 0 0 0
A d
B 2 1 0 AB 1 1 0 1 1 0 1
A e 3 1 1 AB 1 1 1 1 0 0 1
B
A f K-map
b
B
2
A g
B A B 1
0 1
=AB+AB+AB+AB AB AB
=(AB+AB)+(AB+AB) 1 1
=A(B+B)+A(B+B) 0 0 1
=A(1)+A(1) = A+A = 1 AB AB 1
1 1
b = 1 1 2 3
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6562211 digital logic design 23
: 7
(SOP) :2 : 7
0-1-2-3
00-01-10-11
A a input output
B
A b Dec. A B a b c d e f g
B 0 0 0 AB 1 1 1 1 1 1 0
A c
B 1 0 1 AB 0 1 1 0 0 0 0
A d 1 1 0 1 0 1
2 1 0 AB 1
B
A e 3 1 1 AB 1 1 1 1 0 0 1
B
f K-map c
A
2
B
A g A+B
B A B 0 1
AB+AB=A(B+B) =A1=A AB AB
1 1 A
AB+AB=B(A+A) =B1=B 0 0 1
AB AB
0 1
c = A+B 1 2 3
B
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6562211 digital logic design 24
: 7
(SOP) :2 : 7
0-1-2-3
00-01-10-11
A a input output
B
A b Dec. A B a b c d e f g
B
A c
0 0 0 AB 1 1 1 1 1 1 0
B 1 0 1 AB 0 1 1 0 0 0 0
A d
B 2 1 0 AB 1 1 0 1 1 0 1
A e 3 1 1 AB 1 1 1 1 0 0 1
B
A f K-map
e
B
2
A g B
B A B 0 1
AB AB
1 0
AB+AB=B(A+A) =B1=B 0 0 1
B
AB AB
1 0
e = B 1 2 3
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6562211 digital logic design 25
: 7
(SOP) :2 : 7
0-1-2-3
00-01-10-11
A a input output
B
A b Dec. A B a b c d e f g
B
A c
0 0 0 AB 1 1 1 1 1 1 0
B 1 0 1 AB 0 1 1 0 0 0 0
A d
B 2 1 0 AB 1 1 0 1 1 0 1
A e 1 1 1 0 0 1
3 1 1 AB 1
B
A f K-map f
2
B
A g AB
B A B 0 1
AB AB
1 0
0 0 1
AB AB
f = AB 1
0
2
0
3
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6562211 digital logic design 26
: 7
(SOP) :2 : 7
0-1-2-3
00-01-10-11
A a input output
B
A b Dec. A B a b c d e f g
B
A c
0 0 0 AB 1 1 1 1 1 1 0
B 1 0 1 AB 0 1 1 0 0 0 0
A d
B 2 1 0 AB 1 1 0 1 1 0 1
A e 3 1 1 AB 1 1 1 1 0 0 1
B
A f K-map
g
B
2
A g A
B A B 0 1
AB AB
0 0
AB+AB=A(B+B) =A1=A 0 0 1
A
AB AB
1 1
g = A 1 2 3
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6562211 digital logic design 27
: 7
(SOP)
0-1-2-3
00-01-10-11
3
0
a = A+B
b =1
c = A+B
d = A+B
e = B
f = AB
g = A
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: 7
0 1
00 01
2 3
10 11
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4
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1.
2.
2-3-4
SOP POS
3.
K-map
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