6562211

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 6562211

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5




1

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 5

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6562211 digital logic design 5
 : (Flip-Flop)
1. Flip-flop 1
2. Flip-flop :T Flip-flop, D Flip-flop,
RS Flip-flop, JK Flip-flop
3. Flip-flop

4. Flip-flop 2
5. logic gate Flip-flop
logic gate
Flip-flop

6. Flip-flop

7. -
/ Flip-flop
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6562211 digital logic design 6


1. 2
1 combinational logic circuit


AND, OR, NOT
2 sequential logic circuit

Flip-flop
counter, shift register,
memory
sequential logic circuit
Asynchronous ( ) / Synchronous
( )

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2

1) combinational logic circuit
2) memory element
Digital system combinational
Combinational logic circuit 2
logic circuit
A
B 1

C
D 2



logic gate

Flip-flop
Flip-flop

Memory element
Latch bistable multivibrator
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6562211 digital logic design 8
SR flip-flop

input output operation

: Q(t), Q(t) S R Q(t+1) Q(t+1)

S Q 0 0 Q(t) Q(t) hold

1 0 1 0 set
R Q 0 1 0 1 reset
1 1 x x undefined

set reset hold set hold hold reset hold

Q(t)

Q(t)
t0 t1 t2 t3 t4 t5 t6 t7
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6562211 digital logic design 9
SR flip-flop
1 ( asynchronous)
S R Q(t+1) Q(t+1)
S Q 0 0 Q(t) Q(t) Hold
0 1 0 1 Reset
R Q 1 0 1 0 Set
1 1 x x NC
S-R Flip-flop

set reset hold reset set set reset hold reset set hold hold reset hold

Q
t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13
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6562211 digital logic design 10
SR flip-flop Positive Edge triggering
2 ( synchronous) clk
S R Pos.Edge Neg.Edge Q(t+1) Q(t+1)
S Q
0 0 Q(t) Q(t) Hold
clk Positive
0 1 0 1 Reset Edge
R Q trigggering
1 0 1 0 Set
1 1 x x NC
Negative
Edge
set reset hold reset set set reset hold reset set hold hold reset hold trigggering

Q
t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13
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6562211 digital logic design 11
SR flip-flop Negative Edge triggering
2 ( synchronous) clk
S R Pos.Edge Neg.Edge Q(t+1) Q(t+1)
S Q
0 0 Q(t) Q(t) Hold
clk Positive
0 1 0 1 Reset Edge
R Q trigggering
1 0 1 0 Set
1 1 x x NC
Negative
clk Edge
set reset hold reset set set reset hold reset set hold hold reset hold trigggering

Q
t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13
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6562211 digital logic design 12
 JK Flip-Flop


JK Flip-Flop input output operation
set-reset-hold-toggle J K Q(t+1) Q(t+1)

J Q 0 0 Q(t1) Q(t) hold

1 0 1 0 set
K Q 0 1 0 1 reset
1 1 Q(t) Q(t) toggle

set reset hold toggle toggle toggle reset hold

Q(t)

Q(t)
t0 t1 t2 t3 t4 t5 t6 t7
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6562211 digital logic design 13
JK flip-flop
1 ( asynchronous)
J K Q(t+1) Q(t+1)
J Q 0 0 Q(t) Q(t) Hold
0 1 0 1 Reset
K Q 1 0 1 0 Set
1 1 Q(t) Q(t) Toggle
J-K Flip-flop

set reset hold toggle set toggle reset hold toggle set toggle hold reset toggle

Q
t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13
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6562211 digital logic design 14
JK flip-flop Positive Edge triggering


( synchronous) clk
J K Pos.Edge Neg.Edge Q(t+1) Q(t+1)
J Q
0 0 Q(t) Q(t) Hold
clk Positive
0 1 0 1 Reset Edge
K Q trigggering
1 0 1 0 Set
1 1 Q(t) Q(t) Toggle
Negative
Edge
set reset hold reset set toggle reset hold reset toggle hold hold reset hold trigggering

Q
t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13
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6562211 digital logic design 15
JK flip-flop Negative Edge triggering


( synchronous) clk
J K Pos.Edge Neg.Edge Q(t+1) Q(t+1)
J Q
0 0 Q(t) Q(t) Hold
clk Positive
0 1 0 1 Reset Edge
K Q trigggering
1 0 1 0 Set
1 1 Q(t) Q(t) Toggle
Negative
Edge
set reset hold reset set toggle reset hold reset toggle reset hold reset hold trigggering

Q
t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13
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6562211 digital logic design 16
D flip-flop Positive edge triggering


( synchronous) clk
D Q D Pos.Edge Neg.Edge Q(t+1) Q(t+1)
clk 0 0 1 Positive
Q Edge
1 1 0 trigggering

Negative
Edge
trigggering

clk

D D=0 D=1 D=0 D=0

Q Q=0 Q=1 Q=0 Q=0

Q
t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13
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6562211 digital logic design 17
D flip-flop Negative Edge triggering


( synchronous) clk
D Q D Pos.Edge Neg.Edge Q(t+1) Q(t+1)
clk 0 0 1 Positive
Q Edge
1 1 0 trigggering

Negative
Edge
clk trigggering

D D=0 D=1 D=0 D=0

Q Q=0 Q=1 Q=0 Q=0

Q
t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13

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6562211 digital logic design 18
D flip-flop SR flip-flop
SR Flip-Flop hold RS
D flip-flop
clk
S R Pos.Edge Neg.Edge Q(t+1) Q(t+1)
S Q
0 0 Q(t) Q(t) Hold
Positive
0 1 0 1 Reset
R Q Edge
1 0 1 0 Set trigggering
clk
1 1 x x NC
Positive edge triggering Negative
Edge
set reset set reset set set reset reset reset set set set reset reset trigggering

D=1 D=0 D=0 D=1

S

Q=1 Q=0 Q=0 Q=1

Q

Q
t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13
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6562211 digital logic design 19
D flip-flop JK flip-flop
hold toggle JK
D flip-flop
J K Pos.Edge Neg.Edge Q(t+1) Q(t+1) clk
J Q
0 0 Q(t) Q(t) Hold
0 1 0 1 Reset Positive
K Q
1 0 1 0 Set Edge
clk trigggering
1 1 Q(t) Q(t) toggle
Positive edge triggering
Negative
set reset set reset set set reset reset reset set set set reset reset Edge
trigggering
D=1 D=0 D=0 D=1
J

Q=1 Q=0 Q=0 Q=1

Q

Q
t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13
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6562211 digital logic design 20
JK flip-flop with clear and preset
Negative edge triggering ( synchronous)

pre
J K Pre Clr Neg.Edge Q(t+1) Q(t+1)
J Q x x 0 0 x undefined
- -
clk Reset
x x 1 0 0 1
Q
K x x 0 1 1 0 Set
x x 1 1 Q(t) Q(t) hold
clr

reset set hold reset reset hold reset hold reset set set hold reset hold

Pre

Clr

Q
t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13
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6562211 digital logic design 21
 JK Flip-Flop

J Q Input output operation
J K Q(t+1) Q(t+1)

K Q 0 0 Q(t) Q(t) hold JK Flip-Flop
1 0 1 0 set set-
reset 0 1 0 1 reset reset-hold-toggle
hold
1 1 Q(t) Q(t) toggle
J

t=0; Q(t+1)=Q(0+1) Q(t=1)
Q(t)=Q(0) Q(t=0)
Q(t) J K Q(t+1)

0 0
K Q(t) J K Q(t+1)
0 1 reset

0 0
0 1 reset
Q(t) 0 0 hold
Q(t) J K Q(t+1) 0 X

Q(t)
0 0 0
0 hold
T=0 T=1
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6562211 digital logic design 22
 JK Flip-Flop

J Q input output operation
J K Q(t+1) Q(t+1)

K Q 0 0 Q(t) Q(t) hold JK Flip-Flop
1 0 1 0 set set-
set 0 1 0 1 reset reset-hold-toggle
toggle 1 1 Q(t) Q(t) toggle

t=0; Q(t+1)=Q(0+1) =Q(1)
J
Q(t)=Q(0) =Q(0)
Q(t) J K Q(t+1) Q(t) J K Q(t+1)

0 1 0 1
K 1 0 set
1 0 set toggle
1 1
Q(t) 1 X
Q(t) J K Q(t+1)

Q(t) 0 1 1
1 toggle
T=0 T=1
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6562211 digital logic design 23
 JK Flip-Flop

J Q input output operation


J K Q(t+1) Q(t+1)
JK Flip-Flop
0 0 Q(t) Q(t) hold
K Q set-
1 0 1 0 set
reset-hold-toggle
reset 0 1 0 1 reset
toggle 1 1 Q(t) Q(t) toggle

J
t=0; Q(t+1)=Q(0+1) =Q(1)
Q(t)=Q(0) =Q(0)
Q(t) J K Q(t+1) Q(t) J K Q(t+1)

1 0 1 0
K 0 1 reset
0 1 reset toggle
1 1
Q(t) X 1
Q(t) J K Q(t+1)

Q(t)

T=0 T=1
111 0 toggle

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6562211 digital logic design 24
 JK Flip-Flop

J Q input output operation


J K Q(t+1) Q(t+1)
JK Flip-Flop
0 0 Q(t) Q(t) hold
K Q set-
1 0 1 0 set
reset-hold-toggle
set 0 1 0 1 reset
toggle
1 1 Q(t) Q(t) toggle

J
t=0; Q(t+1)=Q(0+1) =Q(1)
Q(t)=Q(0) =Q(0)
Q(t) J K Q(t+1) Q(t) J K Q(t+1)

1 1 1 1
K 1 0 set
1 0 set
0 0 hold
Q(t) X 0
Q(t) J K Q(t+1)

Q(t)

T=0 T=1
1 0 0
1 hold
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6562211 digital logic design 25
JK Flip-Flop

Q(t+1)

JK Flip-Flop

Q(t)
set-
Q(t) J K Q(t+1)
reset-hold-toggle
Q(t) J K Q(t+1)

0 0 0 1
0 1 reset 1 0 set
0 0 hold 1 1 toggle
0 X 1 X

Q(t) J K Q(t+1) Q(t) J K Q(t+1)

1 1
set
1 0
0 1 reset 1 0
1 1 toggle 0 0 hold
X 1 X 0

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6562211 digital logic design 26
 0-3-6
Q(t) J K Q(t+1) Q(t) J K Q(t+1)

0 1 reset 1 0 set

0 0 0 0 hold 1 0 0 1 hold JK Flip-Flop
0 X X 0 set-
Q(t) J K Q(t+1) Q(t) J K Q(t+1) reset-hold-toggle
1 0 set 0 1 reset
0 1 1 1 toggle 1 1 1 0 toggle

1 X
1
X 1




1
0-3-6 JK
Q(t) Q(t+1)

Dec. A B C Dec. A B C
0 0 0 0 3 0 1 1

3 0 1 1 6 1 1 0

6 1 1 0 0 0 0 0
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6562211 digital logic design 27
 0-3-6
Q(t) J K Q(t+1) Q(t) J K Q(t+1)

0 1 reset 1 0 set

0 0 0 0 hold 1 0 0 1 hold JK Flip-Flop
0 X X 0 set-
reset-hold-toggle
Q(t) J K Q(t+1) Q(t) J K Q(t+1)

1 0 set 0 1 reset
0 1 1 1 toggle 1 1 1 0 toggle
1 X X 1

1
0-3-6
Q(t)
Q(t+1) FFA FFB FFC
Dec. A B C Dec. A B C JA KA JB KB JC KC
0 0 0 0 3 0 1 1 0 X 1 X 1 X
3 0 1 1 6 1 1 0 1 X X 0 X 1
6 1 1 0 0 0 0 0 X 1 X 1 0 X
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6562211 digital logic design 28
 0-3-6

1
0-3-6
Q(t)
Q(t+1) FFA FFB FFC
Dec. QA QB QC Dec. QA QB QC JA KA JB KB JC KC
0 0 0 0 31 0 1 1 0 X 1 X 1 X
3 0 1 1 6 1 1 0 1 X X 0 X 1
6 1 1 0 0 0 0 0 X 1 X 1 0 X
J K QA QB QC K-map
2



0-3-6 dont care term(X)
2.1 JA KA QA K-map
QBQC QBQC
00 01 11 10 QA 00 01 11 10
QA ABC ABC ABC ABC ABC ABC
ABC ABC
0 0 0 X 1 1 3 X 2 0 X 0 X 1 X 3 X 2
ABC ABC ABC ABC ABC ABC ABC ABC
1 X 4 X 5 X 7 X 6 1 X 4 X 5 X 7 1 6

QB JA = QB 1 KA = 1
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6562211 digital logic design 29
 0-3-6

1
0-3-6
Q(t)
Q(t+1) FFA FFB FFC
Dec. QA QB QC Dec. QA QB QC JA KA JB KB JC KC
0 0 0 0 3 0 1 1 0 X 1 X 1 X
3 0 1 1 6 1 1 0 1 X X 0 X 1
6 1 1 0 0 0 0 0 X 1 X 1 0 X
J K QA QB QC K-map ()
2



0-3-6 dont care term(X)
2.2 JB KB QB K-map

QBQC QBQC
00 01 11 10 QA 00 01 11 10
QA ABC ABC ABC ABC ABC ABC
ABC ABC
0 1 0 X 1 X 3 X 2 0 X 0 X 1 0 3 X 2
ABC ABC ABC ABC ABC ABC ABC ABC
1 X 4 X 5 X 7 X 6 1 X 4 X 5 X 7 1 6

1 JB = 1 QC KB = QC
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6562211 digital logic design 30
 0-3-6

1
0-3-6
Q(t)
Q(t+1) FFA FFB FFC
Dec. QA QB QC Dec. QA QB QC JA KA JB KB JC KC
0 0 0 0 3 0 1 1 0 X 1 X 1 X
3 0 1 1 6 1 1 0 1 X X 0 X 1
6 1 1 0 0 0 0 0 X 1 X 1 0 X

2 J K QA QB QC K-map ()

QB
0-3-6 dont care term(X)
2.3 JC KC QC K-map

QBQC QBQC
00 01 11 10 QA 00 01 11 10
QA ABC ABC ABC ABC ABC ABC
ABC ABC
0 1 0 X 1 X 3 X 2 0 X 0 X 1 1 3 X 2
ABC ABC ABC ABC ABC ABC ABC ABC
1 X 4 X 5 X 7 0 6 1 X 4 X 5 X 7 X 6

QA JC = QA 1 KC = 1
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6562211 digital logic design 31

1
0-3-6
Q(t)
Q(t+1) FFA FFB FFC
Dec. QA QB QC Dec. QA QB QC JA KA JB KB JC KC
0 0 0 0 3 0 1 1 0 X 1 X 1 X
3 0 1 1 6 1 1 0 1 X X 0 X 1
6 1 1 0 0 0 0 0 X 1 X 1 0 X
J K QA QB QC K-map
2

JA = QB QB

3
K
KAA =
=11
JB = 1
KB = QC JA QA JB QB JC QC
JC = QA
KA QA KB QB KC QC
KC = 1

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6562211 digital logic design 32
 0-3-6

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 5

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1. (Flip-flop)

2.


3.
4.

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36