6562211

2 2

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 6562211

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 2

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2 2


8

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1) 5)
A A A
AB A+B
B B (A+B)(C+D)
1
2) C
A A D
A+B C+D
B

3) 6)

A A AB A AB
B B
1
4) C
A A D (AB)+(CD)
1 AB CD
B
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 (2)
7)
AB
A (AB)C
B
((AB)C)+(DE)
C
(DE)
D 1
E

Q = ((AB)C)+(DE)

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 (3)
8)

AB
A (AB)+C
B ((AB)+C)D

C
1
D (EF)
E
F
(((AB)+C)D)+(EF)



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 (4)
9)

A+B
A (A+B)C
B

C
1

D
E
((A+B)C)+(DE)
(DE)



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 (5)
10)
(AB)
A (AB)(CD)
B
(CD)
C
D
(A+B)
A (A+B)+(C+D)
B
(C+D)
C
D
(A+B)
A (A+B)(C+D)
B
(C+D)
C
D
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 (5)
11) A (AB)
B (AB)+(CD)
(CD)
C
D
(A+B)
A (A+B)(CD)
B
(CD)
C
D
(A+B)
A (A+B)(C+D)
B
(C+D)
C
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6562211 digital logic design 11
 (5)
12) (AB)
A (AB)(CD)
B
(CD)
C
D

(AB)
A (AB)+(CD)+(EF)
B
(CD)
C
D
(EF)
E
F
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6562211 digital logic design 12


A B Q = (A AND B) = (A B)

0 0 0

0 1 0

1 0 0 1 1
1 1 1

A

t0 t1 t2 t3 t4 t5 t6 t7 t8
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A B Q = (A AND B) = (A B)

0 0 0

0 1 0

1 0 0 1 1
1 1 1

A

t0 t1 t2 t3 t4 t5 t6 t7 t8

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A B Q = (A OR B) = (A + B)

0 0 0
0 1 1

1 0 1
1 1 1

A

t0 t1 t2 t3 t4 t5 t6 t7 t8

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A B Q = (A NAND B) = (A B)

0 0 1
0 1 1

1 0 1
1 1 0

A

t0 t1 t2 t3 t4 t5 t6 t7 t8
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A B Q = (A NOR B) = (A + B)

0 0 1
0 1 0

1 0 0
1 1 0

A

t0 t1 t2 t3 t4 t5 t6 t7 t8
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A B Q = (A XOR B) = (A B)

0 0 0
0 1 1

1 0 1
1 1 0

A

t0 t1 t2 t3 t4 t5 t6 t7 t8
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A B Q = (A XNOR B) = (A B)

0 0 1
0 1 0

1 0 0
1 1 1

A

t0 t1 t2 t3 t4 t5 t6 t7 t8
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A A A AB
AB
Input A input B

B 0 1 0 0
0 1 1 1


1 0 0 0
1 0 1 0
A
0 0 1 1
A
1 1 0 0
B
0 1 0 1
Q
t0 t1 t2 t3 t4 t5 t6 t7 t8
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A A
Input A A Input B A+B
A+B 0 1 0 1
B
0 1 1 1

1 0 0 0
1 0 1 1
A

Q
t0 t1 t2 t3 t4 t5 t6 t7 t8
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A AB
A A
Input A Input B
AB 0 1 0 1
B
0 1 1 0

1 0 0 0
1 0 1 1
A

Q
t0 t1 t2 t3 t4 t5 t6 t7 t8
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A AB
A A
Input A Input B
AB 0 1 0 1
B
0 1 1 0

1 0 0 0
1 0 1 1
A

Q
t0 t1 t2 t3 t4 t5 t6 t7 t8
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6562211 digital logic design 23

A B C AB ABC A AB ABC
0 0 0 0 0
B
1
0 1 0 0 0 C
1 0 0 0 0
A0 0 1 1 0 0 1 1 0 1 1 0
1 1 0 1 0
0 0 1 0 0 B 0 1 0 1 0 1 0 1 0 1 0 1
0 1 1 0 0 0
1 0 1 0 0 C0 0 0 0 1 1 1 1 1 1 1 0
1 1 1 1 1

AB 0 0 0 1 0 0 0 1 0 1 0 0
0

ABC 0 0 0 0 0 0 0 1 0 1 0 0
t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11
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6562211 digital logic design 24

A B C A+B (A+B)C A A+B
0 0 0 0 0 B (A+B)C
1
0 1 0 1 0 C
1 0 0 1 0
A 0 0 1 1 0 0 1 1 0 1 1 0
1 1 0 1 0
0 0 1 0 0
B 0 1 0 1 0 1 0 1 0 1 0 1
0 1 1 1 1 0
1 0 1 1 1
C 0 0 0 0 1 1 1 1 1 1 1 0
1 1 1 1 1

A+B 0 1 1 1 0 1 1 1 0 1 1 1

(A+B)C 0 0 0 0 0 1 1 1 0 1 1 0
t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11
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A B C A+B (A+B)C A A+B
0 0 0 0 0 B (A+B)C
1
0 1 0 1 0 C
1 0 0 1 0
A0 0 1 1 0 0 1 1 0 1 1 0
1 1 0 1 0
0 0 1 0 0
B 0 1 0 1 0 1 0 1 0 1 0 1
0 1 1 1 1 0
1 0 1 1 1
C 0 0 0 0 1 1 1 1 1 1 1 0
1 1 1 1 1

A+B 0 1 1 1 0 1 1 1 0 1 1 1

(A+B)C 0 0 0 0 0 1 1 1 0 1 1 0
t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11
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 8

1 E
4 A
0000 1010 0 A
E A
11100000 E 0
AND
:
1


1

XOR
:
1

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 8

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1 0100 1
0
0 0111 0 0
1
1 0000 1 0

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1 01 0 0 1

0 01 1 1 0

0 1 0 0 0 0

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 2

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1.
2. NOT-AND-OR-
XOR-NAND-NOR-XNOR
3.
4.
5.

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6562211 digital logic design 35