module afisaj7seg (input [3:0] in,

output reg [6:0] out);

always@*
case (in)
0: out = 7'b0001000;

1: out = 7'b1101110;

2: out = 7'b0000011;

3: out = 7'b0000110;

4: out = 7'b1100101;

5: out = 7'b1000100;

6: out = 7'b1000000;

7: out = 7'b0101110;

8: out = 7'b0000000;

9: out = 7'b0000100;

10: out = 7'b0100000;

11: out = 7'b1000001;

12: out = 7'b1010000;

13: out = 7'b0000011;

14: out = 7'b1010000;

15: out = 7'b1110000;

endcase

endmodule