A4 Boards Systems grow! | personally remember a project where | started out expect- ing that the code would fit in 4 K on-chip. At last report the code had gone off-chip and grown to use most of 64 K—the entire address space. J suspect the bulk of the code was not elaborate algorithms, but rather extensive user- prompt messages to send to the display. Nevertheless, the foiks at Keil tell me that the majority of the applications they encounter are ones with code far beyond the 2 K that they offer in the compiler version with this book.' Chapter 2 illustrates the addition of off-chip ROM, RAM, and I/O de- vices. When you hit the 64 K (16-bit addressing) limit for code you have two options. You can migrate to 16-bit processors such as Intel's x86 fam- ily, the 8096 family, or Motorola’s 68000 family.” Alternatively, if you are reluctant to abandon your existing code and experience, you can go to bank switching where some port pins serve as additional address tines. 1 describe the hardware for that first, ‘Obviously they hope that any commercial user will tum around and buy the version for larger code modiites, although they assure me the included version is full-featured in every other respect. 2There are two families of code-compatible processor families now—the 251 family (Tniel) and 8951EX family (Phillips). 390Appendix 4 Boards 391 Next I discuss two development boards—the MCB520°hoard from Kei} with the Dallas 520 (available with an 8031 as well) and the PUSS2 hoard developed at Purdue using the ‘552." BANK-SWITCHING CODE What do you do if 64 K (sixteen address lines) is not enough? First you should look closely at code efficiency and your whole approach, but assum- ing that doesn’t reveal any significant savings, you can go to bank switch- ing. It involves having more than 64 K of total code with additional hard- ware to direct the code access to different blocks of code at different times. One to four port pins that are changed by software before a given bank is addressed supplement the sixteen address lines.* The process is best done while the program counter is in a space that does not change (called the common space—perhaps the lower 32 K). Then the various functions or code arrays that are switched in and out can be located in various 32 K upper banks.> A schematic of a bank-switched design is shown next. If you look closely, this is a configuration with 512 K (64 K X 8) EPROMs so each one occupies the entire data space. The upper 3 hits of P! control the hank selec- tion.® The 74LS138 decodes this into the chip selects for the individual EPROMs. For power consumption reasons it is better to drive the OE/ line from PSEN and let the decoder drive the CS/ lines. That way the nonse- lected chips do not go through the internal fetching with the corresponding power drain, *Dr. Richard Barnett, an associate of mine in the Electrical Engineering Technology Depart- ment (and author of The 80S! Family of Microcontrollers [1995 Prentice Hall, Englewood Cliffs, NI (ISBN 0-02-306281-9)]) originally developed the 552 board. The board was re- vised by Rostek John Rosheck) who is now handling the marketing and production (see Ap- pendix AG for addresses for these boards as well as a number of other suppliers). “This is analogous to the four register banks in the idata space. When the software. switches toa different hank it must first change 2 bits in the PSW register, “It is possible to instead bank switch the entire 64 K space, given a duplicate image of the common code area at the same place in each bank. That may seem wasteful of EPROM, but with 27C512s being quite affordable, it can actually involve less hardware and cost as well as allowing for a smaller common space. “Actually, with only four banks it could be done with 2 bits but [ decided to show an expand- able arrangement. This could hold eight banks—Keil/Franklin supports up to sixteen banks. hut somewhere you have to give up.392 Section \V_ Appendices s[o-Fwe_10 co a ijn & “else aa a oe 3 cele a Bos 8 aslo as is os be oda eye & ae cee lo Sol i pe © cela as he Eo alo7 yar] a7 7 i o7| wee WB os ne one sox ie Bee rea|o 6 z 2 rg 3 tes an g Siaszaas 3]5)3]s1=Tslel= [ee 29] oO on 02 onl 05 os los | los os} jos 6] jor orto _a07, ow suo he vec ae ce ie Bank-switched EPROM With the circuit configuration shown, you would duplicate the com- mon code in each of the EPROMs but the code for a given bank would ap- pear in just one of the chips (usually in the higher address space), You can do your own bank-switching in assembly (or perhaps in C), but Keil/Franklin tools are very amenable to doing bank switching for you.” Compile or assemble the various modules in the usual manner and then use the banked linker/locator (BL51) to direct the code to the appropriate banks. The tinker then conveniently adds the bank-switching instructions so the en- "Technically 1 suppose you could get around the 2 K limit of the included tools by imple- menting your own switching and keeping all your code in 2 K banks, bul life is too short to expend all that effort!Appendix 4 Boards 393 tire process requires no user-written code to do the switching. You only specify the number of banks possible, the port or xdata address of the bank control logic, and the first bit of the port controlling the bank selection. The linker manual describes the details of setting up the banks. For best effi- ciency you should apportion your functions so that frequently used ones are in the common area. The changing of banks takes about fifty processor cy- cles and eats up 2 bytes of stack, so you do not want to be switching unnec- essarily. There are directives (BANKn, and COMMON) you can use within the modules or in invoking the linker/locator to determine where code func- tions or data will go.* PU552 MICROCONTROLLER BOARD The PUS52 board is a single-board computer intended for application in project development.” Features include: 1. The Phillips 83C552 microcontroller. The microcontroller features in- clude: * 256 bytes of internal RAM four 8-bit ports (+2 gone to off-chip expansion) eight channels of 10-bit A/D two pulse-width modulated outputs: A watch-dog timer An extensive counter array,” One serial port multiprocessor serial communications (17°C bus) 2. The board’s features additionally include: « An8 K ROM (replaceable with a 32 K) in off-chip code space . + *although the free Keil software includes a cobbled version of the banking linker, BLS1, | think anyone doing bank switching will have exceeded the 2 K limit and should buy the com- plete version of the Keil/Franklin € compiler with the manuals—get more information there! °This board’s initial development was made possible by Robert and Helen Hoffer via the Hoffer Plastics Foundation who provided the seed money to produce the original set of boards. In addition, the Signetics Company initially donated the 552 microcontrollers and the INTEL. Corporation donated the ROM memories. Dr. Richard H. Barnett, PE, designed the board. The monitor and test programs are likewise his work. "For further details, refer to the 80C552 specification and application notes from Philips/Sig- netics.394 Section IV Appendices + An 8 K RAM (replaceable with a 32 K) which may either appear both in xdata and code space or xdata space only * One serial RS-232 port (converts the on-chip UART to RS-232) * Accessible expansion bus connector with all necessary address. data, and control lines 3. In order to use the board for software development you must have: * APC with an uncommitted serial port (COM2, usually) ¢ A custom serial cable with a single-in-line connector on one end with transmit, receive, and ground signals! + A terminal emulator program or the freely available SEND31 pro- gram + Software development tools such as the C compiler and linker pro- vided with this hook Bas 4 es EY ove EI 8 Q.. 22 PortADC. Buss Connector RE RE 7a.S373 Oe a fi Serial Power MemConfig. U6 int = Pin #1 PU552-1 part layout (later versions have different layout) "'You may prefer to make up a DB-9 or DB-25 socket from the PU5S52 board and se con- ventional serial cables.Appendix 4 Boards 395 TFsev 400 075 Toso 40_s0fko Bln _Av0 Has 4 ‘ADI 12] on aye AL Ai sat orf AD Tap ela\ (252 6] 02 aa[o ae NY/ ra] a oe [sana +. aseNY A051 os asl7 as NY] as 29 [a0 lo 1faosNY76=-14 o« nae ae N/a a] ae oa eae as ole res 708g nes BN las sola Taps faosN|/n05 | 08S ne[e nee Tans St fae 6 sepNY-F6r | or $url ANU ara 8 or is aor aah sehaoe CS ECR Oe CC mea fave BS asleccreN recede Sala zee | [ther ssol amo NVR at| ato vm (2 wer ofS 24] eye: | ree 20l cer an [23a “Air_28] ait cero caRan ApS 26[ ena Zoe! an[z ae N/a 2 [ne a9 Be ander 20foene | [27] aw as5]267AS NY Atg 27] 08 ole Tope sole rot sof - - Maps stor PUSS2 BOARD jyra Mote: adaltlona! 4G ie 23/2 Sorcper 1 2(2(zlele(eelel ow hele ei £888 neh a oleate e ‘shown oo} 9}o}s)o)2|2/8]2| 8)2)8}=|2)2) #2) s)=] seseggesse 8 THESTS JEVBA PLD easeasesed g TR e]e]=/8]= 1 PPE P PPP alsialelslelels|=| & SE REBEL olelelélalaly 7 77 wv a/e/8/s/s/s/8/8/2/2/2|z/2/2/2/8| = 3 ‘al : felt 25 [s/alslalalalglalel=|s|als/9|2|5) Sb Bee eggegSgse8e eat Fw |e Pa) 9 fe Tper SER ES &A fae g ; ras ne bona ricapee voew [ar Foe, 8 10 rss wea Wey rn ror 31 [roy AE 2 [Prades non § ‘3 |rs6 v4 10 [aa YT rar 5ces2 ras wr fer 6 )ro MICROCONTROLLER —— an ber ane AE fh ers Tepe $8 ES zajr's 1 2. El a & fo ene “ont iy Blo a ozeend - TESSeeeeeee?e slat tots) aan on aT*]e}-/a/8] 3/8] 3/3) 8|8 SieEL fz m i? sesEg ra WDog ww 2832 2 we ale, Say babe vnineser 2 | | boorone]) PU552 SchematicAppendix 4 Boards 399 OPERATION As delivered, the PU552 will function with minimum setup. Connect the power pins to 5VDC and a serial cable to JP1. Connect your PC to the serial cable and start a communications program such as SEND31. Apply power to the PU552 and the monitor should sign on, ready for operation (in other words, PU> prompt should appear with sign-on message).'* You can test the PUSS2 by compiling and downloading the program shown here (you may need to modify the pathnames on the #include state- ments). This program will cause Port 4 to exactly duplicate the inputs on Port 5, and wil! blink alternate bits on Port | at a visible rate (it can be seen on LEDs—not provided). Likewise, the test program will echo any charac- ters typed at the keyboard ta the CRT and will exit to the monitor when a 0 (zero) is typed. /*Test Program for PU552 Board*/ #include #include void X0() interrupt 0 using 2 {} void TMO0() interrupt 1 using 2 (} void K1() interrupt 2 using 2 (} void TMI(\ interrupt 3 using 2 (1 void S0() interrupt 4 using 2 (} void S1() interrupt 5 using 2? {} void CTO{} interrupt 6 using 2 (} void CT1() interrupt 7 using 2 {)} void CT2({) interrupt 8 using 2 {} void CT3() interrupt 9 using 2 {} void ADC() interrupt 10 using 2 [} void CMO() interrupt 11 using 2 {} void CMi{} interrupt 12 using 2 {) void CM2{) interrupt 13 using 2 (} void TM2() interrupt 14 using 2 {} extern void gomon{); /*function to enter monitor*/ main() { unsigned int count; P1=0x55; /*set Port 1 starting value*/ while (SOBUF != 0x30) {/*loop while zero not typed*/ P4=P5; /*echo Port 5 to Port 4*/ count++; /*increment delay counter for LEDs*/ “Some details of the FET moniter are covered in Chapter 9 beginning on page 249,Section 'V_ Appendices if (count==10000) {/*change LEDs if time elapsed*/ count = 0; /*clear count for next cycle*/ Pi=~Pl; /*complement Port 1‘/ } VE(RT==1}(/*check for serial character received*/ RI=0; /*clear Receive flag*/ SORUFSSARTF: /*echo character to screen*/ ) } gomon(}; /*exit to monitor*/ MCB520 EVALUATION BOARD Keil Software, who provides the C compiler with this book, markets several boards including the one described here. This is a considerably more elaborate board than the PUSS2. It can be tun with a 87C51 or 87C52, but performs much faster with the Dallas 520 chip which runs instructions with fewer clock cycles and supports the sec- ond UART. 1, Features that distinguish this board from other 8051 boards: Tt includes 8 LEDs tied to port 1. It supports the 87C520's two serial ports with DB-9 cables. The MONS| program uses SIO}, so S100 is available for your programs. Jt runs directly off 5 V, but has an on-board voltage regulator and connector so it can run off, say, a 9 V wall transformer. Program development for most 8051-family target systems can use the same resources as the final version. The address decoding logic device relocates MONS 1 at 8000H on reset so downloaded programs can begin running at Q0OOH. The common serial port (0) is available during debugging because MONS uses port | (in the 520 only). It has switch settings to support up to four code banks using a 256 Kx 8 EPROM or FLASH memory device. The code banking is di- rectly supported by the compiler/linker which manages the banks by controlling address hits A16 and A17 from port pins (P1.6 and P1.7 respectively). It can support two 64 K byte banks of RAM (under direct user pro- gramming of port bit P1.5 to switch A16).Schematic The MCB520 Evaluation Board Schematic is below, ous Ti oo: [N21 50} 29_ 200, A s00_2[ tah Ao wofa poe RR] rat ane aor NAO 3]20 aa [row rani a 2 ps2imor 02 [57 _AD2 AN Ada 2] 8D tree) to § 2B NEPRNY 105 Benes roe slo soles N Ber fem Nepece soe fer aloo B fea) ran se co IQS Kspoen x toe fet ~a0s Caos 7]e0 8 aces Ye psewe ave [a8 ~ane AN area] 70 rps Whsr-xor 3407 [32 A07 AN A079] 80 ahaa, vr Broen Borate Rone: ale ela 420] vee solar ne Torr anole far tip mo pio 8 role—ao\ | > jas eA Z Po M0[ es no NSS as ose Pr ‘sir2 azar nO fo 00 0. as ale aos ata [25 a eae or fa_on a 3 25/674 ra N3[28 AS Az jx2 02 [0% ejaeaGm fo sige\Neee abe Jar © v1 PANT 6 ins[BTAB NN Be 8] 44 _ als 0a laa ™ 0 [a/v Vee|a0 as_7|ss 2 05[o os wer owolio_y “9 reser ale pe’ amelie & 05 [20 06 ae Es oes Seely eas s se pr fee peat noe |e vel = nose |? a ie msae no Nvee fhe Tor: Naw Jato ca2 [20 a0 ans ]ant anole 2 30 ne ave © csqeaT pee ar Ena 86 kear aso oes ae RAM le 5 i eanoes 7 34 (28 lp as PE 3 22 {2 10 at EX) ft Sopate” be 20 /% a 20S 19] Ha ery 2 18 28l2 Bis & 7 ala 7p & ON SAC 616 veol se aie ot Arla © vpplt 8 BNR poaro cols “Be bao 21 3 ho Boia _or uo v2 fs pe 1 Q oso os 8 maf De wo osha os 6 [20a on [zo Taye 20 uM Sense 4) FSH KA fe) pro rovoje Wear, pers a Ln301 sm