9/5/2011

Programable Programable Logic Array, c ma trn AND v OR

Array Logic (a) u lp trnh c.
Programable Tit kim dung lng ma trn.
ROM (b) B hn ch bi s lng cc cng AND khi s u vo
PAL thng mi ca cng OR ln hn s cng AND.
Tr truyn lan ln hn v mt tch hp nh.

Lp
trnh

A B C Yu cu: F = AB = ABC + ABC

email ktmt@soict.hut.edu.vn 49 email ktmt@soict.hut.edu.vn 50

Generic Array Logic nng FPGA gm 3 thnh phn chnh

cp t PAL, gm mt ma Khi logic Logic Block (LB): n v x l.
trn AND lp trnh c Khi Vo ra IO cell: giao tip vi bn ngoi.
(cu to t EEPROM) v
Lin kt ni Interconnection: lin kt cc n v x l.
ma trn OR c nh.
Tuy nhin, cc cng OR Configurable
Logic Block
nm trong cc macrocell
c ni vi flip-flop v cc Thnh phn khc I/O Block Connect
Connec
t
b dn knh c th chn Buffer
tn hiu ra. ClockDll
V d: Dng GAL iu khin
Tn gi chung ca cc thit n giao thng:
b nh PAL, PLA, GAL l
Programable Logic Device
email ktmt@soict.hut.edu.vn 51 email ktmt@soict.hut.edu.vn 52

1
 9/5/2011

1/3 2/3

C 3 thnh phn: khi logic, khi vo ra, lin kt Vi FPGA, lp trnh l qu trnh nh tuyn gia
ni, u lp trnh c. cc phn t logic, flipflop c ch to c
nh sn, thc thi mt tc v no .
Lp trnh cho khi logic l hnh ng: c kt ni
hay khng phn t logic A vi phn t logic B? Mt tuyn u c ch to sn, v nh km mt
kha ng m. Tuyn c thit lp hoc
Lp trnh cho khi vo ra l hnh ng: c kt ni
hy, tng ng vi trng thi kha ng hay m.
hay khng u ra logic A vi chun ngoi vi B?
Mi trng thi ca kha ng/m ng vi mt bit
Lp trnh cho lin kt ni l hnh ng: c kt ni
nh trng thi 0/1 tng ng.
hay khng khi logic A vi khi logic/vo ra B?
Tp hp cc bt nh to thnh b nh cu hnh
cho FPGA.

Bng nh tuyn c lu tr trong b nh.

Cng c CAD s dch HDL thnh bng nh tuyn.
email ktmt@soict.hut.edu.vn 53

LB

3/3
nh x vo
Phn tch FPGA c th Tt c ASIC lp trnh c, bao gm FPGA, u
cha cc khi logic (cell logic) c bn ging nhau
HDL RTL BIT file
c := a + b; 01000100
to thnh di.
if (c == 1) then cf := 1; 11010101
10001001
C 4 loi khi logic:
I/O Cell I/O Cell I/O Cell
Da vo bng tm kim
(LUT Lookup Table) Xilinx I/O
LB LB LB
I/O
Cell Cell
B nh cu hnh Da vo b ghp knh
I/O I/O
(Multiplexers) Actel Cell
LB LB LB
Cell

Da vo PAL/PLA I/O
LB LB LB
I/O
Altera Cell Cell

Transistor Pairs I/O Cell I/O Cell I/O Cell

email ktmt@soict.hut.edu.vn 55 email ktmt@soict.hut.edu.vn 56

2
 9/5/2011

1/3
RAM 16bit WE

A0 0 MUX Mux 2x1 c th Biu din

Bng tm kim, LUT, 0 0 G4
1 0 G
A1 1 thc hin c mc Look-Up Table, l mt 2 0
G3
G2
Func
Func..
Gen.
SRAM c K u vo vi
S G4 3 1 G1
cc hm bn transistor G3 4 1
SA G2
G1 5 1
2K bit nh, thc hin 6
7
1
1
1

Cu trc cell logic ACT 1 (n module) c mi hm logic c 8

9
0
0
G4

Cell ACT 1 ch c K bin. 10

11
1
0
G3
G2

mt module logic. Thng thng, K = 4.

12
13
0
0
G1

14 0
Cell ACT 2, 3 c 15 1

nhiu module Tn hiu ra ca mt LUT c th quay tr li, thnh

logic hn v c u vo ca chnh LUT , hoc LUT khc.
Flip Flop ring.
Trong mt LB, thng c 3 LUT v c gi l b
Cu to Flip Flop thc hin hm F, G v H.
email ktmt@soict.hut.edu.vn 57 email ktmt@soict.hut.edu.vn 58

2/3 3/3

Cc LUT F v G tng ng v c lp vi S liu a vo LB c th c x l bi cc hm

nhau, thc thi cc hm 4 bin v a kt qu tnh 4 u vo, c th c cht thanh ghi, c th
ton ra ngoi CLB, hoc nh vo FF. c chn knh, hoc bi c 3 thao tc trn.
Nu php ton c nhiu hn 4 bin th LUT F, G
s a kt qu ti LUT H m rng thm.
Flip-Flop ng vai tr:
Khi logic lp trnh
Bit nh hoc c, CLB, ca
XC4000 E/X
Cht d liu
Hai FF c th set/reset ng
b/khng ng b, tch cc
theo sn m/dng
Cu trc c bn ca LB dng LUT

email ktmt@soict.hut.edu.vn 59 email ktmt@soict.hut.edu.vn 60

3
 9/5/2011

Cn c gi l CrossPoint FPGA.
S lng cng t, ~ 4000
LE(LB) ca Altera Cyclone II

email ktmt@soict.hut.edu.vn 61 email ktmt@soict.hut.edu.vn 62

LB LB LB Ma trn i xng LB LB LB LB LB
Symmetrical Array
FPGA k tha nhiu tng thit k ca cc sn
phm trc
s quen thuc trong kin trc. LB LB LB LB LB LB LB LB
Nhng s chc nng, mc tch hp, kh nng
tnh ton ca tng n v x l trong FPGA c Cu trc dng
khc nhau, gm Coarse /k:s/ , v Fine. LB LB LB Row-based LB LB LB LB LB

Coarse-grained: n v x l l mt tp hp ca
cc PLD, cc khi cu hnh c CLB, thc thi Sea-of-Gates
c hm phc tp, c yu cu tnh ton ln. V PLD PLD

d: Actel Mux, Xilinx LUT. PLD PLD

Fine-grained: n v x l ch gm cc khi cu PLD phn cp

Hierarchical
PLD PLD

hnh c CLB nh, thc thi cc hm logic n (CPLD) PLD PLD

gin. V d Transistor Pairs.

email ktmt@soict.hut.edu.vn 63 email ktmt@soict.hut.edu.vn 64

4
 9/5/2011

1/3 2/3

Kt ni a nng Kt ni di Kt ni trc tip Kt ni di

LB LB Kt ni trc tip Kt ni a nng

Ma trn
SM SM SM
chuyn mch
Lin kt ni di, tn hiu clk lin thng ton b di.
Lin kt ni trc tip gia 2 khi LB.
Lin kt ni a nng gm nhiu kt ni v cc
chuyn mch.
email ktmt@soict.hut.edu.vn 65 email ktmt@soict.hut.edu.vn 66

3/3
Kt ni di
Phn ln cc kt ni to thnh cc li kt ni
theo hng v theo ct.
LB LB
Giao ct gia cc kt ni theo hng v theo ct s
tp trung cc im cn lp trnh kt ni, to thnh
ma trn chuyn mch (Switching Matrix), nm
phn tn trong FPGA.
LB LB

SM

LB LB

email ktmt@soict.hut.edu.vn 67 email ktmt@soict.hut.edu.vn 68

5
 9/5/2011

QuickLogic
Cypress
Lucent 2% 2%
Lattice 6%
6%
Spartan Arrix Virtex Vantis
low end middle end high end Xilinx
7% 36%

Actel
10%

Cyclone Arria Stratix Altera

low end middle end high end 31%

email ktmt@soict.hut.edu.vn 69 email ktmt@soict.hut.edu.vn 70

Ngn ng HDL ph hp.

B cng c CAD, EDA ph hp.
c lng c s lng cc CLB cn thit
D kin s lng cc chn I/O cn thit.
in p hot ng. Cc FPGA mi s dng mc
in p thp LVTTL, LVCMOS, i hi phi
chuyn i in p tng thch vi in p
TTL, cung cp mt hoc nhiu vng s dng ng
thi a mc in p.
Tc FPGA.
Xem Flow ca
Kh nng ti chnh. Aldec-Active

email ktmt@soict.hut.edu.vn 71 email ktmt@soict.hut.edu.vn 72

6
 9/5/2011

1/4 2/4

Thit k h thng
(System Design) Bc 1 - Thit k h thng
Phn chc nng thc hin trn FPGA
Tch hp vo ra Phn chc nng ny tch hp (kt hp) vi phn cn
(I/O integration) li ca h thng nh th no

c t thit k Bc 2 - Tch hp vo ra vi phn cn li ca h

(Design Specification)
thng
Tng hp
(Synthesis)

Kim tra thit k

(Design Verification)

Copyright (c) 10/2006 by NPB 73 Copyright (c) 10/2006 by NPB 74

3/4 4/4

Bc 3 - c t thit k Bc 5 - Kim tra thit k

M t chc nng ca thit k bng: Thc hin cc m phng, phn tch cui cng
Cc trnh son s logic (RTL, thi gian)
Cc ngn ng c t phn cng Xc nh cc thng s ca ASIC thit k
Kt hp m phng (tn s xung nhp)
Bc 4 - Tng hp logic
Ging bc Tng hp logic trong quy trnh y

Kt hp ti u:
tr
nng lng hao ph Np chip v chy th trn h thng!
Copyright (c) 10/2006 by NPB 75 Copyright (c) 10/2006 by NPB 76

7
 9/5/2011

1/3 2/3

Spactan II 200 Userguide.pdf ProASIC3 Evaluation Board

Spactan II 300
PCI 32bits
RS232

email ktmt@soict.hut.edu.vn 77 email ktmt@soict.hut.edu.vn 78

1/2 2/2

IDE ca nh sn xut FPGA. Mt s gi chng trnh ca bn th 3:

Leonardo Spectrum, CT tng hp ca Mentor
Graphics
Synplify, CT tng hp ca Synplicity
Atera Xilinx Actel ModelSim , CT m phng ca Mentor Graphics.
Active-HDL, CT thit k v m phng ca Aldec Active
Ch c nh sn xut mi thu hiu nguyn tc
hot ng ca FPGA ca h.

ch c cc IDE ca nh sn xut mi routing,
timing, cu hnh c cho FPGA.
EDA ca bn th 3 ch x l mc logic, ri gi IDE
ca nh sn xut m nhim mc vt l.
email ktmt@soict.hut.edu.vn 79 email ktmt@soict.hut.edu.vn 80