1 2 3 4 5 6

A A

REV Descripton DATE designer

V1.0 INITIAL RELEASE 2017/07/10 Qxn

B B

C C

D
Seeed Studio D
TITLE:

CC-BY-SA Design: Check:

Date: 2017/7/11 11:38 Vision:

1 2 3 4 5 6
 1 2 3 4 5 6

A A

CJ2305

VDD_5V/3.3B 500mA R1
R33

B B
Q1
10k

Q2

GPIO5/3.1C R34 10R

2N7002
10k R35
1 D1 APA102-2020
8 1 D2 APA102-2020
8 1 D3 APA102-2020
8 1 D4 APA102-2020
8 1 D5 APA102-2020
8 1 D6 APA102-2020
8
10R VDD VDD1 VDD VDD1 VDD VDD1 VDD VDD1 VDD VDD1 VDD VDD1
4 3 4 3 4 3 4 3 4 3 4 3
SPI_MOSI/3.1B 10R SDI SDO SDI SDO SDI SDO SDI SDO SDI SDO SDI SDO
R3 5 2 5 2 5 2 5 2 5 2 5 2
SPI_SCLK/3.1B CKI CKO CKI CKO CKI CKO CKI CKO CKI CKO CKI CKO
R4 6 7 6 7 6 7 6 7 6 7 6 7
GND GND1 GND GND1 GND GND1 GND GND1 GND GND1 GND GND1
C1
C2
10uF
10uF

7 6 7 6 7 6 7 6 7 6 7 6
GND1 GND GND1 GND GND1 GND GND1 GND GND1 GND GND1 GND
C 2
3
CKO CKI
5
4
2
3
CKO CKI
5
4
2
3
CKO CKI
5
4
2
3
CKO CKI
5
4
2
3
CKO CKI
5
4
2
3
CKO CKI
5
4
C
SDO SDI SDO SDI SDO SDI SDO SDI SDO SDI SDO SDI
8 1 8 1 8 1 8 1 8 1 8 1
VDD1 VDD VDD1 VDD VDD1 VDD VDD1 VDD VDD1 VDD VDD1 VDD
APA102-2020 D12 APA102-2020 D11 APA102-2020 D10 APA102-2020 D9 APA102-2020 D8 APA102-2020 D7

D
Seeed Studio D
TITLE:

CC-BY-SA Design: Check:

Date: 2017/7/11 11:38 Vision:

1 2 3 4 5 6
 1 2 3 4 5 6

A A
VDD_3V3/4.1B

VDD_5V/2.1B

VDD_3V3/4.1B
1 2
3V3 5V0
3 4
I2C_SDA/4.1B GPIO2/SDA1 5V0
5 6
I2C_SCL/4.1B GPIO3/SCL1 GND
7 8
GPIO4/GCKL TXD0/GPIO14
9 10 R29 10k
GND RXD0/GPIO15 I2C_SDA/4.1B
B GPIO17
11
GPIO17/GEN0 GPIO18
12 I2S_CLK/4.1B I2C_SCL/4.1B R30 10k B
13 14
GPIO27/GEN2 GND
15 16
GPIO22/GEN3 GEN4/GPIO23
17 18
3V3 GEN5/GPIO24
19 20
SPI_MOSI/2.1C GPIO10/MOSI GND
21 22
GPIO9/MISO GEN/6GPIO25
23 24
SPI_SCLK/2.1C GPIO11/SCLK CE0/GPIO8
25 26
GND CE/GPIO7
27 28
ID_SD ID_SC
29 30
GPIO5/2.1B GPIO5 GND
31 32
GPIO6 GPIO12 GPIO12 J1 Grove J2 Grove
33 34
GPIO13 GPIO13 GND 1 1
35 36 I2C_SCL/4.1B GPIO12
I2S_LRCLK/4.1B GPIO19 GPIO16 2 2
37 38 I2C_SDA/4.1B GPIO13
GPIO26 GPIO20 I2S_ADC/4.1B 3 3
39 40 VDD_3V3/4.1B VDD_3V3/4.1B
GND GPIO21 I2S_DAC 4 4

C C

D
Seeed Studio D
TITLE:

CC-BY-SA Design: Check:

Date: 2017/7/11 11:38 Vision:

1 2 3 4 5 6
 1 2 3 4 5 6

AVCC_3V3

MIC1
C3 100nF 1
VDD
A 2 A

1uF

1uF
GND
C4 100nF R6 0R 3
GAIN
C7 10nF R7 51R 1% 4
MIC1P OUT

TP1
TP2
TP3
C5

C6
R32 0R AVCC_3V3 C8 SPU0414HR5H-SB 312030079
U1 AC108
45 46 C9 1uF 33pF
VDD_5V/3.3B DLDOIN DLDOOUT
27 C10 10nF R8 51R 1%
VDD_5V/3.3B ALDOIN 30 C11 1uF MIC1N
R9 10k 44 VREF
CP_EN 28 C12 1uF
C13 1uF 43 ALDOOUT
CP_VPP 29 C14 1uF AVCC_3V3
42 RVCC
CP_VPN 20 C15 1uF MIC2
AVCC_ANA1
C16 1uF 7 40 C17 1uF C18 100nF 1
VCC_DIO AVCC_ANA2 VDD
C19 1uF 11 31 C20 1uF 2
VCC_I2S VRP GND
32 C21 100nF R10 0R 3
R11 10k 19 VRN GAIN
VDD_3V3/3.5B RSTN C22 10nF R12 51R 1% 4
10 41 MIC2P OUT
I2C_SDA/3.5B SDA VDD_CPOUT TP4
9 6

10uF
I2C_SCL/3.5B SCK VDD_CORE C24 SPU0414HR5H-SB 312030079

C23
4
DEV_ID0 21
B 5
TEST
MICBIAS1
C25 10nF
33pF
R13 51R 1%
B
22 MIC2N
R14 10R 8 MIC1P MIC1P
MCLK MCLK 23
R15 10R 15 MIC1N MIC1N
I2S_CLK/3.3B BCLK AVCC_3V3
R16 10R 18 24
I2S_LRCLK/3.1C LRCK MICBIAS2 MIC3
R17 10R 16
I2S_ADC/3.3C SDOUT1 25 C26 100nF 1
17 MIC2P MIC2P VDD
SDOUT2 26 2
MIC2N MIC2N GND
R18 10R 48 C27 100nF R19 0R 3
DMICDAT1 GPIO_1/DMICDAT1 34 GAIN
TP5 R20 10R 1 MICBIAS3 C28 10nF R21 51R 1% 4
DMICCLK GPIO_2/DMICCLK MIC3P OUT
TP6 R22 10R 2 35
DMICDAT2 GPIO_3/DMICDAT2 MIC3P MIC3P C29 SPU0414HR5H-SB 312030079
TP7 R23 10R 3 36
GPIO4 GPIO_4 MIC3N MIC3N
TP8 12 33pF
NC1 37
13 MICBIAS4 C30 10nF R24 51R 1%
NC2 MIC3N
AGND

14 38
NC3 MIC4P
GND

MIC4P
47 39
NC4 MIC4N MIC4N AVCC_3V3
MIC4
C C
33

PAD

C31 100nF 1
VDD
2
GND
C32 100nF R26 0R 3
GAIN
C33 10nF R27 51R 1% 4
MIC4P OUT
C34 SPU0414HR5H-SB 312030079

33pF
MIC4N C35 10nF R28 51R 1%

100nF
VDD_3V3/3.5B
X1 24MHz 306020014 C36

D
1

2
ENABLE

GND
VDD

OUT
4

3 MCLK
Seeed Studio D
TITLE:

CC-BY-SA Design: qxn

Check:

Date: 2017/7/11 11:38 Vision: v1.0

1 2 3 4 5 6