5/9/2017 nhn truyn chui k t cho STM32f103vct6 | Din n in T

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nhn truyn chui k t cho STM32f103vct6

Tho lun trong 'STM32' bt u bi nongdanbk.nb, 16 Thng by 2014.

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cc tin bi gip em vi .Em mi m mn lp trnh c mt trng trnh,yu cu

u bi l vit mt chng trnh truyn nhn d liu kiu chui t PC xung
STM32f103vct6 khung truyn ca em bt u bng k t * v kt thc bng k t
#,truyn ln my tnh chui d liu va nhn tr 2 k t * v #. chng trnh ca em;

#include "stm32f10x.h"
nongdanbk.nb
New Member int i=0,j=0,c=0;

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char Data; THNH VIN

Tm kim din n Recent Posts ng nhp hoc ng k

char receive[40];
void nhan(char data);
void truyen ();
void USART3_IRQHandler(void);
void Delay(__IO uint32_t num)
{
__IO uint32_t index = 0;

/* default system clock is 72MHz */

for(index = (7200 * num); index != 0; index--)
{
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5/9/2017 nhn truyn chui k t cho STM32f103vct6 | Din n in T

}
}

void usart_setup(void)
{
USART_InitTypeDef USART_InitStructure;// cu lenh gn cau trc
GPIO_InitTypeDef GPIO_InitStructure;// cu lenh gn cau trc
NVIC_InitTypeDef NVIC_InitStructure;
RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOD |
RCC_APB2Periph_AFIO, ENABLE);
RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART3,ENABLE);

// cau hnh cho PA2 v PA3

// RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOD |
RCC_APB2Periph_AFIO, ENABLE);

/* This sequence sets up the TX and RX pins

* so they work correctly with the USART1 peripheral
*/
/* Configure PA9 for USART Tx as alternate function push-pull */
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
GPIO_Init(GPIOD, &GPIO_InitStructure);

/* Configure PA10 for USART Rx as input floating */

GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
GPIO_Init(GPIOD, &GPIO_InitStructure);

NVIC_PriorityGroupConfig(NVIC_PriorityGroup_1);

/* Enable the USARTy Interrupt */

H Tr Khch Hng V K Thut

NVIC_InitStructure.NVIC_IRQChannel = USART3_IRQn;

NVIC_InitStructure.NVIC_IRQChannelSubPriority = 2;

NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;

NVIC_Init(&NVIC_InitStructure);

// RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART3,ENABLE);
USART_InitStructure.USART_BaudRate = 9600;
USART_InitStructure.USART_WordLength = USART_WordLength_8b;
USART_InitStructure.USART_StopBits = USART_StopBits_1;
USART_InitStructure.USART_Parity = USART_Parity_No;
USART_InitStructure.USART_HardwareFlowControl =
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5/9/2017 nhn truyn chui k t cho STM32f103vct6 | Din n in T

USART_HardwareFlowControl_None;
USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
USART_Init(USART3, &USART_InitStructure);
USART_Cmd(USART3,ENABLE); //mo cong uart3

USART_ITConfig(USART3, USART_IT_RXNE, ENABLE); //cho phep ngat nhan

USART_ITConfig(USART3, USART_IT_TXE, ENABLE); // cho phep ngat truyen
}

//void UART3_ISR_Handler(void)
//{
// if(USART_GetITStatus(USART3, USART_IT_RXNE) != RESET) //co ngat nhan
duoc bat
// {
// /* Read one byte from the receive data register */
// c = USART_ReceiveData(USART3);
// }

void UART3_ISR_Handler(void)
{
u8 data;

/* Pick up the character, prepare its binary form */

data = USART_ReceiveData(USART3);
/* Decode data, put data to buffer*/

//pc_conn_decode(data);
nhan(data);

void nhan(char data)

{

int nhan_ky_tu=0;
switch(data)
{
case'*':
nhan_ky_tu=1;
i=0;
break;

case'#':

nhan_ky_tu=0;
truyen();
break;
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5/9/2017 nhn truyn chui k t cho STM32f103vct6 | Din n in T

default:
if(nhan_ky_tu=1)
{receive[i++]=data;
receive=0;
if (i>=40)
i=0;
}
break;

void truyen()
{

unsigned char uData;

while(USART_GetFlagStatus(USART3, USART_FLAG_TXE)==RESET);
USART_SendData(USART3,uData);
}
void ghi()
{

for(i=0;receive!='\0';i++)
{
truyen(receive);
// delay();
}
}

int main(void)

{
usart_setup();

USART3_IRQHandler();

ghi();

Delay(1);
}

EM CHY M N KHNG RA NH YU CU.MONG C CC TIN BI

GIP

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5/9/2017 nhn truyn chui k t cho STM32f103vct6 | Din n in T
nongdanbk.nb, 16 Thng by 2014 #1

nongdanbk.nb said:

cc tin bi gip em vi .Em mi m mn lp trnh c mt trng trnh,yu cu u bi l vit

mt chng trnh truyn nhn d liu kiu chui t PC xung STM32f103vct6 khung truyn ca
em bt u bng k t * v kt thc bng k t #,truyn ln my tnh chui d liu va nhn tr 2
k t * v #. chng trnh ca em;
quang.dt7bk
Admin
#include "stm32f10x.h"

int i=0,j=0,c=0; Click to expand...

Cho bn!
Bn tham kho chng trnh mnh vit theo yu cu, chy trn KIT STM32 START ca
ca hng banlinhkien.vn, s dng STM32F103C8T6. Khi nhn c khung d liu
*DATA# mnh s gi ngc li d liu DATA ln ngun gi (bn c th s dng
Terminal trn PC test nh).

http://www.fshare.vn/file/FE0SQHD3FU/

Nu bn i su tm hiu, bn hy tm hiu vn IDLE m Stm32 h tr nh. IDLE rt

tuyt vi trong vic gip bn gii quyt cc vn truyn nhn khung d liu qua
USART (v d c th l bn khng cn phi ng gi d liu vo khung truyn kiu
*DATA# na ).
Chc bn thnh cng!
quang.dt7bk, 17 Thng by 2014 #2

(Bn phi ng nhp hoc ng k tr li bi vit.)

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