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Verilog Codes For Basic Circuits
Verilog Codes For Basic Circuits
module logic_gates(a,b,y1,y2,y3,y4,y5,y6,y7,y8);
input a,b;
output y1,y2,y3,y4,y5,y6,y7,y8;
buf (y1,a);
not (y2,a);
or (y3,a,b);
nor (y4,a,b);
and (y5,a,b);
nand (y6,a,b);
xor (y7,a,b);
xnor (y8,a,b);
endmodule
module full_adder(a,b,c,sum,carry);
input a,b,c;
output sum,carry;
assign sum = a^b^c;
assign carry = (a&b)|(b&c)|(c&a);
endmodule
PARALLEL SUBTRACTOR
module parallel_subtractor(x,y,bin,difference,bout);
input [3:0] x,y;
input bin;
output [3:0] difference;
output bout;
assign {bout,difference}= x - y - bin;
endmodule
module full_add(a,b,c,sum,carry);
input a,b,c;
output sum,carry;
assign sum = a^b^c;
assign carry = (a&b)|(b&c)|(c&a);
endmodule
module decoder3_to_8(a,b,c,d0,d1,d2,d3,d4,d5,d6,d7);
input a,b,c;
output d0,d1,d2,d3,d4,d5,d6,d7 ;
assign d0 = (~a & ~b&~c),
d1 = (~a & ~b&c ),
d2 = (~a & b&~c ),
d3 = (~a & b&c ),
d4 = (a & ~b&~c ),
d5 = (a & ~b&c ),
d6 = (a & b&~c ),
d7 = (a &b&c );
endmodule
1 :8 DEMULTIPLEXER & 4:1 MULTIPLEXER
module demux1_to_8(i,s0,s1,s2,d0,d1,d2,d3,d4,d5,d6,d7);
input i,s0,s1,s2;
output d0,d1,d2,d3,d4,d5,d6,d7;
assign d0 = (i & ~s2 & ~s1 & ~s0),
d1 = (i & ~s2 & ~s1 & s0),
d2 = (i & ~s2 & s1 & ~s0),
d3 = (i & ~s2 & s1 & s0),
d4 = (i & s2 & ~s1 & ~s0),
d5 = (i & s2 & ~s1 & s0),
d6 = (i & s2 & s1 & ~s0),
d7 = (i & s2 & s1 & s0);
endmodule
module mux4_to_1(i0,i1,i2,i3,s0,s1,out);
input i0,i1,i2,i3,s0,s1;
output out;
assign out = (i0 & ~s1 & ~s0)|(i1 & ~s1 & s0)|(i2 & s1 & ~s0)|(i3 & s1 & s0);
endmodule
8 BIT MULTIPLIER
module multiplier_8_bit (a,b,c);
input [7:0]a;
input [7:0]b;
output [15:0]c;
assign c[15:0] = a[7:0]*b[7:0];
endmodule
D FLIPFLOP
module D_FF (D,clk,reset,Q);
input D,clk,reset;
output Q;
reg Q;
always @ (posedge reset or negedge clk)
if (reset)
Q = 1'b0;
else
Q = D;
endmodule
T FLIPFLOP
module T_FF (T,clk,reset,Q);
input T,clk,reset;
output Q;
wire w;
assign w = T^Q;
D_FF dff1(w,clk,reset,Q);
endmodule
JK FLIPFLOP
module JK_FF (J,K,clk,reset,Q);
input J,K,clk,reset;
output Q;
wire w;
assign w = (J&~Q)|(~K&Q);
D_FF dff1(w,clk,reset,Q);
endmodule
case ({s1,s0})
2'b00:{q3,q2,q1,q0}={q3,q2,q1,q0}; // No change
2'b01:{q3,q2,q1,q0}={RTin,q3,q2,q1}; // Shift right
2'b10:{q3,q2,q1,q0}={q2,q1,q0,LFin}; // Shift left
2'b11:{q3,q2,q1,q0}=PIin; // Parallel load input
endcase
endmodule
CMOS INVERTER
module my_inv(in,out);
input in;
output out;
supply1 pwr;
supply0 gnd;
pmos ( out,pwr,in);
nmos (out,gnd,in);
endmodule
module sr_flipflop(s,r,clk,q,qbar);
input s,r,clk;
output q,qbar;
reg q,qbar;
always@(posedge clk)
begin
case ({s,r})
2'b00:q=q;
2'b01:q=1'b0;
2'b10:q=1'b1;
2'b11:q=1'bx;
endcase
qbar=~q;
end
endmodule
module serial_adder(count2,count1,count0,clk,a0,a1,a2,a3,a4,a5,a6,a7,a8,result,add);
input count2,count1,count0;
input clk;
input a0,a1,a2,a3,a4,a5,a6,a7,a8;
output [3:0]add ,result;
reg [3:0]result,add;
always @ (posedge clk )
case ({count2,count1,count0})
3'b000 :begin
add=a0+a1;
end
3'b001 :begin
add=add+a2;
end
3'b010 :begin
add=add+a3;
end
3'b011 :begin
add=add+a4;
end
3'b100 :begin
add=add+a5;
end
3'b101 :begin
add=add+a6;
end
3'b110 :begin
add=add+a7;
end
3'b111 :begin
result=add+a8;
end
endcase
endmodule
TRAFFIC LIGHT CONTROLLER
module tlc(state2,state1,state0,clk,r0,y0,g0,p0,r1,y1,g1,p1);
input state2,state1,state0;
input clk;
output r0,y0,g0,p0,r1,y1,g1,p1 ;
reg r0,y0,g0,p0,r1,y1,g1,p1;
always @ (posedge clk )
case ({state2,state1,state0})
3'b000 :begin
r0=1;
y0=0;
g0=0;
p0=1;
r1=1;
y1=0;
g1=0;
p1=1;
end
3'b001 :begin
r0=0;
y0=1;
g0=0;
p0=1;
r1=1;
y1=0;
g1=0;
p1=1;
end
3'b010 :begin
r0=0;
y0=0;
g0=1;
p0=0;
r1=1;
y1=0;
g1=0;
p1=0;
end
3'b011 :begin
r0=0;
y0=1;
g0=0;
p0=0;
r1=0;
y1=1;
g1=0;
p1=0;
end
3'b100 :begin
r0=1;
y0=0;
g0=0;
p0=0;
r1=0;
y1=0;
g1=1;
p1=0;
end
3'b101 :begin
r0=1;
y0=0;
g0=0;
p0=0;
r1=0;
y1=1;
g1=0;
p1=0;
end
default :begin
r0=0;
y0=0;
g0=0;
p0=0;
r1=0;
y1=0;
g1=0;
p1=0;
end
endcase
endmodule