DEC7

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-- Company:
-- Engineer:
--
-- Create Date: 18:17:27 03/31/2017
-- Design Name:
-- Module Name: DEC7 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating

-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity DEC7 is

Port ( D3 : in STD_LOGIC;
D2 : in STD_LOGIC;
D1 : in STD_LOGIC;
D0 : in STD_LOGIC;
SEL : in STD_LOGIC;
A : out STD_LOGIC;
B : out STD_LOGIC;
C : out STD_LOGIC;
D : out STD_LOGIC;
E : out STD_LOGIC;
F : out STD_LOGIC;
G : out STD_LOGIC;
CAT : out STD_LOGIC);
end DEC7;

architecture Behavioral of DEC7 is

begin

CAT <= SEL;

A<=(NOT(D2) AND NOT (D0))OR((D3) AND NOT (D1) AND NOT(D0))OR((D1) AND NOT (D0))OR((D2)
AND (D1))OR(NOT(D3) AND (D1) AND (D0))
OR(NOT (D3) AND (D2) AND (D0))OR((D3) AND NOT (D2) AND NOT (D1));

B<=(NOT(D2) AND NOT (D0))OR(NOT(D3) AND NOT (D2))OR(NOT (D3) AND (D1) AND (D0))OR(NOT
(D3) AND NOT (D1) AND NOT (D0))OR
((D3) AND NOT (D1) AND (D0));

C<=(NOT (D3) AND (D2))OR(NOT (D3) AND NOT (D1))OR(NOT (D3) AND (D0))OR(NOT (D1) AND
(D0))OR((D3) AND NOT (D2));

D<=(NOT (D2) AND NOT (D1) AND NOT (D0))OR((D3) AND (D2) AND NOT (D1))OR((D2) AND NOT
(D1) AND (D0))OR(NOT (D2) AND (D1) AND (D0))
OR(NOT (D3) AND NOT (D2) AND (D1))OR((D2) AND (D1) AND NOT (D0));

E<=(NOT(D2) AND NOT (D0))OR((D1) AND NOT (D0))OR((D3) AND (D2))OR((D3) AND (D1) AND
(D0));

F<=(NOT(D1) AND NOT (D0))OR((D3) AND NOT (D2))OR((D3) AND (D1))OR(NOT (D3) AND (D2) AND
NOT (D1))OR((D2) AND (D1) AND NOT (D0));

G<=((D3) AND NOT (D2))OR((D1) AND NOT (D0))OR((D3) AND (D0))OR(NOT (D3) AND (D2) AND
NOT (D1))OR(NOT (D2) AND (D1) AND (D0));

end Behavioral;

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ULA

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-- Company:
-- Engineer:
--
-- Create Date: 18:27:34 03/31/2017
-- Design Name:
-- Module Name: ULA - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY ULA IS GENERIC ( nbits : integer := 8 );

PORT (
a: IN std_logic_vector(nbits - 1 DOWNTO 0);
b: IN std_logic_vector(nbits - 1 DOWNTO 0);
opcode: IN std_logic_vector(3 DOWNTO 0);
carry : OUT std_logic;
zero : OUT std_logic;
neg : OUT std_logic;
result: OUT std_logic_vector(nbits - 1 DOWNTO 0)
);

END ENTITY ULA;

ARCHITECTURE Behavioral OF ULA IS

CONSTANT zeroval : std_logic_vector(nbits - 1 DOWNTO 0) := (OTHERS => '0');

SIGNAL result_int: std_logic_vector(nbits - 1 DOWNTO 0);

BEGIN
ula:
PROCESS(a, b, opcode)
BEGIN

carry <= '0';

CASE opcode IS
WHEN "0000" => --SUMA
result_int (nbits - 1 DOWNTO 0) <= a + b;

WHEN "0001" => -- RESTA

result_int (nbits - 1 DOWNTO 0) <= a - b;
 WHEN "0010" => -- NEG
result_int (nbits - 1 DOWNTO 0) <= zeroval - a;

WHEN "0011" => -- NOT

result_int (nbits - 1 DOWNTO 0) <= NOT a;

WHEN "0100" => -- OR

result_int (nbits - 1 DOWNTO 0) <= a OR b;

WHEN "0101" => -- AND

result_int (nbits - 1 DOWNTO 0) <= a AND b;

WHEN "0110" => -- XOR

result_int (nbits - 1 DOWNTO 0) <= a XOR b;

WHEN "0111" => -- LSL, ASL

result_int <= a(6 DOWNTO 0) & '0';
carry <= a(3);
WHEN "1000" => -- LSR
result_int <= '0' & a(7 DOWNTO 1);
carry <= a(0);
WHEN "1001" => -- a
result_int (nbits - 1 DOWNTO 0) <= a;
WHEN "1010" => -- b
result_int (nbits - 1 DOWNTO 0) <= b;
WHEN "1011" => -- ROR
result_int <= a(0) & a(7 DOWNTO 1);
carry <= a(0);
WHEN OTHERS =>
result_int <= (OTHERS => '0');
END CASE;

END PROCESS ula;

zero <= '1' WHEN result_int = zeroval ELSE '0';

neg <= result_int(7);

result <= result_int;

END ARCHITECTURE Behavioral;

/////////////////////////////////////////////////////////////

DIV

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-- Company:
-- Engineer:
--
-- Create Date: 18:52:24 03/31/2017
-- Design Name:
-- Module Name: DIV - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity clk50KHz is
Port (
entrada: in STD_LOGIC;
reset : in STD_LOGIC;
salida : out STD_LOGIC
);
end clk50KHz;

architecture Behavioral of clk50KHz is

signal temporal: STD_LOGIC;
signal contador: integer range 0 to 499 := 0;
begin
divisor_frecuencia: process (reset, entrada) begin
if (reset = '1') then
temporal <= '0';
contador <= 0;
elsif rising_edge(entrada) then
if (contador = 499) then
temporal <= NOT(temporal);
contador <= 0;
else
contador <= contador+1;
end if;
end if;
end process;

salida <= temporal;

end Behavioral;