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Compal La 4111p r0.4 Schematics
Compal La 4111p r0.4 Schematics
1 1
Compal confidential 2
Schematics Document
Mobile AMD S1G2 CPU with ATI
3
RS780M(NB) & SB700(SB) core logic 3
2008-03-07
REV:0.4
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Sheet
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4111P 0.4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, March 07, 2008 Sheet 1 of 54
A B C D E
A B C D E
Compal Confidential
Page 30 Page 6
DDR2 800MHz 1.8V BANK 0, 1, 2, 3 Page 8, 9 Clock Generator
Dual Channel SLG8SP626VTR
Fan conn
638-PIN uFCPGA 638 Page 15
Page 4
Page 4, 5, 6, 7
Side-Port DDR2 SDRAM
Hyper Transport Link 256Mbits(16Mbx16) Page 12
16X16
SATA Slave
CardReader Realtek Mini-Card*2 Express Card FingerPrinter AES1610
JMicron 8102E(10/100M) WLAN & WWAN
SATA Slave
USBx1 daughter board
Page 26 Page 19, 20, 21, 22, 23 page 35
JMB385-LGEZ0A
Page 27 Page 25 Page 26
MDC V1.5 daughter board
Page 34
Codec_IDT9271B7
Page 27 Page 28 TPA6017A2 Page 29
*Consumer IR
*USB x1 Power On/Off CKT.
*DC JACK P35
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/08/02 Deciphered Date 2008/08/02 Title
DC/DC Interface CKT. THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Block Diagram
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Page 35 Page 36 DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4111P 0.4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, March 07, 2008 Sheet 2 of 54
A B C D E
A B C D E
+5VS
+3VS : means Analog Ground
+1.5VS
power Layout Notes
plane +0.9V L
+VCCP Please see VGA@ as no install. No support RX780M.
+5VALW +1.8V +CPU_CORE
+B
+3VALW +VGA_CORE
+2.5VS
: Question Area Mark.(Wait check)
State +1.8VS
+1.2VS "*" as default BOM setting
+0.9VGA *PA@ : means install when Ripley PA.
PR@ : means install when Ripley PR.
2 RM@ : means install when Rachman. 2
S5 S4/AC
O O X X
S5 S4/ Battery only
O X X X
S5 S4/AC & Battery
don't exist X X X X SMBUS Control Table
THERMAL
SERIAL SENSOR
SOURCE INVERTER BATT EEPROM CPU & SODIMM CLK CHIP MINI CARD LCD HDMI G-Sensor
ADM1032 I / II Slot 2
3 3
SMB_EC_CK1
I2C / SMBUS ADDRESSING KB926 X V V VCPU X X X X X X
SMB_EC_DA1
SMB_EC_CK2
DEVICE HEX ADDRESS SMB_EC_DA2
KB926 X X X V
ADM1032 X X X X X X
DDR SO-DIMM 0 A0 10100000 I2C_CLK
DDR SO-DIMM 1 A4 10100100 I2C_DATA
RS780M
X X X X X X X V X X
CLOCK GENERATOR (EXT.) D2 11010010 DDC_CLK0
DDC_DATA0
RS780M X X X X X X X X V X
DDC_CLK1
EC SM Bus1 address EC SM Bus2 address DDC_DATA1
RS780M X X X X X X X X X X
SCL0
Device HEX Address Device HEX Address
SDA0
SB700 X X X X V V X X X X
Smart Battery 16H 0001 011X b CPU 98H 1001 100X b SCL1
24C16 A0H 1010 000X b ADI1032-2 CPU 9AH 1001 101X b SDA1
SB700 X X X X X X V X X X
SCL2
SDA2
SB700 X X X X X X X X X V
4 4
SCL3
SDA3
SB700 X X X X X X X X X X
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/08/02 Deciphered Date 2008/08/02 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Notes List
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4111P 0.4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, March 07, 2008 Sheet 3 of 54
A B C D E
A B C D E
1 1
+1.2V_HT
VLDT CAP.
250 mil
1 1 1 1 1 1
C1 C2 C3 C4 C5 C6
H_CADIP[0..15] H_CADOP[0..15] 4.7U_0805_10V4Z 4.7U_0805_10V4Z 0.22U_0603_16V4Z 0.22U_0603_16V4Z 180P_0402_50V8J 180P_0402_50V8J
10 H_CADIP[0..15] H_CADOP[0..15] 10
H_CADIN[0..15] H_CADON[0..15] 2 2 2 2 2 2
10 H_CADIN[0..15] H_CADON[0..15] 10
J3 Y1
10
10
H_CLKIP0
H_CLKIN0 J2
J5
L0_CLKIN_H0
L0_CLKIN_L0
L0_CLKOUT_H0
L0_CLKOUT_L0 W1
Y4
H_CLKOP0
H_CLKON0
10
10 PWM Fan Control circuit JP2
10 H_CLKIP1 L0_CLKIN_H1 L0_CLKOUT_H1 H_CLKOP1 10
1
10 H_CLKIN1 K5 L0_CLKIN_L1 L0_CLKOUT_L1 Y3 H_CLKON1 10 1 1 1 1
C8 C9 2
3 D1 0.1U_0402_16V4Z 2 3
10 H_CTLIP0 N1 L0_CTLIN_H0 L0_CTLOUT_H0 R2 H_CTLOP0 10
P1 R3 CH751H-40PT_SOD323-2 4.7U_0805_10V4Z 3
10 H_CTLIN0 L0_CTLIN_L0 L0_CTLOUT_L0 H_CTLON0 10 2 2 GND
10 H_CTLIP1 P3 T5 H_CTLOP1 10 4
2
L0_CTLIN_H1 L0_CTLOUT_H1 GND
10 H_CTLIN1 P4 L0_CTLIN_L1 L0_CTLOUT_L1 R5 H_CTLON1 10
ACES_88231-02001
+VCC_FAN CONN@
FOX_PZ6382A-284S-41F_GRIFFIN
CONN@
1
2
5
6
1
Athlon 64 S1
Processor Socket D Q1 @ D2
9/20 SP07000DM00/SP07000EQ00 G
3 RLZ5.1B_LL34
33 FAN_PWM S SI3456BDV-T1-E3_TSOP6
2
4
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AMD CPU S1G2 HT I/F
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4111P 0.4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, March 07, 2008 Sheet 4 of 54
A B C D E
A B C D E
2
1 DDR_B_D16 D20 G18 DDR_A_D16
R1 DDR_B_D17 MB_DATA16 MA_DATA16 DDR_A_D17
A21 MB_DATA17 MA_DATA17 C19
C14 DDR_B_D18 D24 D22 DDR_A_D18
1.5P_0402_50V9C 1K_0402_1% DDR_B_D19 MB_DATA18 MA_DATA18 DDR_A_D19
C25 MB_DATA19 MA_DATA19 E20
DDR_B_CLK#0 2 DDR_B_D20 DDR_A_D20
B20 E18
1
+MCH_REF DDR_B_D21 MB_DATA20 MA_DATA20 DDR_A_D21
C20 MB_DATA21 MA_DATA21 F18
DDR_B_CLK1 DDR_B_D22 B24 B22 DDR_A_D22
MB_DATA22 MA_DATA22
2
1 1 1 DDR_B_D23 C24 C23 DDR_A_D23
R2 C12 C13 DDR_B_D24 MB_DATA23 MA_DATA23 DDR_A_D24
E23 MB_DATA24 MA_DATA24 F20
C15 DDR_B_D25 E24 F22 DDR_A_D25
1.5P_0402_50V9C 1K_0402_1% DDR_B_D26 MB_DATA25 MA_DATA25 DDR_A_D26
G25 MB_DATA26 MA_DATA26 H24
DDR_B_CLK#1 2 2 2 DDR_B_D27 DDR_A_D27
G26 J19
1
1000P_0402_25V8J DDR_B_D28 MB_DATA27 MA_DATA27 DDR_A_D28
C26 MB_DATA28 MA_DATA28 E21
0.1U_0402_16V4Z DDR_B_D29 D26 E22 DDR_A_D29
2 DDR_B_D30 MB_DATA29 MA_DATA29 DDR_A_D30 2
G23 MB_DATA30 MA_DATA30 H20
+0.9V +0.9V DDR_B_D31 G24 H22 DDR_A_D31
JCPUB DDR_B_D32 MB_DATA31 MA_DATA31 DDR_A_D32
AA24 MB_DATA32 MA_DATA32 Y24
DDR_B_D33 AA23 AB24 DDR_A_D33
DDR_B_D34 MB_DATA33 MA_DATA33 DDR_A_D34
D10 VTT1 W10 AD24 AB22
Place them close to CPU within 1" C10 MEM:CMD/CTRL/CLK VTT5 AC10 DDR_B_D35 AE24
MB_DATA34 MA_DATA34
AA21 DDR_A_D35
VTT2 VTT6 DDR_B_D36 MB_DATA35 MA_DATA35 DDR_A_D36
B10 VTT3 VTT7 AB10 AA26 MB_DATA36 MA_DATA36 W22
AD10 AA10 DDR_B_D37 AA25 W21 DDR_A_D37
R4 39.2_0402_1% VTT4 VTT8 DDR_B_D38 MB_DATA37 MA_DATA37 DDR_A_D38
VTT9 A10 AD26 MB_DATA38 MA_DATA38 Y22
1 2 AF10 DDR_B_D39 AE25 AA22 DDR_A_D39
MEMZP VTT_SENSE DDR_B_D40 MB_DATA39 MA_DATA39 DDR_A_D40
+1.8V 1 2 AE10 MEMZN VTT_SENSE Y10 PAD T1 AC22 MB_DATA40 MA_DATA40 Y20
R3 39.2_0402_1% DDR_B_D41 AD22 AA20 DDR_A_D41
+MCH_REF DDR_B_D42 MB_DATA41 MA_DATA41 DDR_A_D42
T2 PAD H16 RSVD_M1 MEMVREF W17 AE20 MB_DATA42 MA_DATA42 AA18
DDR_B_D43 AF20 AB18 DDR_A_D43
DDR_A_ODT0 DDR_B_D44 MB_DATA43 MA_DATA43 DDR_A_D44
8 DDR_A_ODT0 T19 MA0_ODT0 RSVD_M2 B18 PAD T3 AF24 MB_DATA44 MA_DATA44 AB21
DDR_A_ODT1 V22 DDR_B_D45 AF23 AD21 DDR_A_D45
8 DDR_A_ODT1 MA0_ODT1 MB_DATA45 MA_DATA45
U21 W26 DDR_B_ODT0 DDR_B_D46 AC20 AD19 DDR_A_D46
MA1_ODT0 MB0_ODT0 DDR_B_ODT0 9 MB_DATA46 MA_DATA46
V19 W23 DDR_B_ODT1 DDR_B_D47 AD20 Y18 DDR_A_D47
MA1_ODT1 MB0_ODT1 DDR_B_ODT1 9 MB_DATA47 MA_DATA47
Y26 DDR_B_D48 AD18 AD17 DDR_A_D48
DDR_CS0_DIMMA# MB1_ODT0 DDR_B_D49 MB_DATA48 MA_DATA48 DDR_A_D49
8 DDR_CS0_DIMMA# T20 MA0_CS_L0 AE18 MB_DATA49 MA_DATA49 W16
DDR_CS1_DIMMA# U19 V26 DDR_CS0_DIMMB# DDR_B_D50 AC14 W14 DDR_A_D50
8 DDR_CS1_DIMMA# MA0_CS_L1 MB0_CS_L0 DDR_CS0_DIMMB# 9 MB_DATA50 MA_DATA50
U20 W25 DDR_CS1_DIMMB# DDR_B_D51 AD14 Y14 DDR_A_D51
MA1_CS_L0 MB0_CS_L1 DDR_CS1_DIMMB# 9 MB_DATA51 MA_DATA51
V20 U22 DDR_B_D52 AF19 Y17 DDR_A_D52
MA1_CS_L1 MB1_CS_L0 DDR_B_D53 MB_DATA52 MA_DATA52 DDR_A_D53
AC18 MB_DATA53 MA_DATA53 AB17
DDR_CKE0_DIMMA J22 J25 DDR_CKE0_DIMMB DDR_B_D54 AF16 AB15 DDR_A_D54
8 DDR_CKE0_DIMMA MA_CKE0 MB_CKE0 DDR_CKE0_DIMMB 9 MB_DATA54 MA_DATA54
DDR_CKE1_DIMMA J20 H26 DDR_CKE1_DIMMB DDR_B_D55 AF15 AD15 DDR_A_D55
8 DDR_CKE1_DIMMA MA_CKE1 MB_CKE1 DDR_CKE1_DIMMB 9 MB_DATA55 MA_DATA55
DDR_B_D56 AF13 AB13 DDR_A_D56
DDR_B_D57 MB_DATA56 MA_DATA56 DDR_A_D57
N19 MA_CLK_H5 MB_CLK_H5 P22 AC12 MB_DATA57 MA_DATA57 AD13
N20 R22 DDR_B_D58 AB11 Y12 DDR_A_D58
DDR_A_CLK0 MA_CLK_L5 MB_CLK_L5 DDR_B_CLK0 DDR_B_D59 MB_DATA58 MA_DATA58 DDR_A_D59
8 DDR_A_CLK0 E16 MA_CLK_H1 MB_CLK_H1 A17 DDR_B_CLK0 9 Y11 MB_DATA59 MA_DATA59 W11
DDR_A_CLK#0 F16 A18 DDR_B_CLK#0 DDR_B_D60 AE14 AB14 DDR_A_D60
8 DDR_A_CLK#0 MA_CLK_L1 MB_CLK_L1 DDR_B_CLK#0 9 MB_DATA60 MA_DATA60
DDR_A_CLK1 Y16 AF18 DDR_B_CLK1 DDR_B_D61 AF14 AA14 DDR_A_D61
3 8 DDR_A_CLK1 MA_CLK_H7 MB_CLK_H7 DDR_B_CLK1 9 MB_DATA61 MA_DATA61 3
DDR_A_CLK#1 AA16 AF17 DDR_B_CLK#1 DDR_B_D62 AF11 AB12 DDR_A_D62
8 DDR_A_CLK#1 MA_CLK_L7 MB_CLK_L7 DDR_B_CLK#1 9 MB_DATA62 MA_DATA62
P19 R26 DDR_B_D63 AD11 AA12 DDR_A_D63
MA_CLK_H4 MB_CLK_H4 MB_DATA63 MA_DATA63
P20 MA_CLK_L4 MB_CLK_L4 R25 9 DDR_B_DM[7..0] DDR_A_DM[7..0] 8
DDR_B_DM0 A12 E12 DDR_A_DM0
8 DDR_A_MA[15..0] DDR_B_MA[15..0] 9 MB_DM0 MA_DM0
DDR_A_MA0 N21 P24 DDR_B_MA0 DDR_B_DM1 B16 C15 DDR_A_DM1
DDR_A_MA1 MA_ADD0 MB_ADD0 DDR_B_MA1 DDR_B_DM2 MB_DM1 MA_DM1 DDR_A_DM2
M20 MA_ADD1 MB_ADD1 N24 A22 MB_DM2 MA_DM2 E19
DDR_A_MA2 N22 P26 DDR_B_MA2 DDR_B_DM3 E25 F24 DDR_A_DM3
DDR_A_MA3 MA_ADD2 MB_ADD2 DDR_B_MA3 DDR_B_DM4 MB_DM3 MA_DM3 DDR_A_DM4
M19 MA_ADD3 MB_ADD3 N23 AB26 MB_DM4 MA_DM4 AC24
DDR_A_MA4 M22 N26 DDR_B_MA4 DDR_B_DM5 AE22 Y19 DDR_A_DM5
DDR_A_MA5 MA_ADD4 MB_ADD4 DDR_B_MA5 DDR_B_DM6 MB_DM5 MA_DM5 DDR_A_DM6
L20 MA_ADD5 MB_ADD5 L23 AC16 MB_DM6 MA_DM6 AB16
DDR_A_MA6 M24 N25 DDR_B_MA6 DDR_B_DM7 AD12 Y13 DDR_A_DM7
DDR_A_MA7 MA_ADD6 MB_ADD6 DDR_B_MA7 MB_DM7 MA_DM7
L21 MA_ADD7 MB_ADD7 L24
DDR_A_MA8 L19 M26 DDR_B_MA8 DDR_B_DQS0 C12 G13 DDR_A_DQS0
MA_ADD8 MB_ADD8 9 DDR_B_DQS0 MB_DQS_H0 MA_DQS_H0 DDR_A_DQS0 8
DDR_A_MA9 K22 K26 DDR_B_MA9 DDR_B_DQS#0 B12 H13 DDR_A_DQS#0
MA_ADD9 MB_ADD9 9 DDR_B_DQS#0 MB_DQS_L0 MA_DQS_L0 DDR_A_DQS#0 8
DDR_A_MA10 R21 T26 DDR_B_MA10 DDR_B_DQS1 D16 G16 DDR_A_DQS1
MA_ADD10 MB_ADD10 9 DDR_B_DQS1 MB_DQS_H1 MA_DQS_H1 DDR_A_DQS1 8
DDR_A_MA11 L22 L26 DDR_B_MA11 DDR_B_DQS#1 C16 G15 DDR_A_DQS#1
MA_ADD11 MB_ADD11 9 DDR_B_DQS#1 MB_DQS_L1 MA_DQS_L1 DDR_A_DQS#1 8
DDR_A_MA12 K20 L25 DDR_B_MA12 DDR_B_DQS2 A24 C22 DDR_A_DQS2
MA_ADD12 MB_ADD12 9 DDR_B_DQS2 MB_DQS_H2 MA_DQS_H2 DDR_A_DQS2 8
DDR_A_MA13 V24 W24 DDR_B_MA13 DDR_B_DQS#2 A23 C21 DDR_A_DQS#2
MA_ADD13 MB_ADD13 9 DDR_B_DQS#2 MB_DQS_L2 MA_DQS_L2 DDR_A_DQS#2 8
DDR_A_MA14 K24 J23 DDR_B_MA14 DDR_B_DQS3 F26 G22 DDR_A_DQS3
MA_ADD14 MB_ADD14 9 DDR_B_DQS3 MB_DQS_H3 MA_DQS_H3 DDR_A_DQS3 8
DDR_A_MA15 K19 J24 DDR_B_MA15 DDR_B_DQS#3 E26 G21 DDR_A_DQS#3
MA_ADD15 MB_ADD15 9 DDR_B_DQS#3 MB_DQS_L3 MA_DQS_L3 DDR_A_DQS#3 8
DDR_B_DQS4 AC25 AD23 DDR_A_DQS4
9 DDR_B_DQS4 MB_DQS_H4 MA_DQS_H4 DDR_A_DQS4 8
DDR_A_BS#0 R20 R24 DDR_B_BS#0 DDR_B_DQS#4 AC26 AC23 DDR_A_DQS#4
8 DDR_A_BS#0 MA_BANK0 MB_BANK0 DDR_B_BS#0 9 9 DDR_B_DQS#4 MB_DQS_L4 MA_DQS_L4 DDR_A_DQS#4 8
DDR_A_BS#1 R23 U26 DDR_B_BS#1 DDR_B_DQS5 AF21 AB19 DDR_A_DQS5
8 DDR_A_BS#1 MA_BANK1 MB_BANK1 DDR_B_BS#1 9 9 DDR_B_DQS5 MB_DQS_H5 MA_DQS_H5 DDR_A_DQS5 8
DDR_A_BS#2 J21 J26 DDR_B_BS#2 DDR_B_DQS#5 AF22 AB20 DDR_A_DQS#5
8 DDR_A_BS#2 MA_BANK2 MB_BANK2 DDR_B_BS#2 9 9 DDR_B_DQS#5 MB_DQS_L5 MA_DQS_L5 DDR_A_DQS#5 8
DDR_B_DQS6 AE16 Y15 DDR_A_DQS6
9 DDR_B_DQS6 MB_DQS_H6 MA_DQS_H6 DDR_A_DQS6 8
DDR_A_RAS# R19 U25 DDR_B_RAS# DDR_B_DQS#6 AD16 W15 DDR_A_DQS#6
8 DDR_A_RAS# MA_RAS_L MB_RAS_L DDR_B_RAS# 9 9 DDR_B_DQS#6 MB_DQS_L6 MA_DQS_L6 DDR_A_DQS#6 8
DDR_A_CAS# T22 U24 DDR_B_CAS# DDR_B_DQS7 AF12 W12 DDR_A_DQS7
8 DDR_A_CAS# MA_CAS_L MB_CAS_L DDR_B_CAS# 9 9 DDR_B_DQS7 MB_DQS_H7 MA_DQS_H7 DDR_A_DQS7 8
DDR_A_WE# T24 U23 DDR_B_WE# DDR_B_DQS#7 AE12 W13 DDR_A_DQS#7
8 DDR_A_WE# MA_WE_L MB_WE_L DDR_B_WE# 9 9 DDR_B_DQS#7 MB_DQS_L7 MA_DQS_L7 DDR_A_DQS#7 8
FOX_PZ6382A-284S-41F_GRIFFIN FOX_PZ6382A-284S-41F_GRIFFIN
Athlon 64 S1 Athlon 64 S1
4 Processor Processor Socket 4
Socket CONN@
CONN@
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AMD CPU S1G2 DDRII I/F
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4111P 0.4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, March 07, 2008 Sheet 5 of 54
A B C D E
A B C D E
+2.5VDDA
VDDA=300mA
L1
+2.5VS 1 2 3300P_0402_50V7K 1 2
02/27 Change net name to EN0.
+1.8V
1 FBM_L11_201209_300L_0805 R10 10K_0402_5% @ R6 0_0402_5%
1 1 1 1 2 1 2 EN0 37,39
@ C16 + R5 300_0402_5%
02/15 Reserve C16.
2
B
100U_D2_10VM 4.7U_0805_10V4Z C17 C18 C19 Q3 1 2 H_THERMTRIP#_EC 33
0.22U_0603_16V4Z R16 0_0402_5%
2 2 2 2
C
CPU_THERMTRIP#_R 3 1 1 2 H_THERMTRIP# 20
PMBT3904_SOT23 R7 0_0402_5%
JCPUD
+1.8V 2 1
F8 M11 R11 @ 10K_0402_5%
1 VDDA1 KEY1 1
Place close to CPU wihtin 1.5" F9 VDDA2 KEY2 W18 1 2
2
B
R9 300_0402_5% @ MMBT3904_NL_SOT23-3
1 2 3900P_0402_50V7K CPU_CLKIN_SC_P A9 A6 CPU_SVC Q2
15 CLK_CPU_BCLK CLKIN_H SVC CPU_SVC 43
E
C20 CPU_CLKIN_SC_N A8 A4 CPU_SVD CPU_PROCHOT#_1.8 3 1
CLKIN_L SVD CPU_SVD 43 H_PROCHOT# 19
C
LDT_RST# B7 1 2
0718 Silego -- 216 ohm R8 H_PWRGD_CPU A7
RESET_L 02/12 Remove R59. @ R59 0_0402_5%
169_0402_1% LDT_STOP# PWROK CPU_THERMTRIP#_R
F10 LDTSTOP_L THERMTRIP_L AF6
CPU_LDT_REQ# C6 AC7 CPU_PROCHOT#_1.8 R17 +1.8V
2
LDTREQ_L PROCHOT_L CPU_MEMHOT#_1.8V
15 CLK_CPU_BCLK# 1 2 MEMHOT_L AA8 2 1 +1.8V
C21 3900P_0402_50V7K CPU_SIC AF4 R22 1K_0402_5%
CPU_SID SIC @ 300_0402_5% CPU_SVC
Address:100_1100 AF5 SID 1 2
AE6 W7 THERMDC_CPU CPU_SVD 1 2
ALERT_L THERMDC THERMDA_CPU R23 1K_0402_5%
THERMDA W8
R13 1 2 44.2_0402_1% CPU_HTREF0 R6
R14 HT_REF0
+1.2V_HT 1 2 44.2_0402_1% CPU_HTREF1 P6 HT_REF1 0718 AMD --> 1K ohm
CPU_VDD0_FB_H F6 W9
43 CPU_VDD0_FB_H
43 CPU_VDD0_FB_L CPU_VDD0_FB_L E6
VDD0_FB_H VDDIO_FB_H
Y9
PAD
PAD
T42
T43
+1.8V sense no support
VDD0_FB_L VDDIO_FB_L +CPU_CORE_NB
43 CPU_VDD1_FB_H CPU_VDD1_FB_H Y6 H6 VDD_NB_FB_H
VDD1_FB_H VDDNB_FB_H VDD_NB_FB_H 43
43 CPU_VDD1_FB_L CPU_VDD1_FB_L AB6 G6 VDD_NB_FB_L R484 10_0402_5%
VDD1_FB_L VDDNB_FB_L VDD_NB_FB_L 43
VDD_NB_FB_H 1 2
CPU_DBRDY G10 VDD_NB_FB_L 1 2
CPU_TMS DBRDY CPU_DBREQ# R485 10_0402_5%
AA9 TMS DBREQ_L E10
CPU_TCK AC9
CPU_TRST# TCK CPU_TDO
AD9 TRST_L TDO AE9 Close to CPU
CPU_TDI AF9 TDI
+1.8VS T4 PAD CPU_TEST23_TSTUPD AD7 J7 CPU_TEST28_H_PLLCHRZ_P route as differential
+CPU_CORE_0 TEST23 TEST28_H PAD T5
H8 CPU_TEST28_L_PLLCHRZ_N as short as possible
TEST28_L PAD T6
R487 10_0402_5% CPU_TEST19_PLLTEST0 H10 testpoint under package
TEST18
2
2 2
1 2CPU_VDD0_FB_H CPU_TEST18_PLLTEST1 G9 TEST19 TEST17 D7 CPU_TEST17_BP3
PAD T7
R15 1 2CPU_VDD0_FB_L E7 CPU_TEST16_BP2
TEST16 PAD T8
300_0402_5% R486 10_0402_5% T9 PAD CPU_TEST25_H_BYPASSCLK_H E9 F7 CPU_TEST15_BP1
TEST25_H TEST15 PAD T10
T11 PAD CPU_TEST25_L_BYPASSCLK_L E8 C7 CPU_TEST14_BP0
TEST25_L TEST14 PAD T12
Close to CPU
1
@ C1 C5
R21 @ C939 0.1U_0402_16V4Z RSVD5 RSVD6
300_0402_5% R175
@ R814 FOX_PZ6382A-284S-41F_GRIFFIN
+3VS 2 1 2 1 CONN@
1
0.1U_0402_16V7K
2
CPU_SID 3 1 SMB_EC_DA1
02/15 Change R18 and R19
3 SMB_EC_DA1 32,33,34,37 3
R18 @ from 390 to 2.2K ohm.
S
+1.8V 2 1 Q127
2.2K_0402_5% FDV301N_NL_SOT23-3
+1.8VS R19
03/04 Reserve R175, R814, C939, Q127 and Q129.
+1.8V 2 1
2
G
2.2K_0402_5% FDV301N_NL_SOT23-3
2
300_0402_5%
EC is PU to 5VALW
1
@ 220_0402_5% R38
@ 220_0402_5% R39
@ 220_0402_5% R40
300_0402_5% R41
0.01U_0402_25V4Z Max = 1.5V CPU_TEST21_SCANEN R26 1 2 300_0402_5%
@ +3VS CPU_TEST20_SCANCLK2 R27 2 1 @ 300_0402_5%
1
1
2 CPU_TEST24_SCANCLK1 R28 300_0402_5%
2 1
CPU_TEST22_SCANSHIFTEN R29 2 1 @ 300_0402_5%
JP3 CPU_TEST12_SCANSHIFTENB R31 2 1 @ 300_0402_5%
0.1U_0402_16V4Z
CPU_TDI
R30 THERMDA_CPU 2 CPU_TRST# 15 16
D+ SDATA 7 SMB_EC_DA2 33 17 18
5
300_0402_5% C27 CPU_TDO U1
THERMDC_CPU 3 19 20 LDT_RST#
1 2 6 2
P
2200P_0402_50V7K D- ALERT# 21 22 HDT_RST# B
4
1
4 CPU_LDT_REQ# 23 24 Y 4
CPU_LDT_REQ# 11,19 4 THERM# GND 5 26 A 1 SB_PWRGD 20,33,43
G
2200p change to NOTE: HDT TERMINATION IS REQUIRED
1 1000p for ADT7421 @ NC7SZ08P5X_NL_SC70-5
FOR REV. Ax SILICON ONLY.
3
C24 ADM1032ARMZ-2REEL_MSOP8 @ SAMTEC_ASP-68200-07
0.01U_0402_25V4Z 9/20 SP020016900
@ Address:100_1101
2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AMD CPU S1G2 CTRL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4111P 0.4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, March 07, 2008 Sheet 6 of 54
A B C D E
A B C D E
+0.9V
3 Under CPU Socket Near Power Supply 3
VTT decoupling. 1
C: Change to NBO CAP
+ C59
220U_Y_4VM
2
Between CPU Socket and DIMM
+1.8V
+0.9V
1 1 1 1
C55 C56 C57 C58
0.22U_0603_16V4Z 0.22U_0603_16V4Z 0.22U_0603_16V4Z 0.22U_0603_16V4Z
2 2 2 2 1 1 1 1 1 1 1 1
C66 C67 C68 C69 C70 C71 C72 C73
4.7U_0805_10V4Z 4.7U_0805_10V4Z 0.22U_0603_16V4Z 0.22U_0603_16V4Z 1000P_0402_25V8J 1000P_0402_25V8J 180P_0402_50V8J 180P_0402_50V8J
1 1 1 1 1 1
Near CPU Socket Right side.
C60 C61 C62 C63 C64 C65 +0.9V
0.01U_0402_25V4Z 0.01U_0402_25V4Z 180P_0402_50V8J 180P_0402_50V8J 180P_0402_50V8J 180P_0402_50V8J
2 2 2 2 2 2
A: Add C165 and C176 1 1 1 1 1 1 1 1
to follow AMD Layout C79 C80 C81 C82 C83 C84 C85 C86
4.7U_0805_10V4Z 4.7U_0805_10V4Z 0.22U_0603_16V4Z 0.22U_0603_16V4Z 1000P_0402_25V8J 1000P_0402_25V8J 180P_0402_50V8J 180P_0402_50V8J
+1.8V
review recommand for
EMI 2 2 2 2 2 2 2 2
4 4
1
C: Change to NBO CAP
1 1 1 1
+ C78 Near CPU Socket Left side.
C74 C75 C76 C77 220U_Y_4VM
4.7U_0805_10V4Z 4.7U_0805_10V4Z 4.7U_0805_10V4Z 4.7U_0805_10V4Z
2 2 2 2 2 @
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AMD CPU S1G2 PWR & GND
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4111P 0.4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, March 07, 2008 Sheet 7 of 54
A B C D E
A B C D E
+V_DDR_MCH_REF
2
RP4
41 42 R43 DDR_A_MA5 8 1 1 2
DDR_A_D16 VSS VSS DDR_A_D20 1K_0402_1% DDR_A_MA8 C93 0.1U_0402_16V4Z
43 DQ16 DQ20 44 7 2
DDR_A_D17 45 46 DDR_A_D21 DDR_A_MA9 6 3 1 2
DQ17 DQ21 DDR_A_MA12 C94 0.1U_0402_16V4Z
47 48 5 4
1
DDR_A_DQS#2 VSS VSS +V_DDR_MCH_REF
49 DQS2# NC 50 +V_DDR_MCH_REF 9
DDR_A_DQS2 51 52 DDR_A_DM2 47_0804_8P4R_5%
DQS2 DM2 RP5
53 VSS VSS 54 1 1
2
DDR_A_D18 55 56 DDR_A_D22 C95 C96 DDR_A_BS#0 8 1 1 2
DDR_A_D19 DQ18 DQ22 DDR_A_D23 R44 DDR_A_MA10 C98 0.1U_0402_16V4Z
57 DQ19 DQ23 58 7 2
59 60 1K_0402_1% DDR_A_MA1 6 3 1 2
DDR_A_D24 VSS VSS DDR_A_D28 2 2 DDR_A_MA3 C97 0.1U_0402_16V4Z
61 DQ24 DQ28 62 5 4
DDR_A_D25 63 64 DDR_A_D29 1000P_0402_25V8J
1
DQ25 DQ29 47_0804_8P4R_5%
65 VSS VSS 66
DDR_A_DM3 67 68 DDR_A_DQS#3 0.1U_0402_16V4Z RP6
DM3 DQS3# DDR_A_DQS3 DDR_A_ODT1
69 NC DQS3 70 8 1 1 2
71 72 DDR_CS1_DIMMA# 7 2 C100 0.1U_0402_16V4Z
2 DDR_A_D26 VSS VSS DDR_A_D30 DDR_A_WE# 2
73 DQ26 DQ30 74 6 3 1 2
DDR_A_D27 75 76 DDR_A_D31 DDR_A_CAS# 5 4 C99 0.1U_0402_16V4Z
DQ27 DQ31
77 VSS VSS 78
DDR_CKE0_DIMMA 79 80 DDR_CKE1_DIMMA 47_0804_8P4R_5%
5 DDR_CKE0_DIMMA CKE0 NC/CKE1 DDR_CKE1_DIMMA 5
81 82 RP7
VDD VDD DDR_A_MA15 DDR_CS0_DIMMA#
83 NC NC/A15 84 8 1 1 2
DDR_A_BS#2 85 86 DDR_A_MA14 DDR_A_RAS# 7 2 C102 0.1U_0402_16V4Z
5 DDR_A_BS#2 BA2 NC/A14
87 88 DDR_A_MA13 6 3 1 2
DDR_A_MA12 VDD VDD DDR_A_MA11 DDR_A_ODT0 C101 0.1U_0402_16V4Z
89 A12 A11 90 5 4
DDR_A_MA9 91 92 DDR_A_MA7
DDR_A_MA8 A9 A7 DDR_A_MA6 47_0804_8P4R_5%
93 A8 A6 94
95 VDD VDD 96 Cross between +1.8V and +0.9V power plan
DDR_A_MA5 97 98 DDR_A_MA4
DDR_A_MA3 A5 A4 DDR_A_MA2
99 A3 A2 100
DDR_A_MA1 101 102 DDR_A_MA0
A1 A0
103 VDD VDD 104
DDR_A_MA10 105 106 DDR_A_BS#1
A10/AP BA1 DDR_A_BS#1 5
DDR_A_BS#0 107 108 DDR_A_RAS#
5 DDR_A_BS#0 BA0 RAS# DDR_A_RAS# 5
DDR_A_WE# 109 110 DDR_CS0_DIMMA#
5 DDR_A_WE# WE# S0# DDR_CS0_DIMMA# 5
111 VDD VDD 112
DDR_A_CAS# 113 114 DDR_A_ODT0
5 DDR_A_CAS# CAS# ODT0 DDR_A_ODT0 5
DDR_CS1_DIMMA# 115 116 DDR_A_MA13
5 DDR_CS1_DIMMA# NC/S1# NC/A13
117 VDD VDD 118
DDR_A_ODT1 119 120
5 DDR_A_ODT1 NC/ODT1 NC
121 VSS VSS 122
DDR_A_D32 123 124 DDR_A_D36
DDR_A_D33 DQ32 DQ36 DDR_A_D37
125 DQ33 DQ37 126
127 VSS VSS 128
DDR_A_DQS#4 129 130 DDR_A_DM4
DDR_A_DQS4 DQS4# DM4
131 DQS4 VSS 132
133 134 DDR_A_D38
DDR_A_D34 VSS DQ38 DDR_A_D39
135 DQ34 DQ39 136
3 DDR_A_D35 3
137 DQ35 VSS 138
139 140 DDR_A_D44
DDR_A_D40 VSS DQ44 DDR_A_D45
141 DQ40 DQ45 142
DDR_A_D41 143 144
DQ41 VSS DDR_A_DQS#5
145 VSS DQS5# 146
DDR_A_DM5 147 148 DDR_A_DQS5
DM5 DQS5
149 VSS VSS 150
DDR_A_D42 151 152 DDR_A_D46
DDR_A_D43 DQ42 DQ46 DDR_A_D47
153 DQ43 DQ47 154
155 VSS VSS 156
DDR_A_D48 157 158 DDR_A_D52
DDR_A_D49 DQ48 DQ52 DDR_A_D53
159 DQ49 DQ53 160
161 VSS VSS 162
163 NC,TEST CK1 164 DDR_A_CLK1 5
165 VSS CK1# 166 DDR_A_CLK#1 5
DDR_A_DQS#6 167 168
DDR_A_DQS6 DQS6# VSS DDR_A_DM6
169 DQS6 DM6 170
171 VSS VSS 172
DDR_A_D50 173 174 DDR_A_D54
DDR_A_D51 DQ50 DQ54 DDR_A_D55
175 DQ51 DQ55 176
177 VSS VSS 178
DDR_A_D56 179 180 DDR_A_D60
DDR_A_D57 DQ56 DQ60 DDR_A_D61
181 DQ57 DQ61 182
183 VSS VSS 184
DDR_A_DM7 185 186 DDR_A_DQS#7
DM7 DQS7# DDR_A_DQS7
187 VSS DQS7 188
DDR_A_D58 189 190
DDR_A_D59 DQ58 VSS DDR_A_D62
191 DQ59 DQ62 192
193 194 DDR_A_D63
VSS DQ63
9,15,20,30 SMB_CK_DAT0 195 SDA VSS 196
9,15,20,30 SMB_CK_CLK0 197 SCL SA0 198
+3VS 199 VDDSPD SA1 200
4 4
1
C103 FOX_AS0A426-N8RN-7F
0.1U_0402_16V4Z CONN@
2 9/20 SP07000BZ00/SP07000EU00
DDR2 SOCKET H9.2 (REV)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDRII SO-DIMM 0
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4111P 0.4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, March 07, 2008 Sheet 8 of 54
A B C D E
A B C D E
47_0804_8P4R_5%
41 VSS VSS 42
DDR_B_D21 43 44 DDR_B_D20 RP11
DDR_B_D17 DQ16 DQ20 DDR_B_D16 DDR_B_MA5
45 DQ17 DQ21 46 8 1 2 1
47 48 DDR_B_MA8 7 2 C111 0.1U_0402_16V4Z
DDR_B_DQS#2 VSS VSS DDR_B_MA9
49 DQS2# NC 50 6 3 1 2
DDR_B_DQS2 51 52 DDR_B_DM2 DDR_B_MA12 5 4 C112 0.1U_0402_16V4Z
DQS2 DM2
53 VSS VSS 54
DDR_B_D18 55 56 DDR_B_D22 47_0804_8P4R_5%
DDR_B_D19 DQ18 DQ22 DDR_B_D23
57 DQ19 DQ23 58
59 60 RP12
DDR_B_D24 VSS VSS DDR_B_D28 DDR_B_MA10
61 DQ24 DQ28 62 8 1 2 1
DDR_B_D25 63 64 DDR_B_D29 DDR_B_BS#0 7 2 C114 0.1U_0402_16V4Z
DQ25 DQ29 DDR_B_MA1
65 VSS VSS 66 6 3 1 2
DDR_B_DM3 67 68 DDR_B_DQS#3 DDR_B_MA3 5 4 C113 0.1U_0402_16V4Z
DM3 DQS3# DDR_B_DQS3
69 NC DQS3 70
71 72 47_0804_8P4R_5%
DDR_B_D26 VSS VSS DDR_B_D30
73 DQ26 DQ30 74
DDR_B_D27 75 76 DDR_B_D31 RP13
2 DQ27 DQ31 DDR_B_ODT1 2
77 VSS VSS 78 8 1 2 1
DDR_CKE0_DIMMB 79 80 DDR_CKE1_DIMMB DDR_CS1_DIMMB# 7 2 C116 0.1U_0402_16V4Z
5 DDR_CKE0_DIMMB CKE0 NC/CKE1 DDR_CKE1_DIMMB 5
81 82 DDR_B_CAS# 6 3 1 2
VDD VDD DDR_B_MA15 DDR_B_WE# C115 0.1U_0402_16V4Z
83 NC NC/A15 84 5 4
DDR_B_BS#2 85 86 DDR_B_MA14
5 DDR_B_BS#2 BA2 NC/A14
87 88 47_0804_8P4R_5%
DDR_B_MA12 VDD VDD DDR_B_MA11
89 A12 A11 90
DDR_B_MA9 91 92 DDR_B_MA7 RP14
DDR_B_MA8 A9 A7 DDR_B_MA6 DDR_B_RAS#
93 A8 A6 94 8 1 2 1
95 96 DDR_B_BS#1 7 2 C118 0.1U_0402_16V4Z
DDR_B_MA5 VDD VDD DDR_B_MA4 DDR_B_ODT0
97 A5 A4 98 6 3 1 2
DDR_B_MA3 99 100 DDR_B_MA2 DDR_B_MA13 5 4 C117 0.1U_0402_16V4Z
DDR_B_MA1 A3 A2 DDR_B_MA0
101 A1 A0 102
103 104 47_0804_8P4R_5%
DDR_B_MA10 VDD VDD DDR_B_BS#1
105 A10/AP BA1 106 DDR_B_BS#1 5 Cross between +1.8V and +0.9V power plan
DDR_B_BS#0 107 108 DDR_B_RAS#
5 DDR_B_BS#0 BA0 RAS# DDR_B_RAS# 5
DDR_B_WE# 109 110 DDR_CS0_DIMMB#
5 DDR_B_WE# WE# S0# DDR_CS0_DIMMB# 5
111 VDD VDD 112
DDR_B_CAS# 113 114 DDR_B_ODT0
5 DDR_B_CAS# CAS# ODT0 DDR_B_ODT0 5
DDR_CS1_DIMMB# 115 116 DDR_B_MA13
5 DDR_CS1_DIMMB# NC/S1# NC/A13
117 VDD VDD 118
DDR_B_ODT1 119 120
5 DDR_B_ODT1 NC/ODT1 NC
121 VSS VSS 122
DDR_B_D32 123 124 DDR_B_D36
DDR_B_D33 DQ32 DQ36 DDR_B_D37
125 DQ33 DQ37 126
127 VSS VSS 128
DDR_B_DQS#4 129 130 DDR_B_DM4
DDR_B_DQS4 DQS4# DM4
131 DQS4 VSS 132
133 134 DDR_B_D38
DDR_B_D34 VSS DQ38 DDR_B_D39
135 DQ34 DQ39 136
DDR_B_D35 137 138
DQ35 VSS DDR_B_D44
139 VSS DQ44 140
3 DDR_B_D40 DDR_B_D45 3
141 DQ40 DQ45 142
DDR_B_D41 143 144
DQ41 VSS DDR_B_DQS#5
145 VSS DQS5# 146
DDR_B_DM5 147 148 DDR_B_DQS5
DM5 DQS5
149 VSS VSS 150
DDR_B_D42 151 152 DDR_B_D46
DDR_B_D43 DQ42 DQ46 DDR_B_D47
153 DQ43 DQ47 154
155 VSS VSS 156
DDR_B_D48 157 158 DDR_B_D52
DDR_B_D49 DQ48 DQ52 DDR_B_D53
159 DQ49 DQ53 160
161 VSS VSS 162
163 NC,TEST CK1 164 DDR_B_CLK1 5
165 VSS CK1# 166 DDR_B_CLK#1 5
DDR_B_DQS#6 167 168
DDR_B_DQS6 DQS6# VSS DDR_B_DM6
169 DQS6 DM6 170
171 VSS VSS 172
DDR_B_D50 173 174 DDR_B_D54
DDR_B_D51 DQ50 DQ54 DDR_B_D55
175 DQ51 DQ55 176
177 VSS VSS 178
DDR_B_D56 179 180 DDR_B_D60
DDR_B_D57 DQ56 DQ60 DDR_B_D61
181 DQ57 DQ61 182
183 VSS VSS 184
DDR_B_DM7 185 186 DDR_B_DQS#7
DM7 DQS7# DDR_B_DQS7
187 VSS DQS7 188
DDR_B_D58 189 190
DDR_B_D59 DQ58 VSS DDR_B_D62
191 DQ59 DQ62 192
193 194 DDR_B_D63
VSS DQ63
8,15,20,30 SMB_CK_DAT0 195 SDA VSS 196
8,15,20,30 SMB_CK_CLK0 197 SCL SAO 198 +3VS
+3VS 199 VDDSPD SA1 200
1 201 GND GND 202
4 C119 TYCO_292527-4 4
0.1U_0402_16V4Z CONN@
2
9/20 SP07000ET00/SP07000GN00
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDRII SO-DIMM 1
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4111P 0.4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, March 07, 2008 Sheet 9 of 54
A B C D E
A B C D E
U3B
D4 GFX_RX0P GFX_TX0P A5 TMDS_B_DATA2 18
C4 GFX_RX0N PART 2 OF 6 GFX_TX0N B5 TMDS_B_DATA2# 18
A3 GFX_RX1P GFX_TX1P A4 TMDS_B_DATA1 18
B3 GFX_RX1N GFX_TX1N B4 TMDS_B_DATA1# 18
C2 GFX_RX2P GFX_TX2P C3 TMDS_B_DATA0 18
C1 GFX_RX2N GFX_TX2N B2 TMDS_B_DATA0# 18
E5 GFX_RX3P GFX_TX3P D1 TMDS_B_CLK 18
F5 GFX_RX3N GFX_TX3N D2 TMDS_B_CLK# 18
G5 GFX_RX4P GFX_TX4P E2
G6 GFX_RX4N GFX_TX4N E1
1 1
H5 GFX_RX5P GFX_TX5P F4
H6 GFX_RX5N GFX_TX5N F3
J6 GFX_RX6P GFX_TX6P F1
J5 GFX_RX6N GFX_TX6N F2
J7 GFX_RX7P GFX_TX7P H4
J8 GFX_RX7N GFX_TX7N H3
L5 GFX_RX8P GFX_TX8P H1
L6 GFX_RX8N GFX_TX8N H2
M8 GFX_RX9P GFX_TX9P J2
L8 GFX_RX9N GFX_TX9N J1
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
RS780-HT/PCIE
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4111P 0.4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, March 07, 2008 Sheet 10 of 54
A B C D E
A B C D E
1 1
+3VS
L2 AVDD=100mA
1 2 +AVDD1
+1.8VS
BLM18PG121SN1D_0603 1
L4
+AVDD2 C170
+1.8VS 0_0603_5% 2.2U_0603_6.3V4Z
R67 1 2
L6
1 2 NB_LDTSTOP# 1 2 +AVDDQ C172
6,19 LDT_STOP#
BLM18PG121SN1D_0603 2.2U_0603_6.3V4Z U3C
0_0402_5% 2
1 F12 AVDD1(NC) TXOUT_L0P(NC) A22 LVDS_A0+ 17
E12 AVDD2(NC) PART 3 OF 6 TXOUT_L0N(NC) B22 LVDS_A0- 17
C175 F14 AVDDDI(NC) A21 LVDS_A1+ 17
2.2U_0603_6.3V4Z TXOUT_L1P(NC)
R68 G15 AVSSDI(NC) TXOUT_L1N(NC) B21 LVDS_A1- 17
2
H15 AVDDQ(NC) TXOUT_L2P(NC) B20 LVDS_A2+ 17
1 2 NB_ALLOW_LDTSTOP H14 AVSSQ(NC) A20 LVDS_A2- 17
6,19 CPU_LDT_REQ# TXOUT_L2N(DBG_GPIO0)
TXOUT_L3P(NC) A19
0_0402_5% T46 PAD TV_CRMA E17 B19
T47 PAD TV_LUMA C_Pr(DFT_GPIO5) TXOUT_L3N(DBG_GPIO2)
CRT/TVOUT
F17 Y(DFT_GPIO2)
T48 PAD TV_COMPS F15 B18
RED COMP_Pb(DFT_GPIO4) TXOUT_U0P(NC)
1
@ R62
2
150_0402_1% RED G18
TXOUT_U0N(NC) A18
A17
PA_RS780A4
16 RED RED(DFT_GPIO0) TXOUT_U1P(PCIE_RESET_GPIO3)
1 2 GREEN G17 REDb(NC) TXOUT_U1N(PCIE_RESET_GPIO2) B17 placement close to NB ball
@ R63 150_0402_1% GREEN E18 D20
02/22 Reserve R62, R63, R64. 1 2 BLUE
16 GREEN
F18
GREEN(DFT_GPIO1) TXOUT_U2P(NC)
D21
@ R64 150_0402_1% BLUE GREENb(NC) TXOUT_U2N(NC)
16 BLUE E19 BLUE(DFT_GPIO3) TXOUT_U3P(PCIE_RESET_GPIO5) D18
F19 BLUEb(NC) TXOUT_U3N(NC) D19
2 +1.1VS L9 CRT_HSYNC A11 B16 2
14,16 CRT_HSYNC DAC_HSYNC(PWM_GPIO4) TXCLK_LP(DBG_GPIO1) LVDS_ACLK+ 17
1 2 CRT_VSYNC B11 A16 LVDS_ACLK- 17
14,16 CRT_VSYNC DAC_VSYNC(PWM_GPIO6) TXCLK_LN(DBG_GPIO3)
BLM18PG121SN1D_0603 1 F8 D16
+1.8VS 16 UMA_CRT_CLK DAC_SCL(PCE_RCALRN) TXCLK_UP(PCIE_RESET_GPIO4)
L7 C178 E8 D17
1 2
16 UMA_CRT_DAT DAC_SDA(PCE_TCALRN) TXCLK_UN(PCIE_RESET_GPIO1) 03/03 Add C1120.
BLM18PG121SN1D_0603 1 2.2U_0603_6.3V4Z R65 1 2 715_0402_1% G14 L3
+1.8VS L10 C176 2 DAC_RSET(PWM_GPIO1) +VDDLTP18
VDDLTP18(NC) A13 1 2 +1.8VS
1 2 +NB_PLLVDD A12 B13 1 1 BLM18PG121SN1D_0603
BLM18PG121SN1D_0603 2.2U_0603_6.3V4Z +NB_HTPVDD PLLVDD(NC) VSSLTP18(NC)
1 D14 PLLVDD18(NC)
+1.8VS L11 C179 2 +VDDLT18 C171 C1120
B12 A15
LVTM
PLLVSS(NC) VDDLT18_1(NC) 2.2U_0603_6.3V4Z 0.1U_0402_16V4Z
1 2 B15
PLL PWR
BLM18PG121SN1D_0603 2.2U_0603_6.3V4Z +VDDA18HTPLL VDDLT18_2(NC) 2 L5 2
1 H17 VDDA18HTPLL VDDLT33_1(NC) A14
2
VDDLT33_2(NC) B14 1 2 +1.8VS
C180 +VDDA18PCIEPLL D7 1 1 BLM18PG121SN1D_0603
2.2U_0603_6.3V4Z VDDA18PCIEPLL1
E7 VDDA18PCIEPLL2 VSSLT1(VSS) C14
2 R66 0_0402_5% C173 C174
VSSLT2(VSS) D15
14,19,25,26,27,32,33 PLT_RST# 1 2 NB_RESET# D8 SYSRESETb VSSLT3(VSS) C16 0.1U_0402_16V4Z 4.7U_0805_10V4Z
NB_PWRGD 2 2
20 NB_PWRGD A10 POWERGOOD VSSLT4(VSS) C18
NB_LDTSTOP# C10 C20 0.08A/10mil/1vias
1 2 NB_ALLOW_LDTSTOP C12
LDTSTOPb VSSLT5(VSS)
E20 L
PM
+1.8VS ALLOW_LDTSTOP VSSLT6(VSS)
R371 300_0402_5% C22
02/18 Change R371 from 10K to 300 ohm. VSSLT7(VSS)
15 CLK_NBHT C25
C24
HT_REFCLKP 03/03 Add D58 and connect to PWM
15 CLK_NBHT# HT_REFCLKN
E11
03/06 Add R1085 and R1086.
15 NB_OSC_14.318M REFCLK_P/OSCIN(OSCIN)
CLOCKs
F11 E9 R69 1 2 0_0402_5% UMA_ENVDD 17 @ R1084
REFCLK_N(PWM_GPIO3) LVDS_DIGON(PCE_TCALRP) NB_PWM 0_0402_5%
LVDS_BLON(PCE_RCALRP) F7 1 2 INV_PWM 17,33
+1.1VS 1 2 1 2 T2 G12 1 2 0_0402_5% ENBKL 33
15 NBGFX_CLK GFX_REFCLKP LVDS_ENA_BL(PWM_GPIO2)
R71 R72 T1 @ R73
15 NBGFX_CLK# GFX_REFCLKN
4.7K_0402_5% 4.7K_0402_5%
U1 1 2 R1085 1 2 0_0402_5% ENBKL
GPP_REFCLKP @ R1072 100K_0402_5%
U2 GPP_REFCLKN
3 3
15 CLK_SBLINK_BCLK V4 GPPSB_REFCLKP(SB_REFCLKP) 1 2
V3 R1086 100K_0402_5%
15 CLK_SBLINK_BCLK# GPPSB_REFCLKN(SB_REFCLKN)
17 LCD_DDC_CLK B9 I2C_CLK
17 LCD_DDC_DAT A9
B8
I2C_DATA MIS. TMDS_HPD(NC) D9
D10
HPD 18
18 HDMIDAT_UMA DDC_DATA0/AUX0N(NC) HPD(NC)
18 HDMICLK_UMA A8 DDC_CLK0/AUX0P(NC) SUS_STAT_R# 14 Strap pin
14 RS780_DFT_GPIO_0 B7 DDC_CLK1/AUX1P(NC) SUS_STAT#(PWM_GPIO5) D12 1 2 SUS_STAT# 20
Strap pin A7 R77 0_0402_5%
DDC_DATA1/AUX1N(NC)
THERMALDIODE_P AE8 NB_THERMAL_DA PAD T49
+3VS 2 1 B10 STRP_DATA THERMALDIODE_N AD8 NB_THERMAL_DC PAD T50 NB temp to SB
R88 10K_0402_5%
G11 RSVD TESTMODE D13 1 2
R80
C8 1.8K_0402_5%
14 AUX_CAL AUX_CAL(NC)
Strap pin
RS780MN_FCBGA528
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
RS780 VEDIO/CLK GEN
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4111P 0.4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, March 07, 2008 Sheet 11 of 54
A B C D E
A B C D E
U61 U3D
MEM_BA0 L2 B9 MEM_DQ15 PAR 4 OF 6
MEM_BA1 BA0 DQ15 MEM_DQ11 MEM_A0 MEM_DQ0
L3 BA1 DQ14 B1 AB12 MEM_A0(NC) MEM_DQ0/DVO_VSYNC(NC) AA18
D9 MEM_DQ13 MEM_A1 AE16 AA20 MEM_DQ1
MEM_A12 DQ13 MEM_DQ12 MEM_A2 MEM_A1(NC) MEM_DQ1/DVO_HSYNC(NC) MEM_DQ2
R2 A12 DQ12 D1 V11 MEM_A2(NC) MEM_DQ2/DVO_DE(NC) AA19
MEM_A11 P7 D3 MEM_DQ8 MEM_A3 AE15 Y19 MEM_DQ3
MEM_A10 A11 DQ11 MEM_DQ10 MEM_A4 MEM_A3(NC) MEM_DQ3/DVO_D0(NC) MEM_DQ4
M2 A10/AP DQ10 D7 AA12 MEM_A4(NC) MEM_DQ4(NC) V17
1 MEM_A9 MEM_DQ9 MEM_A5 MEM_DQ5 1
P3 A9 DQ9 C2 AB16 MEM_A5(NC) MEM_DQ5/DVO_D1(NC) AA17
MEM_A8 P8 C8 MEM_DQ14 MEM_A6 AB14 AA15 MEM_DQ6
MEM_A7 A8 DQ8 MEM_DQ3 MEM_A7 MEM_A6(NC) MEM_DQ6/DVO_D2(NC) MEM_DQ7
P2 A7 DQ7 F9 AD14 MEM_A7(NC) MEM_DQ7/DVO_D4(NC) Y15
MEM_A6 N7 F1 MEM_DQ7 MEM_A8 AD13 AC20 MEM_DQ8
MEM_A5 A6 DQ6 MEM_DQ1 MEM_A9 MEM_A8(NC) MEM_DQ8/DVO_D3(NC) MEM_DQ9
N3 A5 DQ5 H9 AD15 MEM_A9(NC) MEM_DQ9/DVO_D5(NC) AD19
SBD_MEM/DVO_I/F
MEM_A4 N8 H1 MEM_DQ6 MEM_A10 AC16 AE22 MEM_DQ10
MEM_A3 A4 DQ4 MEM_DQ5 MEM_A11 MEM_A10(NC) MEM_DQ10/DVO_D6(NC) MEM_DQ11
N2 A3 DQ3 H3 AE13 MEM_A11(NC) MEM_DQ11/DVO_D7(NC) AC18
MEM_A2 M7 H7 MEM_DQ0 MEM_A12 AC14 AB20 MEM_DQ12
MEM_A1 A2 DQ2 MEM_DQ4 MEM_A12(NC) MEM_DQ12(NC) MEM_DQ13
M3 A1 DQ1 G2 Y14 MEM_A13(NC) MEM_DQ13/DVO_D9(NC) AD22
MEM_A0 M8 G8 MEM_DQ2 AC22 MEM_DQ14
A0 DQ0 MEM_BA0 MEM_DQ14/DVO_D10(NC) MEM_DQ15
AD16 MEM_BA0(NC) MEM_DQ15/DVO_D11(NC) AD21
1
MEM_BA1 AE17
R91 MEM_CLKN MEM_BA2 MEM_BA1(NC) MEM_DQS_P0
K8 CK VDDQ A9 +1.8V_MEM_VDDQ AD17 MEM_BA2(NC) MEM_DQS0P/DVO_IDCKP(NC) Y17
MEM_CLKP J8 C1 W18 MEM_DQS_N0 MEM_COMP_P and MEM_COMP_N trace
100_0402_1% CK VDDQ MEM_RAS# MEM_DQS0N/DVO_IDCKN(NC) MEM_DQS_P1
C3 W12 AD20
SIDE@ MEM_CKE K2
VDDQ
C7 MEM_CAS# Y12
MEM_RASb(NC) MEM_DQS1P(NC)
AE21 MEM_DQS_N1 width >=10mils and 10mils spacing from
2
MEM_DQS_P0 F7 SIDE@1U_0603_10V6K
MEM_DQS_N0 LDQS 2
E8 LDQS VSSQ A7 Layout Note: 50 mil for VSSDL
VSSQ B2
VSSQ B8
VSSQ D2
MEM_DQS_P1 B7 D8
MEM_DQS_N1 UDQS VSSQ
A8 UDQS VSSQ E7
VSSQ F2
VSSQ F8
+MEM_VREF J2 H2
VREF VSSQ
VSSQ H8
A2 NC
E2 NC VSS A3
MEM_BA2 L1 E3
NC VSS
R3 NC VSS J3
R7 NC VSS N1
R8 NC VSS P9
HY5PS561621AFP-25_FBGA84
SIDE@
3 3
Side Port disable,VREF need
connect to +1.8VS for DDR2
+1.8V_MEM_VDDQ +1.8V_MEM_VDDQ
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
2
1K_0402_1%
1K_0402_1%
1 1
+1.8V_MEM_VDDQ
+1.8VS
C195
C196
R97
L15
2 2
1 2
1
22U_0805_6.3V6M
1U_0402_6.3V4Z
1U_0402_6.3V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
SIDE@ 0_0805_5%
+MEM_VREF +MEM_VREF1
2 2 1 1 1 220 ohm @ 100MHz,2A
0.1U_0402_16V4Z
0.1U_0402_16V4Z
C608
C607
C201
C202
1 1 2 2 2
1K_0402_1%
1K_0402_1%
C199
C200
R99
1
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
RS780 Side-Port DDR2 SDRAM
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4111P 0.4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, March 07, 2008 Sheet 12 of 54
A B C D E
A B C D E
U3F
1 1
A25 VSSAHT1 VSSAPCIE1 A2
02/15 Change L16, L18, L19, L22 from bead to 0 ohm resistor. D23 VSSAHT2 PART 6/6 VSSAPCIE2 B1
E22 VSSAHT3 VSSAPCIE3 D3
G22 VSSAHT4 VSSAPCIE4 D5
L 0.6A/50mil/4vias G24 VSSAHT5 VSSAPCIE5 E4
G25 VSSAHT6 VSSAPCIE6 G1
L16 2A
2 1 +VDDHT
03/03 Remove L20, L21 and use PJP604 to replace. H19
J22
VSSAHT7 VSSAPCIE7 G2
G4
+1.1VS VSSAHT8 VSSAPCIE8
0.1U_0402_16V4Z 0.1U_0402_16V4Z L17 H7
0_0805_5% VSSAHT9 VSSAPCIE9
1 C206 1 1 C2081 1 L22 VSSAHT10 VSSAPCIE10 J4
C210 0.7A/60mil/4vias L17 L24 R7
C209
4.7U_0805_10V4Z C207
L 1 2 +1.1VS L25
VSSAHT11
VSSAHT12
VSSAPCIE11
VSSAPCIE12 L1
0.1U_0402_16V4Z VDDA_12=2.5A FBMA-L11-201209-221LMA30T_0805 M20 L2
2 2 2 2 2 U3E VSSAHT13 VSSAPCIE13
N22 VSSAHT14 VSSAPCIE14 L4
0.1U_0402_16V4Z J17 A6 +VDDA11PCIE P20 L7
VDDHT_1 VDDPCIE_1 C211 10U_0805_10V4Z VSSAHT15 VSSAPCIE15
K16 VDDHT_2 PART 5/6 VDDPCIE_2 B6 R19 VSSAHT16 VSSAPCIE16 M6
GROUND
H18 VDDHTRX_1 VDDPCIE_9 J9 1 2 W22 VSSAHT23 VSSAPCIE23 U4
4.7U_0805_10V4Z C216 0.1U_0402_16V4Z G19 K9 C224 2 1 0.1U_0402_16V4Z W24 V8
2 2 2 2 2 VDDHTRX_2 VDDPCIE_10 C223 0.1U_0402_16V4Z VSSAHT24 VSSAPCIE24
F20 VDDHTRX_3 VDDPCIE_11 M9 2 1 W25 VSSAHT25 VSSAPCIE25 V6
0.1U_0402_16V4Z E21 L9 Y21 W1
VDDHTRX_4 VDDPCIE_12 VSSAHT26 VSSAPCIE26
D22 VDDHTRX_5 VDDPCIE_13 P9 AD25 VSSAHT27 VSSAPCIE27 W2
B23 VDDHTRX_6 VDDPCIE_14 R9 VSSAPCIE28 W4
POWER
02/15 Remove L95. V18 VDDHTTX_8 VDDC_6 M12
L 7A/280mil/16vias VDD_CORE=5A U11 VSS20 VSSAPCIE38 AE1
U17 VDDHTTX_9 VDDC_7 L14 U15 VSS21 VSSAPCIE39 AE4
4.7U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z T17 L11 330U_D2E_2.5VM_R15 V12 AB2
0.1U_0402_16V4Z 0.1U_0402_16V4Z VDDHTTX_10 VDDC_8 VSS22 VSSAPCIE40
R17 VDDHTTX_11 VDDC_9 M13 W11 VSS23
P17 VDDHTTX_12 VDDC_10 M15 W15 VSS24
L 0.25A/30mil/2vias M17 VDDHTTX_13 VDDC_11 N12 AC12 VSS25 VSS1 AE14
C247
C240
C241
C242
C243
C230
C231
C244
C232
C233
C245
L22 2A N14 1 AA14 D11
+VDDA18PCIE VDDC_12 C234 VSS26 VSS2
+1.8VS 2 1 J10 VDDA18PCIE_1 VDDC_13 P11 1 1 1 1 1 1 1 1 1 1 1 Y18 VSS27 VSS3 G8
P10 P13 + AB11 E14
0_0805_5% VDDA18PCIE_2 VDDC_14 VSS28 VSS4
1 1 1 1 1 1 K10 VDDA18PCIE_3 VDDC_15 P14 AB15 VSS29 VSS5 E15
10U_0805_10V4Z
10U_0805_10V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
M10 VDDA18PCIE_4 VDDC_16 R12 AB17 VSS30 VSS6 J15
C235 C246 C236 C237 C238 C239 2 2 2 2 2 2 2 2 2 2 2 2
L10 VDDA18PCIE_5 VDDC_17 R15 AB19 VSS31 VSS7 J12
4.7U_0805_10V4Z W9 T11 AE20 K14
2 2 2 2 2 2 VDDA18PCIE_6 VDDC_18 VSS32 VSS8
H9 VDDA18PCIE_7 VDDC_19 T15 AB21 VSS33 VSS9 M11
T10 VDDA18PCIE_8 VDDC_20 U12 K11 VSS34 VSS10 L15
R10 VDDA18PCIE_9 VDDC_21 T14
4.7U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z Y9 J16 RS780MN_FCBGA528
0.1U_0402_16V4Z 0.1U_0402_16V4Z VDDA18PCIE_10 VDDC_22
AA9 VDDA18PCIE_11
AB9 VDDA18PCIE_12 VDD_MEM1(NC) AE10
AD9 AA11 +1.8VS
VDDA18PCIE_13 VDD_MEM2(NC)
AE9 VDDA18PCIE_14 VDD_MEM3(NC) Y11
U10 VDDA18PCIE_15 VDD_MEM4(NC) AD10
AB10 SIDE@0_0603_5% C249 2 1 SIDE@4.7U_0805_10V4Z
VDD_MEM5(NC) +1.8V_VDD_MEM 1 C248 SIDE@0.1U_0402_16V4Z
+1.8VS F9 VDD18_1 VDD_MEM6(NC) AC10 2 2 1
G9 R1054 C597 2 1 SIDE@0.1U_0402_16V4Z
VDD18_2
1 2 +1.8V_VDD_SP AE11 H11 0.15A/30mil/2vias C598 2 1 SIDE@0.1U_0402_16V4Z
3
+1.8VS
R1051 0_0603_5% AD11
VDD18_MEM1(NC)
VDD18_MEM2(NC)
VDD33_1(NC)
VDD33_2(NC) H12 L C599 2 1 SIDE@0.1U_0402_16V4Z
3
1 1 RS780MN_FCBGA528
C251 +3VS
1U_0402_6.3V4Z C252
1U_0402_6.3V4Z 1 2
2 2 0.1U_0402_16V4Z C250
1 2
0.1U_0402_16V4Z C253
3 VREF NC 7 1
@ 10U_0805_10V4Z C1065
2 R1015 4 VOUT NC 8
1K_0402_1% @ 1U_0603_10V6K
2
9
2
TP
@ G2992F1U_SO8
@ +VREF1.35V
+1.35VS
1
Q163 R1016
@ 2N7002_SOT23-3 2 1
1
4 D @ 3K_0402_5% C1067 4
36 VLDT_EN# 1 2 2
2
C1068
@ 0.1U_0402_16V7K @ 0.1U_0402_16V7K
1
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/08/02 Deciphered Date 2008/08/02 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
RS780 PWR/GND
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4111P 0.4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, March 07, 2008 Sheet 13 of 54
A B C D E
A B C D E
1 1
DFT_GPIO5:STRAP_DEBUG_BUS_GPIO_ENABLEb
RS780 DFT_GPIO5 mux at CRT_VSYNC pull low to 3K
11,16 CRT_VSYNC 2 1 +3VS Enables the Test Debug Bus using GPIO.
R101 1K_0402_5%
1 : Disable (RS780) Enable (RX780)
2 1
R102 @ 1K_0402_5% 0 : Enable (RS780) Disable (RX780)
PIN: RX780:NB_TV_C; RS740: RS740_DFT_GPIO5; RS780: VSYNC#
2 2
DFT_GPIO1: LOAD_EEPROM_STRAPS
11 AUX_CAL 1 2
@ R104 150_0402_1% Selects Loading of STRAPS from EPROM
D4 @ CH751H-40PT_SOD323-2
1 : Bypass the loading of EEPROM straps and use Hardware Default Values
RS780 DFT_GPIO1 2 1 0 : I2C Master can load strap values from EEPROM if connected, or use
11 SUS_STAT_R# PLT_RST# 11,19,25,26,27,32,33
default values if not connected
RS740/RX780: DFT_GPIO1 RS780:SUS_STAT
RX780 DFT_GPIO1 mux at GREEN(Ball E18) and change pull low form 150 to 3K.
3 3
DFT_GPIO0: STRAP_DEBUG_BUS_PCIE_ENABLEb
11 RS780_DFT_GPIO_0 2 1
@ R105 1K_0402_5% RX780: Enables the Test Debug Bus using PCIE bus
1 : Disable ( Can still be enabled using nbcfg register access )
0 : Enable
RS780 use HSYNC to enable SIDE PORT (internal pull high)
RS740/RS780: Enables Side port memory ( RS780 use HSYNC#)
1. Disable (RS740/RS780)
11,16 CRT_HSYNC 2 1
R107 SIDE@3K_0402_5% 0 : Enable (RS740/RS780)
2 1 +3VS
R1064 3K_0402_5%
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
RS780 STRAPS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4111P 0.4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, March 07, 2008 Sheet 14 of 54
A B C D E
A B C D E
+3VS +3VS_CLK
R167
+1.2V_HT +VDDCLK_IO
1 2
R168 0_0805_5% 1 1 1 1 1 1 1 1
1 2 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z C445 C446 C447 C448 C449 C450 @ C451
0_0805_5% C444
1 1 1 1 1 1
10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 1U_0402_6.3V4Z
C452 C453 C454 C455 C456 C457 2 2 2 2 2 2 2 2
10U_0805_10V4Z
2 2 2 2 2 2
0.1U_0402_16V4Z 0.1U_0402_16V4Z 1 1 1 1
C458 C459 C460 C461
1 1
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
2 2 2 2
CLK_48M_USB
+3VS_CLK
CLK_XTAL_OUT 1 2 RS780 1.1V 200R/100R 12P_0402_50V8J
R380 90.9_0402_1% 2
1
CLK_XTAL_IN R220 33_0402_5%
1 2
03/06 Add C1123. C1076 2
CLK_14M_SIO 32
Y2 CLK_NBHT 11
+3VS_CLK
+3VS_CLK
2
NB_OSC_14.318M_R
NB C1123
CLK_NBHT# 11
12P_0402_50V8J
CLK_48M_USB_R
2 1 1 2
CLK_XTAL_OUT
1 2 +3VS_CLK C1075
CLK_CPU_BCLK 6
CLK_XTAL_IN
14.31818MHZ_20P_6X1430004201 R174 8.2K_0402_5% 12P_0402_50V8J
SEL_SATA
1U_0402_6.3V4Z
2
27M_SEL
1 1
2 C464 C465 CLK_CPU_BCLK_R R186 2
1 2
R946 0_0402_1% @ 261_0402_1% CPU
22P_0402_50V8J 22P_0402_50V8J CLK_CPU_BCLK#_R 1 2
2 2 R945 0_0402_1%
1
+3VS_CLK
CLK_CPU_BCLK# 6
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
Routing the trace at least 10mil U10
1
GND
XTAL_IN
REF_1/SEL_SATA
VSS_48
48MHz_0
48MHz_1
VDD_48
XTAL_OUT
HTT_0/66M_0
HTT_0#/66M_1
PD#
CPU_K8_0
VSS_REF
REF_0/SEL_HTT66
REF_2/SEL_27
VDD_REF
VDD_HTT
VSS_HTT
CPU_K8_0#
C1106
0.1U_0603_25V7K
2
8,9,20,30 SMB_CK_CLK0 1 SCL VDD_CPU 54 +3VS_CLK
8,9,20,30 SMB_CK_DAT0 2 SDA VDD_CPU_I/O 53 +VDDCLK_IO
+3VS_CLK 3 VDD_DOT VSS_CPU 52
4 51 CLKREQ_NCARD#
SRC_7#/27M CLKREQ_1# CLKREQ_MCARD2# CLKREQ_NCARD# 26
5
6
SRC_7/27M_SS CLKREQ_2# 50
49
CLKREQ_MCARD2# 26 02/25 Add C1106.
VSS_DOT VDD_A +3VS_CLK
7 SRC_5# VSS_A 48
8 SRC_5 VSS_SATA 47
PA_RS7X0A1 11 CLK_SBLINK_BCLK# 9 SRC_4# SRC_6/SATA 46 CLK_SBSRC_BCLK 19 PA_RS7X0A1
SB LINK 11 CLK_SBLINK_BCLK 10 SRC_4 SRC_6#/SATA# 45 CLK_SBSRC_BCLK# 19 SB SRC
11 VSS_SRC VDD_SATA 44 +3VS_CLK
+VDDCLK_IO 12 43 CLKREQ_MCARD1#
VDD_SRC_IO CLKREQ_3# CLKREQ_MCARD1# 26
13 42 CLKREQ4
26 CLK_PCIE_MCARD1# SRC_3# CLKREQ_4#
MiniCard_1 26 CLK_PCIE_MCARD1 14 SRC_3 SB_SRC_SLOW# 41 1 2 +3VS_CLK
15 40 R372 10K_0402_5% For ICS need to pull high.
26 CLK_PCIE_MCARD2# SRC_2# SB_SRC_0
MiniCard_2 26 CLK_PCIE_MCARD2 16 SRC_2 SB_SRC_0# 39 For SLG is NC
+3VS_CLK 17 VDD_SRC VDD_SB_SRC 38 +3VS_CLK
+VDDCLK_IO 18 VDD_SRC_IO VDD_SB_SRC_IO 37 +VDDCLK_IO
VDD_ATIG_IO
VSS_SB_SRC
ATIGCLK_2#
ATIGCLK_1#
ATIGCLK_0#
CLKREQ_0#
SB_SRC_1#
ATIGCLK_2
ATIGCLK_1
ATIGCLK_0
SB_SRC_1
VDD_ATIG
VSS_ATIG
3 3
VSS_SRC
SRC_1#
SRC_0#
SRC_1
SRC_0
SLG8SP626VTR_QFN72_10x10
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
CLKREQ_NCARD# 1 2 +3VS_CLK
+3VS_CLK 9/20 SA00001Z300 S IC SLG8SP626VTR QFN 72P CLK GEN R324 8.2K_0402_5%
9/20 SA000025B00 S IC RTM880N-795-GRT QFN 72P CLK GEN CLKREQ_MCARD2# 1 2
R325 8.2K_0402_5%
CLKREQ_MCARD1# 1 2
2
R326 8.2K_0402_5%
+3VS_CLK
@ R179 CLKREQ_LAN#
+VDDCLK_IO
1 2
8.2K_0402_5% R1039 8.2K_0402_5%
CLKREQ4 1 2
R1045 @ 8.2K_0402_5%
NBGFX_CLK 11
1
+3VS_CLK
SEL_SATA
NBGFX_CLK# 11 NB GFX
CLK_PCIE_MCARD0 27
CLK_PCIE_MCARD0# 27 Card Reader
2
CLKREQ_LAN#
CLKREQ_LAN# 25
R181 R180
CLK_PCIE_LAN 25
8.2K_0402_5% 8.2K_0402_5% GLAN NB CLOCK INPUT TABLE
CLK_PCIE_LAN# 25
NB CLOCKS RX780 RS780
CLK_PCIE_NCARD 26
1
NB_OSC_14.318M
1 configure as single-ended 66MHz output Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/08/02 Deciphered Date 2008/08/02 Title
0* configure as differential 100MHz output
* default
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Clock generator
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4111P 0.4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, March 07, 2008 Sheet 15 of 54
A B C D E
A B C D E
1
CRT CONNECTOR 1
1
@ D35 @ D37 @ D34 1
RB491D_SOT23 1A_6VDC_MINISMDC110
C475
0.1U_0402_16V4Z
+3VS 2
02/22 Change R214, R211, R217 from 150 ohm to 75 ohm. DAN217_SC59 DAN217_SC59DAN217_SC59
3
02/22 Change C858, C476, C472 from 22pF to 6pF.
JCRT
6 RGND
L47
RED 1 2 RED_L
11
1
ID0 02/25 Add C1107.
11 RED Red
BLM15AG121SN1D_0402 7
L48 D_DDCDATA GGND
12 SDA
11 GREEN GREEN 1 2 GREEN_L 2
BLM15AG121SN1D_0402 Green
8 BGND
L49 HSYNC 13 +CRT_VCC
BLUE BLUE_L Hsync
11 BLUE 1 2 3 Blue
BLM15AG121SN1D_0402 +CRT_VCC 9 +5V
6P_0402_50V8K
6P_0402_50V8K
6P_0402_50V8K
6P_0402_50V8K
6P_0402_50V8K
6P_0402_50V8K
VSYNC 14 1
Vsync
1 1 1 4 res
1
75_0402_1%
75_0402_1%
75_0402_1%
1 1 1 10 C1107
C471 C859 C469 C858 C476 C472 D_DDCCLK SGND 0.1U_0603_25V7K
15 SCL
R214 R211 R217 2
5 GND
2 2 2 2 2
2 2 2
16
2
GND
17 GND
CONN@ SUYIN_070546FR015S263ZR
RED_L 35
GREEN_L 35
+3VS BLUE_L 35
+CRT_VCC
+CRT_VCC
D_VSYNC 35
1
1 2 D_HSYNC 35
R237 R238 C473
5
1
4.7K_0402_5% 4.7K_0402_5% R100 R218 0.1U_0402_16V4Z
P
OE#
2
A Y
G
11 UMA_CRT_DAT 1 6 D_DDCDATA U14
D_DDCDATA 35
Q10A SN74AHCT1G125GW_SOT353-5
3
2N7002DW-7-F_SOT363-6
5
11 UMA_CRT_CLK 4 3 D_DDCCLK 1 2
D_DDCCLK 35
5
1
Q10B @ C477
2N7002DW-7-F_SOT363-6 1 1 0.1U_0402_16V4Z
P
OE#
2 4 D_VSYNC R241 1 2 0_0603_5% VSYNC
11,14 CRT_VSYNC A Y
@ C857 @ C856
10P_0402_50V8J
10P_0402_50V8J
3 U13 3
470P_0402_50V8J 2 2 470P_0402_50V8J SN74AHCT1G125GW_SOT353-5 1 1
3
@ C474 @ C470
2 2
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CRT Connector
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4111P 0.4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, March 07, 2008 Sheet 16 of 54
A B C D E
A B C D E
1
U54
G916 Vref=1.25V when U54 install
1
PJP4 PJP6
1 PAD-OPEN 2x2m PAD-OPEN 2x2m 1 5 R891 G916-390T1UF 1
VIN VOUT
2 @ 215K_0402_1% C718 install when U54 is
GND
2 L
2
2 3 4 C719 RT9193-39GB
C720 EN BP
1
RT9193-39GB_SOT23-5 1 10U_0805_10V4Z
10U_0805_10V4Z C718 R892 1
1
1
R1013 0.1U_0402_16V4Z @ 100K_0402_1% Close to JLVDS
2 L
2
0_0402_5%
D22
2
@ R1014 +USB_CAM 4 2 USB20_P5
VIN IO1
1 2 CAM_SHDN# 21
0_0402_5% USB20_N5 3 1
IO2 GND
@ PRTR5V0U2X_SOT143-4
02/26 Add PJP6 to connect to +5VS. Stuff R1013 and reserve R1014.
+LCDVDD +5VALW
2
2 2
R225 R224 +3VS
220_0402_5% 1M_0402_5%
03/06 Change R225 from 470 ohm to 220 ohm.
80mil
6 2
3
S
SI2301BDS-T1-E3_SOT23-3
G
Q45A 2
2N7002DW-7-F_SOT363-6 R222 Q43
2 1 2
100K_0402_5% D
2
1
3
C863 80mil
B+ +LCDVDD
1000P_0402_50V7K
+LCDVDD INVPWR_B+ 1
11 UMA_ENVDD 5
Q45B 1
2
1 2N7002DW-7-F_SOT363-6
4
R276 C487 C491
680P_0402_50V7K L44 C1108 2.2K_0402_5% 4.7U_0805_10V4Z 0.1U_0402_16V4Z
C479 680P_0402_50V7K 2
1 2
FBMA-L11-201209-221LMA30T_0805 2
1
1
1
C480
680P_0402_50V7K
LVDS CONN 02/25 Add C1108.
2
2 JLVDS
1 2 LVDS_A2- LVDS_A2- 11
LVDS_A2- C1056 1 2
1 2 @ 10P_0402_50V8J LVDS_A2+ 3 3 4 4 LVDS_A2+ LVDS_A2+ 11
5 6 LVDS_A1- LVDS_A1- 11
LVDS_A1- C1057 5 6
1 2 @ 10P_0402_50V8J LVDS_A1+ 7 7 8 8 LVDS_A1+ LVDS_A1+ 11
3 LVDS_A0- 3
9 9 10 10 LVDS_A0- 11
LVDS_A0- C1058 1 2 @ 10P_0402_50V8J LVDS_A0+ 11 12 LVDS_A0+ LVDS_A0+ 11
USB20_P5 11 12 LVDS_ACLK-
20 USB20_P5 13 13 14 14 LVDS_ACLK- 11
LVDS_ACLK- C1059 1 2 @ 10P_0402_50V8J LVDS_ACLK+ 20 USB20_N5 USB20_N5 15 16 LVDS_ACLK+ LVDS_ACLK+ 11
15 16
17 17 18 18
19 19 20 20
21 21 22 22
+3VS 23 24 DMIC_DAT +5VS
23 24 DMIC_DAT 28
25 26 DMIC_CLK DMIC_CLK 28 R491
25 26
27 27 28 28 1 2 200_0805_5%
29 30 INV_PWM INV_PWM 11,33
29 30
1
680P_0402_50V7K
680P_0402_50V7K
41 42 BKOFF# 1 2
GND GND @ 4.7K_0402_5% R483
1 1
680P_0402_50V7K
680P_0402_50V7K
ACES_88242-4001
C482
C483
CONN@ LCD_DDC_CLK 1 2
C866
C867
4.7K_0402_5% R274
9/20 SP02000EA00/SP02000BW00 2 2
2
2
@ @ LCD_DDC_DAT 1 2
@ @ 4.7K_0402_5% R275
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LCD CONN. / WebCam
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4111P 0.4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, March 07, 2008 Sheet 17 of 54
A B C D E
A B C D E
+3VS +HDMI_5V_OUT
2
R176 R209
4.7K_0402_5% 4.7K_0402_5%
1 R210 R236 1
2
+HDMI_5V_OUT 6.8K_0402_5% 6.8K_0402_5%
1
HDMI_HPD 1 6 HDMI_SDATA
C851 11 HDMIDAT_UMA Q134A
2
2 1 +3VS 2N7002DW-7-F_SOT363-6
2
R615 2
5
1
5
0.1U_0402_16V4Z 2.2K_0402_5% C850
1 R628
P
OE#
2 4 100K_0402_5% 0.1U_0402_16V4Z 4 3 HDMI_SCLK
A Y HPD 11 1 11 HDMICLK_UMA Q134B
1
G
U39 2N7002DW-7-F_SOT363-6
SN74AHCT1G125GW_SOT353-5 C:Chg. PN to SB770020010.
2 2
03/07 Reserve 0 ohm and stuff common choke.
C852 1
1 1 2 2
HDMI Connector
10 TMDS_B_DATA2# 2 0.1U_0402_16V7K HDMI_TX2-
C853 1 2 0.1U_0402_16V7K HDMI_TX2+ 4 3 +HDMI_5V_OUT
10 TMDS_B_DATA2 4 3 JHDMI
WCM-2012-900T_4P 18 +5V
HDMI_TX0- 1 2 HDMI_R_D0- HDMI_SDATA 16 SDA 13
3 HDMI_CLK- HDMI_TX0- HDMI_TX1- HDMI_TX2- @ R116 0_0402_5% HDMI_SCLK CEC 3
15 SCL Reserved 14
HDMI_CLK+ HDMI_TX0+ HDMI_TX1+ HDMI_TX2+ HDMI_HPD 19 HP_DET
GND 2
HDMI_R_CK- 12 5
CK- GND
2
1
2
2
2
2
1
1
1
1
L88
1 1 2 2
4 4 3 3
03/07 Chagnge R315, R307, R173, R297, R172, R304, R139, R141 from 750 ohm to 715 ohm.
WCM-2012-900T_4P
HDMI_TX2- 1 2 HDMI_R_D2-
@ R120 0_0402_5%
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HDMI
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4111P 0.4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, March 07, 2008 Sheet 18 of 54
A B C D E
A B C D E
+3VALW
C506
2 1 Check AMD need pull low or not
5
@ 0.1U_0402_16V4Z U16
PCICLK2 23
2 1 2 NB_RST#_R U15A
P
B
Y 4PLT_RST# PLT_RST# 11,14,25,26,27,32,33
R300 @ 8.2K_0402_5%
SB700
NB_RST#_R 1 NB_RST#_R N2 P4
A A_RST# PCICLK0
G
@ NC7SZ08P5X_NL_SC70-5 Part 1 of 5 P3
PCICLK1
PCI CLKS
C492 1 2 0.1U_0402_16V7K SB_RX0P_C V23 P1
10 SB_RX0P
3
C493 0.1U_0402_16V7K SB_RX0N_C PCIE_TX0P PCICLK2 CLK_PCI_SIO_R R301 1 0_0402_5% PCI_CLK3
10 SB_RX0N 1 2 V22 PCIE_TX0N PCICLK3 P2 2 PCI_CLK3 23
C494 1 2 0.1U_0402_16V7K SB_RX1P_C V24 T4
10 SB_RX1P PCIE_TX1P PCICLK4 PCI_CLK4 23
C495 1 2 0.1U_0402_16V7K SB_RX1N_C V25 T3
10 SB_RX1N PCIE_TX1N PCICLK5/GPIO41 PCI_CLK5 23
2 1 C496 1 2 0.1U_0402_16V7K SB_RX2P_C U25
10 SB_RX2P PCIE_TX2P
R312 33_0402_5% C497 1 2 0.1U_0402_16V7K SB_RX2N_C U24
1 10 SB_RX2N PCIE_TX2N 1
C498 1 2 0.1U_0402_16V7K SB_RX3P_C T23
10 SB_RX3P PCIE_TX3P
C499 1 2 0.1U_0402_16V7K SB_RX3N_C T22 N1
10 SB_RX3N PCIE_TX3N PCIRST#
PCI INTERFACE
NB_HT_CLKP CBE0#
M25 NB_HT_CLKN CBE1# U7
AA7 C1086 12P_0402_50V8J
CBE2# CLK_PCI_SIO
P17 CPU_HT_CLKP CBE3# Y1 1 2
M18 CPU_HT_CLKN FRAME# AA6
W5 C1087 12P_0402_50V8J
DEVSEL# CLK_PCI_EC
M23 SLT_GFX_CLKP IRDY# AA5 1 2
M22 SLT_GFX_CLKN TRDY# Y5
PAR U6
J19 GPP_CLK0P STOP# W6
J18 GPP_CLK0N PERR# W4
SERR# V7 PCI_SERR# 33
L20 GPP_CLK1P REQ0# AC3
L19 GPP_CLK1N REQ1# AD4
@ R314 20M_0402_5% AB7
REQ2#
1 2 M19 GPP_CLK2P REQ3#/GPIO70 AE6
M20 AB6 PAD T15 @ R303 1 2 33_0402_5% CLK_PCI_SIO2
GPP_CLK2N REQ4#/GPIO71 CLK_PCI_SIO2 32
C643 GNT0# AD2
CLOCK GENERATOR
N22 GPP_CLK3P GNT1# AE4
1 2 SB_32KHI P22 AD5
GPP_CLK3N GNT2#
GNT3#/GPIO72 AC6
18P_0402_50V8J Y3 L18 AE5 PAD T16 LPCCLK1 R308 1 2 33_0402_5% CLK_PCI_SIO
25M_48M_66M_OSC GNT4#/GPIO73 CLK_PCI_SIO 32
1
INTF#/GPIO34
INTG#/GPIO35 AE2
3 SB_32KHO 3
1 2 J20 25M_X2 INTH#/GPIO36 AE3 PCI_PIRQH# R967 2 1 0_0402_5% ACCEL_INT 30
18P_0402_50V8J R302 33_0402_5%
LPCCLK0 G22 CLK_PCI_EC_R 1 2 CLK_PCI_EC CLK_PCI_EC 23,33
Close to SB LPCCLK1 E22 LPCCLK1 LPCCLK1 23
SB_32KHI A3 X1 LAD0 H24 LPC_AD0 32,33 STRAP PIN
LAD1 H23
J25
LPC_AD1 32,33 EC & Debug RP@ RM@
LAD2 LPC_AD2 32,33
J24 ZZZ ZZZ1
RTC XTAL
2
R1079 9/20 SA00001S510 S IC 218S7EALA11FG SB700 BGA 528P SB 0FH C509 C510 DAN202U_SC70 1K_0402_5% 3
J1 GND
1 2 4
2
43 H_PWRGD 2 2 GND
@ JUMP_43X39
0_0402_5%
03/04 Change net name from H_PWRGD to H_PWRGD_SB. 1U_0402_6.3V4Z CONN@ ACES_85205-02001
1
+RTCBATT_R
0.1U_0402_16V4Z 9/20 SP020008T00
03/04 Add R1079 and connect to CPU core.
1
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SB700-PCIE/PCI/ACPI/LPC/RTC
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4111P 0.4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, March 07, 2008 Sheet 19 of 54
A B C D E
A B C D E
11 NB_PWRGD
R1052 2 1 NBPWRGD
0_0402_5%
R1053 2 1
@ 100_0402_5%
For SB700 A11 divider to U15D
1.8V for RS & RX780
SB700 Part 4 of 5
E1 PCI_PME#/GEVENT4#
E2 RI#/EXTEVNT0# USBCLK/14M_25M_48M_OSC C8 CLK_48M_USB 15
1 demo circuit LID use RI# 1
H7 SLP_S2/GPM9#
F5 G8 USB_RCOMP 1 2
+3VS 33 SLP_S3# SLP_S3# USB_RCOMP
G1 11.8K_0402_1% R323
33 SLP_S5# SLP_S5#
USB MISC
33 PWRBTN_OUT# H2 PWR_BTN#
1 2 SUS_STAT# H1
6,33,43 SB_PWRGD PWR_GOOD
R388 4.7K_0402_5% SUS_STAT# K3
11 SUS_STAT# SUS_STAT#
SB_TEST2 H5 E6
SB_TEST1 TEST2 USB_FSD13P
H4 TEST1 USB_FSD13N E7
+3VALW SB_TEST0 H3 TEST0
USB 1.1
SB_TEST2
33 GATEA20 Y15 GA20IN/GEVENT0# USB_FSD12P F7 Touch Screen (delete)
1 2 33 KB_RST# W15 KBRST#/GEVENT1# USB_FSD12N E8
R320 @ 2.2K_0402_5% K4
33 EC_SCI# LPC_PME#/GEVENT3#
1 2 SB_TEST1 K24 H11 USB20_P11
33 EC_SMI# LPC_SMI#/EXTEVNT1# USB_HSD11P USB20_P11 26
R321 @ 2.2K_0402_5% PAD T19 F1 J10 USB20_N11 USB-11 New Card
S3_STATE/GEVENT5# USB_HSD11N USB20_N11 26
1 2 SB_TEST0 J2
R322 @ 2.2K_0402_5% PCIE_WAKE# SYS_RESET#/GPM7# USB20_P10
H6 WAKE#/GEVENT8# USB_HSD10P E11 USB20_P10 26
F2 F11 USB20_N10 USB-10 MiniCard(TV)
BLINK/GPM6# USB_HSD10N USB20_N10 26
H_THERMTRIP# J6
+3VS 6 H_THERMTRIP# SMBALERT#/THRMTRIP#/GEVENT2#
NBPWRGD W14 A11
NB_PWRGD USB_HSD9P
R328 SMB_CK_CLK0 EC_RSMRST# USB_HSD9N B11 USB-9 Card Reader (delete)
1 2 2.2K_0402_5% 33 EC_RSMRST# D3 RSMRST#
C10 USB20_P8
USB_HSD8P USB20_P8 26
2
R329 1 2 2.2K_0402_5% SMB_CK_DAT0 SB700 has internal PD D10 USB20_N8 USB-8 MiniCard(WWAN)
USB_HSD8N USB20_N8 26
R327
CH751H-40PT_SOD323-2 2.2K_0402_5% AE18 G11 USB20_P7
SATA_IS0#/GPIO10 USB_HSD7P USB20_P7 31
1 2 EC_RSMRST# AD18 H12 USB20_N7 USB-7 Fingerprint
+3VALW 39,41 3/5V_OK CLK_REQ3#/SATA_IS1#/GPIO6 USB_HSD7N USB20_N7 31
D58 AA19
1
SMARTVOLT1/SATA_IS2#/GPIO4 USB20_P6
W17 CLK_REQ0#/SATA_IS3#/GPIO0 USB_HSD6P E12 USB20_P6 31
R331 2 2.2K_0402_5% SMB_CK_CLK1 USB20_N6 USB-6 Bluetooth
1 03/06 Add D58. V17
W20
CLK_REQ1#/SATA_IS4#/FANOUT3/GPIO39 USB_HSD6N E14 USB20_N6 31
R332 SMB_CK_DAT1 CLK_REQ2#/SATA_IS5#/FANIN3/GPIO40 USB20_P5
1 2 2.2K_0402_5% 28 SB_SPKR W21 C12
USB 2.0
SPKR/GPIO2 USB_HSD5P USB20_P5 17
8,9,15,30 SMB_CK_CLK0 SMB_CK_CLK0 AA18 D12 USB20_N5 USB-5 USB Camera
2 SCL0/GPOC0# USB_HSD5N USB20_N5 17 2
8,9,15,30 SMB_CK_DAT0 SMB_CK_DAT0 W18
SMB_CK_CLK1 SDA0/GPOC1#
26 SMB_CK_CLK1 K1 SCL1/GPOC2# USB_HSD4P B12
SMB_CK_DAT1 K2 A12 USB-4 Left side
+3VALW 26 SMB_CK_DAT1 SDA1/GPOC3# USB_HSD4N
AA20 DDC1_SCL/GPIO9
+3VS
GPIO
Y18 G12 USB20_P3
R83 DDC1_SDA/GPIO8 USB_HSD3P USB20_P3 35
C1 G14 USB20_N3 USB-3 Dock
LLB#/GPIO66 USB_HSD3N USB20_N3 35
2
1 2 SB_GPIO5 Y19
R540 10K_0402_5% SMARTVOLT2/SHUTDOWN#/GPIO5 USB20_P2
G5 DDR3_RST#/GEVENT7# USB_HSD2P H14 USB20_P2 31
10K_0402_5% H15 USB20_N2 USB-2 Left Side
USB_HSD2N USB20_N2 31
A13 USB20_P1
03/06 Stuff R83. USB20_P1 31
1
USB_HSD1P USB20_N1
PCIE_WAKE# USB_HSD1N B13 USB20_N1 31 USB-1 Right side
25 LAN_PCIE_WAKE# 2 1
R993 0_0402_5% B14 USB20_P0
USB_HSD0P USB20_P0 31
2 1 B9 A14 USB20_N0 USB-0 Right side (S/W Debug Port)
26 MINI_PCIE_WAKE# USB_OC6#/IR_TX1/GEVENT6# USB_HSD0N USB20_N0 31
R994 @ 0_0402_5% B8 USB_OC5#/IR_TX0/GPM5#
A8 A18
USB OC
R82 0_0402_5% USB_OC4#/IR_RX0/GPM4# IMC_GPIO8
33 EC_LID_OUT# A9 USB_OC3#/IR_RX1/GPM3# IMC_GPIO9 B18
26 EXP_CPPE# EXP_CPPE# 1 2 E5 F21
CR_CPPE# USB_OC2#/GPM2# IMC_PWM0/IMC_GPIO10
27 CR_CPPE# 1 2 F8 USB_OC1#/GPM1# SCL2/IMC_GPIO11 D21
R333 33_0402_5% 1 2 R81 0_0402_5% E4 F19
28 HDA_BITCLK_CODEC USB_OC0#/GPM0# SDA2/IMC_GPIO12
R334 33_0402_5% 1 2 HDABITCLK 1 2 HDA_BITCLK E20
34 HDA_BITCLK_MDC SCL3_LV/IMC_GPIO13
R335 33_0402_5% 1 2 R1080 0_0402_5% M1 E21
34 HDA_SDOUT_MDC AZ_BITCLK SDA3_LV/IMC_GPIO14
R336 33_0402_5% 1 2 HDA_SDOUT M2 E19
28 HDA_SDOUT_CODEC AZ_SDOUT IMC_PWM1/IMC_GPIO15
HDA_SDIN0
28 HDA_SDIN0
HDA_SDIN1
J7 AZ_SDIN0/GPIO42 IMC_PWM2/IMC_GPO16 D19 GPIO16 23 STRAP PIN
34 HDA_SDIN1 J8
L8
AZ_SDIN1/GPIO43 IMC_PWM3/IMC_GPO17 E18 GPIO17 23 STRAP PIN
HD AUDIO
AZ_SDIN2/GPIO44
M3 AZ_SDIN3/GPIO46 IMC_GPIO18 G20
R337 33_0402_5% 1 2 HDA_SYNC L6 G21
34 HDA_SYNC_MDC AZ_SYNC IMC_GPIO19
R338 33_0402_5% 1 2 M4 D25
28 HDA_SYNC_CODEC AZ_RST# IMC_GPIO20
L5 AZ_DOCK_RST#/GPM8# IMC_GPIO21 D24
R339 33_0402_5% HDARST#
INTEGRATED uC
28 HDA_RST#_CODEC 1 2 IMC_GPIO22 C25
3 R340 33_0402_5% 3
34 HDA_RST#_MDC 1 2 IMC_GPIO23 C24
PAD T41 IMC_GPIO24 B25
IMC_GPIO25 C23
23,33 HDARST#
STRAP PIN IMC_GPIO26 B24
B23
IMC_GPIO27
IMC_GPIO28 A23
IMC_GPIO29 C22
IMC_GPIO30 A22
IMC_GPIO31 B22
IMC_GPIO32 B21
C1088 82P_0402_50V8J A21
HDA_BITCLK_CODEC IMC_GPIO33
1 2 H19 IMC_GPIO0 IMC_GPIO34 D20
H20 IMC_GPIO1 IMC_GPIO35 C20
C1089 82P_0402_50V8J
INTEGRATED uC
H21 SPI_CS2#/IMC_GPIO2 IMC_GPIO36 A20
1 2 HDA_BITCLK_MDC F25 B20
IDE_RST#/F_RST#/IMC_GPO3 IMC_GPIO37
IMC_GPIO38 B19
C1090 82P_0402_50V8J D22 A19
HDA_SDOUT_MDC IMC_GPIO4 IMC_GPIO39
1 2 E24 IMC_GPIO5 IMC_GPIO40 D18
E25 IMC_GPIO6 IMC_GPIO41 C18
C1091 82P_0402_50V8J D23
HDA_SDOUT_CODEC IMC_GPIO7
1 2
218S7EALA11FG_BGA528_SB700
+3VS
@ U66
7 VDD 1 HDA_BITCLK
CLKIN
4 HDABITCLK 4
6 CLKOUT NC 2
@ R1081
1
2 1 5
10K_0402_5% SSON NC 8
@ R1082 +3VS 03/05 Add SSC circuit for HDA_BITCLK.
@C1122 4 3 2 1
GND SS 10K_0402_5%
2
0.1U_0402_16V4Z ASM3P623S00BF-08TR_TSSOP8
2 @ R1083
10K_0402_5% Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/08/02 Deciphered Date 2008/08/02 Title
SB700 USB/AC97
1
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4111P 0.4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, March 07, 2008 Sheet 20 of 54
A B C D E
A B C D E
1
Y4
R341
25MHz_20pF_6X25000017 10M_0402_5%
2
10P_0402_50V8J 2 1 C517 SATA_X2
1 1
U15B
ATA 66/100/133
IDE_D2/GPIO17 AE22
31 SATA_RXN2_C AE12 SATA_RX2N IDE_D3/GPIO18 AC22
31 SATA_RXP2_C AD12 SATA_RX2P IDE_D4/GPIO19 AD21
SERIAL ATA
IDE_D8/GPIO23
24 SATA_RXN3_C AB14
AC14
SATA_RX3N IDE_D9/GPIO24 AC20
AD20
Samsung 0 1 0
24 SATA_RXP3_C SATA_RX3P IDE_D10/GPIO25
IDE_D11/GPIO26 AE21
AE14 SATA_TX4P IDE_D12/GPIO27 AB22
AD14 SATA_TX4N IDE_D13/GPIO28 AD22
AE23
AD15
IDE_D14/GPIO29
AC23
LFB_ID0 to LFB_ID2 got internal PU 10K to S5.
2 SATA_RX4N IDE_D15/GPIO30 2
AE15 SATA_RX4P LFB_ID2 R344 1 2 1K_0402_5%
AB16 R1032
SATA_TX5P LFB_ID1 R367 1
AC16 SATA_TX5N +3VALW 1 2 2 1K_0402_5%
G6 @ 10K_0402_5%
SPI_DI/GPIO12 LFB_ID0 R345 1
AE16 SATA_RX5N SPI_DO/GPIO11 D2 +3VALW 1 2 2 1K_0402_5%
AD16 D1 @ 10K_0402_5%
SATA_RX5P SPI_CLK/GPIO47 R1033
F4
SPI ROM
SATA_CAL SPI_HOLD#/GPIO31
2 1 V12 SATA_CAL SPI_CS1#/GPIO32 F3
R342 1K_0402_1%
SATA_X1 Y12 U15
R343 10K_0402_5% SATA_X1 LAN_RST#/GPIO13
ROM_RST#/GPIO14 J1
+3VS 1 2 SATA_X2 AA12 SATA_X2
FANOUT0/GPIO3 M8
34 SATA_LED# W11 SATA_ACT#/GPIO67 FANOUT1/GPIO48 M5 CR_WAKE# 27
+1.2V_HT M7 +3VALW
L54 FANOUT2/GPIO49
2 1 +PLLVDD_SATA AA11 P5
BLM18PG121SN1D_0603 PLLVDD_SATA FANIN0/GPIO50
FANIN1/GPIO51 P8 HDD_HALTLED# 34
SATA PWR
2 2 W12 XTLVDD_SATA FANIN2/GPIO52 R8 SB_INT_FLASH_SEL
1
C522 C523 C6 THERMAL_DC R1062 1 2 0_0402_5% R1071
1U_0402_6.3V4Z TEMP_COMM
1U_0402_6.3V4Z TEMPIN0/GPIO61 B6 WLOFF# 26 10K_0402_5%
1 1
TEMPIN1/GPIO62 A6 BT_COMBO_EN# 26
A5 WWOFF# 26
2
TEMPIN2/GPIO63
B5 EC_THERM# 33
HW MONITOR
TEMPIN3/TALERT#/GPIO64
+3VS A4 AC_IN_SB 2 1
VIN0/GPIO53 AC_IN 33,38
L55 B4 D56
VIN1/GPIO54 BT_OFF 31
2 1 +XTLVDD_SATA C4 CH751H-40PT_SOD323-2
VIN2/GPIO55 CAM_SHDN# 17
BLM18PG121SN1D_0603 2 D4
VIN3/GPIO56 LFB_ID0
VIN4/GPIO57 D5
3 C524 LFB_ID1 3
VIN5/GPIO58 D6
1U_0402_6.3V4Z A7 LFB_ID2
1 VIN6/GPIO59
B7
02/18 Add R1071 and D56 to connect to AC_IN.
VIN7/GPIO60
+3VALW
L56
F6 +SB_AVDD 2 1
AVDD BLM18PG121SN1D_0603
1 1
AVSS G7
C526
2.2U_0603_6.3V4Z
2 2
218S7EALA11FG_BGA528_SB700
C525
0.1U_0402_16V4Z
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SB700 SATA/IDE/SPI
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4111P 0.4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, March 07, 2008 Sheet 21 of 54
A B C D E
A B C D E
+
2 1 T15 VDDQ_3 VDD_3 M14 1 2 VSS_2 A25
1 C528 22U_0805_6.3V6M 22U_A_4VM C529 1
U9 N13 B1
CORE S0
C531 1U_0402_6.3V4Z VDDQ_4 VDD_4 1U_0402_6.3V4Z C532 VSS_3
1 2 U16 VDDQ_5 VDD_5 P12 2 1 VSS_4 D7
C530 1 2 1U_0402_6.3V4Z U17 P14 1U_0402_6.3V4Z 2 1 C534 T10 F20
VDDQ_6 VDD_6 AVSS_SATA_1 VSS_5
PCI/GPIO I/O
C533 1 2 1U_0402_6.3V4Z V8 R11 1U_0402_6.3V4Z 2 1 C538 U10 G19
C549 1U_0402_6.3V4Z VDDQ_7 VDD_7 1U_0402_6.3V4Z C537 AVSS_SATA_2 VSS_6
1 2 W7 VDDQ_8 VDD_8 R15 2 1 U11 AVSS_SATA_3 VSS_7 H8
C535 1 2 1U_0402_6.3V4Z Y6 T16 0.1U_0402_16V4Z 2 1 C527 U12 K9
C539 1U_0402_6.3V4Z VDDQ_9 VDD_9 0.1U_0402_16V4Z C540 AVSS_SATA_4 VSS_8
1 2 AA4 VDDQ_10 2 1 V11 AVSS_SATA_5 VSS_9 K11
C541 1 2 0.1U_0402_16V4Z AB5 V14 K16
C542 0.1U_0402_16V4Z VDDQ_11 AVSS_SATA_6 VSS_10
1 2 AB21 VDDQ_12 W9 AVSS_SATA_7 VSS_11 L4
Y9 AVSS_SATA_8 VSS_12 L7
L 0.45A/30mil/3vias Y11 AVSS_SATA_9 VSS_13 L10
IDE/FLSH I/O
CLKGEN I/O
C543 @ 22U_0805_6.3V6M VDD33_18_3 CKVDD_1.2V_3 C546 1U_0402_6.3V4Z AVSS_SATA_14 VSS_18
AE25 VDD33_18_4 CKVDD_1.2V_4 L25 1 2 AB13 AVSS_SATA_15 VSS_19 M10
C544 1 2 @ 1U_0402_6.3V4Z C545 1 2 1U_0402_6.3V4Z AB15 M11
C547 AVSS_SATA_16 VSS_20
1 2 @ 1U_0402_6.3V4Z C548 2 1 0.1U_0402_16V4Z AB17 AVSS_SATA_17 VSS_21 M13
C536 1 2 @ 1U_0402_6.3V4Z C551 2 1 0.1U_0402_16V4Z AC8 M15
C550 10U_0805_10V4Z AVSS_SATA_18 VSS_22
1 2 AD8 AVSS_SATA_19 VSS_23 N4
AE8 AVSS_SATA_20 VSS_24 N12
VSS_25 N14
+PCIE_VDDR P6
L61 POWER VSS_26
VSS_27 P9
+1.2V_HT 2 1 VSS_28 P10
0_0805_5% A15 P11
AVSS_USB_1 VSS_29
L 0.8A/50mil/4vias P18 PCIE_VDDR_1 +3VALW
B15 AVSS_USB_2 VSS_30 P13
C552
2 1
4.7U_0805_10V4Z
P19 PCIE_VDDR_2 L 0.1A/30mil/2vias ? C14 AVSS_USB_3 VSS_31 P15
P20 PCIE_VDDR_3 D8 AVSS_USB_4 VSS_32 R1
C553 1 2 1U_0402_6.3V4Z P21 A17 +S5_3V 1 2 D9 R2
A-LINK I/O
C555 1U_0402_6.3V4Z PCIE_VDDR_4 S5_3.3V_1 R564 0_0805_5% AVSS_USB_5 VSS_33
1 2 R22 PCIE_VDDR_5 S5_3.3V_2 A24 D11 AVSS_USB_6 VSS_34 R4
2 C554 1U_0402_6.3V4Z 2
1 2 R24 PCIE_VDDR_6 S5_3.3V_3 B17 1 2 D13 AVSS_USB_7 VSS_35 R9
GROUND
C558 1 2 1U_0402_6.3V4Z R25 J4 22U_0805_6.3V6M C556 D14 R10
PCIE_VDDR_7 S5_3.3V_4 AVSS_USB_8 VSS_36
3.3V_S5 I/O
C557 1 2 0.1U_0402_16V4Z J5 1U_0402_6.3V4Z 2 1 C559 D15 R12
C560 0.1U_0402_16V4Z S5_3.3V_5 1U_0402_6.3V4Z 2 C561 AVSS_USB_9 VSS_37
1 2 S5_3.3V_6 L1 1 E15 AVSS_USB_10 VSS_38 R14
L2 1U_0402_6.3V4Z 2 1 C562 F12 T11
+1.2V_SATA S5_3.3V_7 0.1U_0402_16V4Z 2 C563 AVSS_USB_11 VSS_39
1 F14 AVSS_USB_12 VSS_40 T12
L63 0.1U_0402_16V4Z 2 1 C564 G9 T14
0.1U_0402_16V4Z 2 C565 AVSS_USB_13 VSS_41
+1.2V_HT 2 1 AA14 AVDD_SATA_1 1 H9 AVSS_USB_14 VSS_42 U4
0_0805_5% AB18 +1.2VALW H17 U14
AVDD_SATA_4 AVSS_USB_15 VSS_43
L <1.25A/50mil/4vias AA15 AVDD_SATA_2 +S5_1.2V L64 0_0603_5%
J9 AVSS_USB_16 VSS_44 V6
2 1 AA17 G2 J11 Y21
CORE S5
AVDD_SATA_3 S5_1.2V_1 AVSS_USB_17 VSS_45
SATA I/O
C566 22U_0805_6.3V6M AC18 G4 J12 AB1
C567 1U_0805_16V7K AVDD_SATA_5 S5_1.2V_2 +1.2VALW 1U_0402_6.3V4Z AVSS_USB_18 VSS_46
1 2 AD17 AVDD_SATA_6 2 1 C569 J14 AVSS_USB_19 VSS_47 AB19
C568 1 2 1U_0805_16V7K AE17 0.1U_0402_16V4Z 2 1 C570 J15 AB25
C571 0.1U_0402_16V4Z AVDD_SATA_7 +1.2_USB L65 0_0603_5% AVSS_USB_20 VSS_48
1 2 K10 AVSS_USB_21 VSS_49 AE1
C572 1 2 0.1U_0402_16V4Z A10 K12 AE24
USB_PHY_1.2V_1 AVSS_USB_22 VSS_50
+
USB_PHY_1.2V_2 B10 1 2 K14 AVSS_USB_23
22U_A_4VM C573 K15
1U_0402_6.3V4Z 2 C574 AVSS_USB_24
1 PCIE_CK_VSS_9 P23
C567,C568 change to 1U_0402 when SI-2 1U_0402_6.3V4Z 2 1 C575 R16
L +AVDD_USB
PCIE_CK_VSS_10
PCIE_CK_VSS_11 R19
PCIE_CK_VSS_12 T17
L66 U18
+V5_VREF 1K_0402_5% 2 PCIE_CK_VSS_13
+3VALW 2 1 A16 AVDDTX_0 V5_VREF AE7 1 R346 +5VS H18 PCIE_CK_VSS_1 PCIE_CK_VSS_14 U20
0_0805_5% B16 D14 J17 V18
L <1.25A/50mil/4vias? C16
AVDDTX_1
AVDDTX_2 AVDDCK_3.3V J16 +AVDDCK_3.3V
2 2
1 2 +3VS J22
PCIE_CK_VSS_2
PCIE_CK_VSS_3
PCIE_CK_VSS_15
PCIE_CK_VSS_16 V20
C576 1 2 10U_0805_10V4Z D16 C578 C579 K25 V21
C577 10U_0805_10V4Z AVDDTX_3 +AVDDCK_1.2V 0.1U_0402_16V4Z 1U_0603_10V4Z CH751H-40PT_SOD323-2 PCIE_CK_VSS_4 PCIE_CK_VSS_17
1 2 D17 K17 M16 W19
PLL
0.1U_0402_16V4Z 2 1 C586
218S7EALA11FG_BGA528_SB700
L68
+AVDDCK_1.2V 2 1 +1.2V_HT
0_0805_5%
2.2U_0603_6.3V4Z 2 1 C587
0.1U_0402_16V4Z 2 1 C588
L69
+AVDDCK_3.3V 2 1 +3VS
0_0805_5%
2.2U_0603_6.3V4Z 2 1 C589
0.1U_0402_16V4Z 2 1 C590
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SB700 PWR/GND
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4111P 0.4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, March 07, 2008 Sheet 22 of 54
A B C D E
A B C D E
REQUIRED STRAPS NOTE: SB700 HAS INTERNAL 15K PULL UP RESISTOR FOR RTC_CLK
PCI_CLK2 PCI_CLK3 PCI_CLK4 PCI_CLK5 AZ_RST_CD# LPC_CLK1 RTC_CLK LPC_CLK0 GP17 GP16
PULL BOOTFAIL USE RESERVED RESERVED ENABLE PCI CLKGEN INTERNAL EC Internal pull up
1 HIGH TIMER DEBUG MEM BOOT ENABLED RTC ENABLED 1
H,H = Reserved
ENABLED STRAPS
DEFAULT
H,L = SPI ROM
EXT. RTC
PULL BOOTFAIL IGNORE DISABLE PCI CLKGEN (PD on X1, EC
LOW TIMER DEBUG MEM BOOT DISABLED apply DISABLED L,H = LPC ROM (Default)
DISABLED STRAPS 32KHz to DEFAULT L,L = FWH ROM
DEFAULT DEFAULT DEFAULT DEFAULT RTC_CLK)
+3VS +3VS +3VS +3VS +3VALW +3VALW +3VALW +3VALW +3VALW +3VALW
1
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
R356
R347
R348
R349
R350
R351
R352
R353
R354
R355
2.2K_0402_5%
2
@
@
@ @ @ @ @ @ @
19 PCICLK2
19 PCI_CLK3
19 PCI_CLK4
19 PCI_CLK5
19,33 CLK_PCI_EC
19 LPCCLK1
2
19 RTC_CLK 2
20,33 HDARST#
20 GPIO17
20 GPIO16
1
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
2.2K_0402_5%
2.2K_0402_5%
2.2K_0402_5%
R363
R365
R366
R357
R358
R359
R360
R361
R362
R364
2
2
@ @ @ @
DEBUG STRAPS
SB700 HAS 15K INTERNAL PU FOR PCI_AD[28:23]
USE USE PCI USE ACPI USE IDE USE DEFAULT RESERVED
3
PULL LONG PLL BCLK PLL PCIE STRAPS 3
HIGH RESET
DEFAULT DEFAULT DEFAULT DEFAULT DEFAULT
19 PCI_AD28
19 PCI_AD27
19 PCI_AD26
19 PCI_AD25
19 PCI_AD24
19 PCI_AD23
1
1
2.2K_0402_5%
2.2K_0402_5%
2.2K_0402_5%
2.2K_0402_5%
2.2K_0402_5%
2.2K_0402_5%
R373
R374
R375
R376
R377
R378
2
2
@ @ @ @ @ @
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SB700 STRAPS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4111P 0.4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, March 07, 2008 Sheet 23 of 54
A B C D E
A B C D E
HDD Connector
+5VS JP9
GND 1
10U_0805_10V4Z
0.1U_0402_16V4Z
2 SATA_TXP0 SATA_TXP0 21
A+ SATA_TXN0
1 1 1 1 A- 3 SATA_TXN0 21
C593
C595
4 0.01U_0402_16V7K
1 GND SATA_RXN0 1
C594 C591
B- 5 2 1 C592 SATA_RXN0_C SATA_RXN0_C 21
6 SATA_RXP0 2 1 C596 SATA_RXP0_C SATA_RXP0_C 21
2 2 2 2 B+ 0.01U_0402_16V7K
GND 7
0.1U_0402_16V4Z 0.1U_0402_16V4Z
Near CONN side.
V33 8 +3VS_HDD1
Pleace near HD CONN (JP23) V33 9
V33 10
GND 11
+3VS +3VS_HDD1 12
@R1009 GND
GND 13
1 2 V5 14
10U_0805_10V4Z
0.1U_0402_16V4Z
0_0805_5% 15 +5VS
V5
1 1 1 1 V5 16
C1032
C1035
GND 17
@ C1033 @ C1034 18
Reserved
GND 19
@ 2 2 2 2 @
V12 20
0.1U_0402_16V4Z 0.1U_0402_16V4Z 21
V12
V12 22
Multi-Bay Connector-option
2 2
+5VS
Max 3A
10U_0805_10V4Z
0.1U_0402_16V4Z
1 1 1 1
C601
C604
C602 C603
2 2 2 2 +3VS_HDD2 +5VS CONN@ JP10
0.1U_0402_16V4Z 0.1U_0402_16V4Z 2 1
VCC5 GND SATA_TXP1
4 VCC5 TX+ 3 SATA_TXP1 21
6 5 SATA_TXN1 SATA_TXN1 21
VCC5 TX- 0.01U_0402_16V7K
Pleace near HD CONN (JP23) 8 VCC3 GND 7
10 9 SATA_RXN1 2 1 C605 SATA_RXN1_C SATA_RXN1_C 21
VCC3 RX- SATA_RXP1
12 VCC3 RX+ 11 2 1 C606 SATA_RXP1_C SATA_RXP1_C 21
+3VS +3VS_HDD2 14 13 0.01U_0402_16V7K
@R1010 GND GND
16 15
1 2
GND GND Near CONN side.
10U_0805_10V4Z
0.1U_0402_16V4Z
0_0805_5% 18 17
GND GND
1 1 1 1
C1036
C1039
TYCO_2023087-3
@ C1037 @ C1038
@ 2 2 2 2 @
0.1U_0402_16V4Z 0.1U_0402_16V4Z
CD-ROM Connector
JP11
+5VS
GND 1
Placea caps. near ODD CONN. 2 SATA_TXP3 SATA_TXP3 21
A+ SATA_TXN3
A- 3 SATA_TXN3 21
4 0.01U_0402_16V7K
GND SATA_RXN3
B- 5 2 1 C612 SATA_RXN3_C SATA_RXN3_C 21
6 SATA_RXP3 2 1 C611 SATA_RXP3_C SATA_RXP3_C 21
B+ 0.01U_0402_16V7K
GND 7
0.1U_0402_16V4Z
1U_0603_10V4Z
10U_0805_10V4Z
R970 0_0402_5%
1 1 1 1
Near CONN side.
C613
DP 8 1 2
C614
C615
C616 9
10U_0805_10V4Z V5
V5 10 +5VS
2 2 2 2
MD 11
GND 12
GND 13
CONN@ SUYIN_127382FR013G509ZR
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HDD/CDROM
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4111P 0.4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, March 07, 2008 Sheet 24 of 54
A B C D E
A B C D E
1 2
+3VALW @ R1067 0_0805_5%
1 2 +3V_LAN
R1055 3.6K_0402_5% 40 mils
D
3 1 +3V_LAN
2
U17 2
LAN_DO R1056
G
4 5 2
2
LAN_DI DO GND C1078 C1077 Q144
3 DI NC 6 100K_0402_5%
LAN_SK_LAN_LINK# 2 7 0.1U_0402_16V4Z SI2301BDS-T1-E3_SOT23-3
LAN_CS SK NC 1
1 8 +3V_LAN
1
CS VCC 1
33 LAN_POWER_OFF 1 2
@ AT93C46-10SI-2.7_SO8 R1057 0_0402_5% 0.1U_0402_16V4Z
1 1
2
R1058
1
10K_0402_5%
03/06 Stuff Q144, R1056, R1057, C1077 and reserve R1067.
+LAN_VDD12
Close to Pin1,37,29
Place Close to Chip U20
Close to Pin10,13,30,36 +3V_LAN
RTL8102EL-GR_LQFP48_7X7 2 2
C1082
C1081
1U_0402_6.3V4Z 0.1U_0402_16V4Z
1 1
Y5
LAN_X1 2 1 LAN_X2
25MHz_20pF_6X25000017
1 1
C653 C654
27P_0402_50V8J
2 27P_0402_50V8J 2 02/22 Update JRJ45 connector PCB Footprint.
3 LAN Conn. 3
U19 JRJ45
+3V_LAN 13 Yellow LED+
LAN_MDI0+ 1 16 RJ45_MIDI0+ RJ45_MIDI0+ 35
LAN_MDI0- RD+ RX+ RJ45_MIDI0- LAN_ACTIVITY# R391
2 RD- RX- 15 RJ45_MIDI0- 35 2 1 300_0402_5% 14 Yellow LED-
C648 1 2 0.01U_0402_16V7K LAN_CT0 3 14 RJ45_CT0 75_0402_1% 1 16
CT CT C1083 1 SHLD1
4 NC NC 13 2 0.01U_0603_100V7-M RJ45_CT0_C 1 R394 2 8 PR4-
5 NC NC 12 C1084 1 2 0.01U_0603_100V7-M RJ45_CT1_C 1 2 RJ45_GND C656
DETECT PIN1 9
C647 1 2 0.01U_0402_16V7K LAN_CT1 6 11 RJ45_CT1 R396 @68P_0402_50V8K 7
LAN_MDI1+ CT CT RJ45_MIDI1+ 75_0402_1% 2 PR4+
7 TD+ TX+ 10 RJ45_MIDI1+ 35 1
LAN_MDI1- 8 9 RJ45_MIDI1- RJ45_MIDI1- 35 C658 RJ45_MIDI1- 6
TD- TX- PR2-
1000P_1206_2KV7K 5
NS681680 2 PR3-
4 PR3+
RJ45_MIDI1+ 3 PR2+
RJ45_MIDI0- 2 PR1-
DETCET PIN2 10
LAN_ACTIVITY# 2 RJ45_MIDI0+ 1
LAN_SK_LAN_LINK# PR1+
SHLD1 15
@C657 +3V_LAN 11
68P_0402_50V8K Green LED+
3
2
LAN_SK_LAN_LINK# 1 R395 2 1 300_0402_5% 12 Green LED-
FOX_JM36113-P1122-7F
CONN@ LANGND
@ D55 1 1
C661 C662
1
PACDN042Y3R_SOT23-3
4 0.1U_0402_16V4Z 4.7U_0805_10V4Z 4
2 2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
RTL8111C/8102E 10/100/1000 LAN
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4111P 0.4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, March 07, 2008 Sheet 25 of 54
A B C D E
A B C D E
Mini Card Slot 2---WLAN +3VALW Mini Card Slot 1---TV tuner / WWAN / Robson
+3VS Max 1A +3VS_WLAN +1.5VS Max 0.5A +1.5VS_WLAN +3VALW_WLAN +3VS_WLAN
@ R1043 0_0603_5%
2 R407 1 1 R406 2 1 2 +3VALW +3VS Max 2.7A +1.5VS Max 0.5A
0_0805_5% 0_0805_5% R1042 0_0603_5% +3VS_MINI PA@ +3VALW_WWAN PA@ +3VS_MINI PA@ +1.5VS_MINI
1 1 1 1 1 1 1 2 R971 0_0603_5% L78 L79
C665 C666 C668 C669 C670 C667 2 1 1 2 0.01U_0402_16V7K 4.7U_0805_10V4Z 2 1 4.7U_0805_10V4Z
@ R972 0_0603_5% 0_1206_5% 0_0805_5%
0.1U_0402_16V4Z 4.7U_0805_10V4Z 0.01U_0402_16V7K 4.7U_0805_10V4Z 0.1U_0402_16V4Z 2 1 PA@ 1 PA@ 1 PA@ 1 PA@ 1 PA@ 1 PA@ 1
2 2 2 2 2 2 C785 C786 C787 C781 C782 C783
1 1
PA@C671 @ C784
0.1U_0402_16V4Z 0.1U_0402_16V7K
0.1U_0402_16V4Z 2 2 2 2 2 2
1 JP14 2 2 1
MINI_PCIE_WAKE# 1 2 +3VS_WLAN 0.1U_0402_16V4Z 0.01U_0402_16V7K 0.1U_0402_16V4Z
CH_DATA 1 2
31 CH_DATA 3 3 4 4
31 CH_CLK CH_CLK 5 6 +1.5VS_WLAN JP13
5 6
15 CLKREQ_MCARD2# 7 7 8 8 20 MINI_PCIE_WAKE# 1 1 2 2 +3VS_MINI
9 9 10 10 3 3 4 4
15 CLK_PCIE_MCARD2# 11 11 12 12 5 5 6 6 +1.5VS_MINI
15 CLK_PCIE_MCARD2 13 14 15 CLKREQ_MCARD1# 7 8 UIM_PWR 1 1
13 14 7 8 UIM_DATA PA@
15 15 16 16 9 9 10 10
15 CLK_PCIE_MCARD1# 11 12 UIM_CLK C1093
11 12 UIM_RST PA@ 39P_0402_50V8J
15 CLK_PCIE_MCARD1 13 13 14 14
UIM_VPP C1092 2 2
17 17 18 18 15 15 16 16
19 20 WL_OFF# 39P_0402_50V8J
19 20 PLT_RST#
21 21 22 22
10 PCIE_PTX_C_IRX_N2 23 23 24 24 +3VALW_WLAN 17 17 18 18
10 PCIE_PTX_C_IRX_P2 25 26 19 20 WW_OFF#
25 26 Max 0.3A 19 20 PLT_RST# Max 0.3A
27 27 28 28 21 21 22 22
29 30 SMB_CK_CLK1 10 PCIE_PTX_C_IRX_N5 23 24 +3VALW_WWAN
29 30 SMB_CK_DAT1 23 24
10 PCIE_ITX_C_PRX_N2 31 31 32 32 10 PCIE_PTX_C_IRX_P5 25 25 26 26
10 PCIE_ITX_C_PRX_P2 33 33 34 34 27 27 28 28
35 36 29 30 SMB_CK_CLK1 1
35 36 USB20_N8 20 29 30
37 38 10 PCIE_ITX_C_PRX_N5 31 32 SMB_CK_DAT1 PA@ C1094
37 38 USB20_P8 20 31 32
39 40 10 PCIE_ITX_C_PRX_P5 33 34 39P_0402_50V8J
R47 39 40 33 34
+3VS_WLAN 1 2 0_0603_5% 41 41 42 42 35 35 36 36 USB20_N10 20
WL_LED# 2
43 43 44 44 WL_LED# 34 37 37 38 38 USB20_P10 20
45 46 PA@ 39 40
45 46 R401 1 39 40
47 47 48 48 +3VS_MINI 2 0_0603_5% 41 41 42 42 WW_LED# WW_LED# 34
49 49 50 50 1 43 43 44 44
21 BT_COMBO_EN# 1 R49 2 CH_CLK 51 51 52 52 WL_OFF# 2 1 WLOFF# 21 45 45 46 46
D59 PA@ C738 47 48
0_0402_5% CH751H-40PT_SOD323-2 39P_0402_50V8J 47 48
G1
G2
G3
G3
49 49 50 50
1
2
51 51 52 52
2 R48 CONN@ 2
03/06 Add D59.
53
54
55
56
FOX_AS0B226-S99N-7F
G1
G2
G3
G3
1 1
4.7K_0402_5% PA@
9/20 SP01000HS00/SP01000LX00 CONN@ PA@ C1095 C1096
2
53
54
55
56
FOX_AS0B226-S99N-7F 39P_0402_50V8J 39P_0402_50V8J
9/20 STANDOFF (H=7.5 mm) ES000000D00 2 2
9/20 SP01000HS00/SP01000LX00
WW_OFF# 2 1 WWOFF# 21
New Card
D60 9/20 STANDOFF (H=7.5 mm) ES000000D00
CH751H-40PT_SOD323-2
S
17 15 1 3
D
+3VALW AUX_IN AUX_OUT +3V_PEC
RP@
11,14,19,25,27,32,33 PLT_RST# PLT_RST# 1 R54 2 6 19
0_0402_5% SYSRST# OC#
G
2
33,34,36,40 SYSON 20 8 PERST#
SHDN# PERST#
33 WWAN_POWER_OFF
28,33,36,38,41 SUSP# 1 STBY# NC 16
10 7
03/06 Add power on/off control circuit.
CPPE# GND
3 EXP_CPPE# 3
20 EXP_CPPE# 9 CPUSB#
THERMAL_PAD 21
18 +3VS_MINI
RCLKEN
R5538D001-TR-F_QFN20_4X4~D JP6
1 1
UIM_PWR 2
USE TI TPS2231MRGPR UIM_DATA 3
2
3
UIM_CLK 4
Near to Express Card slot. 9/20 SP02000B000 +3VS_PEC UIM_RST 5
4
5
9/20 SP02000IQ00
UIM_VPP 6 8
JEXP 4.7U_0805_10V4Z 6 G1
7 7 G2 9
1 1 1 ACES_88266-07001
GND RP@ RP@
20 USB20_N11 2 USB_D- CONN@
20 USB20_P11 3 C677 C678
EXP_CPPE# USB_D+
4 CPUSB# 2 2
5 RSV
6 0.1U_0402_16V4Z
SMB_CK_CLK1 RSV
20 SMB_CK_CLK1 7 SMB_CLK R1037
20 SMB_CK_DAT1 SMB_CK_DAT1 8 SMB_DATA +1.5VS_PEC UIM_DATA UIM_PWR 0.1U_0402_16V4Z
+1.5VS_PEC 9 +1.5V 1 2
10 +1.5V
MINI_PCIE_WAKE# 11 4.7U_0805_10V4Z @ 10K_0402_5% 1 PA@ 1 PA@
WAKE# C1070 C1071
+3V_PEC 12 +3.3VAUX 1 1
PERST# 13 RP@ RP@
PERST# C683 C682 4.7U_0805_10V4Z
+3VS_PEC 14 +3.3V 2 2
15 +3.3V
CLKREQ_NCARD# 2 2
15 CLKREQ_NCARD# 16 CLKREQ#
EXP_CPPE# 17 CPPE# 0.1U_0402_16V4Z
15 CLK_PCIE_NCARD# 18 REFCLK-
15 CLK_PCIE_NCARD 19 REFCLK+
4 4
20 GND
10 PCIE_PTX_C_IRX_N0 21 PERn0
10 PCIE_PTX_C_IRX_P0 22 PERp0
23 +3V_PEC
GND
10 PCIE_ITX_C_PRX_N0 24 PETn0
10 PCIE_ITX_C_PRX_P0 25 4.7U_0805_10V4Z
PETp0
26 GND
1 1
27 GND
RP@
C684
RP@
C685
Security Classification Compal Secret Data Compal Electronics, Inc.
28 GND Issued Date 2007/08/02 Deciphered Date 2008/08/02 Title
CONN@ SANTA_130801-5_LT 2 2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
WLAN/TV tuner/Express Card
0.1U_0402_16V4Z AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4111P 0.4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, March 07, 2008 Sheet 26 of 54
A B C D E
A B C D E
JREAD
3 21 R45 10K_0402_5% +3VS_CR
+VCC_4IN1 XD-VCC SD-VCC +VCC_4IN1
+3VS U22 XDWP#_SDWP# 2
40mil XD_SD_MS_D0 32
MS-VCC 28 1
R121 4.7K_0402_5%
XD_SD_MS_D1 XD-D0 SDCLK XD_RB# XDCD0#_SDCD# 2
3 IN OUT 1 10 XD-D1 7 IN 1 CONN SD_CLK 20 2 1 1
4 5 XD_SD_MS_D2 9 14 XD_SD_MS_D0 R106 10K_0402_5%
EN OUT XD_SD_MS_D3 XD-D2 SD-DAT0 XD_SD_MS_D1 R111 4.7K_0402_5%
1 8 XD-D3 SD-DAT1 12
1
C895 2 1 XD_SD_D4 7 30 XD_SD_MS_D2 XDCD1#_MSCD# 2 1
GND XD_SD_D5 XD-D4 SD-DAT2 XD_SD_MS_D3
6 XD-D5 SD-DAT3 29
@ 0.1U_0402_16V4Z @ G5250C2T1U_SOT23-5 XD_SD_D6 5 27 XD_SD_D4
2 @ C896 XD_SD_D7 XD-D6 SD-DAT4 XD_SD_D5 D40
4 XD-D7 SD-DAT5 23
1 2 XD_SD_D6 1
18 2
2
1U_0603_10V4Z @ R123 SDCMD_MSBS_XDWE# 34 SD-DAT6 XD_SD_D7 XD_CD#
XD-WE SD-DAT7 16 1
XDWP#_SDWP# 33 25 SDCMD_MSBS_XDWE# 3 1
XD_ALE XD-WP SD-CMD XDCD0#_SDCD#
35 XD-ALE SD-CD-SW 1
150K_0402_5% XD_CD# 40 DAN202U_SC70 C696
XD_RB# XD-CD XDWP#_SDWP# 270P_0402_50V7K
reserved power circuit 39 XD-R/B SD-WP-SW 2
2
XD_RE# 38
XDCE# XD-RE
37 XD-CE
XD_CLE 36 26 MSCLK
XD-CLE MS-SCLK XD_SD_MS_D0
MS-DATA0 17
11 15 XD_SD_MS_D1
Use 0805 type and over 20 mils 31
7IN1 GND MS-DATA1
19 XD_SD_MS_D2
7IN1 GND MS-DATA2 XD_SD_MS_D3
trace width on both side MS-DATA3 24
XDCD1#_MSCD#
Strap pin for JMicro
MS-INS 22
13 SDCMD_MSBS_XDWE# +3VS_CR
+VCC_OUT +VCC_4IN1 MS-BS
41 7IN1 GND
42 2 1 XD_CLE
7IN1 GND 10K_0402_5% R405
1 R383 2 CONN@ TAITW_R015-B10-LM 2 1 XD_ALE
0_0805_5% 10K_0402_5% @ R122
1 1
02/15 Reserve R122 and add pull low resistor R1069. 2 1
SDCLK MSCLK XDCE# 10K_0402_5% R1069
C689 C694
2
10U_0805_10V4Z 0.1U_0402_16V4Z
2 2
@ R413 @ R412 @ R411
100_0402_5% 100_0402_5% 100_0402_5%
2 1 XD_RE#
1
2 2 2 place near pin 5 and 200K_0402_5% R86
pin 10. +1.8VS
@ C902 @ C901 @ C900
100P_0402_25V8K 100P_0402_25V8K 100P_0402_25V8K +1.8VS_OUT
2 1 1 1 2
+3VS 20mil 0.1U_0402_16V4Z 1000P_0402_50V7K 2 R1020 1
1 1 1 1 0_0603_5%
2 1
Q54 0.1U_0402_16V4Z C695
1 3 CPPE#
20 CR_CPPE# Power Circuit +3VS_CR +3VS
D
MDIO11 XD_RE#
MDIO12 25
CPPE# 13 23 XD_RB#
SEEDAT MDIO13
2
D @ Q53
GND 31
2 CR_LED# 21 32
G CR1_LEDN GND
S 2N7002_SOT23-3
8mA sink current GND 33
3
@ R454 JMB385-LGEZ0A_LQFP48_7X7
4.7K_0402_5%
White LED: VF=3V, IF = 10mA, Res = 200 ohm
2
4 4
02/15 Reserve Q53 and R454.
Add R1070 to change LED active status.
Change net name from CR_LED to CR_LED#.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCI-E I/F Card Reader-JM385
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4111P 0.4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, March 07, 2008 Sheet 27 of 54
A B C D E
A B C D E
CODEC POWER
+3VDD_CODEC +3VS_HDA +3VS +VDDA_CODEC_R +VDDA_CODEC
R885 R978 R979 +5VALW +VDDA_CODEC
W=40Mil U32 (4.75V(4.56~4.94V))
+3VS 1 2 0.1U_0402_16V4Z 1 2 1 2
BLM18BD601SN1D_0603 BLM18BD601SN1D_0603 0_0603_5%
1 1 1 1 1
1
C728
2
0.1U_0402_16V4Z
1 IN
5
300mA
C734 C733 C1046 C730 C731 OUT
2 GND 1
C729
0.1U_0402_16V4Z 1U_0603_10V4Z 26,33,36,38,41 SUSP# 3 4
2 2 2 2 2 SHDN BYP 2.2U_0805_16V4Z
G9191-475T1U_SOT23-5 1 2
1U_0603_10V4Z 0.1U_0402_16V4Z C732
1 1
0.1U_0402_16V4Z
2
U27
VOL_DN/DMIC_1/GPIO 2 4
+VDDA_CODEC_R 25 AVDD1*
GPIO 3 30
38 AVDD2**
HDA_BITCLK_CODEC 31
VREFOUT-E / GPIO 4
1
1
C979 37 24 MIC_INR
NC PORTC_R @ R911
0.1U_0402_16V4Z 18 23 MIC_INL 0_0603_5% Internal MIC
2 NC PORTC_L
19 C984 0.022U_0603_25V7K
2
NC LINE_OUT_R
PORTD_R 36 LINE_OUT_R 29 1 2 MIC_IN_L 29
20 NC
35 LINE_OUT_L LINE_OUT_L 29 Internal SPKR.
PORTD_L
10U_0805_10V4Z
C744 1 2 VC_REFA 27 15 DOCK_MICR 1 2 DOCK_MIC_R 35
VREFFILT PORTE_R C985 1U_0603_10V6K
DOCK_MICL
DOCK MIC
26 AVSS1* PORTE_L 14 1 2 DOCK_MIC_L 35
C986 1U_0603_10V6K
3 3
42 AVSS2**
PORTF_R 17
7 DVSS**
PORTF_L 16
92HD71B7X5NLGXA1X8_QFN48_7X7
@ C746
1 2
0.1U_0402_16V4Z
@ C747
1 2
0.1U_0402_16V4Z
@ C748
SENSE A SENSE B 1 2
0.1U_0402_16V4Z
C 10K G 10K R198 Security Classification Compal Secret Data Compal Electronics, Inc.
1 2 GNDA 29,35 Issued Date 2007/08/02 Deciphered Date 2008/08/02 Title
0_1206_5%
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Audio Codec-IDT9271B7
D 5.11K H 5.11K AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
GND GNDA DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4111P 0.4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, March 07, 2008 Sheet 28 of 54
A B C D E
A B C D E
+5VAMP +5VS
R594 SPEAKER
0.1U_0402_16V4Z 1 2
0_1206_5% JP20
1 1 1
GAIN0 GAIN1 Av(inv) SPKR- 1
C766 C767 C1051 SPKR+ 1
2 2
10U_0805_10V4Z SPKL- 3
SPKL+ 3
2 2 2
0 0 6dB 4 4
+5VS 5
1 1 1 1 GND1
0.1U_0402_16V4Z 0 1 10dB 6
C760 C761 C762 C763 GND2
15.6dB
CONN@ E&T_3806-F04N-02R
1 2 2 2 2 1
1 0 15.6dB
100P_0402_50V8J
16
15
6
1
U28 100P_0402_50V8J
1 1 21.6dB 100P_0402_50V8J 100P_0402_50V8J
VDD
PVDD1
PVDD2
R1000 R1001
@ 100K_0402_5% 100K_0402_5%
2
C1049 1 2 0.022U_0603_25V7K 7 2
RIN+ GAIN0
1 2
C1052 47P_0402_50V8J 3
R1002 GAIN1
1
2 1 C1050 1 2 0.022U_0603_25V7K 17
28 LINE_OUT_R RIN- SPKR+
1 2 ROUT+ 18
0_0402_5% C1053 47P_0402_50V8J R1003 R1004
@ 100K_0402_5%
14 SPKR-
2
C1040 ROUT-
1 2 0.022U_0603_25V7K 9 LIN+
1 2 100K_0402_5%
C1054 47P_0402_50V8J 4 SPKL+
R1005 LOUT+ +VDDA_CODEC
2 1 C1041 1 2 0.022U_0603_25V7K 5 R906 C743
28 LINE_OUT_L LIN- SPKL- 0_0402_5% 1U_0603_10V4Z
1 2 LOUT- 8
0_0402_5% C1055 47P_0402_50V8J 2 1 1 2
+VDDA_CODEC INTMIC IN
1
1
1
R904 R905 R951
12 4.7K_0402_5% 4.7K_0402_5% 100K_0402_5%
NC
2
THERMAL PAD
10 JP42
2
EC_MUTE# BYPASS
33 EC_MUTE# 19 SHUTDOWN 1 1
1 Keep 10 mil width 28 MIC_IN_L 2 2
28 MIC_IN_R 3 3
GND1
GND2
GND3
GND4
2 C1044 2
4 4
1U_0805_50V4Z 2 1
2 +3VS
R955 10K_0402_5% 5 GND1
33 ANA_MIC_DET 6
20
13
11
1
21
GND2
1
TPA6017A2_TSSOP20 D ACES_88231-04001
Q151 2 CONN@
28 INTMIC_DET# G
1
D 2N7002_SOT23-3 S
3
Q160 2
G
2N7002_SOT23-3 S 9/20 SP02000H700/SP02000H900
3
R909 Close to CODEC U27
28 VREFOUT_B 2 1 C742 1 2
0_0402_5%
1U_0603_10V4Z
1
R907 R908
4.7K_0402_5% 4.7K_0402_5%
Audio/B & CIR
2
28 MIC_EXT_R MIC_EXT_R
JP43
28 MIC_EXT_L MIC_EXT_L EXTMIC IN MIC_EXT_R 1 1
MIC_EXT_L 2 2
3 3
HP_OUT_R 4
HP_OUT_L 4
5 5
3 Close to CODEC U27 3
6 6
EXTMIC_DET# 7
B+ 28 EXTMIC_DET# 7
28,35 JACK_DET# HP_DET# 8 8
9 9
10 10
CIR_IN 11
33,35 CIR_IN 11
1
+3VALW +3VALW 12
+5VL 12
1
D R975 13 13
2 330K_0402_5% 14 14
2
G
R973 R974 S Q161 CONN@ ACES_87213-1400G
3
6 1
9/20 SP02000H800
2N7002DW-7-F_SOT363-6
5
Q145B
HP_DET# 2N7002DW-7-F_SOT363-6
2
4
Q145A
1
Q147A
R968
2N7002DW-7-F_SOT363-6 C775 150U_Y_6.3VM
DOCK_LOUT_R 2 DOCK_LOUT_CR_R DOCK_LOUT_C_R
+
28 HP_OUTR 6 1 1 1 2 DOCK_LOUT_C_R 35
47_0603_1%
5
Q147B
2N7002DW-7-F_SOT363-6 C776 150U_Y_6.3VM
R969 HP OUT For Docking
DOCK_LOUT_L 2 DOCK_LOUT_CR_L DOCK_LOUT_C_L
+
28 HP_OUTL 3 4 1 1 2 DOCK_LOUT_C_L 35
47_0603_1%
C773 150U_Y_6.3VM
HP_OUT_R
+
1 2
4 C774 150U_Y_6.3VM 4
HP_OUT_L HP OUT For M/B
+
1 2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AMP & Audio Jack
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4111P 0.4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, March 07, 2008 Sheet 29 of 54
A B C D E
A B C D E
1 1
ACCELEROMETER
CH751H-40PT_SOD323-2
1 1 RP@
RP@ C1030 C1031
10U_0805_6.3V6M
2 2
2 0.1U_0402_16V4Z 2
SMB_CK_CLK0
SMB_CK_CLK0 8,9,15,20
RP@
14
U63
VDDIO absolute man
0011101b
SCL / SPC
rating is VDD+0.1
+3VS_ACL_IO 1 13 SMB_CK_DAT0
Vdd_IO SDA / SDI / SDO SMB_CK_DAT0 8,9,15,20
RP@
R997 2 12 RP@ R998
0_0402_5% GND SDO 0_0402_5%
1 2 3 Reserved Reserved 11 1 2
4 GND GND 10
3 3
CS
LIS302DLTR_LGA14_3x5
7
RP@
2 1
R999 10K_0402_5%
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Accelerometer
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4111P 0.4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, March 07, 2008 Sheet 30 of 54
A B C D E
A B C D E
Left side USB CONNECTOR Right side USB 0&1 Board Conn
Max 0.5A JP47
Max 2.5A D11 +USB_VCCA
+5VALW 1 1
+5VALW +USB_VCCA 4 2 USB20_P2_R L51 JESAT 2
+USB_VCCA VIN IO1 2
4 4 3 1 USB 3
20 USB20_N2 3 VBUS 3
U40 USB20_N2_R 3 1 USB20_N2_R 2 USB_EN# 4
1 IO2 GND D- 33 USB_EN# 4 1
1 8 W=100mils USB20_P2_R 3 5
GND OUT @ PRTR5V0U2X_SOT143-4 D+ 20 USB20_N0 5
2 IN OUT 7 20 USB20_P2 1 1 2 2 4 GND 20 USB20_P0 6 6
1000P_0402_50V7K
150U_D_6.3VM
0.1U_0402_16V4Z
0.1U_0402_16V4Z
3 IN OUT 6 1 D12 7 7
1 4 5 1 1 1 WCM-2012-900T_4P 5 8
EN# OC# GND 20 USB20_N1 8
C789
+
C790
C791
C1121
C788 +USB_VCCA 4 2 SATA_TXP2 21 SATA_TXP2 SATA_TXP2 6 9
TPS2061IDGN_MSOP8~N VIN IO1 SATA_TXN2 A+ ESATA 20 USB20_P1 9
21 SATA_TXN2 7 A- 10 10
4.7U_0805_10V4Z SATA_TXN2 3 1 8
2 2 2 2 2 IO2 GND GND +5VALW
21 SATA_RXN2_C C792 1 2 1000P_0402_50V7KSATA_RXN2 9 B-
@ PRTR5V0U2X_SOT143-4 21 SATA_RXP2_C C793 1 2 1000P_0402_50V7KSATA_RXP2 10 B+
11 GND 1 11 GND1
12 GND2
USB_EN# C1109
03/03 Add C1121. 12
13
GND 820P_0402_25V7K ACES_87213-1000G
GND 2
03/06 Change C792 and C793 from 0.01uF to 1000pF. 14 9/20 SP02000DX00
GND
15 GND CONN@
CONN@ TYCO_1759576-1
02/25 Add C1109.
2 2
+3VS_FB USB20_N6
D
3 1 1 2 5 5 USB20_N6 20
1 0_0603_5% 4
4 BT_LED 34
C832 3 @ R517 1 2 1K_0402_5%
0.1U_0402_16V4Z 3 @ R518 1 1K_0402_5% CH_DATA 26
G
2 2 CH_CLK 26
2
USB_EN# 2
1 1
2 JP39
D16
1 ACES 87213-0800G
USB20_N7 1 USB20_P6
20 USB20_N7 2 2 +3VAUX_BT 4 VIN IO1 2
USB20_P7 3
20 USB20_P7 3
4 9/20 SP02000HC00/SP02000HB00 USB20_N6 3 1
4 IO2 GND
5 5
6 @ PRTR5V0U2X_SOT143-4
D21 6
7 GND
+3VS_FB 4 2 USB20_P7 8 +3VS +3VAUX_BT
VIN IO1 GND Q24 SI2301BDS-T1-E3_SOT23-3
USB20_N7 3 1 ACES_85201-06051
IO2 GND 0.1U_0402_16V4Z
S
CONN@
D
3 1
@ PRTR5V0U2X_SOT143-4 9/20 SP01000B000
02/15 Change from +3VALW to +3VS
G
1 1 1 1
2
3 C798 R519 C799 C800 C801 3
1U_0603_10V4Z 100K_0402_5%
2 2 2 2
2
0.01U_0402_16V7K 4.7U_0805_10V4Z
R520
21 BT_OFF 1 2 1 2
10K_0402_5% C802 0.1U_0402_16V4Z
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
USB, BT, eSATA,FPR
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4111P 0.4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, March 07, 2008 Sheet 31 of 54
A B C D E
A B C D E
+3VL
1
R996 0_0402_5% 1
1 C803 SPI_CS# INT_SPI_CS# 1
33 SPI_CS# 1 2 1 S
R521 R221 0_0402_5%
0.1U_0402_16V4Z 100K_0402_5% 1 2 SPI_CLK_R 6
2 33 SPI_CLK C
U31 R227 0_0402_5%
2
8 VCC A0 1 33 EC_SO_SPI_SI 2 1 EC_SO_SPI_SI_R 5 D Q 2 EC_SI_SPI_SO_R 2 1 EC_SI_SPI_SO 33
7 2 R229 0_0402_5% R223 0_0402_5%
WP A1 MX25L8005M2C-15G_SOP 8P
6,33,34,37 SMB_EC_CK1 6 SCL A2 3
6,33,34,37 SMB_EC_DA1 5 SDA GND 4
L Need add back R221 if no ext BIOS design U30 install.
@ AT24C16AN-10SI-2.7_SO8
1
R526
100K_0402_5%
2
2 2
+3VS
1
C1118
3 +3VS 3
JP41
H31 1
+3VALW 1
2 2 02/26 Add 1118.
3 3
6 5 LPC_DRQ# 4
LPC_DRQ# 19 4
5 CLK_14M_SIO
5 CLK_14M_SIO
6 6 CLK_14M_SIO 15
SIRQ 7 4 PLT_RST# 7 LPC_AD0
19,33 SIRQ PLT_RST# 11,14,19,25,26,27,33 7
1
8 LPC_AD1
8 LPC_AD2 @ R310
9 9
LPC_AD3 8 3 LPC_AD2 10 LPC_AD3 100_0402_5%
19,33 LPC_AD3 LPC_AD2 19,33 10
11 LPC_FRAME#
11 LPC_DRQ#
12
2
LPC_AD1 LPC_AD0 12 PLT_RST#
19,33 LPC_AD1 9 2 LPC_AD0 19,33 13 13 1
14 R137 1 2 @ 0_0402_5%
14 CLK_PCI_SIO2 @ C502
15 15 CLK_PCI_SIO2 19
LPC_FRAME# 10 1 CLK_PCI_SIO 16 SIRQ 100P_0402_25V8K
19,33 LPC_FRAME# CLK_PCI_SIO 19 16 2
17 17
18 18
2
19 19
@ DEBUG_PAD @ R232 20
22_0402_5% 20
9/20 ??????
@ ACES_85201-2005
1
2 9/20 DC233105000
@ C486
22P_0402_50V8J
1
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
BIOS ROM/Debug Tool
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4111P 0.4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, March 07, 2008 Sheet 32 of 54
A B C D E
A B C D E
111
125
1 KSI0 KSI0 @ C824 100P_0402_25V8K 1
22
33
96
67
13 13 1 2
9
U33 KSO1 14 KSO1 @ C825 1 2 100P_0402_25V8K
KSO5 14 KSO5 @ C826 100P_0402_25V8K
15 1 2
VCC
VCC
VCC
VCC
VCC
VCC
AVCC
KSI3 15 KSI3 @ C875 100P_0402_25V8K
02/22 Add R1078. KSI2
16
17
16 KSI2 @ C876
1
1
2
2 100P_0402_25V8K
R1078 0_0402_5% KSO0 17 KSO0 @ C877 100P_0402_25V8K
18 18 1 2
GATEA20 1 21 EC_PWM 1 2 KSI5 19 KSI5 @ C878 1 2 100P_0402_25V8K
20 GATEA20 GA20/GPIO00 INVT_PWM/PWM1/GPIO0F INV_PWM 11,17 19
KB_RST# 2 23 FAN_PWM KSI4 20 KSI4 @ C884 1 2 100P_0402_25V8K
20 KB_RST# KBRST#/GPIO01 BEEP#/PWM2/GPIO10 FAN_PWM 4 20
SIRQ 3 26 EC_BEEP KSO9 21 KSO9 @ C885 1 2 100P_0402_25V8K
19,32 SIRQ SERIRQ# FANPWM1/GPIO12 EC_BEEP 28 21
LPC_LFRAME# 4 27 ACOFF KSI6 22 KSI6 @ C886 1 2 100P_0402_25V8K
19,32 LPC_FRAME# LFRAME# ACOFF/FANPWM2/GPIO13 ACOFF 38 22
C810 R530 19,32 LPC_AD3 LPC_AD3 5 0.01U_0402_16V7K KSI7 23 KSI7 @ C887 1 2 100P_0402_25V8K
LPC_AD2 LAD3 C812 ECAGND KSI1 23 KSI1 @ C888 100P_0402_25V8K
1 2 1 2 19,32 LPC_AD2 7 LAD2 PWM Output 1 2 24 24 1 2
@ 33_0402_5% 19,32 LPC_AD1 LPC_AD1 8 63 BATT_TEMP BATT_TEMP 37
@ 15P_0402_50V8J LPC_AD0 LAD1 BATT_TEMP/AD0/GPIO38 BATT_OVP
19,32 LPC_AD0 10 LAD0 LPC & MISC BATT_OVP/AD1/GPIO39 64 BATT_OVP 37
ADP_I/AD2/GPIO3A 65 ADP_I 38
CLK_PCI_EC 12 AD Input 66 ADP_ID 37 25
19,23 CLK_PCI_EC PCICLK AD3/GPIO3B GND1
PLT_RST# 13 75 TP_BTN# TP_BTN# 34 26
11,14,19,25,26,27,32 PLT_RST# PCIRST#/GPIO05 AD4/GPIO42 GND2
+3VL_EC R533 1 2 ECRST# 37 76 ANA_MIC_DET 29
47K_0402_5% EC_SCI# ECRST# SELIO2#/AD5/GPIO43 ACES_85201-24051
20 EC_SCI# 20 SCI#/GPIO0E
20,23 HDARST# 38 CLKRUN#/GPIO1D CONN@
DAC_BRIG/DA0/GPIO3C 68 DAC_BRIG 17
C811 2 1 70 VCTRL 38 9/20 SP01000FF00/SP01000G300
0.1U_0402_16V4Z EN_DFAN1/DA1/GPIO3D IREF +5VS_LED
DA Output IREF/DA2/GPIO3E 71 IREF 38
KSI0 55 72
KSI1 56
KSI0/GPIO30 DA3/GPIO3F AC_SET 38 KB Back Light Conn
KSI1/GPIO31
1
KSI2 57
KSI3 KSI2/GPIO32 R516
02/22 Add R1076, C1104 and R1077 for EMI request. KSI4
58
59
KSI3/GPIO33 PSCLK1/GPIO4A 83
84
EC_MUTE# 29
KSI4/GPIO34 PSDAT1/GPIO4B USB_EN# 31
KSI5 60 85 I2C_INT 34 150_0603_1%
+3VALW KSI6 KSI5/GPIO35 PSCLK2/GPIO4C JP48
61 PS2 Interface 86 MUTE_LED 35
2
R1076 KSI7 KSI6/GPIO36 PSDAT2/GPIO4D TP_CLK
62 KSI7/GPIO37 TP_CLK/PSCLK3/GPIO4E 87 TP_CLK 34 1 1
100_0402_1% KSO0 39 88 TP_DATA TP_DATA 34 2
KSO0/GPIO20 TP_DATA/PSDAT3/GPIO4F 2
1
2 ESB_CLK 2
34 ESB_CLK 1 2 EC_CLK KSO1 40 KSO1/GPIO21 5 G1 3 3
R538 34 ESB_DAT ESB_DAT 1 2 EC_DAT KSO2 41 6 4
10K_0402_5% KSO3 KSO2/GPIO22 G2 4
42 KSO3/GPIO23 SDICS#/GPXOA00 97 AC_LED# 37
1 100_0402_1% KSO4 43 98 DOCK_VOL_UP# 35 ACES_85201-04051
R1077 KSO5 KSO4/GPIO24 SDICLK/GPXOA01
44 KSO5/GPIO25 Int. K/B 99 DOCK_VOL_DWN# 35 CONN@
2
R528
4.7K_0402_5% L KSO12 51
KSO11/GPIO2B
KSO12/GPIO2C
SPICLK/GPIO58
SPICS# 128
SPI_CLK 32
SPI_CS# 32
+5VL 10K_0402_5%
2 1 SMB_EC_DA1 KSO13 52 KSO13/GPIO2D
DOCK_VOL_UP# 2 1
4.7K_0402_5% KSO14 53 R46 1 2 10K_0402_5%
+3VS R529 KSO14/GPIO2E
2 1 SMB_EC_CK1 KSO15 54 KSO15/GPIO2F CIR_RX/GPIO40 73 CIR_IN
CIR_IN 29,35
DOCK_VOL_DWN# 2 1
4.7K_0402_5% KSO16 81 74 RP@ R590
R531 KSO16/GPIO48 CIR_RLC_TX/GPIO41
2 1 SMB_EC_DA2 KSO17 82 KSO17/GPIO49 FSTCHG/SELIO#/GPIO50 89 FSTCHG
FSTCHG 38
10K_0402_5%
4.7K_0402_5%
R532 2 1 SMB_EC_CK2
BATT_CHGI_LED#/GPIO52 90
91
STD_ADP 38 02/15 Change R1040 from 100K to 10K ohm
CAPS_LED#/GPIO53 CAPS_LED# 34
10K_0402_5% 6,32,34,37 SMB_EC_CK1 SMB_EC_CK1 77 SCL1/GPIO44 GPIO BATT_LOW_LED#/GPIO54 92 BAT_LED#
BAT_LED# 34 and connect to +3VL_EC
R513 1 2 WL_BLUE_BTN 6,32,34,37 SMB_EC_DA1 SMB_EC_DA1 78 SDA1/GPIO45 SUSP_LED#/GPIO55 93 ON/OFFBTN_LED#
ON/OFFBTN_LED# 34 2 1
6 SMB_EC_CK2 SMB_EC_CK2 79 SM Bus 95 SYSON R541 10K_0402_5%
SMB_EC_DA2 SCL2/GPIO46 SYSON/GPIO56 VR_ON SYSON 26,34,36,40 R534 +5V_TP
6 SMB_EC_DA2 80 SDA2/GPIO47 VR_ON/XCLK32K/GPIO57 121 VR_ON 43
127 AC_IN_EC 2 1 10K_0402_5%
02/18 Chagne R514 and R515 to 4.7K ohm. AC_IN/GPIO59 D54
AC_IN 21,38
TP_CLK 1 2
CH751H-40PT_SOD323-2 R535
20 SLP_S3# SLP_S3# 6 100 EC_RSMRST# 2 1 +3VL_EC 10K_0402_5%
+3VL SLP_S5# PM_SLP_S3#/GPIO04 EC_RSMRST#/GPXO03 EC_RSMRST# 20 R1040 TP_DATA
20 SLP_S5# 14 PM_SLP_S5#/GPIO07 EC_LID_OUT#/GPXO04 101 EC_LID_OUT# 20 1 2
R514 4.7K_0402_5% 20 EC_SMI# EC_SMI# 15 102 10K_0402_5%
EC_SMI#/GPIO08 EC_ON/GPXO05 EC_ON 36,39
1 2 EC_CLK 34 LID_SW# LID_SW# 16 LID_SW#/GPIO0A EC_SWI#/GPXO06 103 WL_BLUE_LED# 34 1 2
+3VL_EC EC_CLK 17 104 SB_PWRGD C1073
SUSP#/GPIO0B ICH_PWROK/GPXO06 SB_PWRGD 6,20,43
2 1 EC_DAT EC_DAT 18 PBTN_OUT#/GPIO0C GPO BKOFF#/GPXO08 105 BKOFF#
BKOFF# 17
100P_0402_50V8J
3 R515 4.7K_0402_5% WL_BLUE_BTN 3
34 WL_BLUE_BTN 19 EC_PME#/GPIO0D GPIO WL_OFF#/GPXO09 106 WWAN_POWER_OFF 26
2
1
2 1 E51_RXD 31 110 VFIX_EN 43
1
2
C813 GPXID5 PWRBTN_OUT# SUSP# 26,28,36,38,41
GPXID6 117 PWRBTN_OUT# 20
15P_0402_50V8J 118 NMI_DBG# 1 2
GPXID7 PCI_SERR# 19
1 2 CRY2 122 XCLK1 0_0402_5%
123 XCLK0 V18R 124 2 1
C814 4.7U_0805_10V4Z
1
AGND
Y7
GND
GND
GND
GND
GND
3 4 @
NC OUT R545 Need 4.7uf for 926 C version +3VS
2 1 20M_0402_5% KB926QFC0_LQFP128_14X14 R1050
11
24
35
94
113
69
NC IN TP_BTN# 1 2
2
32.768KHZ_12.5PF_Q13MC30610003 10K_0402_5%
1 2 CRY1
+3VL_EC
C815
ECAGND
15P_0402_50V8J
1
+EC_AVCC L80
03/06 Stuff R544. 0_0603_5%
R544
L81
2
LAN_POWER_OFF 1 2 E51_RXD 1 2 1 2
4 25 LAN_POWER_OFF 4
C816 0.1U_0402_16V4Z 0_0603_5%
EC DEBUG port 0_0402_5%
E51_TXD
Security Classification Compal Secret Data Compal Electronics, Inc.
1 2 Issued Date 2007/08/02 Deciphered Date 2008/08/02 Title
0_0603_5%
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
EC KB926/KB conn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4111P 0.4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, March 07, 2008 Sheet 33 of 54
A B C D E
A B C D E
2
1
1
+5VALW_LED
@ C819 @ D31
JP1 R1038 0.1U_0402_16V4Z PSOT24C_SOT23-3
SW1 @ 10K_0402_5% 2
1
1
ON/OFF# 1 SMT1-05-A_4P JP37
33 ON/OFF# 2 02/22 Reserve for EMI request.
2
ON/OFFBTN_LED# 3 2 TP_BTN#
33 ON/OFFBTN_LED# 3 G1 5 3 1 TP_BTN# 33 1 1
4 6 2 TP_CLK TP_CLK 33
4 G2 2 TP_DATA
1 02/15 Remove SW2. ACES_85201-04051
4 2 5
6
G1 3 3
4
TP_DATA 33
@ R1074 @ C1102 1
CONN@ G2 4 ESB_CLK1 2 1 2 1
5
6
ACES_85201-04051
CONN@ 1 1 33_0402_5% 15P_0402_50V8J
9/20
SP01000KC00/SP01E000900
9/20 SP01000J100 @ C820 @ C821 @ R1075 @ C1103
MDC 1.5 Conn. 9/20 STANDOFF (H= 5.0 mm) ES000000800 Max 0.5A 100P_0402_50V8J 2 2 100P_0402_50V8J ESB_DAT1 2 1 2 1
+5VALW @ R235 0_0603_5% +5V_TP 33_0402_5% 15P_0402_50V8J
1 2
L Please close to JP36
S
JP25
D
1 2
3 1 02/22 Add C1098.
1 2 +3VS
SWITCH BOARD.
1
20 HDA_SDOUT_MDC 3 4 Q85
3 4 R645 SI2301BDS-T1-E3_SOT23-3
G
5 6 +3VS
2
5 6 +3VL_CAP +5VALW_LED
20 HDA_SYNC_MDC 7 7 8 8
20 HDA_SDIN1 1 R495 2HDA_SDIN1_MDC 9 9 10 10 10K_0402_5%
02/19 Change from +3VL to +3VL_CAP.
20 HDA_RST#_MDC 33_0402_5% 11 12 HDA_BITCLK_MDC 20
2
11 12
1
+3VS R554 R555
GND
GND
GND
GND
GND
GND
2
ON/OFFBTN_LED# R1065 1 2 RM@ 0_0402_5% EC_CLK1
1
R496 D ON/OFF# R1066 1 2 RM@ 0_0402_5% EC_DAT1 RP@ 0_0603_5% RM@ 0_0603_5%
ACES_88020-12101 @ 10_0402_5% 2 Q34
13 26,33,36,40 SYSON
14
15
16
17
18
2
CONN@ G 2N7002_SOT23-3 +3VL_R
1 1 1
S
02/22 Change R1048, R1049 from bead to 0 ohm.
4.7U_0603_6.3V6K
C780 1 33 WL_BLUE_BTN R1034 1 2 RM@ 0_0402_5% +3VL_R 1
C778 C779 @4.7U_0805_10V4Z C777 WL_BLUE_LED# R1035 1 2 RM@ 0_0402_5%
2 2 2 +5VS_LED JP36 C1098
@ 10P_0402_50V8J 1
1000P_0402_50V7K 2 1 2
2 2
2 0.1U_0402_16V4Z R1046 1 EC_CK1 2
6,32,33,37 SMB_EC_CK1 2 RP@ 0_0402_5% 3 3
33 ESB_CLK R1048 1 2 RP@ 0_0402_5% ESB_CLK1 4
R1049 1 4
33 ESB_DAT 2 RP@ 0_0402_5% ESB_DAT1 5 5
33 I2C_INT 6 6
ENEESB 7 7
8
CY SMB_EC 33
1
NUM_LED#
2 EC_DA1 9
8
R1047 0_0402_5% 9
10
TouchPAD ON/OFF LED 6,32,33,37 SMB_EC_DA1 RP@ 1 11
10
GND
12
HDD/G-Sensor LED +5VS_LED +3VS
+5VS_LED C1119
0.1U_0402_16V4Z ACES_85201-1005N
GND
2 CONN@
1
03/01 Change R558 to C1119. 9/20 SP01000H400
R984 R983
1
2
200_0402_5% 390_0402_5% HT-297UY5/BP5_YELLOW-WHITE
1
+5VS
02/19 Add LDO control circuit for ENE cap. board.
2
R20
2
PA@ PR@
3
WHITE
YELLOW
WHITE
Q7B D18 @ R985
2
WHITE
YELLOW
+5VL 1 2 3 EN BP 4
5 HT-297UY5/BP5_YELLOW-WHITE 10K_0402_5% R1073 10K_0603_5%
2
2
1
GND
6
HT-297UY5/BP5_YELLOW-WHITE 1
4
@ 2N7002_SOT23-3S Q153 S 2
3
02/18 Modify circuit WLAN/WWAN/BT LED control. 02/26 Connect JP40 pin 4 to +3VALW.
02/22 Add C1100 and C1101
Battery Charge LED WLAN and BT LED inform pin to KBC
+5VALW_LED
WHITE +3VS
R989
D6 R1041
33 BAT_LED# 1 2 1 R550 2 1 2 2 1 +3VS
200_0402_5% @ 10K_0402_5%
HT-F196BP5_WHITE 47K_0402_5% Reed switch BOARD.
WL_BLUE_LED# 2 1 WL/WW_LED# 1 2 +3VALW
CAPS LOCK LED 33 WL_BLUE_LED#
D57 R1007 0_0402_5%
WL_LED# 26
JP40
CH751H-40PT_SOD323-2 1 1
1
+5VS_LED Q55 D
WHITE 1 2 WW_LED# 2633 LID_SW# 2 2
2N7002_SOT23-3 2 R1008 0_0402_5% 3 5
D7 G 3 G1
4 4 G2 6
1 2 1 R552 2 S
3
POWER LED 1 1
1
200_0402_5%
HT-F196BP5_WHITE
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
TP,MDC,ON/OFF,S/W,LED,Reed
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4111P 0.4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, March 07, 2008 Sheet 34 of 54
A B C D E
A B C D E
JDOCK
1 2 41 +DOCKVIN
B+ GND
GND 42
RP@ RP@ D43 45 43
PAD-OPEN 2x2m GND GND
+5VS 1 2 2 46 GND GND 44
R586 1K_0402_5% 1 DOCK_PWR_ON
+3VALW 1 2 3
R585 1K_0402_5% CONN@ FOX_QL1122L-H212AR-9F
RP@ DAN202U_SC70
2
1
D R588
2 10K_0402_5%
03/03 Change JDOCK Footprint
36,42 SYSON#
G RP@
S
3
Q36
2
2N7002_SOT23-3
L R976/Q149/R646 be option with R992/C945 2
RP@
R_VOL_UP# R_VOL_DWN# +1.5VS
SPDIF
1 1
2
RP@ RP@
C843 C844 R976 R646
1000P_0402_50V7K 1000P_0402_50V7K 1 2
+3VL_EC 2 2 @ 33_0402_5% @ 0_0402_5%
1 1
RP@ RP@
2
C C945 R647
R565 DOCK_LOUT_C_R DOCK_LOUT_C_L Q149 2 1 2 1 2 SPDIF_OUT 28
10K_0402_5% @ MMBT3904_NL_SOT23-3 B 220_0402_5%
1
1 1 E RP@ 1 0.1U_0402_16V7K
RP@
3
RP@ RP@ R992 C944 R573
1
2
1
R566
2K_0402_5%
RP@
MIC_Dock Need 600 Ohm 500 mA
2
RP@ L94
RP@ R942 10K_0402_5% FCM1608KF-601T02_2P
28 DOCK_MIC_R 2 1 DOCK_MIC_R_R 1 2 DOCK_MIC_R_C
3 H32 H33 H34 H35 H36 RP@ R943 10K_0402_5% 3
@ H_2P8 @ H_2P8 @ H_2P8 @ H_2P8 @ H_2P8 28 DOCK_MIC_L 2 1 DOCK_MIC_L_R 1 2 DOCK_MIC_L_C
FCM1608KF-601T02_2P
1
RP@ L93 1 1
1
RP@ R980
1
2
@ H_2P8 @ H_2P8 @ H_2P8 @ H_2P8
2
+3VS
1
2
@ H_2P8 @ H_4P2 @ H_4P2 @ H_4P2
RP@ SENSE_B# 28
R915
2
R914 10K_0402_5%
1
1
RP@ D
1
10K_0402_5% 2 Q100
H47 H48 G
1
@ H_3P3 @ H_3P3 D 2N7002_SOT23-3
02/22 Change to PTH hole. S RP@
3
RP@ Q16 2
H53 H54 H55 RP@ PMBT3904_SOT23 G
1
@ H_3P3X0P6N @ H_3P3X0P6N @ H_5P6N R912 C S
1
3
DOCK_MIC_L_C 1 2 2 RP@ Close to CODEC U27
10K_0402_5% B Q18
2
H52 2 E 2N7002_SOT23-3
1
3
@ H_1P5N
R913 C978
4 RP@ 47K_0402_5% 1 4
02/19 Add screw hole.
1
1
RP@ 1U_0603_10V6K
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DOCK CONN
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4111P 0.4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, March 07, 2008 Sheet 35 of 54
A B C D E
A B C D E
Q32 SI2301BDS-T1-E3_SOT23-3
PJP7
D
1 2 3 1
+5VALW TO +5VS +3VALW TO +3VS +5VALW
PAD-OPEN 2x2m 1
1
+3VALW +3VS C836
G
02/25 Add C1110~C1117.
2
+5VALW +5VS R587 0.1U_0402_16V4Z
4.7U_0805_10V4Z 10K_0402_5%
4.7U_0805_10V4Z 2
1 1 1
1 1 1 Q14 C839 C838
2
1 Q35 C833 C835 C1110 1
8 D S 1
8 1 C1111 7 2 0.1U_0603_25V7K DIM_LED#
D S 0.1U_0603_25V7K D S 2 2 2
7 D S 2 6 D S 3
2 2 2
6 D S 3 5 D G 4
1
1U_0402_6.3V4Z D
5 D G 4
1U_0402_6.3V4Z SI4800BDY_SO8 RUNON 2 R152 1 B+ 33 DIM_LED DIM_LED 2 Q51
0.01U_0402_25V7K
SI4800BDY_SO8 1 1 1 330K_0402_5% G 2N7002_SOT23-3
1 1 S
3
1
C1112 D
C1113 C864 RUNON 0.1U_0603_25V7K C834 Q17
2 SUSP +5VS_LED
0.1U_0603_25V7K 4.7U_0805_10V4Z 2 2 C840 2 2N7002_SOT23-3
G
2 2 S Q166 SI2301BDS-T1-E3_SOT23-3
PJP8
D
+5VS 1 2 3 1
4.7U_0805_10V4Z
PAD-OPEN 2x2m 1
C1069
G
2
0.1U_0402_16V4Z
DIM_LED# 2
10U_0805_10V4Z 4.7U_0805_10V4Z
Q4 1 2 1 Q11 1 1 1
2 IRF8113PBF_SO8 C848 C841 IRF8113PBF_SO8 C846 C862 2
8 1 C1114 8 1 C1115
7 2 0.1U_0603_25V7K 7 2 0.1U_0603_25V7K
2 1 2 2 2 2
6 3 6 3
5 5
1U_0402_6.3V4Z 1U_0402_6.3V4Z
1 1 2 R233 1 B+
4
0.01U_0402_25V7K
1 1 1 330K_0402_5%
C1116 C842
1
0.1U_0603_25V7K C1117 C847 D +5VL
2 2 1.8VS_ENABLE R138 2 0.1U_0603_25V7K 4.7U_0805_10V4Z C837 Q12 VLDT_EN#
1 B+ 2
330K_0402_5% 2 2 2 2N7002_SOT23-3
G
1
1
S
3
1
D R598
4.7U_0805_10V4Z C849 2 SUSP
2 G 100K_0402_5%
0.01U_0402_25V7K S Q13
3
2
2N7002_SOT23-3
EC_ON#
1
D
2 Q44
33,39 EC_ON
G 2N7002_SOT23-3
S
Discharge circuit
3
+5VS +1.8VS +1.2V_HT +1.8V +1.2VALW
2
2
3 3
R239 R279 R280 R284
470_0805_5% 470_0805_5% 470_0805_5% 470_0805_5% R368
@ 470_0805_5%
1
1
1
1
D D D D D
SUSP 2 Q46 SUSP 2 Q48 VLDT_EN# 2 Q37 SYSON# 2 Q41 EC_ON# 2 Q42
G G G G G
S 2N7002_SOT23-3 S 2N7002_SOT23-3 S 2N7002_SOT23-3 S 2N7002_SOT23-3 S @ 2N7002_SOT23-3
3
1
+3VS +0.9V +1.5VS +1.1VS
R595 R596 R597
2
2
470_0805_5% 470_0805_5% 470_0805_5% 470_0805_5% SYSON# SUSP
35,42 SYSON# SUSP 42
13 VLDT_EN# VLDT_EN#
1
1
1
1
D D D D Q38 D D Q39 D
SUSP 2 Q47 SYSON# 2 Q49 SUSP 2 Q50 SUSP 2 Q52 SYSON 2 2 VLDT_EN 2 Q40
4 26,33,34,40 SYSON SUSP# 26,28,33,38,41 33 VLDT_EN 4
G G G G G G G 2N7002_SOT23-3
S 2N7002_SOT23-3 S 2N7002_SOT23-3 S 2N7002_SOT23-3 S 2N7002_SOT23-3 2N7002_SOT23-3 S S 2N7002_SOT23-3 S
3
3
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/08/02 Deciphered Date 2008/08/02 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DC/DC Circuits
FM1 FM2 FM3 CF1 CF2 CF3 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
1 1 1 1 1 1 DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4111P 0.4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, March 07, 2008 Sheet 36 of 54
A B C D E
A B C D E
BATT1
1 +3VALW 1
PQ3
3
TP0610K-T1-E3_SOT23-3
BATT
499K_0402_1% 340K_0402_1%
2 AC_LED# 33
PR1 1
+5VALW
1
ADP_ID 33
0.01U_0402_25V7K
PR9
100K_0402_5%
2 1
2
PC12
2
1
PC1
PR8
PR4 1
100_0402_5% PD4 @1000P_0402_50V7K
PR2
2
10K_0402_5%
PC15 0.1U_0402_16V7K
VIN +DOCKVIN
2
1 2
1
2
ACES_88334-057N RLZ3.6B_LL34
8
ADP_SIGNAL 1 2 PR5
5 PR3 3 10K_0402_5%
P
5 10K_0402_5% +
4 4 0 1 2 1 BATT_OVP 33
3 PL1 PL2 2
3 -
G
105K_0402_1%
2 SMB3025500YA_2P SMB3025500YA_2P
2
PR6 1
0.01U_0402_25V7K
1 ADPIN 1 2 2 1
4
1
1
PU1A
PJP1
PC6
LM358ADT_SO8
100P_0402_50V8J
2
1000P_0402_50V7K
390P_0402_50V7K
2
2
3
820P_0402_50V7K
2200P_0402_50V7K
100P_0402_50V8J
PD1
1
1
PC5
PC13
2 2
PC14
PC4
PC7
PC3
2
2
PC2
1000P_0402_50V7K
@PJSOT24C_SOT23-3
1
1
3 3 1
2 2 2
1 PC8 PC9
2
2
1 1000P_0402_50V7K 0.01U_0402_50V4Z
GND 9
GND 10
3
PR7
SUYIN_200275MR008GXOLZR +5VS 47K_0402_1%
3 3
CPU 1 2
1
1
PD3
1
PR14 @SM24.TC_SOT23-3
1
PR13 100_0402_5%
100_0402_5% PH1
2
2
2
PR10
8
SMB_EC_CK1 SMB_EC_CK1 6,32,33,34 15K_0402_1%
1
D
1 2 5
P
+ PQ1
BAT_ID 38 7 2
0 G @SSM3K7002FU_SC70-3
1 2 6 -
G
+5VALW PR11 PU1B S
3
PR16 1 150K_0402_1% LM358ADT_SO8
4
1
1
6.49K_0402_1% +3VL
1
PC10 PR12
1 2
2.55K_0402_1% PR15
0.22U_0603_10V7K
2
1
150K_0402_1% PC11
2
2
1000P_0402_50V7K EN0 6,39
2
PR17
1K_0402_5%
1
D
BATT_TEMP 33
2
2 PQ2
G SSM3K7002FU_SC70-3
S
3
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DC Connector/CPU_OTP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4111P 0.4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, March 07, 2008 Sheet 37 of 54
A B C D E
A B C D
P4 B+
BATT
VIN P2
PQ102
AM4835EP-T1-PF_SO8
PQ101 PQ103 1 8
1
PR102 PL101 2 7 1
AM4835EP-T1-PF_SO8 AM4835EP-T1-PF_SO8 0.012_2512_1% HCB2012KF-121T50_0805 3 6
8 1 1 8 1 2 1 2 CHG_B+ 5
7 2 2 7 PR103
6 3 3 6 47K_0402_5%
4
220P_0402_50V7K
1200P_0402_50V7K
330P_0402_50V7K
PC102
4.7U_0805_25V6-K
4.7U_0805_25V6-K
4.7U_0805_25V6-K
5 5 1 2 VIN
PR101 1U_0603_6.3V6M
1
47P_0402_50V8J
1
PC103
PC104
PC105
PC128
PC129
PC130
0.1U_0603_25V7K
1 2 0_0402_5%
33 AC_SET 1 2 ACSET
2
1
3
DTA144EUA_SC70-3 PR105
PC101
1
PQ104
100K_0402_5%
10K_0402_5%
0.22U_0603_16V7K
PC108
2
2
1
PC109
200K_0402_5%
PR140
2 PC107 ACOFF#
2
1
@0.1U_0603_25V7K
PC106
PR106
@0.01U_0402_16V7K
1
CHG_B+
2
PR107 CHGEN#
2
47K_0402_1% PR108
1 2 2 10_1206_5%
1
1
1 2 2 ACOFF 33
ACP
LPREF
ACSET
ACDET
LPMD
ACN
CHGEN
PQ105 29
TP
1
5
6
7
8
D DTC115EUA_SC70-3 PR110 PC110
3
2 0_0402_5% 1U_0805_25V6K
3
G PR109 26,28,33,36,41 SUSP# 1 2 8 28 1 2 PQ106
150K_0402_5% IADSLP PVCC PC111 DTC115EUA_SC70-3
S
3
2
SSM3K7002FU_SC70-3 9 27 BST_CHG 1 2 4 AO4466_SO8
AGND BTST
PC112 BQ24740VREF PU101
PACIN_1 39 1 2 10 BQ24740RHDR_QFN28_5X5 26 DH_CHG BATT
VREF HIDRV PL102 PR112
3
2
1
PR111 1U_0603_6.3V6M +3VL 10U_LF919AS-100M-P3_4.5A_20% 0.015_1206_1%
1
3K_0402_1% D LX_CHG
11 VDAC PH 25 1 2 1 2
PACIN 1 2 2 PQ109
2
G SSM3K7002FU_SC70-3 PD102 PR139
5
6
7
8
S PR113 VADJ 12 24 REGN 2 1 @4.7_1206_5%
3
@680P_0603_50V7K
ACOFF# PR114 1SS355_SOD323-2
4.7U_0805_25V6-K
4.7U_0805_25V6-K
4.7U_0805_25V6-K
4.7U_0805_25V6-K
2 1 2 2
@0_0402_5% 13 23 DL_CHG
2
1 1
EXTPWR LODRV
1
1SS355_SOD323-2
33 VCTRL 1 2
PC113
PC114
PC115
PC116
4
1
PC131
14 22
2
ISYNSET PGND
1
DPMDET
2
1
PC117 PR115
IADAPT
1 2
SRSET
CELLS
1
1U_0603_10V6K 100K_0402_1% PC119 PQ110
SRN
SRP
2
3
2
1
BAT
PR116
2
2
0.1U_0402_10V7K
15
16
17
18
19
20
21
PR117
100K_0402_5% BQ24740VREF
IADAPT
PR118
Charge Detector 1 2
1
10K_0402_5%
1 2 47K_0402_5%
33 ADP_I
1
D PR119
100P_0402_50V8J
0.22U_0603_10V7K
1
1
PQ111 2 BAT_ID 37
2
PC120
PC121
SSM3K7002FU_SC70-3 G
S
BATT
2
3
VIN
0.1U_0603_25V7K
@0.1U_0603_25V7K
PR120
2 1 IREF 33
2
PC122
PC124
133K_0402_1%
1
PD104 PC123
1
2
PR121 681K_0402_1%
200K_0402_1% 1 2
1
PR123
2
1M_0402_5%
3
1 2 3
VIN_1 PR124
+3VL VIN 1K_0402_5%
VIN
1 2
1
1
PR125
47_1206_5% PR126
1
10K_0402_5%
100K_0402_1% PR127
VIN PR130 10K_0402_1%
2
8
+3VL
10K_0402_1%
PR128
2.15K_0402_1% PU102B
2
1 2 5
P
+
1
PR129
7
2
O
1
PACIN
100K_0402_5%
PR131 6 -
G
133K_0402_1% PC125 CHGEN#
2
1
PR132
1
0.047U_0402_16V7K 10K_0603_0.1%
2
PR134
2
2
1
D PD103
3 10K_0402_5%
P
2
+ PQ112 RLZ4.3B_LL34
O 1 2
1
2 G SSM3K7002FU_SC70-3
2
-
G
PU102A S
PR135
3
LM393DG_SO8 FSTCHG#
4
10K_0603_0.1% PR136
60.4K_0402_1%
2
D
1 2 VIN_1
1.24VREF 33 FSTCHG 2 PQ113
G SSM3K7002FU_SC70-3
S
3
STD_ADP 33
PU103
1
PC127 2
PR137 NC
22P_0402_50V8J
1
100K_0402_1%
4
20K_0402_1% 5 1
4
2
ANODE NC
PR138
APL1431LBBC-TR_SOT23-5
2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Charger
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-3941P 0.4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, March 07, 2008 Sheet 38 of 54
A B C D
A B C D E
2VREF_51125
1
1 1
PC302
0.22U_0603_10V7K
2
PR301 PR302
13.7K_0402_1% 30.9K_0402_1%
1 2 1 2
PR303 PR304
B+ B++
20K_0402_1% 20K_0402_1%
B++
PL301 1 2 1 2
HCB2012KF-121T50_0805
1 2 +3VLP
ENTRIP2
ENTRIP1
2200P_0402_50V7K
@0.1U_0402_25V4K
PR305 PR306
390P_0402_50V7K
2200P_0402_50V7K
2200P_0402_50V7K
@0.1U_0402_25V4K
4.7U_0805_25V6-K
4.7U_0805_25V6-K
4.7U_0805_25V6-K
140K_0402_1% 133K_0402_1%
1
1
PC321
PC316
1 2 1 2
1
PC322
PC301
PC303
PC317
PC304
PC305
PC313
PQ301
2
2
6
5
6
7
8
1 D1 1G 8
1
2 7 PC306
ENTRIP2
VFB2
TONSEL
VFB1
ENTRIP1
VREF
D1 1S/2D 10U_0805_6.3V6M PQ302
3 G2 1S/2D 6 25 P PAD AO4466_SO8
UG1_3V
4 5
2
S2 1S/2D
3
2
1
0_0402_5% 0_0402_5% VBST2 VBST1 0_0402_5%
PL302 1 2 PC307 UG_3V 10 21 UG_5V 1 2 PL303
4.7UH_SIQB74B-4R7PF_4A_20% 0.1U_0402_10V7K DRVH2 DRVH1 4.7UH_PCMC063T-4R7MN_5.5A_20%
2 1 LX_3V 11 20 LX_5V 1 2 +5VALWP
+3VALWP LL2 LL1
5
6
7
8
LG_3V 12 19 LG_5V
DRVL2 DRVL1
1
1
SKIPSEL
1
1
VREG5
VCLK
PC309 PR315 +3VL PR316 1 PC319
GND
EN0
1
VIN
PC320 + @4.7_1206_5% 4.7_1206_5% @22U_0805_6.3V6M
2
4 + PC310
1 2
1 2
150U_D_6.3VM
13
14
15
16
17
18
1
2 TPS51125RGER_QFN24_4X4 PR317
PC314 100K_0402_5% PC315 2
1
@680P_0603_50V8J 6,37 EN0 680P_0603_50V8J
2
3
2
1
2
VL PQ304
PR311 FDS6690AS_NL_SO8
2
@620K_0402_5%
3/5V_OK 20,41
1
PC311
10U_0805_10V6K
2
1
B++
PC312
37 ENTRIP1
2
3 0.1U_0603_25V7K 3
2VREF_51125
ENTRIP2
1
D D
PQ305 2 2 PQ306
SSM3K7002FU_SC70-3 G G SSM3K7002FU_SC70-3
S S +3VLP +3VL
3
PJP301
PJP302
2 1
+5VALWP 1 2 +5VALW (4.5A,180mils ,Via NO.= 9)
PR313 PAD-OPEN 2x2m
100K_0402_5%
PAD-OPEN 4x4m
1 2 VL PJP303
3
1
PC318
0.022U_0603_25V7K PR314
2
100K_0402_5%
2
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
3.3VALWP/5VALWP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4111P 0.4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, March 07, 2008 Sheet 39 of 54
A B C D E
A B C D
1 1
PR401
0_0402_5%
1 2 PL401
26,33,34,36 SYSON
1
HCB1608KF-121T30_0603
PC401 1.8V_B+ 1 2 B+
2200P_0402_50V7K
@0.1U_0402_25V4K
4.7U_0805_25V6-K
4.7U_0805_25V6-K
@1000P_0402_50V7K
2
5
6
7
8
1
+5VALW
PC414
PC403
PC404
PC405
PC406
1+5VALW
BST_1.8V
1 2 BST1_1.8V 1 2 470P_0402_50V7K
2
2 2
PR402 PC402
0_0402_5% 0.1U_0402_10V7K 4
PR403
15
14
1
316_0402_1% PU401
PR404
EN_PSV
TP
VBST
255K_0402_1% PQ401
PR410
2
3
2
1
1 2 2 13 DH_1.8V 1 2 DH_1.8V_1 AO4466_SO8 PL402
TON DRVH 2.2UH_PCMC063T-2R2MN_8A_20%
PR405 0_0402_5%
+1.8VP 2 1 3 12 LX_1.8V 1 2 +1.8VP
VOUT LL
220U_D2_4VY_R25M
0_0402_5%
1
4 V5FILT TRIP 11 1 2
5
6
7
8
PR406 PR407
1
5 10 +5VALW 15.4K_0402_1% @4.7_1206_5%
VFB V5DRV +
PC408
1
1
PC409 6 9 PC415
2 2
PGOOD DRVL
PGND
1U_0603_10V6K GND 4.7U_0805_10V6K
2
4
2
2
PC412
+1.8VP TPS51117RGYR_QFN14_3.5x3.5 @680P_0603_50V7K
PR408
7
1
1 2 DL_1.8V
14.3K_0603_0.1% PQ402
3
2
1
FDS6690AS_NL_SO8
1 2
PC413
@10P_0402_50V8J
1
3 3
PR409
10K_0603_0.1%
2
PJP401
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
1.8VP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-3941P 0.4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, March 07, 2008 Sheet 40 of 54
A B C D
A B C D E
1 1
PR518
0_0402_5%
+1.1VS 1 2 PR501 PR502 PR503 PR504
B+++ 11.5K_0402_1% 24.9K_0402_1% 18.7K_0402_1% 11.5K_0402_1%
+1.1VSP 1 2 1 2 1 2 2 1 2 1 +1.2VALWP
PR517
10_0402_5%
B+++
2
PR505 B+++ B+
0_0402_5% PL502
2200P_0402_50V7K
@0.1U_0402_25V4K
4.7U_0805_25V6-K
4.7U_0805_25V6-K
HCB2012KF-121T50_0805
2 1
1
1
1
+1.1VSP
PC517
PC501
PC502
PC518
2
VCCP_POK
2200P_0402_50V7K
470P_0402_50V7K
@0.1U_0402_25V4K
4.7U_0805_25V6-K
8
7
6
5
5
6
7
8
PC503 PU501
1
PC516
PC504
PC505
PC521
2 @0.022U_0603_25V7K PQ502 2
GND
VO2
VFB2
TONSEL
VFB1
VO1
25 AO4466_SO8
2
PQ501 P PAD
2
AO4466_SO8 4 7 24 4
PGOOD2 PGOOD1
PC507
PC506 PR506 8 23 PR507
EN2 EN1 0.1U_0402_10V7K
0.1U_0402_10V7K 0_0402_5% 0_0402_5%
+1.1VSP 2 1 2 1 BST_1.1V 9 22 BST_1.2V 2 1 1 2
1
2
3
3
2
1
VBST2 VBST1
+1.2VALWP
PL501 UG1_1.1V 2 1 UG_1.1V 10 21 UG_1.2V 2 1 UG1_1.2V PL503
2.2UH_PCMC063T-2R2MN_8A_20% 0_0402_5% PR508 DR VH2 DR VH1 PR509 3.3UH 30% MSCDRI-7030AB-3R3N 4.1A
+1.1VSP 2 1 LX_1.1V 11 20 LX_1.2V 0_0402_5% 1 2 +1.2VALWP
LL2 LL1
1
LG_1.1V 12 19 LG_1.2V
DR VL2 DR VL1
8
7
6
5
1
PR515
5
6
7
8
4.7U_0805_6.3V6K
4.7U_0805_6.3V6K
4.7_1206_5% PR516
220U_D2_4VY_R25M
PGND2
PGND1
1 1
V5FILT
TRIP2
TRIP1
4.7_1206_5%
220U_D2_4VY_R25M
V5IN
1
2
+ +
1 2
PC508
PC509
PC510
PC511
1 2
PC519 4 TPS51124RGER_QFN24_4x4
2
13
14
15
16
17
18
1
2 470P_0603_50V8J 2
4
PC520
2
PQ504 470P_0603_50V8J
2
1
PQ503 AO4468_SO8
1
2
3
3
2
1
18.2K_0402_1% PR510 33K_0402_5%
1 2 17.8K_0402_1% 1 2
3/5V_OK 20,39
2
PR513
0_0402_5%
3 3
2 1
26,28,33,36,38 SUSP#
1
PC512
1 2 +5VALW 0.1U_0402_16V7K
2
PR514
3.3_0402_5%
1
PJP501 PJP502
+1.1VSP 1 2 +1.1VS +1.2VALWP 1 2 +1.2VALW
PAD-OPEN 4x4m PAD-OPEN 4x4m
PJP503
4 4
+1.1VSP 1 2 +1.1VS
PAD-OPEN 4x4m
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
1.1VSP/1.2VALWP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4111P 0.4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, March 07, 2008 Sheet 41 of 54
A B C D E
A B C D E
1 1
+1.8V
+1.8V
PU601
1 6 PU603
VIN VCNTL +5VALW
@10U_0805_10V4Z
1 VIN VCNTL 6 +5VALW
@10U_0805_10V4Z
2 GND NC 5
1
PC602
2 GND NC 5
PC609
PC601 3 7
VREF NC
1
10U_0805_10V4Z PC613 3 7
2
2
VREF NC
1
PR601 PC603
4 8 10U_0805_10V4Z
2
1K_0402_1% VOUT NC 1U_0603_16V6K PR606 PC612
4 8
2
1K_0402_1% VOUT NC 1U_0603_16V6K
9
2
TP
9
2
G2992F1U_SO8 TP
G2992F1U_SO8
1 2 VREF1.5V
35,36 SYSON#
0.1U_0402_16V7K
PR602 +0.9VP
1
0.1U_0402_16V7K
0_0402_5%
+1.5VSP
1
PQ601
SSM3K7002FU_SC70-3 PR603 PQ602
1
1
2 D SSM3K7002FU_SC70-3 2
1K_0402_1% PR607
1
PC605 D
36 SUSP 1 2 2 5.1K_0402_1%
2
PC604
G 10U_0805_6.3V6M 1 2 2 PC614
PR604 36 SUSP
PC611
@0_0402_5% S PR608 G 10U_0805_6.3V6M
3
2
1
0_0402_5% S
3
1
PC606
2
@0.1U_0402_16V7K PC610
2
@0.1U_0402_16V7K
4.7U_0805_6.3V6K
1U_0603_6.3V6M
PAD-OPEN 3x3m
1
GND
PC607
PC608
PR605
1 @150_1206_5%
2
PJP603
PJP602
+2.5VSP 1 2 +2.5VS (500mA,40mils ,Via NO.= 1)
PAD-OPEN 3x3m
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
0.9VSP/2.5VSP/1.5VSP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4111P 0.4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, March 07, 2008 Sheet 42 of 54
A B C D E
A B C D E
PL201 2 1
+CPU_CORE_NB 4.7UH 30% MSCDRI-7030AB-4R7N 3.3A
1
@4.7_1206_5%
PQ202
PR245
1 PQ201
AO4466_SO8
10U_0805_6.3V6M
AO4468_SO8
1
+ PC202 1 8 1 8 CPU_B+
PC201
6 VDD_NB_FB_H 220U_D2_4VY_R25M 2 7 2 7
1 2
PC251 3 6 3 6
2
2
2200P_0402_50V7K
2200P_0402_50V7K
470P_0402_50V7K
PC238
PC203
PC258
5 5 PC204
4.7U_0805_25V6-K
1
1
6 VDD_NB_FB_L
4
@680P_0603_50V7K
2
2
1 PR203 1
1
0_0402_5%
0_0402_5%
0_0402_5%
PR206
PR209
UGATE NB1
PR204
PHASE NB
LGATE NB
22K_0402_1%
2
ISL6265_PWROK
1 2
1 2
PC205 PR205
1000P_0402_50V7K 2_0402_5%
+5VS 1 2
1
1
D B+
CPU_B+
1
44.2K_0402_1% 1200P_0402_50V7K
2 PQ209 PC207 PL202
33P_0402_50V8K
33 VFIX_EN G SSM3K7002FU_SC70-3 0.1U_0402_16V7K PC206 SMB3025500YA_2P
15.4K_0402_1%
S 0.1U_0603_16V7K
3
BOOT_NB1 2
1
PC209
PC208
2 1
+5VS
1000P_0402_50V7K
PR207
1
1000P_0402_50V7K
47P_0402_50V8J
PR208 1
1
2200P_0402_50V7K
@47U_25V_M
Connect to EC pin 110. 2_0402_5%
1
330P_0402_50V7K
3300P_0402_50V7K
1800P_0402_50V7K
390P_0402_50V7K
3300P_0402_50V7K
1800P_0402_50V7K
PC211
+
PC253
4.7U_0805_25V6-K
4.7U_0805_25V6-K
4.7U_0805_25V6-K
4.7U_0805_25V6-K
CPU_B+ 1 2
47P_0402_50V8J
PC214
PC215
PC210
2
5
1
PC243
PC239
PC234
PC235
PC212
PC213
PC248
PC254
PC255
PC249
PC250
2.2U_0603_6.3V6K
2
1
1
2
2
PR210
PC216 PR211
2
PC261
0.1U_0603_25V7K 1_0603_5%
2
1 2
+5VS 4
2
1 2
2 +3VS PR212 2
UGATE NB
PHASE NB
LGATE NB
VSEN_NB
0_0402_5% PQ203
RTN_NB
1 2 RQW130N03-FD5_PSOP8
BOOT_NB
3
2
1
PR213
@0_0402_5% 2.2_0603_5% 0.22U_0603_10V7K UGATE0_1
1 2 PR214 PC217 0.36UH_PCMC104T-R36MN1R17_30A_20%
1
10K_0402_1%
48
47
46
45
44
43
42
41
40
39
38
37
1 2 1 2 2 1 +CPU_CORE_0
PR215 PU201
5
6
7
8
5
6
7
8
1
4.7_1206_5%
PC218 4.7_1206_5%
16.5K_0402_1%
PR216
@10K_0402_5% PL203
FB_NB
COMP_NB
FSET_NB
VSEN_NB
PHASE_NB
UGATE_NB
VIN
VCC
RTN_NB
OCSET_NB
PGND_NB
LGATE_NB
47P_0402_50V8J
PR220
PR242
PR221
1 2
BOOT0
1
0_0603_5%
2
PC259
1 36 PR219
OFS/VFIXEN BOOT_NB PR217
1 2
2200P_0603_50V7K 2
2
2 35 4 4 4.02k_0603_1%
33 VGATE PR246 1100K_0402_5% PGOOD BOOT0 PQ204
2 1 2
19 H_PWRGD 1 2 ISL6265_PWROK 3 34 UGATE0 FDS8672S_SO8
6,20,33 SB_PWRGD PR234 @100K_0402_5% PWROK UGATE0 PQ205 PC219 1 2
2
PR218 1 2 SVD 4 33 PHASE0 FDS8672S_SO8 0.1U_0603_25V7K
3
2
1
3
2
1
6 CPU_SVD 0_0402_5% SVD PHASE0 ISP 0
PR222 1 2 SVC 5 32
6 CPU_SVC 0_0402_5% SVC PGND0
6 31 LGATE0 CPU_B+
33 VR_ON PR223 PR224 ENABLE LGATE0
2200P_0402_50V7K
2200P_0402_50V7K
1800P_0402_50V7K
390P_0402_50V7K
47P_0402_50V8J
4.7U_0805_25V6-K
4.7U_0805_25V6-K
4.7U_0805_25V6-K
4.7U_0805_25V6-K
1 2 1 2 7 RBIAS PVCC 30
1
1
1
PC240
PC237
PC236
PC220
PC221
PC252
PC256
PC257
34.8K_0402_1% 82.5K_0402_1% 8 29 LGATE1
OCSET LGATE1
PC222
2
2
PR225 PC223 9 28
2
VDIFF0 ISL6265IRZ-T_QFN48_6X6 PGND1
1 2 1 2 4
10 27 PHASE1
255_0402_1% 4700P_0402_25V7K FB0 PHASE1 PR226
PR227 11 26 UGATE1 1 2 UGATE1_1 PQ206
3 COMP0 UGATE1 0_0603_5% RQW130N03-FD5_PSOP8 3
1 2
3
2
1
12 25 BOOT1 1 2 1 2 2 1 +CPU_CORE_1
1K_0402_1% VW0 BOOT1 PR228 PL204
COMP1
VDIFF1
VSEN0
VSEN1
5
6
7
8
5
6
7
8
1
4.7_1206_5%
4.7_1206_5%
RTN0
RTN1
ISN1
ISP0
VW1
ISP1
1
FB1
16.5K_0402_1%
PR229
PR244
0.22U_0603_10V7K
TP
PR231
PR230 PC225
1 2 1 2
13
14
15
16
17
18
19
20
21
22
23
24
49
47P_0402_50V8J
1 2
1
54.9K_0402_1% 1200P_0402_50V7K PR232 4 4
2
VSEN0
PC260
PR233
VSEN1
+CPU_CORE_0
1 2 1 2
RTN0
RTN1
ISP 0
2
180P_0402_50V8J 6.81K_0402_1% +CPU_CORE_1 PQ207 PQ208 2200P_0603_50V7K 1 2
2
3
2
1
3
2
1
ISP 1 FDS8672S_SO8 FDS8672S_SO8 PC229
@1000P_0402_50V7K
1 2 PC230 0.1U_0603_25V7K 1 2
PC228 1000P_0402_50V7K
1000P_0402_50V7K 2 1
PC231
PC241 180P_0402_50V8J ISP 1
PC244
1 2 1000P_0402_50V7K
@1000P_0402_50V7K
6 CPU_VDD0_FB_H PR235 2 1 2 1
1
6.81K_0402_1% 54.9K_0402_1%
2 1 2 1
2
2
PC232
PC245
1 2 1200P_0402_50V7K
6 CPU_VDD0_FB_L PR237 PR240
1
@1000P_0402_50V7K
0_0402_5% 1K_0402_1%
2 1
2
4 PR243 4
255_0402_1%
@1000P_0402_50V7K
PC242 2 1 2 1
PC246
1 2 1000P_0402_50V7K
6 CPU_VDD1_FB_L PR239 4700P_0402_25V7K
1
0_0402_5% PC233
1
PC247
2
6 CPU_VDD1_FB_H PR241
0_0402_5%
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CPU_CORE
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4111P 0.4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, March 07, 2008 Sheet 43 of 54
A B C D E
A B C D E
4 43 CPU_CORE 9/29 Compal HW request PC202 change the value from 220U_6.3VM_R15 to 220U_D24VY_R25M
2 2
TI FAE suggested that after he review
6 43 CPU_CORE 9/29 Compal the layout. Add PJP201PJP202
7 38 Charger 9/29 Compal the footprint is wrong Change the footprint of PR102
DC Connector
8 37 /CPU_OTP 10/08 Compal for Layout These two choke are parallel ,it's not series.
9 38 Charger 10/08 Compal the footprint is wrong Change the footprint of PR102
DC Connector
12 37 /CPU_OTP 11/01 Compal PWR request Add PD4PC12
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Power Changed-List History-1
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4111P 0.4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, March 07, 2008 Sheet 44 of 54
A B C D E
A B C D E
37 DC Connector 01/09 Compal AC LED change to KBC control AC_LED# connect to KBC pin 97
19 /CPU_OTP
20 37 3.3VALWP/5VALWP 01/14 Compal for layout Change PC309 to D size and add PC320
21 38 Charger 02/27 Compal EMI request CHG_B+ Add 1200pF and 330pF
22 43 CPU_CORE 02/27 Compal EMI request CPU_B+ Add 1800pF*2 2200pF*1 and 390pF*2
2 2
24 37 DC Connector 02/27 Compal EMI request VIN Add 2200pF and 390pF, ADPIN add 820pF
/CPU_OTP
25
37 3.3VALWP/5VALWP 02/27 Compal Change OTC shun down pin. Change OTC shun down pin to PU301 pin13.
26 43 CPU_CORE 02/15 Compal Change high-side MOS for WWAN issue Change PQ203 and PQ206 to powerpak
3 3
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Power Changed-List History-1
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4111P 0.4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, March 07, 2008 Sheet 45 of 54
A B C D E
A B C D E
Realtek RTL8102EL
2 25 LAN 10/29 HPQ Add POE(Power Over Ethernet) design Update the LAN Design page and support circuit 0.2
3 16 CRT 10/29 HW CRT can not display Change the CRT Conn. signals connection first. 0.2
Wait correct symbol for fix
4 29 Audio 10/30 HW Speaker no sound Add R973(10K_0402) to +3VALW on HP_DET# 0.2
5 4 FAN 11/01 HW FAN Conn. not correct part Change JP2 PCB Footprint from ACES_85204-02001_2P to 0.2
ACES_88231-02001_2P
6 29 Speaker 11/01 HW Speaker Conn. not correct part Change JP20 PCB Footprint from ACES_85204-04001_4P to 0.2
ACES_88231-04001_4P
7 34 MDC 11/01 HW MDC Conn. not correct part Change JP20 PCB Footprint from ACES_88018-124G_12P to 0.2
ACES_88020-12101_12P
2
8 11,35 TV_OUT 11/05 HW TV-OUT Function no support Del R59,R60,R61,R115,R116,R117 and TV-OUT related design. 0.2 2
9 11,21 NB/SB Thermal 11/05 HW NB Thermal Function no support (locate too far) Cancel NB_THERMAL_DA/DC connection between NB and 0.2
SB,del C500
10 21,31 SB SATA 11/05 HW SB SATA Port 5 change to Port 2 for ATI Common Change SB SATA port 5 to port 2 0.2
Design
11 21 SB SATA 11/05 HW SB SATA_ACT# Pull High become +3VS Change R343.1 power rail from +5VS to +3VS. Install R343. 0.2
12 21 SB GPIO 11/05 HW Change SB GPIO refer to JBK00 for common 1. Connect U15.C6 to GND by 0_0402. 0.2
2. Change WLOFF# from GPIO50 to GPIO61.
3. Change BT_COMBO_EN# from GPIO51 to GPIO62.
4. Change WWOFF# from GPIO52 to GPIO63.
13 31 SB SATA 11/05 HW Vertical L51 1<-->4 , 2<-->3 for layout routing Vertical L51 1<-->4 , 2<-->3 for layout routing 0.2
14 29 Audio HP OUT 11/05 HW Add 150UF Caps for each DOCK_LOUT_R/L Add 150UF Caps for each DOCK_LOUT_R/L 0.2
3 3
15 25 LAN Transfermor 11/05 HW Correct U19 LAN Transfermor pin definition Correct U19 LAN Transfermor pin definition 0.2
16 21,24 SB SATA 11/06 HW SB SATA Port 4 change to Port 3 for ATI Open Issue Change SB SATA port 4 to port 3 0.2
17 36 DIM LED 11/06 HW Reduce DIM LED unnecessary design Del R1026 and Q167, add Net "DIM_LED#" for connect. 0.2
Change location from PJP604 to PJP8.
18 27 CardReader 11/06 HW Change CardReader Socket for M/E new part and Change JREAD to TAITW_R015-B10-LM. 0.2
Chip for JMicron new version Reserve R413,C902 close to JREAD.20;
R412,C901 close to JREAD.26; R411,C900 close to JREAD.37.
Change R457 close to U23.42
Add R455,R456 close to U23.42
Del Q169,R1051.
Change net CR_LED# become CR_LED connect U23.21 and Q53.2
Add R454 pull down to GND
4 Change R405,R122 from 200K to 10K pull-high 4
Remove C895,U22
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HW Changed-List History-1
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4111P 0.4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, March 07, 2008 Sheet 46 of 54
A B C D E
A B C D E
20 17 LCD 11/07 HW Normalize LCD design for common Change R491 from 200_0402 to 200_0805 0.2
21 18 LCD 11/07 CIC CIC feedback RMA concern for common Change Q43 from AOS3413 to SI2301 0.2
22 33 KBC 11/07 HW Normalize KB926 Crystal part for common Change Y7 from 9H03200413 small to 1TJS125DJ4A420P normal. 0.2
23 17 WebCam 11/09 HW Change U54 WebCam power design and related Change U54 from G916-390T1UF to RT9193-39GB. 0.2
Remove R891,R892 if no use G916-390T1UF.
Add C718 close to U54.4 for RT9193-39GB.
Remove R1027~R1030 for JP7 no install.
Change JP7 from 8pin to 6pin
24 18 HDMI 11/09 HW Reduce HDMI Design Remove R490(100K_0402) 0.2
25 19,32 SB-CLK-Debug 11/09 HW Debug Card no function issue Del R1031,add R303 close to R301 and U15.P2 0.2
Connect for CLK_PCI_SIO2 to JP41.15
2
26 25 LAN 11/09 HW RJ45 LED Power correct back Change JRJ45.13, JRJ45.11 from +3V_LAN_LED to +3V_LAN 0.2 2
41 18 HDMI 11/13 HW Remove EMI solution become reserve for verify Add R112,R113,R115~R120 close to each L85~L88 for co-lay 0.2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HW Changed-List History-2
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4111P 0.4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, March 07, 2008 Sheet 47 of 54
A B C D E
A B C D E
49 21,33 SB,KBC 11/13 HW Reduce SB related design for common Del D51 and R1034, Change the net AC_IN become AC_IN_D 0.2
50 28,33 Codec,KBC 11/13 HPQ EC_BEEP function for KBC add Add R563 close to C955; Add R544 close to U33.31 0.2
51 33 KBC 11/13 HW Reduce S5 Power Consumption Change R1040.1 connection from +3VL_EC to +3VALW 0.2
Del R546 PH to +3VL_EC, Del D26 replace by add R547 close to
U33 for short
52 33 KBC 11/13 HW Reduce KBC Design for common and Ver:C0 Chip Del R537 become Test Point, change R516 become 150_0603 0.2
Change from SA00001J530 to SA00001J540 Remove R1044, change R1040 from 10K to 100K
Change R528.2 , R529.2 connection from +5VALW to +5VL
Install C814 (4.7U_0805)
53 34 Switch Design 11/13 HW Update CSD function board design for common Change JP36.1 connection become +3VL;Change R1046.1 0.2
and R1047.1 connection become SMB_EC_CK1/DA1
Change JP36.7 connection from GND to +5VALW_LED by
54 34 LED 11/14 HW Correct T/P On/Off LED design define Change Q153 from 2N7002DW to 2N7002 0.2
3
Correct G-Sensor LED design define Change R988.1 connection from +5VS_LED to +3VS 3
55 29 Audio-Dock 11/14 HPQ For GS mark requirement Add R968,R969 close to C775/C776. 0.2
56 29 Holes 11/14 ME Update Holes to meet M/E Drawing Add back H52 become H_1P5N; Del CF4 0.2
57 4,24 Multi-Bay 11/14 ME Update Symbol to meet M/E Drawing Update JP2,JP9,JP10,JP11,JP20,JP40,JHDMI,JESAT,JCRT, 0.2
JDOCK Symbol
58 33 Holes 11/14 ME Update Holes to meet M/E Drawing Add back H52 become H_1P5N; Del CF4 0.2
59 20 SB 11/16 ATI Reserve to fix the OTS325055 Issue Reserve R83 PH to +3VS 0.2
60 33 KBC 11/16 EC Change design for EC team debug Change JP34.1 from +5VALW to +5VL 0.2
61 35 DOCK 11/16 EMC Connect DOCK guide pin to GND Add JDOCK.45/46 to GND 0.2
62 33 K/B 11/16 HW Fix KB matrix issue Del KSI6 and KSO9 out of page net connect 0.2
63 28,29 HPQ Make some Audio related design change Change C983,C984 from 1UF to 0.022UF. Change C1049,C1050,C1040,C1041 0.2
AUDIO 11/18 from 0.47UF to 0.022UF. Change R1002,R1005 from 20K to 0 ohm. Change
4 4
C1044 from 10UF to 4.7UF. Remove R1000,R1004; Install R1001,R1003.
64 29 AUDIO 11/19 HPQ Make some Audio related design change Change R968,R969 from 40.2_0402 to 47_0603 0.2
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/08/02 Deciphered Date 2008/08/02 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HW Changed-List History-2
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4111P 0.4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, March 07, 2008 Sheet 48 of 54
A B C D E
A B C D E
66 22 SB 11/20 ATI Design Change for SB A12 Version chip Install R593, remove R592 0.2
67 22 SB 11/20 HW Reduce SB Power Design-No IDE support Remove R12,C543,C544,C547,C536 0.2
68 33,34 Function Board 11/20 HW Reserve for Rachman UMA selective Reserve R555 for +5VALW_LED, add R554 for +3VL close to JP36.1 0.2
Reserve R1034 close to JP36.4,R1035 close JP36.5,Remove R1036
Add R513 PH to +3VS close to U33.19
69 23 SB 11/20 HW Make the SB Strap Seeting for common Install R356 (10K_0402) 0.2
70 31 BlueTooth 11/20 HW Update BT design for common Change R520 from 47K_0402 to 10K_0402 0.2
71 34 Power On Switch 11/22 HW Cancel one reserved power on switch Del SW3 0.2
72 33 KBC 11/22 HW Modify SMB_EC_DA1/CK1 PH for common Change R528,R529 pin 2 connection from +5VL to +3VL 0.2
73 6 CPU 11/22 HW Link PROCHOT# between CPU and NB Add R59 close to Q2 0.2
74 19 SB 11/22 HW Reserve LPCCLK1 for debug card function Add R308 22_0402 for U15.E22 close to R362.1, remove R301 0.2
2
75 26 Express Card 11/22 HW To avoid New Card Switch leakage issue Add R54(0_0402) close to U21.6 0.2 2
76 28 Audio Codec 11/22 HW Reserve SPDIF OUT1 test point for verify Add T21 close to U27.45 0.2
77 10~13 NB, 11/23 HW BOM correct for SI-1 SMT build Update U3(SA00001ZG00-->SA00001ZG20);U10(SA00001Z300--> 0.2
SA00001Z310);U15(SA00001S510-->SA00001S560)
78 19 SB 11/23 HW Change Crystal Res. size for layout space Change R389 from 0603 to 0402 0.2
79 22 SB 11/26 HW Reduce SB SATA Power Caps (Confirm with ATI FAE) Change C567,C568 from 10U_0805 to 1U_0805 0.2
80 28 Codec 11/26 HW SPDIF0 --> 1 design change to follow Vader Change U27.48/45 pin connection 0.2
81 34 T/P 11/28 HW Change T/P Power for reduce S4/S5 power consumption Remove R235; Add Q85, R645, Q34 0.2
82 14 HDMI 11/28 ATI Fix HDMI no function issue Remove R102; Add R101 0.2
83 15 CLK Gen. 11/28 HW Change design for new version CLK Gen. Remove R1045 0.2
84 28 Codec 11/28 HW Change EC_BEEP function become reserve Remove R563 0.2
3
85 20,27 SB,CardReader 11/28 HW Disconnect D3E support for A version to avoid risk Remove R81,R369 0.2 3
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HW Changed-List History-2
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4111P 0.4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, March 07, 2008 Sheet 49 of 54
A B C D E
A B C D E
36 34 Switch board 01/10 EMI Change R1048 and R1049 from 0 ohm to bead. 0.3
36 06 HDT debug port 01/14 AMD Stuff R26, R28 and R41. 0.3
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/08/02 Deciphered Date 2008/08/02 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HW Changed-List History-2
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4111P 0.4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, March 07, 2008 Sheet 50 of 54
A B C D E
A B C D E
01/14 8102E (10/100M 48 pin) can not support DSM function. Reserve R544
39 11 NB 01/15 HW No support daul channel panel. Remove LVDS signal of Channel B. 0.3
40 17 LVDS 01/15 HW No support daul channel panel. Remove LVDS signal of Channel B (remove C1061~C1063) 0.3
41 15 Clock GEN. 01/15 HW To slove noise issue. Chagne C1074~C1076 to 12pF 0.3
42 15 Clock GEN. 01/15 Vendor Clock Gen. spec. update Change R379 to 158 ohm and R380 to 90.9 ohm. 0.3
2 2
3 3
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HW Changed-List History-2
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4111P 0.4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, March 07, 2008 Sheet 51 of 54
A B C D E
A B C D E
13 27 Card Reader 02/15 HW Change Card Reader LED active status. Reserve Q53 and R454, add R1070. 0.4
14 27 Card Reader 02/15 HW Change Card Reader LED active status. Reserve R112 and add pull low resistor R1069. 0.4
15 31 BT 02/15 ME Change JP32 Footprint and reverse pin define. 0.4
16 31 BT 02/15 HW Saving Power consumption. Change BT power source from +3VALW to +3VS. 0.4
17 33 EC 02/15 HW Remove JP34 and reserve R1068 for EC debug. 0.4
18 33 EC 02/15 HW To solve can't power on when first plug in AC adapter. Change R1040 from 100K to 10K ohm and connect to +3VL_EC. 0.4
19 34 Debug SW 02/15 HW Remove SW2. 0.4
20 34 TP LED 02/15 ME Add D19 for PR sku. 0.4
21 11 NB 02/18 HW Change R371 from 10K to 300 ohm. 0.4
22 11 NB 02/18 HW Add pull low resistor R1072. 0.4
3
23 19 SB 02/18 HW Reserve C1085 and R303. 0.4 3
24 21 SB 02/18 HW To solve can't power on when first plug in AC adapter. Add R1071 and D56 to connect to AC_IN. 0.4
25 32 SPI BIOS 02/18 HW Remove U30, C489, R226, and R228. Stuff R221. 0.4
26 34 WL/BT LED control 02/18 HW Modify circuit WLAN/WWAN/BT LED control. 0.4
27 33 EC 02/18 HW Follow Trinity design. Change R514 and R515 from 10K to 4.7K ohm. 0.4
28 35 Screw hole 02/19 ME To slove TP on/off button feeling no good when press. Add H57. 0.4
29 34 S/W board connector 02/19 ENE For ENE cap. board. Add LDO circuit (U65, R1073, C1097,C1099, J2). 0.4
30 34 S/W board connector 02/19 ENE For ENE cap. board. Change R554 pin 1 power plan from +3VL to +3VL_CAP. 0.4
31 34 S/W board connector 02/22 HW For cap. board. Add C1098. 0.4
32 11 NB 02/22 HW To splve CRT rising/falling fail issue. Reserve R62, R63, R64. 0.4
33 16 CRT connector 02/22 HW To splve CRT rising/falling fail issue. Change R211, R214 and R217 from 150 ohm to 75 ohm 0.4
34 16 CRT connector HW 0.4
4 4
02/22 To splve CRT rising/falling fail issue. Change C472, C476, C858 from 22pF to 6pF.
35 34 Lid switch connector 02/22 HW To solve short issue for lid switch board. Move C1100 and C1101 from lid swtich board to M/B 0.4
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/08/02 Deciphered Date 2008/08/02 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HW Changed-List History-2
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4111P 0.4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, March 07, 2008 Sheet 52 of 54
A B C D E
A B C D E
38 34 S/W board connector 02/22 EMI To solve EMI issue for ENE cap. board. Change R1048 and R1049 from bead to 0 ohm. 0.4
39 34 S/W board connector 02/22 EMI To solve EMI issue for ENE cap. board. Reserve R1074/C1102 for ESB_CLK1 and R1075/C1103 for ESB_DAT1. 0.4
40 33 EC 02/22 EMI To solve EMI issue for ENE cap. board. Add R1076, C1104 and R1077. 0.4
41 33 EC 02/22 EMI Add C1105. 0.4
42 36 DC/DC 02/25 EMI For EMI request. Add C1110~C1117. 0.4
43 31 USB connector 02/25 EMI For EMI request. Add C1109. 0.4
44 15 Clock GEN. 02/25 EMI For EMI request. Add C1106. 0.4
45 16 CRT Connector 02/25 EMI For EMI request. Add C1107. 0.4
46 17 LCD Connector 02/25 EMI For EMI request. Add C1108. 0.4
47 32 Debug connector 02/26 EMI For EMI request. Add C1118. 0.4
48 17 WEBcam LDO HW 0.4
2 2
02/26 To reduce power consumption in S3 mode. Add PJP6 to connect to +5VS. Stuff R1013 and reserve R1014.
59 33 EC 03/03 AMD To support VariBright feature. Change JDOCK connector Footprint. 0.4
60 06 CPU 03/04 AMD Reserve R175, R814, C939, Q127 and Q129. 0.4
61 19 SB 03/04 AMD To solve can not power on when use single core CPU. Change net name from H_PWRGD to H_PWRGD_SB. 0.4
62 20 SB 03/05 EMI For EMI request Add SSC circuit (U66, R1080, R1081, R1082, R1083, C1122) for HDA_BITCLK. 0.4
63 21 SB 03/06 AMD For eSATA GEN1 fail issue. Change C520 and C521 from 0.01uF to 1000pF. 0.4
64 21 SB 03/06 AMD For eSATA GEN1 fail issue. Change C520 and C521 from 0.01uF to 1000pF. 0.4
65 31 eSATA connector 03/06 AMD For eSATA GEN1 fail issue. Change C792 and C793 from 0.01uF to 1000pF. 0.4
66 17 LCDVCC circuit 03/06 HW To solve LCD power up sequence fail. Change R225 from 470 ohm to 220 ohm. 0.4
67 15 Clock GEN. 03/06 HW For IDT CLOCK GEN. Add C1123. 0.4
68 20 SB 03/06 HW To avoid CMOS data lose when shutdown suddenly. Add D58 and connect to 3/5V_OK. 0.4
4
67 15 WWAN connector 03/06 HW To support wake on WWAN feature. Add power on/off control circuit (Q167, R1087). 0.4 4
67 15 WWAN/WLAN 03/06 HW To avoid leakage power from SB. Add D59 and D60. 0.4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HW Changed-List History-2
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4111P 0.4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, March 07, 2008 Sheet 53 of 54
A B C D E
A B C D E
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
3 3
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
4
0.4 4
0.4
0.4
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/08/02 Deciphered Date 2008/08/02 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HW Changed-List History-2
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4111P 0.4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, March 07, 2008 Sheet 54 of 54
A B C D E
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