PIC16F627A/628A/648A

FIGURE 3-1: BLOCK DIAGRAM

13 Data Bus 8
Program Counter
Flash
Program
Memory RAM
8-Level Stack
File
(13-bit) Registers

Program 14
Bus RAM Addr (1) 9 PORTA

Addr MUX RA0/AN0

Instruction Reg
RA1/AN1
Direct Addr 7 Indirect RA2/AN2/VREF
8 Addr
RA3/AN3/CMP1
FSR Reg RA4/T0CK1/CMP2
RA5/MCLR/VPP
Status Reg RA6/OSC2/CLKOUT
8 RA7/OSC1/CLKIN

3 MUX PORTB
Power-up
Timer RB0/INT
RB1/RX/DT
Instruction Oscillator
Decode & Start-up Timer RB2/TX/CK
ALU RB3/CCP1
Control
Power-on RB4/PGM
Reset 8
RB5
Timing Watchdog RB6/T1OSO/T1CKI/PGC
Generation Timer W Reg
RB7/T1OSI/PGD
OSC1/CLKIN Brown-out
OSC2/CLKOUT Reset
Low-Voltage
Programming

MCLR VDD, VSS

Comparator Timer0 Timer1 Timer2

VREF CCP1 USART Data EEPROM

Note 1: Higher order bits are from the Status register.

DS40044G-page 12 2009 Microchip Technology Inc.