MUC LUC BANG KY HIRU VIET TAT. LOI MO DAU. CHUONG 1 TONG QUAN VE FPGA VA. NGON NGtVHDL. - 1.1. TONG QUAN VE FPGA. Itt. Lich sic ra di cia FPGA LI. Khai nigm co bin vi ci trie cia FPGA “Cie ing dung cha FPGA 12, TONG QUAN VENGON NOU VHDL, 1.2.1 Git thigu vé ngin ngit ms té phi cing VDI. 1.2.2. Ci tric mt mi hink hi thing mi ta bing ngin ngit VDL 1 CHUONG 2 RO LOC FIR 2 2.1. BQ LOC FIR TRUYEN THONG... sons snl 2.2. BQ LOC FIR SU DUNG KIEN TRUC ‘SYSTOLIC ARRAY 13 2.21. Tig quan vé sole array. : 1B 2.2.2. Bg loc FIR tye hign theo hiém are systole array mpt chi 4 CHONG 3. BO LOC FIR THICH NGHI DUNG THUAT TOAN LMS. 3.1, DATVAN DE. 82, CAUTRUC CUA MACH LOC THICH NGHL 333. MACH LOC WIENER FIR. : 338, CAC THUAT TOAN THICH NGHI VA UNG DUNG. “das Phicomg php gia bude whan nit $42. Thuét ton tom plucong trang Binh ti thiéw LMS) 2s (CHUONG 4. HE THONG 96 BO HALVA CAC PHEP TOAN.. 4.1. BIFU DIEN SO AMTRONG HE THONG SO BU HAL 29 4.2. THYC HIEN CAC PHEP TINH TRONG HE THONG SO BU HA, 30 png trong hg thing $6 bit hai 30 trie tromg hg thing sb bit hai 3 4.23, Hign twgng tri sb 32 4.2.4, Thue hign phep man trong so bis hai 33 CHUONG THUG NGHIEM. 5.1. MOTA PHAN CUNG CUA KIT VIRTEX-I1 PRO, 3s 52. KETQUA THU DUGC VOIBO LOC FIR TRUYEN THON 36 53. KPTQUA THU DUOC VOIBO LOC FIR THEO KIEN TRUC SYSTOLIC 38 54. KETQUA THU DUGC VOIBO LOC FIR THICH NGHI 38 KET LUN osessneninn ao ‘TAL LIEU THAM KHAO. 2 PHY LUC. 43 BANG KY HIEU VIET TATin Giai ASIC Application Specific Integrated Circuit ADC Analog to Digital Converter ALU Arithmetic Logie Unit ASM Auto Senquencing Memory cPLD Complex Programmable Logic De cpu Central Processing Unit DAC Digital to Analog Converter DPU Data Processing Unit FIR Finite Impulse Response FPGA Field Programmable Gate Array HDL. Hardware Description Language Ic Integrated Circuit IEEE Institute of Electrical and Electronics Engineers JTAG Joint Test Action Group LED Light Emitting Diode LUT Look Up Table LMs. Least Mean Square PAL, Programmable Array Logic PLA Programmable Logic Array PCI Peripheral Component Interconnect, PE Process Element RAM Random Access Memory ROM Read Only Memory S232 Recommended Standard 232 SoC ystem on chipSRAM Static Random Access Memory SPLD Simple Programable Logic Device USB Universal Serial Bus Very High Speed Itergrated Circuit VHDL Hardware Description Language VHSIC Very High Speed Hergrated CircuitLOI MO DAU Ngay nay, xir ly tin higu va loc s6 la m6t nganh phat trién hét sire manh ma, céc céng nghé, thuat todn ngay cing duge déi mai va t6i wu hod nham nang cao tinh qua cia n6. Tuy nhign, edng nghé phat trién cang cao thi ddi hoi phan eitng phai da nhanh dé xir ly. Cée mach Ige trong ty rude day khéng cin dit kha nang dé dp img yéu cau dé nita. Vi vay, FPGA da ra dai nhu mét giai phdp cung cdp méi trong lam viée higu qua cho cae img dung thye té, Tinh linh déng cao trong qua trinh thiét ké cho phép FPGA giai quyét nhitng bai todn phite tap ma truée kia chi thyre hign nho phan iu mém may tinh. Ngoai ra, nh mat d6 céng logic cao, FPGA duge img dung cho nhing bai toan ddi hoi khéi long tinh toan lin va ding trong cac hé théng lam vige theo thoi gian thye. Nhiing ing dung trong thy té ctia FPGA rat rong rai, bao gém: cdc hé théng hang khéng, vii tru, quéc phong, tién thiét ké mau ASIC(ASIC protonyping), cic hé théng diéu khién tre quan, phan tich nhan dang anh, nhan dang tiéng noi, mat ma hhge, mé hinh phan eting may tinh...Dae bigt, véi kha nang tai lép trinh, ngudi sit dung 6 thé thay d6i lai thiét ké cua minh chi trong vai gis: Chinh vi tinh thiét thye ma FPGA 4a mang lai, em quyét dinh chon FPGA lam huéng nghién citu cia minh, Trong bai khod ludn nay, em xin trinh bay m6t img dung cu thé cia FPGA trong xir ly tin higu sé d6 la “Thue hign bé loc FIR thich nghi ding thut toan LMS”. Dé tai durge thye hign tai phng thi nghiém muc tiéu “C&e hg tich hgp thng minh ( SIS LAB)” tryc thudc trudmg Dai hoc Cong nghé - DHQG HN. Em xin chan thanh cam on cae thay c6 gido dac biét la PGS.TS Tran Quang Vinh Th.S Nguyén Kiém Hing 4a tan tinh huréng dan va gitip do; em dé ho’n thanh ban luan van nay m6t cach t6t dep. Do thé gian va kién thite e6 han nén cng trinh nay kh6ng thé trénh khOi sai sot, vi vay em rat mong nhan duge cac y kién déng gop cita cac thay cé va cdc ban. Em xin chan thanh eam om ! Ha N6i, Ngay 27 Thang 3 Nam 2008 Nguyén Anh Cuéng Chuong 1 TONG QUAN VE FPGA VA NGON NGU VHDL1.1. TONG QUAN VE FPGA 1.1.1, Lich sit ra doi cia FPGA FPGA duge thiét ké dau tién boi Ross Freeman, nguai sing lap cng ty Xilinx vao nim 1984, kién tric méi cua FPGA cho phép tich hgp sé long tuwong déi lon céc phan tir ban dan vao 1 vi mach so v6i kién truc trude dé li CPLD. FPGA c6 kha nang chita t6i tir 100,000 dén hang vai ty céng logic, trong khi CPLD chi chita tir 10.000 dén 100.000 céng logic; con sé nay déi voi PAL, PLA cén thap hon nita chi dat vai nghin dén 10.000. CPLD duge cau tric tir sé long nhat dinh cac khéi SPLD (Simple programable logic device) thudt ngit chung chi PAL, PLA. SPLD thuang 1a mét mang logic ANDIOR lip trinh durge 06 kich thurde xée dinh va chita mét phan tir nhé ding b6 (clocked register). Cau trie nay han ché kha nang thy hii lung han ché cde nhing ham phite tap va théng thudng higu sudt Lim vige cua vi mach phy thude vao cdu trite cu thé cia vi mach hon La vao yéu cau bai toan. Kién tric cia FPGA 1a kién trie mang céc khéi logic, méi khéi nay nh6 hon nhiéu néu dem so sanh voi m6t khéi SPLD, wu diém nay gitip FPGA cé thé chita nhigu hon cc phan tir logic va phat huy téi da kha nang lap trinh cita cc phan tir logic va hé thong mach két ndi, 48 dat duge muc dich nay thi kién tric cia FPGA phir tap hon nhiéu so véi CPLD. Mét diém khde bigt nita voi CPLD [a trong nhiing FPGA hién dai durge tich hop nhiéu bé logic sé hoc da duoc t6i uu héa, hé tro RAM, ROM, tic dé cao, hay cdc bd nhan, edng ding cho nhimg img dung xir ly tin higu s6. Ngoai kha nang cdu tric Iai vi mach & mie toan cyc, mot sé FPGA hign dai hd tre cdu trie lai 6 mite cue b6, tite 1a kha nang céu tric lai mt bd phan rigng 18 trong khi vn dam bao hoat d6ng binh thudng cho cac bé phan khac1.1.2. KI i¢m co’ ban va cu trac cua FPGA. FPGA (Field-programmable gate array) la vi mach ding cau trac mang phan tir logic ma nguoi ding 6 thé lap trinh duge. Chit field & diy muén chi dén kha nang tai lap trinh “bén ngoai” tuy theo muc dich img dung ciia ngudi sit dung, khong phy thude vao day chuyén san xudt phite tap cia nha may ban din. Kién tric tng quan vé FPGA due mé ta nh hinh 1 & Sy . 2 CMM —M« D -=| | iil so ic om m imc =! | I Kién trac tang quan FPGA Hinh 1: Kién trac tng quan cia FPGA‘Vi mach FPGA duoc céu thanh tir cdc b6 phan: * Cie khdi logic co ban Kip trinh duge (logic block) Phin tir chinh cia FPGA 1a cic khéi logic (logic block). Kh6i logic duge edu thanh tir LUT va m6t phan tir nhé ding bé Mip-flop. LUT (Look up table) la khdi logic c6 thé thyc hién bat ki him logic nao tir 4 dau vao, két qua cua ham nay tity vao muc dich ma giti ra ngoai khdi logic true tiép hay thong qua phan tur nhé flip-flop. Khéi logic duge m6 ta nhu hinh 2: Hinh 2: KhGi logic lap trinh duge cia FPGA ‘Trong tai ligu hung din cia céc dong FPGA ciia Xilinx edn sir dyng khai SLICE, | Slice gém 4 khdi logic tao thanh, s6 lurgng cac Slices thay d6i tir vai nghin dén vai chye nghin tity theo loai FPGA. * HG thong mach lién két lap trinh duge trong FPGA duge cau thanh tir cdc duong két ndi theo hai ic duong két ndi durge chia thinh cée nhém khée nhau, vi du trong XC4000 eiia Xilinx e6 3 loai kat Mang lign phuong ngang va dimg, ty theo timg loai FPGA, néi: ngdn, dai va rat dai, Cac dudng két ndi duge ndi voi nhau théng qua céc khdi chuyén mach lap trinh duge (programable switeh), trong m6 kl mach chira m6t so lugng nut chuyén lap trinh duge, dam bao cho cac dang lién chuyén kkét phite tap khac nhau. © Khdi vao/ra (10 Pads) Khdi vao/ra nhidu hay it 1 tuy thuéc vao timg loai FPGA. Ching cé thé durge két nd thr LED, USB, RS232, RAM....tuy’ theo muc dich sir dung voi cae thi bj ben ngo: * Cac phan tir tich hop sin Ngoii cée khdi logic, tity theo cdc loai FPGA khéc nhau ma e6 ede phan tir tich hop thém khae nhau, vi dy dé thiét ké nhimg tmg dung SoC, trong dong Virtex 4, 5 cia Xilinx 6 chita nhan xit ly PowerPC, hay cho nhing img dung xit ly tinhigu s6 trong FPGA dug thy hign ham A*B+C, vi du ding Virtex ciia Xilinx chita tir vai chue dén hang, tram DSP slices vai A, B, C 18-bit tich hgp céc DSP Slice la b6 nhan, céng tbc 46 cao, Cac tng dung cia FPGA Ung dung cia FPGA bao gom: xir ly tin higu s6, céc hé théng hang khéng, va tru, quéc phang, tién thiét ké mau ASIC(ASIC prototyping), cdc hé thong diéu khién truc quan, phan tich nhan dang anh, nhan dang tiéng néi, mat ma hoc, mé hinh phan cing may tinh, Do tinh linh d6ng cao trong qua trinh thiét ké cho phép FPGA giai quyét lép nhimg bai toan phite tap ma truéc kia chi thye hign nho phan mém may tinh, ngoai ra nha mat d6 céng logic lin FPGA duge img dung cho nhiing bai todn doi hoi khéi lugng tinh (oan lén va ding trong cae hé théng lam vige theo thoi gian thye. 1.2. TONG QUAN VE NGON NGU VHDL, ‘Thiét ké hay lap trinh cho FPGA duge thc hign chi yéu bang cdc ngén ngit mo ta phan cimg HDL nhu VHDL, Verilog ...cde hang san xuat FPGA Ion nhu Xilinx, Altera thuéng cung cap cac g6i phan mém va thiét bi phy tr cho qua trinh thiét ké, ciing cé mét sé cac hang thir ba cung cp cac géi phan mém kiéu nay nhu Synopsys, Synplify... Cae g6i phn mém nay c6 kha nang thuc hign tit ca quy trinh thiét ké IC chuan voi dau vao la ma thiét ké tren HDL (con goi la ma RTL). Trong bai Luan van nay, c6 sit dung ngén ngit mé ta phan cimg VHDL, do dé ta chi tap chung tim hiéu v8 ng6n ng VDL. 1.2.1, Giéi thigu vé ngén ngit mé ta phan cing VHDL. VHDL la ngén ngit mé ta phan cing cho cdc mach tich hgp téc dé rat cao, 1a mot Joai ngén ngi mé ta phin img duge phat trign ding cho trong trinh VHSIC( Very High Speed ltergrated Circuit) cia bo quée phong My. Mue VHDL 1a c6 durge mt ngén ngir m6 phong phan cimng tiéu chudn va théng nhat cho phép thir nghiém cdc hé théng sé nhanh hon cing nhu cho phép dé dang dua cic hé théng dé vao img dung trong thyc té, Ng6n ngit VHDL dugc ba céng ty Intermetics, IBM va Texas Instruments bat dau nghién ciru phat trién vao thang 7 nam 1983. Phién ban dau tién due céng bé vao thing 8-1985. Sau dé VHDL duoc dé xuat a8 16 chiteIEEE xem xét thanh mt tiéu chuan chung. Nam 1987 da dua ra tigu chudn vé VHDL(tigu chuan IEEE-1076-1987) VHDL duge phat trién dé giai quy va lap tai ligu cho cac hé théng cae khé khan trong vige phat trién, thay d6i Nhur ta da biét, mot hé théng s6 c6 rat nhigu tai ligu m6 1a, Dé c6 thé van hanh bao tri sira chita mGt hé thong ta can tim hiéu ky Luong tai ligu d6, V6i m6t ngén ngit mé phong phan cimg t6t vige xem xét cAc tai ligu mé ta tro nén dé dang hon vi bé tai ligu d6 06 thé durge thyc thi dé mé phong hoat déng cia thdng. Nhu thé ta co thé xem xét toan b@ cae phan tir ea hé théng hoat ing trong mét mé hinh théng nhat. Hi bat ky mot phuong phap thiét ké, mt b6 mé ta hay céng nghé phan cig néo. Ngwdi thiét ké c6 VHDL duge phat trign nhu mét ng6n ngir doc lip khéng gin thé ty do Iya chon céng nghé, phuong phap thiét ké trong khi chi sir dung mét ngén ngit duy nhat. Va khi dem so sénh véi cdc ngén ngit mé phong phan cimg khac 4a ra 6 trén ta thay VHDL ¢6 m@t s6 wu diém hon han cée ng6n ngit khée: ~ Thie nhét la tinh céng cong: VHDL duge phat trién dudi sw bao tro cia cl phi My va nay la mét tiéu chuan cia IEEE. VHDL durge su hé tro cia nhigu nha san xudt thiét bi cing nhu nhigu nha cung cdp céng cu thiét ké m6 phéng hé théng. = Thie hai la kha nang hd try nhiéu céng nghé va phuong phap thiét ké, VHDL cho phép thiét ké bang nhigu phuong phap, vi du phuong phap thiét ké tir trén. xudng, hay tir duéi lén dua vao cdc thu vién sin c6, VHDL ciing hé tro cho nhié loai cng ey xay dumg mach nhur sir dung céng nghé ding b6 hay khong dng 9, sir dung ma tran lap trinh duge hay sir dung mang ngdu nhié + Thit ba la tinh dc lép voi cong nghé: VHDL hoan toan dée lap véi cng nghé ché tao phan cing. m6 ta hé théng ding VHDL thiét ké 6 mite céng c6 thé dugc chuyén thanh céc ban téng hop mach khdc nhau tuy thudc céng nghé ché tao phan cimg mdi ra di nd cé thé duge 4p dung ngay cho cdc hé théng da thidt ké. = Thi te la kha nang mé ta mé rong: VHDL cho phép mé ta host dng ciia phan ctmg tir mire hé théng sé cho dén mire céng. VHDL c6 kha nang mé ta hoat d6ng cia hé théng trén nhiéu mire nhung chi str dung mét ca phap chat che théng nhat cho moi mirc. Nhu thé ta cé thé mé phong mét ban thiét ké bao gim cd cae hé con duge mé ta chi tiét~ Thie nam 1a kha nang trao déi két qua: Vi VHDL 1a mét tiéu chuan duge chap nhan, nén m6t mé hinh VHDL cé thé chay trén moi b6 mé ta dap img duge tiéu chuan VHDL. Cac két qua mé ta hé théng co thé duge trao déi gitta cac nha thiét ké sir dung céng cy thiét ké khée nhau nhung cing tuan theo tiéu chuan VHDL. Cang nhur m6t nhém thiét ké 06 thé trao dai mé ta mite cao cia cae hg théng con trong mét hé théng lin (trong d6 cac hé con dé duge thiét ké déc lap), - Thié séu la kha nang ké: VHDL duge phat trién nhu m6t ng6n ngit lap trinh bac cao, vi vay né 6 thé rg thigt ké mite lin va kha nang sir dung lai ede thidt dug sir dung dé thiét ké mt hé théng ln voi sy tham gia cia mét nhom nhi ngudi, Bén trong ngén ngit VHDL cé nhiéu tinh nang hd tra vige quan IY, thir nghiém va chia sé thiét ké. Va n6 cing cho phép ding lai cdc phan da cé sin, 1.2.2. Cau tric mt mé hinh hé théng mé ta bing ngon ng VHDL. Mue dich cia phan nay sé nham gidi thigu so qua vé cau tric khung co ban cia VHDL khi mé ta cho m6t mé hinh thiét ké thue. ‘Théng thuréng mét mé hinh VHDL bao gém ba phan: thu thé, kién tric va cic Ih, DGi khi ta xir dung cdc g6i (packages) vi. m6 hinh théng (testbench). ém tra hogt ding ciia hé + Thye thé (entity); Khai bao thyc thé trong VHDL 1a phan dinh nghia cae chi tigu phia ngoai cua mdi phan tr hay mét hé thong. Thye chat cua viée khai bao thye thé chinh li khai bao giao dign cua hé théng voi bén ngoai. Ta c6 thé c6 tit ca cde théng tin dé két néi mach vao mach khac hoae thiét ké tac nhdn dau vao phuc vu cho myc dich thir nghigm, Tuy nhién hoat dong that sw cia mach khéng nim 6 phan khai bio nay + Kién trac (Architecture): Phan thir 2 trong mé hinh VHDL la khai bao kién tric, Méi mét khai bao thye thé déu phai di kém voi it nhat m6t kién tric tong img. VHDL cho phép tao ra hon mét kién tric cho m6t thy thé. Phan khai bao kién tric c6 thé bao gom cac khai bao vé cac tin higu bén trong, cac phan tir bén trong hé thong, hay cdc ham va thii tue mé ta hoat dong eta hé théng. Tén ciia kién tric 1a nhan duge dat tuy theo ngudi sir dung. C6 hai cdch mé ta kién tric ctia mét phan tit ( hode hé thong) do la m6 hinh hoat dong (Behaviour) hay m6 ta theo m6 hinh cau tric (Structure). Tuy nhién mt hé théng c6 thé bao gom ca mé ta theo mé hinh hoat dong va mé ta theo mé hinh cau tric.+ Mé ta kién tric theo mé hinh hoat dong: M6 hinh hoat déng mé ta cc hoat dong cia hé théng ( hé théng dap img véi céc tin higu vio nhur thé nao va dura ra qua gi ra dau ra) dursi dang cac cau tric ngén ngit lap trinh bac cao. Cau tric 6 c6 thé la PROCESS, WAIT, IF, CASE, FOR-LOOP... + Mé ta kién tric theo m6 hinh c4u trite: M6 hinh cau tric cata mét phan tir (hoac hé théng) c6 thé bao gdm nhiéu cap cau tric bat dau tir m6t cong logic don gian dén xay dung mé ta cho m6t hé théng hoan thign, Thye chat ciia viée mé ta theo m6 hinh cau tric 1a mé ta cae phan tit con bén trong hé thong va sy két ndi clia cdc phan tir con dé. Nhu voi vi dy mé ta mé hinh cau tric mét flip-flop RS gém hai cng NAND cé thé mé ta cng NAND duge dinh nghia twong ty nhu vi du voi cong NOT, sau 46 mé ta so dd méc néi cdc phan tt NAND tao thanh trigo RS + CAu trac Process: Process la khdi co ban ciia viéc mé ta theo hoat dong. Process duge xét dén nhu la mét chudi cac hanh déng don trong sudt qué trinh dich. Cau trie tong quat: [ién nhan]: process I(danh stich cde yéu 6 [khai béo céc bien] begin Fede céu lenh] ich thich hoat déng)] end process; + MOi trudng kiém tra (testbench): M6t trong cdc nhigm vu rat quan trong 1a kiém tra ban mé ta thiét ké. Kiém tra m6t mé hinh VHDL duge thyc hign bang cach quan sat hoat dong ciia né trong khi mé phong va cae gid tri thu duge ¢6 thé dem so sdnh voi yéu cau thiét ké, iém M6i trdng kiém tra co thé higu nhu mét mach kiém tra ao. Méi trung tra sinh ra cdc tac déng lén ban thiét ké va cho phép quan sat ho&c so sénh két qua hoat dgng ciia ban mé ta thiét ké. Théng thudng thi cae ban mé ta déu cung cap chong trinh thir. Nhung ta cling c6 thé ty xay dimg chwong trinh thir (testbench), Mach thir thye chat la sy két hgp eta t6ng hop nhiéu thanh phan, N6é gm ba thanh phan: m6 hinh VHDL da qua kiém tra, nguén dit ligu va b6 quan sat, Hoat déng cia m6 hinh VHDL duge kich thich béi cac nguén dit ligu va kiém tra tinh ding dan théng qua bé quan sit.Chuong 2 BO LOC FIR 2.1, BO LOC FIR TRUYEN THONG B6 loc FIR la b6 loc ¢6 dp tmg xung chigu dai hitu han, tite La dép img xung ehi khac khdng trong mt khoang c6 chigu dai hit han N (tit 0 dén N-1), BO loc FIR véi bac cia bé loc La N duoc bigu dién nhw hinh 3 Hink 3: Cau wie cia b6 loc FIR truyén thong Trong d6: x(n}: 1a tin higu yin higu Idi ra ciia mach hn: 18 dap ting xung eiia mach vao cita mach la Léi ra y{n] va 16i vio x[n] lign hé véi nhau bai cng thite: yin) = Dalek] Dé tinh duge cac gia trj y{k] tir cdc mau Idi vao x[k] thi cdc mau lan luot qua céc 9 tr, b6 nhan va bG eGng. VO b6 Ipc FIR 6 bac la N thi phai sau N phép nhan va N- 1 phép cng thi moi tinh duge gid tri ciia 16i ra. Nhu vay, bé loc FIR c6 cau nhu trén 6 nhuge diém la kha nang dap ing cham, cée mau Ii ra khong duge lign tue ma sau mt khong thoi gian tinh toan xong cdc phép nhan va phép cng méi duge xuit ra. Dé hae phue nhuge diém dé, ta sit dung kién trie systolic array dé nang cao kha nang dap img cia mach2.2. BO LOC FIR SU DUNG KIEN TRUC SYSTOLIC ARRAY 2.2.1, Tong quan vé systolic array Systolic array 1 céu tric xir ly song song dae biét chira cde khéi xir ly dit ligu (data processing unit goi tit i DPU), cae khéi xir ly nay duge sap xép thanh mét mang. DPU twong ty nh CPU nhung né khéng cé b6 dém chuong trinh. Tig khéi DPU nhw la mét trigger truyén théng boi sur luan chuyén dit ligu tir DPU nay dén cdc DPU lan can. Théng thudng, nhimg dit ligu khae nhau thi sé luén chuyén theo cae hung khéc nhau. Cac luéng dit ligu t6i va roi khdi cde céng DPU duge phat tir ASM (Auto senquencing memory Ia thanh phan khéng thé thiéu cia cdu tric Non-Von- Neumann, Trong cau trie na co ché senquencing déng vai tro la bé dém chuong trinh). Mdi ASM dong vai tro 1a bG dém dit ligu. Trong hé théng nay, luéng dit ligu ‘vao cé thé vao tir dau ra ciia thiét bi ngoai vi va ngugc lai. (Cac b6 xi ly (DPU) tinh toan dit figu, lw tri dar Ligu theo nhiing ech de Lap véi mhau, Cée b6 xir ly nay c6 thé e6 mét vai thanh ghi va khéi ALU. Cée DPU 06 kha nang lun trit va xtr ly dit ligu déc lap véi nhau, Mi DPU sau khi xtt ly dit ligu xong se chia sé dit ligu cho cdc Cell lin en. ‘Trong hinh 4, mé ta kién tric Systolic array m@t chiéu, dit ligu chuyén déng theo ‘mt hurdng, PE PE PE PE PE Hinh 4: ‘u trate systolic array mét chiéu Hinh 5 mé ta kign tric s stolic array hai chiéu, dir ligu chuyén d6ng hai huéng theo chigu cia mai tén qua cde b6 DPU. Dit ligu ra eiing theo hai huéngep sent praia oi Be bbb Wee den orem oe Mi weet Hink 5: Kién tric systolic array hai chiéu. 2.2.2. BO Ige FIR thyc hign theo kién trac systolic array mot chiéu Dé cho vige xtr ly dir ligu duge nhanh hon, b6 loc FIR theo kién tnic Systolic array sé bao gim mét day cc phan tir xir ly hay con goi la PE (Process Element). Trong cing mét thii diém, cdc PE sé thye hign ding thoi cae nhigm vu riéng, va do 46, tin higu 6 Idi ra sé dugc dua ra mét cach lién tuc ma khéng phai mat mét khoang théi gian dé tinh toan do né da duge tinh tir trance a6. Céu trie ciia mét PE cia b6 loc FIR SYSTOLIC duge trinh bay nhu trong hinh 6 ie f}-y.0 Hink 6: Cau tric chia mt PE cdu tnic cia b6 Ine FIR Systolic véi bac bé ge la N, gm N+1 PE duge trinh bay nhu hinh 7Yin . eo 4 ; eo Hinh 7: Céu tric b6 loc FIR systolic bac N Khée véi b6 Ige FIR théng thurdng, dau ra cia bd céng lai duge dua qua 2 b6 cht dé lam tr8, n6 © téc dung chia duong truyén tin higu ctia mach thanh nhing doan nhé, do dé lam ting tan sé hoat déng cia mach, déng thoi Lam cho tin higu xin va yin vao bé eng cing mOt lic, do d6, tin higu ra sé durge lign tue, dap mg nhanh, boi vide tinh toan da duge thye hign trude 46, Voi vi chia during truyén dai nhat cia mach thinh nhing doan nhé nhé cdc thanh ghi chét, ta con cé thé t6i uu b6 loc FIR systolic hon nita. t6i uu cia b6 loc FIR systolic. | .o Yin 0" Kot | | 2 M6 hinh nay vé y tong van Hinh 8; Cau tric 16i wu cia bd Igc FIR systolic bac N jong mé hinh truée, bao gom cae thanh ghi chét, bd céng, b6 nhan cita mé hinh trude, tuy nhién, 6 su thay ddi vi tri cua ede thank ghi chét, true bé nhan va bd c6ng ta chén thém mét thanh ghi chét vio dé chia nhé duéng truyén tin higu. Do 46, lam cho tan sé hoat d6ng cia mach tang |én.Chuong 3 BQ LQC FIR THICH NGHI DUNG THUAT TOAN LMS 3.1, DAT VAN DE. Thudt ngd loc ding 48 chi tit ea ede hé thing e6 kha nang Khoi phue Iai dang eta ee thanh phan tin s6 eta tin hi 16i vio 48 tg0 ra tin higu I6i ra hoa man ee yeu cd mong mudn, Vi bé loc FIR trinh bay 6 trén, thi hé s6 ciia bé loc Iuén khdng déi. Do 46, néu c6 sy thay ddi dét ngét cia mOt hoac mét vai yéu t6 dau vao(nhu tin higu nhigu chang han) thi b6 loc sé khng con duge t6i wu nia, Hay ndi cdch khac, ta khéng thu dugc tin higu mong muén. Dé khae phuc nhuge diém trén, nguai ta dua ra mét b6 loc FIR c6 cau trac méi, ma trong dé, cde hé s6 cia b6 Ipc 66 thé thay déi duge dé cé thé thich img véi sw thay 10. Mach loc FIR c6 cac hé 6 thay doi nhu vay duge goi la mach loc FIR thich nghi. Gian dé khdi cita mach loc nhu vay duge trinh bay déi bat ngo cita cae yéu t6 16 trong hinh 9. Tin higu mong mudn din) h{n}=ho,hy, yn] eo Tin higu sai s6 e{n] Tin higu vao x(n] Hinh 9: Gian 48 khdi ciia mach loc thich nghi Trong so dé nay, tin higu Idi vao 1a m6t day théi gian rdi rac x[n], mach loc duge dic tung bi dap img xung h[n], cdn tin higu Idi ra 6 thei diém n La mGt day yn]. 16Léi ra nay durge sir dung dé xéc dinh mét dap img mong muén d{n]. Cac hé sé cia mach loc phai durge chon Iya sao cho day tin higu mong mudn e6 dang phi. hgp nhat véi tin higu y c6 thé duoc thy hign néu day tin higu sai s6 e{n] hi tu vé khéng nhanh nhat. Dé lam durge diéu nay, ta phai tdi ru hoa mét ham sai sé duge xde dinh theo phuong phap thong ké ho§e phuong phap quyét dinh. Doi vei phurong phép thang ké, thi ham sai s8 duge sir dung li gia tri ton phuong trung binh ctia tin higu sai sO e{n]. Néu tin higu vao va tin higu mong muén [a nhiing tin higu ditng, thi vi cyte tig hoa sai s6 toan phuong trung binh dua dén mt mach Ige rat ndi tiéng d6 1a mach loc Wiener, durge goi la ti wu theo nghia toan phurong trung binh. Hau hét céc thuat ton thich nghi la ap dung cho céc loai mach loc Wiener. Trong phuong phap quyét dinh, cach chon ham sai toan phwong. Viéc cyte tiéu hoa ham nay dan dén mét mach loc tdi wu déi voi day dit ligu da cho. Nhu vay, mach loc duge thiét ké hode bing cae céng thite théng ké hodc bing cae céng thite xac dinh. Trong cac thiét ké xde dinh, can phai tinh toan mét sé dai lugng trung binh khi str dung day dit ligu da cho ma mach loc cin xir ly. Noi cach khac, dé higu co sé. Trong trréng hgp nay, cac day tin hiéu co so thudng durge cho 1a tin hiéu thiét ké duoc mach loc Wiener can phai biét true cac tinh chat thong ké cia cdc tin dimg va trung binh theo thi gian bang trung binh théng ké. Mac di phép do tne tiép cac gid trj trung binh cia tin higu c6 thé duge thy hién 48 thu duoc nhimg théng tin can thiét cho vige thiét ké mach loc Wiener hoae céc mach loc tdi wu, nhung trong nhiéu tmg dung thy té, cae gia tri trang binh cua tin higu lai duge sir dung theo cach gian tiép, trong dé sai sd Idi ra cua mach loc tong quan miu cua tin higu vao cua mach loc theo mét sé cach va sir dung két qua cua phuong trinh dé quy dé diéu chinh cac clia mach theo kiéu lp. voi Sit dung phwong phap lap c6 thé dua dén céc Idi giai thich nghi e6 kha nang ue higu chinh. C6 nghia 1a néu cdc tinh chat thong ké cita tin higu thay d6i d6i véi thoi gian, thi nhé nghiém lap, cdc hé sé cita mach loc c6 thé tw digu chinh dé thich_nghi vi cdc tinh chit théng ké mdi. Nghiém lip, ndi chung rat duge wa chudng vi né dé ma hoa trong phan mém va 8 thy thi trong phan cig hon cae nghigm khong lip.3.2, CAU TRUC CUA MACH LOC THICH NGHI ie thurimg duge sit dung trong mach loe thich nghi duge mé ta nhur hinh 10) x(n] -N — sin] xfnN+1] wwefal wilt] welt] {n] - ‘Thuit toan thich nghi ela] G) + {a} Hink 10: Cau tric cia mach loc FIR thich nghi Trong dé: x[n] : Vector tin higu dau vao cua mach loc. x[n]= [xa Xn1 Xnae-- Xavi” w: La vector trong $6 ciia b6 Ige thich nghi w=[WoWs.Wyal yfn] : 1a 16i ra cia mach loc yin] = Dowteletn—k]w" x[n] GB.) d[n) : 1a Idi ra mong muén . en] : la sai sé gitta tin higu mong muén d{n] va tin higu du ra y{n] efn}-d{n]-yin) . 3.2) Bai toan thich nghi sé tw didu chinh ma tran cdc trong s6 w sao cho sai sé ef ‘ho nhat3.3. MACH LOC WIENER FIR Vi w'x{n] la mét v6 huéng nén bang chuyén vi cia n6, tite Lazw'x[n]=x"[n}w. Do dé, tit (3.1) va (3.2) ta 06: eln}d{n)-yh Déi véi mach lge Wiener, ham higu nang duge chon la sai sé toan phuong trung binh: |-d[n}-w'x[n]}=d[n}-x"[njw (3.3) J Elletn?] G4) Trong d6 ky higu E[.] la ky vong thong ké. Thay (3.3) vao (3.4) ta duge: J= E[(d{n]-w'x[n(d[n}-x"[n}w)] G5) Khai trign (3.5) va cha ¥ w 06 thé dura ra ngoai toan tir E[.] vind khong phai [a bign sé théng ké, ta thu duge: JFE(e[nJ}-w"E[x{n]d{n]]- Efd{n)x"[al}w + w'E[x{n)x" [aw G6) Ta dinh nghia vector tuong quan chéo bie Nx P= Efx(n]d{[n]] = [Po Py. Pui ‘ (3.7) Va ma trdn trong quan. 5 Roo Ror Ro Rows Ro Ru Re Rina R=E[x[n]x"[n]] = 8) Ryo Ryii Rvar RyanCho y la: Efd[n]x"[n]] = P*; w'P = P'w, ta thu duge: J=E[d’[n}) — 2w'P + w'RW. G.9) |, ta can phai ‘Dé thu duoc tap trong sé img voi ham phi tén J c6 gid giai hé phuong trinh durgc tao thanh tir dao ham bac nhat cua J déi voi mai tap trong sé w; bing khéng, tire la: 3.10) Cée phurong trinh trén e6 thé viet duréi dang ma tran: VJ=0 G11) 6 day V 1a toan ti vi phan duge xac dinh nhu mét vecto cot: au(0) } cult owt 12) ewlN 1), cdc dao ham riéng cita J déi v6i cdc tap trong sé w; cia mach loc, trurée DE hét phai khai trién hé thite (3.9) thanh dang tuéng minh: JS Ele? [n]]-2¥ Pleo] + Y wee bwtom)a[,m]—G.13) ‘Téng kép trong (3.13) c6 thé khai trién dudi dang: SS ce wimetk = SY dwt REE] tw, FWRI tw Yo wf] REK, mr) G.14) we RIkai] Thay (3.14) vao" (3.13), sau d6 lay deo him riéng phin eva J theo w, va thay thé m cho k ta duoc:a es aug PT MERAY RAT) v 12,...Ne1 G15) Trong truéng hop nay ta thay: = @,fi-k] (3.16) [x{n-k}x{n-i] 6 day @,,{i-4] la him ty trong quan cia x{n] Tuong ty -i] G.17) ding cia ham ty trong quan nén D,{k] =,,[-k], ta thu durge: Ru Ria G.18) ‘Thay (3.18) vao phurong trinh (3.15) ta duge: J _ yp, 4.2 ¥ ati kju{e], voi i= 0,1.2...N-1 G.19) uf] B Phuong trinh trén 06 thé biéu din duéi dang ma tr VI= 2Rw-2P (3.20) Dat VI=0 ta sé thu duge phuong trinh t6i wu hod tép trong sé ctia mach loc Wiener Rwo=P G.21) Day la phuong trinh Wiener-Hopf déi véi vetor trong sé t6i uu w,, Wo = RP G.22) Thay gid tri we vira tim duge tir phuong trinh Wiener-Hopf va Rw.=P vio phuong trinh (3.9) ta sé tim duge gia tri cue tiéu ctia ham phi tén J Jno = Efd?[n]] - wo" P =E{d’[nj] - w,"Rw, (3.23) Dé li sai sé cuc tiéu ma mach oe Wiener FIR W(z) c6 thé dat duge khi tip trong s6 cia né La nghigm cua phuong trinh Wiener-Hopf, nghia la nghiém t6i wu 6 (3.22)3.4, CAC THUAT TOAN THICH NGHI VA UNG DUNG Trong phan nay, chiing ta nghién ciru chai yéu thuat todn toan phuong trung binh, t6i thiéu LMS. Thuat todn nay duge ap dung rng rai trong xi ly sé thich nghi va théng ké do tinh chat bén viing va don gian ciia né. Nhé thuat toan nay ma day sai sé hGi tu vé khéng véi tS d6 nhanh, tuy theo bude giam cp. Vi vay, dyta trén thudt ton nay, ngudi ta da phat trign nhigu thuat toan nhanh 3.4.1, Phuong phap gidm bude nhanh nhat Day la phuong phap lap dé tim tap trong sé twong tng véi diém cure tigu ca mat sai sé cia mach loc Wiener FIR. Trong phuong phép nay, him phi tin cin cuc tiéu hoa duge gia thidt la phn ky va xudt phat tir mét dém bat ky trén mat sai s6, ta Ky moe bude nho theo hung ma trong 46 ham phi t6n giam nhanh nhat, Tai diém dé, ham phi tn ciia mach Ig Wiener sé ¢6 gid tri (61 uu. x(n} x{n-l walt} voted wi) 4 “© Thust ton thich nghi Minh 11: Mach loc Wiener FIR Déi v6i mach Ipc Wiener nhu hinh, day tin higu vao mach Ige la x{n] va day tin higu mong, mudn d[n] va tp trong s6 w; duge gia thiét la nhiing day sé thy. Khi dé, day Idi ra cia mach loc:yln] = w'x[n] = w x"[n] (4.1) Nhic lai rang khi him phi tén dat gid tri cuc tigu thi tap vector trong sé dat dén gid tri t6i wu, thoa man phuong trinh Wiener-Hopf: Rw=P (4.2) O day, thay cho viée giai phuong trinh mét cach truc tigp, ta giai bai todn bang cach tim mt phucmg phap lap. Theo phuong phap nay, xuat phat tir gid tri dy doan tude ddi voi wo, goi la w(0), nho tinh toén dé quy thye hign nhigu phép lap dé hGi w t6i we, Thudt todn lap nay nghi. thurng xuyén durge sir dung trong cdc mach loc Phuong php giam buce nhanh nhat duge thy hign theo céc buce sau: 1 Xuat phat tir cac théng sé du doan ban dau ma céc gia tri ti wu ca no tim durge dé eye tiéu hoa ham phi t6 2. ‘Tim gradient cua him phi t6n img voi cdc théng sé tai diém xuat phat 3. Cp mhat cdc théng sé bang céch lay mét buse theo hudng nguge véi vector gradient thu duge trong bude 2. Diéu d6 tong img véi burde gid nhanh nhat trong ham phi tén, Ngoai ra, kich thurée cia bude duge chon ti Ig vi kich thuéc cia vector gradient 4. Lap lai cde bute 2 va 3 cho dén khi khdng thé thay ddi duge nia trong cc théng sé Theo cac thi tye trén, néu w(k) la vector tap trong s6 tai phép lap thir k, thi phuong trinh truy héi sau day c6 thé durge sir dung dé cp nhat w(k): w(k+1) = w(k) = Wid a3) trong do: VJ = 2Rw(k)-2P (4.4) Théng s6 pt 1a dai long v6 huéng duong duge goi la kich thucde ctia bude. Day 1a théng sé rit quan trong vi téc 46 hGi ty cha w(k) 16i gid tri t6i wu w.phy thude vao théng sé nay, tite 1a vao kich thude etia bude da Iya chon. Néu kich thurée bude ln c6 thé su hi tu s® nhanh hon, nhung bit lai tinh én dinh s® kém honThay (4.4) vao (4.3) ta duge: w(k+1) = w(k) - 2u(Rw(k) ~ P) as) Dé c6 thé thay su cap nhat cdc gid tri w(k) cho héi tu téi w,, ta vidt lai (4.5) w(K #1) = We = (-2HR)Kw(k)-we) (46) Ta dinh nghia vector: v(k) = w(k) - Wo (47) Khi dé (4.6) tro thanh: v(k+1) = (-2uR)v(k) (48) Phuong trinh (4.8) sé e6 dang don gian hon nita néu ta dura ma tran trong quan R vé dang chéo. Nghia la ta dat: R=QKQ" (49) Va thay ma tran don vi I=QQ", khi dé (4.8) tro thanh: v(k+1) = (QQ - 2Q.Q"Wvik) = QC-2H2)Q" Vek) (4.10) Trong dé 4 Li ma tran chéo duge tao thanh tir cde gia tri riéng cua ma tran twong quan R, edn Q Li ma trin duge tgo thinh tir eée vector rigng true giao trong img Dat: vik) = "vi GAb Nhu vay ta thu duge phuong trinh truy héi déi véi vector v’(k) nhu sau: Vik+1) =(-2pv"(k) 4.12) phuong trinh vector (4.12) e6 thé tach thank cae phyong trinh v6 huéng : Vik+1) = (1-2p) WK) v6i iH0,1,....N-T (4.13) 6 day, v"\(k) 1a phn tr thé i etia vector v'(k) Néu bat dau tir day gid tri ban diu v0), v’1(0),...,v’v.(0) va sau k phép lap ching ta st thu durge: Vik) = 1-20) VGH i=0.1,....N-1 (4.14) Tur (4.7) va (4.11) ta thay rang w(k) hdi ty téi w, khi va chi khi v'(k) hi ty t6i wvector khéng. Nhung (4.14) lai cho thay ,(k) hi ty t6i khGng khi va chi khi thong sé bude u duge chon sao cho:[I-2pil <1, v6iiH0,1,....Nel (4.15) Khi (4.15) thoa man thi thanh phan thir i ca vector v’\(k) sé hdi ty nhanh khéng theo him e-mii khi sé lng phép lap tng Ién, Ngoai ra (4.15) ciing la diéu kign dé chon kich thuée ciia bude j1 sao cho thuat todn gidm cap nhanh nhat va Gn dinh. Dieu kign d6 c6 thé khai in durdi dang : -1<1-2)%<1 hay: ot t10 c= 1O0ar 3) voLL 1 -2) -9010 => +1110 aD 11008 oior o1o1 1110 ==> +0010 oe (-5) 1011 1o1t (2) 1110 => +0010 => 1101Lam y: véi vi du (+5)-(+2) =(3) va (-5)-(+2)=(-7) ta 06 thé bo qua bit thir 5. 4.2.3. Hign tung tran sé Néu ding n bit 4é biéu din sé c6 dau thi ta cé thé biéu dién cac sd trong khoang tir --2' dén 2"'— 1, Néu sau qué trinh thy hign phép todn(c6ng, trir, nhén) ma két qua thu duge khong nim trong dai trén thi ta ni e6 hign tong tran Ta xét cde vi du sau: GD o1it (-7) 1001 +42) +0010 +42) +0010 9 Loot os) 1o1r = 0 o=90 GD ot (7) +@2) +1110 + (2) (+5) 10101 9) and & Trong vi du trén, ta thay: (+7)+(+2) = (+9) va -7)+(-2) = (-9) c6 két qua bi tran do (+9) va (-9) khéng cé trong dai biéu di 6 dau 4 bit(tir -8 dén 7). Cae két qua con lai khéng tran do van nam trong dai biéu dign, Ngoai ra, c6 mét cach khie nhén biét duge két qua cd tran hay khong ma khéng can quan tam dén dai bigu dién do 1a: Overflow = cs xor cy Néu ding n bit dé Overflow4.2.4, Thy hign phép nhin trong s6 bit hai ‘True khi thao luan vé phép nhan hai s6 bi hai, ta can phai biét vé phép nhan véi luy thira eta 2 Gia sit B=b,.:by.2...biby. Khi d6: 2 x B= byibs, dO. Ta chi vige dich B sang trai 1 s6 rdi thém 1 sé 0 vao cudi. ‘Téng quat hon, néu ta thyc hign phép nhan: 2x B thi ta chi viée dich B sang trai k s6 roi thém k s6 0 vao cu Ta thay phép nhan cia sé cé dau vdi luy thira cua 2 gidng nhu cia sé khéng dau. Tuy nhién, voi phép chia thi lai khac han. Dé chia sé B cho 2, ta dich sé B sang phai k s6(tire 1a bo di k sé cudi). Sau do, ta thém vao true s6 B k bit dau(bit dau la bit c6 trong s6 cao nhat). Vidu: B= 011000 = (24): , B:2 = 001100 = (12),o, va B:4= 000110 =(6),0 Tuong tr voi s6 ém: B=101000=(-24),0 , B:2= 110100 =(-12)i0 Nhu vay, ta da biét cach thy hign phép nhan va chia cua s6 ba hai voi luy thuy cia 2. Bay gié ta thao luén xem cach nhan 2 sé bit hai duge thyc hign nhu thé nao. ‘Ta xét hai vi dy sau:(14) orto Gt) xOloll 0001110 + 001110 OO1o10L + 000000 ooorolo + 001110 oo1o0L! + 000000] (+154) 0010011010 (14) loo1o Gp XO10LL Ti10010 + 110010 “Trove _+ 000000 “Ti1orer 110010 1101100] 4000000] | 154) 1101100110 Tir 2 vidy trén, ta nit ra duge cach nhan 2 s6 bit hain bit A=a, jay... ajay Va Beb,:by2e-biby trong ty nhur trén, chisag’s THUC NGHIEM 45.1. MO TA PHAN CUNG CUA KIT VIRTEX-II PRO Phan cimg ciia kit Virtex-II Pro bao gam: © FPGA Spartan-II ding dé tao giao tiép PCI hoic USB © 2 LED trang thai hién thj 3 mau:cam, d6, vang © Giic cim cho mach nap JTAG * 2kénh ADC dc lap(ADC 14 bit) vai téc dé lay mau t6i da La 105Mhz © 2kénh DAC déc lap(DAC 14 bit) vei téc d6 bién déi t5i da La 160Mhz © 2ranh ZBT SRAM déc lap voi b6 nhé 512K x 32 * FPGA virtex-II XC2V80-4CS144 dé tao clock * FPGA virtex-II pro XC2VP30-4FF1152 li FPGA chinh cho ngutdi sit dung © C6 dutng két ndi véi clock ngoai © C6 thach anh 65Mhz trong mach ‘Tng thé vé kit virtex-II Pro duge mé ta nhur hinh 14: soci het mca . Hink 14: Toan bG mat trén ciia Kit virtex-II pro 5.2. KET QUA THU DUQC VGI BQ LOC FIR TRUYEN THONG Luu dé tién hanh thy hign b6 loc FIR truyén théng nhu hinh 15:Dao dong ky May ADC FPGA Dac phit Hinh 15: Luu a thie hién bé loc FIR truyén théng Sau khi qua bién d6i ADC, dif ligu durge biéu dién dui dang s6 bi hai sé duge dia vao FPGA dé xir ly. FPGA cé nhiém vu thu hign thuat toan gc theo yéu cau cha ngudi lap trinh, So dé thyte hign thuat toan déi v6i bé loc FIR duvge th bay nur trong hinh 3 cua chuong 2. Trong d6, loi vao x[n] cia b6 loc chinh a cac gia tri sau khi qua bign déi ADC, cac hé s6 h{n] la cae hang sé di duge cho truée(duge tinh toan bing Matlab) va y[n] la két qua sau khi da qua b6 loc FIR. Cac két qua nay cing duge biéu didn dui dang sé bit hai va durge dura qua bé bin déi DAC dé hign lén trén dao dong ky. Trong bai ludn van niy, em thiét ké b6 Ioe FIR théng t ma b6 loc bat dau suy giam va trigt tiéu la tir 800HZ mau 1a 20Khz. vai bie bé loc 1a 50, 1250Hz, tan 36K tan Cée hé sé h{n] sé duge tinh toan bang céng cy fatool trong Matlab. Dap ting tan 86 tinh toan bang Matlab duge mé ta nhu hinh 16; Frm Hinh 16: Dap img tan sé cia mach loc FIR Két qua thu duge khi thy hign trén chip FPGA: © Tin higu bat dau suy giam tai tan sé 700Mhz, duoc cho béi hinh 17:Hink 17: Tin higu bat dau suy giam ‘* Tin higu bj trigt tigu tai tin s6 1237Hz, duge cho boi hinh 18: Hink 18: Tin higu bi trigt tigu5.3. KET QUA THU DUQC VOI BO LOC FIR THEO KIEN TRUC SYSTOLIC V6i b6 loc FIR thyc hign theo kién tric systolic array, luu do va két qua dat duge cling tong ty nhur véi b9 Igc FIR thng thong, Tuy nhién, te 46 thy hign lai nhanh hon nhiéu. Véi céng cy “place and route tools” ctia phan mém ISE, cho ta két qua nhuw sau: © V6i bé loc FIR thuc hién theo kién tric systolic array, tin sé hoat déng lon nhat cia mach 1a 141.947 Mhz va sir dung hét 1775 © Voi bé loc FIR truyén théng, tan sé hoat déng ciia lon nhat cia mach La 19.857 slice Mhz va sir dung hét 417 slice. Nhu vay, ta co thé thay b6 loc FIR thurc hién theo kién tric systolic array c6 téc 46 dap img nhanh hon nhiéu so véi bé loc FIR thong thudng, tuy nhién, né lai tén nhiéu tai nguyén hon. Do dé, tuy theo timg img dung cu thé ma ta chon thiét ké theo phuong phap nao 5.4. KET QUA THU DUGC VOI BO LOC FIR THICH NGHI B6 loc FIR thich nghi c6 rat nhiéu tg dung nhu: Khir nhiéu, nhan dang hé théng chua biét, dy bao két qua vai hé thong co tin higu vao la ngau nhién... Trong bai luan van nay, em xin trinh bay vé img dung ciia bé loc FIR thich nghi 4é khir nhigu 50Hz-la nhiéu do ngué huang I6n dén cac thiét bi din tir. inh ra. Day la loai nhiéu pho bién va gay anh Luu 46 cho vige khit nhigu SOHZ duge mé ta nhu hinh 19: (neva) wo va etn) t rR output LMs Hink 19: Mé binh khir nhiéu 50 HzTrong 46: s(n) la tin higu mong muén v(n) 1a tin higu nhigu vi(n) la tin higu ciing dang véi v(n)(o6 thé khaée nhau vé bién dé va pha) v'(n) dau ra ciia bé loc FIR thich nghi (n) 1a tin higu sai s6, déng thai la Ioi ra Thuat toan LMS sé c6 nhigm vy diéu chinh cde hé s6 cita bé loc FIR sao cho 16i ra v'(n) c6 dang gan nhat voi tin higu nhiéu v(n). Khi dé, e(n)-d(n) - v'(n) sé dat dén tin higu mong muén s(n). Tite 1a ta da khir duge nhiéu. Kt qua thu duge khi tién hanh trén chip FPGA: Tin higu lin voi nhigu SOHz trude khi loc, durge cho boi hinh 20 Hink 20: Tin higu lan voi nhigu© Tin higu sau khi loc duge cho bai hinh 21 Hinh 21: Tin higu thu duge sau khi loc Tin higu thu duge sau khi qua b6 loc FIR thich nghi da loai bd durge nhigu SOHz. Tuy nhién, van khéng duge tron tru va co 6 map mé nho. So di nhu vay la do cic nguyén nin sau: * Do bé bién déi ADC Ia 14 bit, nén khi qua b6 loc FIR(bao gém cdc b6 nhan va b6 céng) thi dit ligu 1én t6i 28 bit, ma dau ra DAC chi hd trg 14 bit, vi vay, truéc khi dir ligu duge dua vao b6 loc FIR, ta phai chia dit ligu cho 27 dé dau ra DAC la 14 bit. Do dé, két qua co sai s6 nhat dinh * B6 bién déi DAC chi hé tro cdc sé nguyén, do dd, ta phai Lim tron cdc hé sé thanh sé nguyén, vi vay, két qua dat duge cing khéng duge nhu ly thuyét KET LUANTrong thai gian tién hanh hoan thién khod lun t6t nghigp, ngoai vige cling cé lai nhitng kién thite da duge hoc trong suét 4 nam qua, em con thu duge mét s6 kien thite va két qua nhat dinh: © Duge tim hidu va thyc hanh trén chip FPGA cia hang Xilinx © Biét sir dung thanh thao phan mém ISE © C6 thém nhigu kinh nghigm trong vige lap trinh v6i ngén ngtt VHDL © Thyc hign thanh cing b6 loc FIR théng thép irén FPGA theo kién tric truyén théng va theo kién tric systolic array. So sinh durge wu diém, huge diém eta timg loai ‘+ Thuc hign thanh edng bé loc FIR thich nghi ding thudt toan LMS én FPGA dé loai bo nhiéu 50 HzTAL LIEU THAM KHAO [1] Simon Haykin, Adaptive filter theory, Third edition [2] Uwe Meyer-Baese.Digital Signal Processing with Field Programmable Gate Arrays, Third Edition [3] John G.Proaskis Dimitris G.Manolakis. Digital Signal Processing, Third edition [4] Alexander D-Poularikas, Zayed M.Ramanda. Adaptive filtering primer with matlab, 2006. [5] Douglas L.Perry. VHDL: Programming by Example McGraw ~ Hill, Fourth Edition: [6]. Volnei A.Pedroni, Circuit Design With VHDL, MIT Press, 2004 [7] Jan Van der Spiegel. VHDL tutorial [8] Nguyén Kim Giao, KP thud dién ti sd, Nha xuat ban Dai hoc Quée gia Ha N6i, 2006. [9]. Téng Van On, Thiét ké mach sé véi VHDL va Verilog, Nha xuat ban lao déng xa hi, 2007. [10] Hd Van Sung. Xie bt sé tin higu da tc dg va dan loc, Nha xuat ban KH-KT, 2007 [11] hitp://en. wikipedia.org [12] http://www. xilinx.com [13] http://www fpgadfun.com