2.

Thit k mch gii m Mch m ha

2.1. Thit k mch gii m
2.1.1. Thit k mch gii m 2 ng sang 4 ng
Bc 1: V s khi ca mch

Bc 2: Lp bng trng thi

Bc 3: Vit chng trnh

module decoder (out,i);
(*LOC="A12,B11,D11,C11"*) output [3:0] out; (*LOC="J12,J11"*) input [1:0] i;
reg [3:0] out;
always @(i)
begin
if (i=='b00) out='b0001;
if (i=='b01) out='b0010;
if (i=='b10) out='b0100;
if (i=='b11) out='b1000;
end
endmodule
2.1.2. Thit k mch gii m 3 ng sang 8 ng vi ng ra tch cc mc 0, 1 ng vo cho php E
Bc 1: V s khi ca mch

Bc 2: Lp bng trng thi

 Bc 3: Vit chng trnh
module decoder (out,i,e);
(*LOC="B14,A14,B13,A13,A12,B11,D11,C11"*) output [7:0] out;
(*LOC="H16,J12,J11"*) input [2:0] i; (*LOC="H13"*) input e;
reg [7:0] out;
always
begin if(e) begin if (i=='b000) out='b11111110;
if (i=='b001) out='b11111101;
if (i=='b010) out='b11111011;
if (i=='b011) out='b11110111;
if (i=='b100) out='b11101111;
if (i=='b101) out='b11011111;
if (i=='b110) out='b10111111;
if (i=='b111) out='b01111111;
end
else out='b11111111;
end
endmodule
2.1.2. Thit k mch m ha t 4 ng sang 2 ng
Bc 1: V s khi ca mch

Bc 2: Lp bng trng thi

Bc 3: Vit chng trnh

 module encoder (out,i);
(*LOc="D11,C11"*) output [1:0] out; (*LOC="H13,H16,J12,J11"*) input [3:0] i;
reg [1:0] out;
always begin if (i=='b0001) out='b00;
if (i=='b0010) out='b01;
if (i=='b0100) out='b10;
if (i=='b1000) out='b11;
end
endmodule
2.2. Thit k mch a hp gii a hp
2.2.1. Thit k mch a hp 4 ng vo, 1 ng ra v 2 ng la chn
Bc 1: V s khi ca mch

Bc 2: Lp bng trng thi

Bc 3: Vit chng trnh

module mux4 (out,i,s);
(*LOc="C11"*) output out; (*LOC="H13,H16,J12,J11"*) input [3:0] i;
(*LOC="E14,G12"*) input [1:0] s;
reg out;
always begin if (s=='b00) out=i[0];
if (s=='b01) out=i[1];
if (s=='b10) out=i[2];
if (s=='b11) out=i[3];
end
endmodule
2.2.2. Thit k mch gii a hp 1 ng vo, 4 ng ra, 2 ng la chn

Bc 1: V s khi ca mch

Bc 2: Lp bng trng thi

 Bc 3: Vit chng trnh
module demux4 (out,i,s);
(*LOc="A12,B11,D11,C11"*) output [3:0] out;
(*LOC="J11"*) input i; (*LOC="H16,J12"*) input [1:0] s;
reg out;
always begin if (s=='b00) out[0]=i;
if (s=='b01) out[1]=i;
if (s=='b10) out[2]=i;
if (s=='b11) out[3]=i;
end
endmodule
Bi Tp
1. Thiet ke mach giai ma 2 ng sang 4 ng vi ngo ra tch cc mc thap va
co mot tn hieu cho phep E tch cc mc cao.
2. Thiet ke mach giai ma 2 ng sang 4 ng vi ngo ra tch cc mc thap va
co mot tn hieu cho phep E1 tch cc mc cao, va mot tn hieu cho phep E2 tch
cc mc thap.
3. Thiet ke mach giai ma ben trong co 4 mach giai ma 2 ng sang 4 ng vi
ngo ra tch cc mc thap.
4. Thiet ke mach giai ma 3 ng sang 8 ng vi ngo ra tch cc mc thap va
co mot tn hieu cho phep E1 tch cc mc cao, va mot tn hieu cho phep E2 tch
cc mc thap.
5. Thiet ke mach ma hoa 8 ng sang 3 ng vi cac ngo vao tch cc mc
thap.
6. Thiet ke mach ma hoa 8 ng sang 3 ng vi cac ngo vao tch cc mc
cao.
7. Thiet ke mach a hp 8 ngo vao, 1 ngo ra va 3 ngo la chon.
8. Thiet ke mach giai a hp 1 ngo vao, 8 ngo ra va 3 ngo la chon.
9. Thiet ke mach so sanh 2 so 4 bit A va B va co 3 led hien th LEDLH, LEDBA,
LEDNH. Neu A>B th LEDLH sang, neu A=B th LEDBA sang, neu A<B th LEDNH
sang.
10. Thiet ke mach chuyen oi so nh phan 8 bit thanh so BCD.
11. Thiet ke mach kiem tra chan le cua mot so nh phan 8 bit, neu la so chan
th en chan sang, neu la so le th en le sang.
12. Thiet ke mach kim tra mt s nh phn 8 bit nu s bit 1 nhiu hn 4 th n A sng, n
B tt, ngc li th n A tt, n B sng.
13. Thiet ke mach kim tra mt s nh phn 8 bit bit cc trng thi l s nh phn chn hay
l, ln hn 100, bng 100 hay nh hn 100.
3. Thit k cc loi flipflop
3.1. FlipFlop JK
Bc 1: V s khi ca mch

Bc 2: Lp bng trng thi

Bc 3: Vit chng trnh

Bc 1: V s khi ca mch

Bc 2: Lp bng trng thi

Bc 3: Vit chng trnh

Bc 1: V s khi ca mch

Bc 2: Lp bng trng thi

Bc 3: Vit chng trnh

Bc 1: V s khi ca mch

Bc 2: Lp bng trng thi

 Bc 3: Vit chng trnh

Bc 1: V s khi ca mch

Bc 2: Lp bng trng thi

Bc 3: Vit chng trnh

Bc 1: V s khi ca mch

Bc 2: Lp bng trng thi

Bc 3: Vit chng trnh

Bc 1: V s khi ca mch

Bc 2: Lp bng trng thi

Bc 3: Vit chng trnh

Bc 1: V s khi ca mch

Bc 2: Lp bng trng thi

Bc 3: Vit chng trnh

Bc 1: V s khi ca mch

Bc 2: Lp bng trng thi

Bc 3: Vit chng trnh

Mch m nh phn 8 bit m ln
module up_counter (out,enable,clk,reset);
(*LOC="B14,A14,B13,A13,A12,B11,D11,C11"*) output [7:0] out;
(*LOC="J11"*) input enable; (*LOC="B8"*) input clk; (*LOC="J12"*) input reset;
reg [7:0] out; reg [31:0] out1;
always @(posedge clk)
begin if (reset) out = 'b0 ;
else if (enable) out1 = out1 + 1; if(out1=='d10000000) begin out=out + 1; out1='d0; end
end
endmodule
Mch m nh phn 8 bit m ln/ m xung
module up_counter (out,enable,clk,reset,ud);
(*LOC="B14,A14,B13,A13,A12,B11,D11,C11"*) output [7:0] out;
(*LOC="J11"*) input enable; (*LOC="B8"*) input clk;
(*LOC="J12"*) input reset; (*LOC="h16"*) input ud;
reg [7:0] out; reg [31:0] out1;
always @(posedge clk)
begin
if (reset) out = 'b0 ;
else if (enable)
begin
if(ud) begin out1 = out1 + 1; if(out1=='d10000000) begin out=out + 1; out1='d0; end end
else begin out1 = out1 + 1; if(out1=='d10000000) begin out=out - 1; out1='d0; end end
end
end
endmodule
mch