GHI CH V TH VIN NGOI VI CA TIVA (DO TI CUNG CP)

I. V cc hm h thng
Mt s hm h thng s c dng h tr s vn hnh ca vi iu khin.
1. Hm SysCtlClockSet()
Hm ny dng cu hnh xung nhp cho vi iu khin Tiva (ch cho lp Blizzard), ch c mt i
s, l OR lun l ca mt s gi tr xc nh ngun xung c bn, tn s ng vo, c dng PLL
hay khng, v b chia tn s h thng. B chia tn s h thng c ci t bng mt trong cc
gi tr SYSCTL_SYSDIV_1 n SYSCTL_SYSDIV_64. Vic c dng PLL th hin qua mt trong
hai gi tr SYSCTL_USE_PLL v SYSCTL_USE_OSC. Tn s ng vo c th hin bi mt
trong cc gi tr sau SYSCTL_XTAL_4MHZ, SYSCTL_XTAL_4_09MHZ,
SYSCTL_XTAL_4_91MHZ, SYSCTL_XTAL_5MHZ, SYSCTL_XTAL_5_12MHZ,
SYSCTL_XTAL_6MHZ, SYSCTL_XTAL_6_14MHZ, SYSCTL_XTAL_7_37MHZ,
SYSCTL_XTAL_8MHZ, SYSCTL_XTAL_8_19MHZ, SYSCTL_XTAL_10MHZ,
SYSCTL_XTAL_12MHZ, SYSCTL_XTAL_12_2MHZ, SYSCTL_XTAL_13_5MHZ,
SYSCTL_XTAL_14_3MHZ, SYSCTL_XTAL_16MHZ, SYSCTL_XTAL_16_3MHZ,
SYSCTL_XTAL_18MHZ, SYSCTL_XTAL_20MHZ, SYSCTL_XTAL_24MHZ, v
SYSCTL_XTAL_25MHZ. Cc gi tr tn s nh hn 5 MHz khng c php s dng nu c
dng PLL.
Ngun dao ng c chn bng mt trong cc gi tr sau: SYSCTL_OSC_MAIN,
SYSCTL_OSC_INT, SYSCTL_OSC_INT4, SYSCTL_OSC_INT30, hoc SYSCTL_OSC_EXT32.
Gi tr SYSCTL_OSC_EXT32 ch c i vi cc vi iu khin c module ng ng, v ch khi
module ny c bt.
Cc b dao ng ni v dao ng chnh b cm bng cc c SYSCTL_INT_OSC_DIS v
SYSCTL_MAIN_OSC_DIS, mt cch tng ng. B dao ng ngoi phi c bt cho php
dng mt ngun xung nhp bn ngoi.
cp xung nhp t ngun ngoi (nh mt thch anh), dng SYSCTL_USE_OSC |
SYSCTL_OSC_MAIN. cp xung nhp t b dao ng chnh, dng SYSCTL_USE_OSC |
SYSCTL_OSC_MAIN. cp xung nhp t PLL, dng SYSCTL_USE_PLL |
SYSCTL_OSC_MAIN, v chn thch anh thch hp bng mt trong cc gi tr SYSCTL_XTAL_xxx
trn. V d cch dng hm:
SysCtlClockSet(SYSCTL_SYSDIV_10 | SYSCTL_USE_PLL | SYSCTL_XTAL_16MHZ |
SYSCTL_OSC_MAIN);

2. Hm SysCtlPeripheralEnable()
Hm ny c dng kch hot cc module ngoi vi khc nhau, v c khai bo trong tp tin
sysctl.h (ngi dng cn c dn hng #include sysctl.h trong tp tin ngun). V d cch dng
hm:
SysCtlPeripheralEnable(SYSCTL_PERIPH_ADC0);
SysCtlPeripheralEnable(SYSCTL_PERIPH_ADC1);
3. Hm SysCtlDelay()
Hm ny dng to ra mt khong tr nh. Hm nhn mt i s l mt s 32-bit, chnh l s ln
lp s c thc hin, vi mi vng lp tiu tn 3 chu k my. V d cch dng hm:
SysCtlDelay(100);

II. V th vin GPIO:

s dng th vin ngoi vi GPIO do TI cung cp, cn thm vo dn hng #include gpio.h
vo tp tin ngun (vi Energia th thc hin thm tp tin gpio.h vo sketch bng lnh menu ca
Energia).
Di y gii thch cng dng v c php s dng cc hm do th vin ny cung cp. Ch rng
ngoi vi phi c kch hot thng qua hm SysCtlPeripheralEnable(), nh c trnh by
trong mc I, v cc hm h thng.

1. Hm GPIOPinWrite()
Hm ny cho php cp nht trc tip mt s bit ca port GPIO trong khi khng lm nh hng
n cc bit khc, trong cng mt thao tc. Hm s dng mt c ch tng t nh bit-banding
nhng c th cp nht cng lc nhiu bit. Hm c 3 i s, vi i s th nht l a ch nn ca
port (theo nh dng GPIO_PORTx_BASE, vi x l k t A, B, C, xc nh port s thao tc), i
s th hai l mt mt n a ch 8-bit (ng vi cc bit 9:2 ca bus a ch), cho bit ch nhng bit
ng vi cc v tr bng 1 trong mt n mi b cp nht trng thi, v i s th ba l gi tr 8-bit s
c ghi ra port (ch rng ch nhng v tr ng vi gi tr 1 trong mt n mi b thay i trng
thi). V d cch dng hm:
GPIOPinWrite(GPIO_PORTA_BASE, GPIO_PIN_2|GPIO_PIN_3, 0x12);

2. Hm GPIOPinTypeGPIOOutput()
Hm ny dng ci t ch ng ra cho cc chn khc nhau ca port GPIO. Hm c 2 i s,
vi i s th nht l a ch nn ca port (theo nh dng GPIO_PORTx_BASE, vi x l k t A,
B, C, xc nh port s thao tc), v i s th hai l mt n a ch 8-bit (ng vi cc bit 9:2 ca
bus a ch), cho bit nhng chn ng vi cc v tr bng 1 trong mt n s c ci t l ng ra.
V d cch dng hm:
GPIOPinTypeGPIOOutput(GPIO_PORTA_BASE, GPIO_PIN_2|GPIO_PIN_3);

3. Hm GPIOPinTypeGPIOInput()
Hm ny dng ci t ch ng vo cho cc chn khc nhau ca port GPIO. Hm c 2 i
s, vi i s th nht l a ch nn ca port (theo nh dng GPIO_PORTx_BASE, vi x l k t
A, B, C, xc nh port s thao tc), v i s th hai l mt n a ch 8-bit (ng vi cc bit 9:2
ca bus a ch), cho bit nhng chn ng vi cc v tr bng 1 trong mt n s c ci t l
ng vo. V d cch dng hm:
GPIOPinTypeGPIOInput(GPIO_PORTA_BASE, GPIO_PIN_2|GPIO_PIN_3);
Ngoi ra, cn mt s hm khc trong th vin cng c th c dng khi c nhu cu. Chng hn,
cc hm GPIOIntDisable() v GPIOIntEnable() c dng cm hoc cho php to ngt t cc
chn GPIO. Cc hm ny u c hai i s, vi i s th nht l a ch nn ca module GPIO,
v i s th hai l mt n chn tn hiu ngt no s b cm hoc cho php (bao gm cc gi tr
GPIO_INT_PIN_0 n GPIO_INT_PIN_7, v GPIO_INT_DMA, c OR lun l vi nhau).

III. V th vin Timer:

s dng th vin ngoi vi Timer do TI cung cp, cn thm vo dn hng #include timer.h
vo tp tin ngun (vi Energia th thc hin thm tp tin timer.h vo sketch bng lnh menu ca
Energia).
Di y gii thch cng dng v c php s dng cc hm do th vin ny cung cp. Ch rng
ngoi vi phi c kch hot thng qua hm SysCtlPeripheralEnable(), nh c trnh by
trong mc I, v cc hm h thng.

1. Hm TimerConfigure()
Hm ny dng cu hnh cho cc timer (GPTM). Hm c 2 i s, vi i s th nht l a ch
nn ca timer (theo nh dng TIMERx_BASE hoc WTIMERx_BASE, vi x mang cc gi tr 0 n
5 xc nh timer s thao tc), v i s th hai l cu hnh mong mun, l mt trong cc gi tr
TIMER_CFG_ONE_SHOT, TIMER_CFG_ONE_SHOT_UP, TIMER_CFG_PERIODIC,
TIMER_CFG_PERIODIC_UP, TIMER_CFG_RTC, v TIMER_CFG_SPLIT_PAIR. Nu
TIMER_CFG_SPLIT_PAIR c dng th n phi c kt hp vi hai gi tr cu hnh cho timer
A v timer B, theo bng di y.
Gi tr i s ngha
TIMER_CFG_A_ONE_SHOT Timer A ch m xung 1 lt
TIMER_CFG_A_ONE_SHOT_UP Timer A ch m ln 1 lt
TIMER_CFG_A_PERIODIC Timer A m xung theo chu k
TIMER_CFG_A_PERIODIC_UP Timer A m ln theo chu k
TIMER_CFG_A_CAP_COUNT Timer A bt ng vo, v m khi c s kin
TIMER_CFG_A_CAP_TIME Timer A bt ng vo, v cht s m khi c s
kin
TIMER_CFG_A_PWM Timer A iu ch rng xung
TIMER_CFG_B_ONE_SHOT Timer B ch m xung 1 lt
TIMER_CFG_B_ONE_SHOT_UP Timer B ch m ln 1 lt
TIMER_CFG_B_PERIODIC Timer B m xung theo chu k
TIMER_CFG_B_PERIODIC_UP Timer B m ln theo chu k
TIMER_CFG_B_CAP_COUNT Timer B bt ng vo, v m khi c s kin
TIMER_CFG_B_CAP_TIME Timer B bt ng vo, v cht s m khi c s
kin
TIMER_CFG_B_PWM Timer B iu ch rng xung

V d cch dng hm:

TimerConfigure(Timer2_BASE, TIMER_CONFIG_PERIODIC);
TimerConfigure(Timer2_BASE, TIMER_CONFIG_SPLIT_PAIR ||
TIMER_CFG_A_CAP_TIME || TIMER_CFG_B_PWM);
2. Hm TimerLoadSet() v TimerLoadGet()
Hm ny dng ci gi tr np li cho timer, trong cc ch 16/32 bit ca TIMERx v ch 32
bit ca WTIMERx (x mang gi tr t 0 n 5). Hm c 3 i s, vi i s th nht l a ch nn
ca timer (theo nh dng TIMERx_BASE hoc WTIMERx_BASE, vi x mang cc gi tr 0 n 5
xc nh timer s thao tc), i s th hai l gi tr ch timer no s c np li (dng mt trong
ba gi tr TIMER_A, TIMER_B, hoc TIMER_BOTH), v i s th ba l gi tr np li s dng
(ch gi tr ny bng gi tr chu k tr i 1 n v). Hm TimerLoadGet() tr v gi tr np li ny
(l mt gi tr khng du 32-bit), do ch cn hai i s u. V d cch dng hm:
TimerLoadSet(Timer2_BASE, TIMER_A, 20000 - 1);
LoadTimer2A = TimerLoadGet(Timer2_BASE, TIMER_A);

3. Hm TimerIntEnable() v TimerIntDisable()
Hm ny dng bt tng ngun tn hiu ngt timer. Hm c 2 i s, vi i s th nht l a
ch nn ca timer (theo nh dng TIMERx_BASE hoc WTIMERx_BASE, vi x mang cc gi tr 0
n 5 xc nh timer s thao tc), v i s th hai l gi tr cho bit ngun tn hiu ngt s c
bt, l gi tr OR lun l ca cc gi tr trong bng di y. Hm ngc vi hm ny l hm
TimerIntDisable().
Gi tr i s ngha
TIMER_TIMB_DMA Ngt bo hiu DMA Timer B hon tt
TIMER_TIMA_DMA Ngt bo hiu DMA Timer A hon tt
TIMER_CAPB_EVENT Ngt bo hiu bt c s kin Timer B
TIMER_CAPB_MATCH Ngt bo hiu khp s m Timer B
TIMER_TIMB_TIMEOUT Ngt bo hiu Timer B m thi gian
TIMER_RTC_MATCH Ngt bo hiu khp s m RTC
TIMER_CAPA_EVENT Ngt bo hiu khp s m Timer B
TIMER_CAPA_MATCH Ngt bo hiu Timer B m thi gian
TIMER_TIMA_TIMEOUT Ngt bo hiu Timer A m thi gian

V d cch dng hm:

TimerIntEnable(Timer2_BASE, TIMER_CAPB_EVENT || TIMER_TIMA_TIMEOUT);
TimerIntDisable(Timer2_BASE, TIMER_TIMA_TIMEOUT);
Ch : c th x l ngt th cc hm IntEnable() v IntMasterEnable() cng cn c s dng
cho php to ngt timer v cho php ngt ton cc, mt cch tng ng. Hm
IntMasterEnable() th khng cn i s, cn hm IntEnable() nhn mt i s th hin ngt s
c bt (trong tng s vi chc ngt c h tr bi Tiva, c th hin trong tp tin
inc\hw_ints.h, ngay pha trn phn nh ngha tng s ngt c h tr). V d cch dng hm
IntEnable():
IntEnable(INT_TIMER0A);

4. Hm TimerEnable() v TimerDisable()
Hm ny bt mt timer c cu hnh. Hm c 2 i s, vi i s th nht l a ch nn ca
timer (theo nh dng TIMERx_BASE hoc WTIMERx_BASE, vi x mang cc gi tr 0 n 5 xc
nh timer s thao tc), v i s th hai xc nh timer c th s c bt (gi tr i s l mt
trong ba gi tr TIMER_A, TIMER_B, hoc TIMER_BOTH). Hm ngc li vi hm ny l
TimerDisable(), dng tt mt timer c bt trc . V d cch dng hm:
TimerEnable(TIMER0_BASE, TIMER_A);

5. Hm TimerIntClear()
Hm ny c dng trong chng trnh x l ngt xa c ngt, v nn c gi ngay khi vo
bt u x l ngt. Hm c 2 i s, vi i s th nht l a ch nn ca timer (theo nh dng
TIMERx_BASE hoc WTIMERx_BASE, vi x mang cc gi tr 0 n 5 xc nh timer s thao tc),
v i s th hai xc nh c ngt c th s c xa (dng cc gi tr nu trong bng mc
3, ni v hm TimerIntEnable() v TimerIntDisable() trn). V d cch dng hm:
TimerIntClear(Timer2_BASE, TIMER_CAPB_EVENT || TIMER_TIMA_TIMEOUT);

Vi CCS, tn ca cc trnh x l ngt c nh ngha trong tp tin ngun startup, do ngi

dng cn cp nht tp tin startup ny khai bo ng tn ca trnh x l ngt s c dng. Vi
Energia, ngi dng cng c th nh ngha tn ca trnh x l ngt bt k, v cn ng k hoc
hy ng k trnh x l ngt ny thng qua cc hm tng ng l TimerIntRegister() v
TimerIntUnregister(). Hm TimerIntRegister() c 3 i s, vi i s th nht l a ch nn ca
timer (theo nh dng TIMERx_BASE hoc WTIMERx_BASE, vi x mang cc gi tr 0 n 5 xc
nh timer s ng k ngt), v i s th hai xc nh timer c th s c ng k ngt (gi tr
i s l mt trong ba gi tr TIMER_A, TIMER_B, hoc TIMER_BOTH). i s th ba l con tr
n hm x l ngt tng ng. Khi thc thi hm TimerIntRegister(), hm IntEnable() s c t
ng gi i vi ngt va c ng k. Hm TimerIntUnregister() ch cn hai i s u tin
hy ng k trnh x l ngt. V d cch dng hm:
TimerIntRegister(TIMER0_BASE, TIMER_A, Timer0_Handler);
TimerIntUnregister(TIMER0_BASE, TIMER_A);

Ngoi ra, cn mt s hm khc lin quan n b nh thi 64-bit, kch hot s kin ADC hay DMA,
v mt s hm khc. Ngi dng nn tm hiu tp tin timer.h v timer.c trong th mc
driverlib ca chip c dng hiu r hn v cch dng v cch hin thc cc chc nng ny
trn vi iu khin Tiva.

IV. V th vin ADC:

s dng th vin ngoi vi ADC do TI cung cp, cn thm vo dn hng #include adc.h vo
tp tin ngun (vi Energia th thc hin thm tp tin adc.h vo sketch bng lnh menu ca
Energia). Module ADC cn phi c kch hot bng hm SysCtlPeripheralEnable(), nh c
trnh by trong mc I, v cc hm h thng.
Di y gii thch cng dng v c php s dng cc hm do th vin ny cung cp.
1. Hm ADCHardwareOversampleConfigure()
Hm ny c dng cu hnh b trung bnh cng phn cng. Cc gi tr ly mu s c t
ng tnh trung bnh cng trc khi ghi vo b m FIFO. Hm c hai i s, i s th nht l a
ch nn ca module ADC, v i s th hai th hin s gi tr mu s c ly trung bnh. i s
th nht c th l mt trong hai gi tr ADC0_BASE v ADC1_BASE. i s th hai c th l mt
trong cc gi tr 2, 4, 8, 16, 32, v 64. V d cch dng hm:
ADCHardwareOversampleConfigure(ADC0_BASE, 32);

2. Hm ADCSequenceConfigure()
Hm ny c dng cu hnh b lp chu trnh ly mu (sequencer). Tiva C c 4 b sequencer
i vi mi module ADC. Hm ny c 4 i s, vi i s th nht l a ch nn ca module ADC,
c th mang mt trong hai gi tr ADC0_BASE v ADC1_BASE. i s th hai l s hiu ca b
sequencer, l mt trong cc gi tr 0, 1, 2, v 3. i s th ba l ngun tn hiu kch hot thao tc
chuyn i A/D, c tm tt trong bng di y. Cn i s th t l mc u tin ca
sequencer, l mt trong cc gi tr 0, 1, 2, v 3 (0 l u tin cao nht v 3 l u tin thp nht).
Nu s dng nhiu sequencer th cn thit lp mi sequencer c mt mc u tin khc bit vi
cc sequencer cn li.
Gi tr i s ngha
ADC_TRIGGER_PROCESSOR B x l s to trigger, thng qua hm
ADCProcessorTrigger()
ADC_TRIGGER_COMP0 B so snh th nht s to trigger, cu hnh bng hm
ComparatorConfigure()
ADC_TRIGGER_COMP1 B so snh th hai s to trigger, cu hnh bng hm
ComparatorConfigure()
ADC_TRIGGER_COMP2 B so snh th ba s to trigger, cu hnh bng hm
ComparatorConfigure()
ADC_TRIGGER_EXTERNAL Tn hiu ni vo chn B4 s to trigger
ADC_TRIGGER_TIMER Mt b nh thi s to trigger, cu hnh bng hm
TimerControlTrigger()
ADC_TRIGGER_PWM0 B pht PWM th nht s to trigger, cu hnh bng
hm PWMGenIntTrigEnable()
ADC_TRIGGER_PWM1 B pht PWM th hai s to trigger, cu hnh bng
hm PWMGenIntTrigEnable()
ADC_TRIGGER_PWM2 B pht PWM th ba s to trigger, cu hnh bng hm
PWMGenIntTrigEnable()
ADC_TRIGGER_PWM3 B pht PWM th t s to trigger, cu hnh bng hm
PWMGenIntTrigEnable()
ADC_TRIGGER_ALWAYS Lun lun c tn hiu trigger (sequencer ly mu lin
tc, min l c mc u tin)

V d v cch dng hm ny:

ADCSequenceConfigure(ADC0_BASE, 1, ADC_TRIGGER_PROCESSOR, 0);

3. Hm ADCSequenceStepConfigure()
Hm ny c dng cu hnh cc bc ca chu trnh ly mu. C 4 b sequencer khc nhau,
v s bc trong mi b sequencer cng c th khc nhau. Sequencer s 0 c 8 bc, sequencer
s 1 v 2 c 4 bc, cn sequencer s 3 ch c 1 bc. Ngi dng cn m bo iu ny khi s
dng hm ADCSequenceStepConfigure(). Hm c 4 i s, vi i s th nht l a ch nn ca
module ADC, i s th hai l s hiu b sequencer (0 n 3), i s th ba l s hiu bc s
cu hnh (cn tng thch vi i s th hai), v i s th t l cu hnh ca bc, vi cc gi tr
c tm tt trong bng di y. i s th t c t hp bng php ton OR lun l ca mt
s trng khc nhau, do cn hiu r cc gi tr ca cng mt trng khng to ra cc cu
hnh xung t hoc dn n gi tr khng mong mun.
Gi tr i s ngha
ADC_CTL_TS Chn ngun tn hiu l cm bin nhit tch
hp trn vi iu khin
ADC_CTL_IE S to ra ngt khi chuyn i xong
ADC_CTL_END Cho bit y l bc cui cng ca chu trnh
ADC_CTL_D Chn kiu tn hiu vi sai thay v so vi GND
ADC_CTL_CH0 n ADC_CTL_CH23 Chn mt trong 24 chn AINx ca vi iu khin
lm ngun tn hiu
ADC_CTL_CMP0 n ADC_CTL_CMP7 C s dng mt trong 8 b so snh tng t

Khi s dng kiu tn hiu vi sai th cc cp chn AINx lin nhau s c s dng, chng hn AIN0
v AIN1 c dng cho knh 0 (ADC_CTL_CH0). Cn ch l nu s dng mt trong 8 b so
snh tng t th gi tr c ly mu s khng c ghi vo b m FIFO. Cc bc ca mt
sequencer phi c cu hnh cng nhau, vi bc cui cng c cu hnh khc vi cc bc
kia. V d cch dng hm ny:
ADCSequenceStepConfigure(ADC0_BASE, 1, 0, ADC_CTL_TS);
ADCSequenceStepConfigure(ADC0_BASE, 1, 1, ADC_CTL_TS);
ADCSequenceStepConfigure(ADC0_BASE, 1, 2, ADC_CTL_TS);
ADCSequenceStepConfigure(ADC0_BASE, 1, 3, ADC_CTL_TS|ADC_CTL_IE|ADC_CTL_END);

4. Hm ADCSequenceEnable()
Hm ny dng kch hot mt b sequencer no , vi i s th nht l a ch nn ca
module ADC, v i s th hai l s hiu ca b sequencer cn kch hot. V d cch dng hm
ny:
ADCSequenceEnable(ADC0_BASE, 1);

5. Hm ADCIntClear()
Hm ny dng xa c bo hiu ngt ca module ADC. Hm c i s th nht l a ch nn
ca module ADC, v i s th hai l s hiu ca b sequencer c c ngt cn c xa. V d
cch dng hm:
ADCIntClear(ADC0_BASE, 1);

6. Hm ADCProcessorTrigger()
Nu cu hnh b sequencer c khi chy (trigger) bng b x l, th hm ny s c dng
to tn hiu trigger cho module ADC. Hm ny c i s th nht l a ch nn ca module
ADC, v i s th hai l s hiu ca b sequencer s nhn tn hiu khi chy. V d cch dng
hm:
ADCProcessorTrigger(ADC0_BASE, 1);

7. Hm ADCIntStatus()
Hm ny c trng thi ngt ca module ADC, v tr v gi tr 32-bit th hin trng thi ca tt c
c ngt lin quan n module ADC. Hm c 3 i s, vi i s th nht l a ch nn ca
module ADC, i s th hai l s hiu ca b sequencer c quan tm, v i s th ba cho
php chn trng thi ngt th (i s l false) hay trng thi ngt che (i s l true). V d
cch dng hm:
ADCIntStatus(ADC0_BASE, 1, false)

8. Hm ADCSequenceDataGet()
Hm ny c dng ly d liu khi chuyn i xong. Hm c 3 i s, i s th nht l a
ch nn ca module ADC, i s th hai l s hiu ca b sequencer, v i s th nht l a ch
u ca mt mng cha ton b kt qu trong b m FIFO ca module ADC (ty vo b
sequencer m FIFO c di 1, 4, hoc 8 nh. V d cch dng hm:
ADCSequenceDataGet(ADC0_BASE, 1, ui32ADC0Value);

Nhn xt: Cc hm t 1 5 c dng trong giai on khi to cho module ADC, cn cc hm

cn li c dng trong vng lp thu thp v x l s liu. Tt nhin cn mt s hm khc trong
th vin cng c th c dng khi c nhu cu.
Chng hn, cc hm ADCIntDisable() v ADCIntEnable() c dng cm hoc cho php to
ngt ADC. Cc hm ny u c hai i s, vi i s th nht l a ch nn ca module ADC, v
i s th hai l s hiu ca b sequencer.
Cc hm ADCIntRegister() v ADCIntUnregister() c dng ng k hoc hy ng k
chng trnh x l ngt ADC. Trong , i s th nht l a ch nn ca module ADC, i s th
hai l s hiu ca b sequencer. Ring hm ADCIntRegister() c i s th ba l con tr n
chng trnh x l ngt.

9. Lu khi dng th vin ADC:

- Sequencer SS0 c v b li, khi chuyn i lin tc th ch c mt s gi tr chuyn i b li (b
m 64 gi tr ch c th dng 32 gi tr u v 16 gi tr cui). C kh nng do trnh dch GCC i
km vi CCS v6.1.
- Khi dng timer kch hot chuyn i A/D th hm TimerControlTrigger() ch c th c gi
sau khi bt timer.
- Hm ADCSequenceDataGet c v b li khi c gi t chng trnh x l ngt, nu s dng
GCC i km vi CCS v6.1. Tuy nhin, hm vn lm vic bnh thng trong chng trnh x l
ngt nu dng trnh dch TI i km vi CCS, hoc GCC i km vi Energia.

V. V th vin PWM:
s dng th vin ngoi vi PWM do TI cung cp, cn thm vo dn hng #include pwm.h
vo tp tin ngun (vi Energia th thc hin thm tp tin pwm.h vo sketch bng lnh menu ca
Energia). Module PWM cn phi c kch hot bng hm SysCtlPeripheralEnable(), nh
c trnh by trong mc I, v cc hm h thng.