Professional Documents
Culture Documents
Dr DC Hendry
October 2007
Outline I
3 Design Example
A X
A B X
0 0 Z
A X
A B X
0 0 Z
A X 0 1 0
A B X
0 0 Z
A X 0 1 0
1 0 Z
A B X
0 0 Z
A X 0 1 0
1 0 Z
1 1 1
B
Vx = min(VB Vt , VA )
Vx = min(VB Vt , VA )
Vx = min(VB Vt , VA )
Vdd
Vdd Vt
Vdd
Two-to-One Mux
S Z
B
S
Figure: Two-to-one Mux
Two-to-One Mux - 2
Two-to-One Mux - 2
Two-to-One Mux - 2
A B
When C = 1, A and B are connected, both logic zero and logic one
are passed without degradation.
Dr DC Hendry Pass Transistor Circuits
Pass Transistor Circuits
The CMOS Transmission Gate
Design Example
Transmission Gate Design Methodology
A B
A B
Design Example:
Design Example:
Design Example:
B
f
1
0
S1 S1 S2 S2
Figure: Implementation with Transmission Gates
1 Note the need for the term 0.S1 S2 . If not present then when
S1 = S2 = 1 the output f would float.
1 Note the need for the term 0.S1 S2 . If not present then when
S1 = S2 = 1 the output f would float.
2 Each transmission gate may now be replaced with two
transistors.
1 Note the need for the term 0.S1 S2 . If not present then when
S1 = S2 = 1 the output f would float.
2 Each transmission gate may now be replaced with two
transistors.
3 Where lines connect only to logic 1 the nMOS devices may be
omitted.
1 Note the need for the term 0.S1 S2 . If not present then when
S1 = S2 = 1 the output f would float.
2 Each transmission gate may now be replaced with two
transistors.
3 Where lines connect only to logic 1 the nMOS devices may be
omitted.
4 Where lines connect only to logic 0 the pMOS devices may be
omitted.
1 Note the need for the term 0.S1 S2 . If not present then when
S1 = S2 = 1 the output f would float.
2 Each transmission gate may now be replaced with two
transistors.
3 Where lines connect only to logic 1 the nMOS devices may be
omitted.
4 Where lines connect only to logic 0 the pMOS devices may be
omitted.
5 nMOS and pMOS devices may be grouped to minimise the
number of wells required.
Transistor Schematic
Vdd
S2 S2 S1 S1
Design Methodology
Design Methodology
Design Methodology
Viable Approaches
Viable Approaches
Viable Approaches
Plotting Variables
f = ab + bc d + acd
Plotting Variables
f = ab + bc d + acd
Plotting Variables
f = ab + bc d + acd
f ab
00 01 11 10
00 1 1 1 0
01 1 0 0 0
cd
11 1 0 1 1
10 1 0 0 0
Dr DC Hendry Pass Transistor Circuits
Pass Transistor Circuits
The CMOS Transmission Gate
Design Example
Transmission Gate Design Methodology
f ab
00 01 11 10
0
1
d d 0
c
1
1 0
d
d
f ab
00 01 11 10
0
1
d d 0
c
1
1 0
d
d