CHUONG 4 LAP TRINH FPGA VOI BANG PHAT TRIEN SPARTAN-3E 4.1. GIGI THIEU Trong chuong 2 bang phittrién Spartan-3E da duge gidi thigu. Trong chuong nay, chiing a s& hge céch sit dung né dé lap trinh FPGA. Cac bude lap trinh FPGA bao gdm: - Viét mét chong trinh nhé bing ng6n ngtt VHDL thyc hign mt mach logic t8 hop don gin. = Néi cde dau yao va dau ra cla chuong trinh véi cdc bé chuyén mach, cde mit (buttons) va ede dn LED trén bang Spartan-3B. = Tai chyong trinh vao bang Sparrtan-3E nhé sir dung phan mém Project Navigator. 4.1.1, Tinh ning thiét ké Tinh ning thiét ké thye hign duge tm tit rong bing 4.1. Bén LEDs trén bang sang phy thude vio céc 16 hyp khée nhau cia cde nit chuyén mach (SW0-3) va cdc niit bam (Push Buttons) trén bing (hinh 4.1). ‘ON/OFF Reset Button PO tis Ones a use Push Buttons i 41; Bhing phét ign Spartan-SE SO0K/1600K 4.1.2, Tailigu lién quan Trude khi bude vao thyc hanh lap trinh FPGA, can phai tai tai ligu huéng dan sir dung bang phat trién Spartan-3E FPGA Development board User Guide. Tai ligu nay mé ta ede chan tin higu (pins) cia chip FPGA va cac thiét lip can thiét dé néi cdc chan tin higu voi cae thiét bi vao/ra khée nhau trén bing,4.2. TRANG BI ‘Nhiing trang bi sau day can phai cé dé lim viée véi céng vide lap trinh FPGA: - Phan mém Xilinx ISE Project Navigator (cic phién ban 12.4 hodc cao hon), Phan mém nay c6 thé tai mién phi tir website, http:/Avww.xilinx,com/, Menu Design =a Summary Window . Workspace Processes Wicow Window Project Tabs Properties, Window Console Window Hinh 4,2; Cita sé khoi ding ban dau cha Project Navigator 12.4 - B6 KIT Spartan-3E bao gém: bang phat trién Spartan-3E (hinh 4.1), cap nguén, cép JTAG va cap USB dé néi voi PC. 43. THU TUC 4.3.1. Khéi dong (Startup) Click vao biéu tugng Xilinx ISE Design Suite 13.1 trén man hinh Desktop, hoic Khoi dong phan mém Project Navigator bang cach: Start->All programs->Xilinx ISE Design Suite 12.4->ISE Design Tools->Project Navigator ‘Xuat hién cita sé ISE Project Navigator 4.3.2. Trg gidp bé xung (Help) Nhu chi ra 6 hinh 4.3, trg gitip cd th8 duge truy nhap théng qua thye don Help trén Project Navigator. Tai phin mém, tai ligu va cdc hdi thao (forums) cd thé duge truy nhip & http://www.xilinx,com/supportCac vi du thiét ke sir dung bG KIT Spartan-3E 6 thé tai tir htip//www.xilinx,com/products/boards/s3estarterireference_designs.htm, inh 4.3: Thye don Help ‘ect he oe of apie source fre rot Hinh 4.4: New Project Wizard, Trang Create New Project 343.3. Tgo mot Project méi peers ‘Chon File->New Project. Sé xuit hién ctra sé New Project Wizard. G6 tutorial_1 trong trueng Name: Chon mét ving thich hp Location: va Working Diecreetory: cho project méi Xem xét Top-level source type: durgc chon nhw HDL. Cée thude tinh phai duge thiét lap nhw chi ra & hinh 4.4. Click Next dé chuyén téi trang Project Settings. Chon va dién vo trong cdc thuge tinh nhur sau: Property Name: Value Product Category: All Family: Spartan3E Device: XC3SS00E Package: FG320 Speed Grade: -4 Top-Level Source Type: HDL Synthesis Tool: XST (VHDL/Verilog) Simulator: ISIM (VHDL/Verilog) Preferred Language: VHDL Property Specification in Project File: Store All Values VHDL Source Analysis Standard: VHDL-93, Enable Message Filtering: unchecked. Hinh 4.5: New Project Wizard, trang Project Settings 47. Click next 48 chuyén dén trang Project Summary (hinh 4.6). Project Summary ‘rot gtr nna ann ott te erg once Srecerres tanguages ‘De, ‘inh 4.6; New Project Wizard, trang Project Summary 8. Click Finish dé rai khoi New Project Wizard tré vé cita sé ISE Project Navigator. 4.3.4, Bd xung ma ngudn VHDL méi ‘Trén ctta sé ISE Project Navigator (hinh 4.7): alaiaaly inh 4.7: Project New Source... 51, Chon Project-> mt click New Source -> sé xuat hign cira sé New Source Wizard 2. Trén cira sé New Source Wizard (hinh 4.8): Select Source Type: chon kiéu nguén: VHDL Module. Hinh 4.8: New Source Project: Select Source Type: VHDL Module 3. Dua vio tén file top_tevel, vi dua vio ving cia file (location: D:\Startan3E\tutorial_1). 4, Add to project box phai durge checked. Click Next dé chuyén dén cia sé New Source Wizard. Trén cita sé New Source Project: Define Module (hinh 4.9): Xac dinh cdc céng (inputs va outputs cla thiét ké) nhé dua vao théng tin cho Port name nhu sau: ooo a0 a oosecooo »| inh 4.9: New Source Project: Define Module 6© SWO0-3 [a cdc bit vao: IN, va sé két ndi véi cdc mit chuyén mach trén bang Spartan-3E. * PUSH_BUTTON [a dau vao: IN, gém 2 bit, va duge két ndi véi hai mit chuyén ‘mach trén Spartan-3E. Vi day li dau vao nhiéu bit, nén Bus check box duge checked, MSB (bit lén nhat) duot thiét lap bing ‘1’, va LSB (bit nhé nhit) duge thiét laajo bing ‘0°. * Cac dén LEDs la dau ra: OUT, gém 4 bit, va s& duge két ndi voi 4 LEDs trén Spartan-3E. Vi day la dau ra nhiéu bit, nén Bus check box durge checked, MSB duge thiét lip bing 3, va LSB duge thiét lap bing 0. 7. Click Next 48 chuyén dén trang Summary (hinh 4.10). ‘inh 4.10: New Source Project, Summary 8, Click Finish dé ra khoi New Source Wizard va tré vé Nhv chi ra 6 hinh 3.11, top_level s& xuat hign trong ctra sé Sources. Click hai lan trén top_level trong cia s6 Sources sé hién thi file, top_level.vhd trong tab.Source code for top_level.vhd appears in this tab ‘Minh 4.11; file ngudn méi top_evel.vhd bién th trong tab 4.3.5. Soan thio ma nguén VHDL . Trong mye 4.3.4, file nguén VHDL méi top_level.vhd di duge to ra. D6 thye chit 1a mt file van bin ASCII 64 thé duge soan théo béi mét céng cu soan thao vin ban. Tuy nhién, ‘thudn tign dé soan file ta sir dung phan mém Project Navigator. File top_level.vhd c6 n6i dung hue cho hinh 4.12, Seemeeas ee ree eererreeeee teenies sence = “inh 4.12: nGi dung file top_level.vhd duge hién th trong Project Navigator, rude ki sogn thio 8Trong hinh 4.12, 6 thé nhan thay ring cée mi VHDL déu cé mau dé cho dé doc. Cic dong binh luan (bat dau bang --) cé miu xanh li cay. CAc ti khéa cé mau xanh da tréi, cdc kiéu cla VHDL c6 mau do. MA trong hinh 4,12 chita ENTITY va ARCHITECTURE, ENTITY xdc dinh céc dau vao va diu ra cita khéi phan etmg. Cac chuyén mach SW0, SW1, SW2, SW3 [a cdc bit ciia dau vio cia kiéu STD_LOGIC. PUSHBUTTON la hai bit dai, va né thugc kiéu STD_LOGIC_VECTOR. Cée LEDs cia dau ra la 4 bit dai, va cing thuge kigu STD_LOGIC_VECTOR, Phin ARCHITECTURE chita ma ma phan cimg thc hign. Né 6 thé duge coi ring ban dau né 1a rng. Néu ma da duoc tai vio FPGA, thi né sé khéng Lim gi ca. Vi vay ta cdn phai bé xung md gitta cdc céu Iinh BEGIN va END trong khéi ARCHTECTURE. Cée thay di ma duge Jam nhur sau: 1, Dua vio ma duéi day gitta cic ciu Ignh BEGIN via END trong khéi ARCHITECTURE. Diéu nay thye hign tinh nang da ligt ké trong bang 4.1. WO or SW1; W2 or SW3; LEDs(2)<=(SWO0 or SW1) and (SW2 or SW3); LEDs(3)<=PUSH_BUTTON(0) or PUSH_BUTTON(1); 2. Lam file nhd File>Save tén the don chinh, Sau khi soan thao, file ngudn top_level.vhd sé xuat hign nhu chi ra 6 hinh 4.13. “inh 4.13: ni dung file top_level.vhd bin th rong Project Navigator sau khi soqn thio 4.3.6. Kiém traci php . Buse tiép theo [a kiém tra ci phap, dé kiém tra ma VHDL cé dua vao ding hay khéng. C6 cdc bude sau day tham chiéu dén man hinh cla Project Navigator cho & hinh 4.14,Click Implementation trén cita sé Design & géc trén bén trai ciia_cira sb Design 2. Xem xét Design tab da durge chon. 3. Click trén ‘+" next to Synthesize-XST. Diéu nay sé mé rng ra cdc khoan hién t] khac nhau, gim ca Check Syntax. Click Check Syntax dé chay kiém tra ct phay Néu cai phép ma khéng sai, s cé checked mau xanh lé cdy bén canh Check Syntax. inh 4.15; Green tick next cho kigm tra ei php (khong 6 Ii) 10Red cross next to Error created by inserting a space between Check Syntax “SW” and “0”. Error Hin 4.16: Vid, trong dé 15 2 xt higm du chéo dd & chd kiém tra 16 Messages 4.3.7. Gan chan tin higu ‘Xét lai ma VHDL cho thye thé top_level: ENTITY top_level IS PORT (SWO: in STD LOGIC; SWI: in STD_LOGIC; SW2: in STD LOGIC; SW3: in STD_LOGIC; PUSH BUTTON: in STD_LOGIC_VECTOR (1 downto 0); LEDs: out STD_LOGIC_VECTOR (3 downto 0)); END top_level; Ta muén néi cdc dau vao va cdc dau ra cla ENTITY top level véi cdc chuyén mach, cdc amit dn buttons va cdc LEDs trén bang Spartan-3E. Vi du, ta muén nhan cdc dau vao SWO, SW1, SW2, va SW3 tir 4 nit chuyén mach. Nhing dau vao nay néi véi cde chan tin higu L13, L14, HI8 vi N17 cia chip FPGA. Tuong tw, ta mudn nhgn cée diu vio PUSH_BUTTON(0) va PUSH_BUTTON(1) tir hai nit bam (Push Button) trén bang Spartan-3E. Trong trong hgp nay, ta sé sir dung cae Buttons bac va déng, ma chiing duge két noi véi céc chan (pins) V4 va H13 cia FPGA. Cudi cing, ta sé néi céc dau ra LEDs(0), LEDs(1), LEDs(2), va LEDs(3) v6i 4 din LEDs trén bing Spartan-3E. Trong trudng hop nay ta sé sir dung 4 dén LEDs bén phai twong img v6i cdc chan tin higu F12, E12, E11 va Fl, Déi v6i timg céng vao ya ra cla ENTITY top_level, bang 4.1 ligt ké tén cia thiét bj trén ‘bang Spartan-3E ma ta muén néi véi céng. cyBing 4.1: ch edng inpuvoutput eda ENTITY top_level Por name, ‘Sparlan-3E board device name | Description, 'Swo. 'Swo ‘Slider switch SWI SWI ‘Slider switch Sw? Sw? ‘Slider switch Sw3) Sw3 ‘Slider switch PUSH_BUTTON@) BIN Noni ‘Push button PUSH BUTTON() BIN East Push button LEDSO) Lo. LED. LEDs), LDL LED LEDs) Lb> LED LEDS) Lbs LED Cée bude sau diy duge sir dung dé néi cdc dau vao va dau ra véi cdc chuyén mach, buttons va LEDs trén bang Spartan-3} 1, Mét Clich vao ‘+? User Constrains. Sé hién thi mé réng ra cdc mye, ké ca 1/0 Pin Planning (PlanAhead) ~ Pre-Synthesis (hinh 4.17). User Constraints VO Pin Planning (PlanAhead) — | Pre-Synthesis Hinh 4.17; M@t khodn cia min hinh Project Navigator, v6i User Constraints duge mé rong, 2. Hai Click I/O Pin Planning (PlanAhead) ~ Pre-Synthesis. Cita s6 cia hinh 4.18 sé xuat hign, yéu cau OK dé tao UCF file. Click Yes. Tho pce gure he an retreat onsrort Fe UF) bene ‘teprgesins ced nen he eed Sey mesa Wess youse Proje Ngee strata) cre UF da te the pct hs ‘inet {yous "Ne you ined teen a ing UCF ote pnject toe nanagin proce Hinh 4.18: Hop hoi thosi yéu ccdy tao UCF file 123. Click Yes & hp héi thoai (hinh 4.18), cira so PlanAhead xuat hign (hinh 4,19). Click vio 1/0 Ports tab, vi sau dé vao float frame icon. Sé hién thi /O Ports trong mét cia s6 riéng (hinh 4.20). Save button 1/0 Ports tab Float Frame Icon wexerer ne -o8 3 Maca Eee remap tee Hinh 4.19: cia sé PlanAhead bién thi kin du Om Ot Oresregh Sete AATe um ovat ame paow Stam rom 2 2 Hinh 4.20; Hign thj cita sé VO Ports rigng 134, Click vaio ‘+ tip dén LEDs(4), PUSH_BUTTON(2) va Scalar ports & hinh 4,20, $8 hién thi tat ca cdc inputs/outputs rigng biét nhu chi ra 6 hinh 4.21. HEEL TLURERRE * Hinh 4.21: Hign tj cis 38 10 Ports mérrdng dén cée ong rigng 5. Dua vao céc ¢6t Site, /O Std, Drive Strength, Slew Type va Pull Type, bing cdc gi tr} da cho & bang 4,2. Céc e6t Bank va Ceco sé duge dign ty dong khi cac c6t Site ‘va I/O Std duge dién gid tri vio. Bing 4.2; Cie gid tr dé dua vio cira s6 1/0 Ports Port Site [VO Std_[ Drive Strength | Slew Type | Pull Type LEDs{O] FI2_[ LvTie [8 SLOW LEDs{I] E12 [LVTTL [8 ‘SLOW LEDs(2] EM [LVTTe [8 ‘SLOW LEDs(3] Fil {LVTt [8 ‘SLOW PUSH _BUTTON(O] | V4 [ LVTTL. PULLDOWN PUSH_BUTTON(!) [ H13_[ LVTTL PULLDOWN ‘wo 3 [LV PULLUP SWI Lis [LVI PULLUP ‘SW? His [ LTT. PULLUP SW3. NUTT EVIL PULLUP thi cita s6 1/0 Ports: visi cdc gid trj da durge 14 Hinh 4.22;6, Click Save trén_cita sé PlanAhead (vj tri ciia nit Save chi ra 6 hinh 4,19), (én file 1a top_level.ucf dé uu cdc chan tin higu da duge dua vio. Ctra sé PlanAhead cé thé duge déng Iai & trang nay. 4.3.8. Synthesize, Translate, Map, va Place & Route Giai doan tiép theo ta phai thye hign la cdc bude: tong hgp (Synthesize), chuyén déi (Translate), Sp xép (Map), va dit vi tri & tuyén (Place & Route). Cac buée nay duge thie hign nhés Project Navigator, va duge mé t4 ngin gon nhu sau: ‘Synthesize: tao cdc danh sach netlists cho timg file nguén. Translate: g6p nhiéu file vao m6t netlist, Map: thiét ké duge sip xép vio cdc manh va cdc khéi VO. Place & Route: thié ké duge dat vao chip va két ndi cdc thinh phan. Nhu chi ra & hinh 4.23, click vao ‘+’ dén Implement Design. S& mo réng dén Translate, Map va Place & Route 2 [Precast Jot Baovont oo o% Sonam tre Connt sag cna 'VO Pin Planning (PlanAnead) - Post Synth. Focrplan Area/TO/Logi Pianahead) Synthesize -XST Implement Design Hinh 4.23: mt khosin cia min hinh Project Navigator, véi mé ra Implement Design Hai Click vao Implement Design. Se giy ra Synthesize-XST chay lan dau, Sau dé, ‘Translate, Map va Place & Route sé chay lin lol. Khi mdi mot buée thye hién xong, mét dau kiém mau xanh ld cay sé xuat hign bén canh. Sau khi tat ca giai doan hoan thanh, man hinh Project Navigator sé xuat hién nhu cho 6 hinh 4.24. 15Create Timing Constraints VO Pin Pianning (PlanAhead) - Pre-Synth.. VO Pin Planning (PlanAhesd) - Post Synth. Floorplan Area/IO/Logic (Planhead) ‘Synthesize -XST ‘View RTL Schematic Hinh 4.24; mot khosn cia man inh Project Navigator, vi m6 ra Implement Design, sau d6 Translate, Map va Place & Router di chay thinh cong, 4.3.9. Tai thiét ké lén bang Spartan-3E starter Cac bude tigp theo [a tao file chuong trinh, va tai né vio bang Spartan-3E mho sir dung. iMPACT. 1, MGI Click vio ++’ 6 Configure Target Device (hinh 4.25), sé mé rng d&n Iya chon Manage Configuration Project (iMPACT). a & % Generate Programming File Configure Target Device - ‘Manage Configuration Project MPACT) Hinh 4.25; mét khodn cia man hinh Project Navigator, véi méra Implement Design 162, Hai Click vio Generate Programming File, Khi chay xong file ny, m@t diu kiém mau xanh la cay xuat hién bén canh Generate Programming File nhu chi ra 6 hinh 4.26. Hinh 4.27; cita sé ban dau cia iMPACT 73. Néi cép ngudn va cap USB véi bang Spartan-3E, Cim c4p USB tir bang Spartan-3E_ vio PC, va bat nguén cho bang Spartan-3E. 4, Clich hai lin In Manager Configuration Project ((MPACT). Cita sd iMPACT sé hién thi nh hinh 4,27, 5. Click hai Kin vao Boudary Scan nhu chi ra & hinh 4.28. Théng bao “Right click to Add Device or Initialize JTAG Chain” sé phai xuat hign phia bén phai man hinh, _— | ptm male mein ent = ed Jim ta oe comme Ome Day tee ty 7] jeujbeao += +0 = Soe a w= ‘Hinh 4.28; eta sé iMPACT, sau khi click hai lin lén Boundary Scan 6. Click chu6t phai lén “Right click to Add Device or Initialize JTAG Chain”, va chon Initialise Chain, nhw hién thi 6 hinh 4.29. 7. Sau mt lie, mt hinh anh eda “chain” s€ xudt hign, theo v6i m6t thong béo Identify Succeeded trong h6p mau blue (hinh 4.30). Chip dau tién, xc3s500¢, la chip FPGA ‘ma ta muén lép trinh. Hai chip khdc, xef40s va xe2e6da trén bing sé bd qua. Hop héi thoai yéu cau “Do you to continue and select configuration file (s)?” sé xuat hign nhu chi ra 6 hinh 4.30). 18Tee tat Wor Opetene Opa tay Winsor ap O88) O80 S27 +e enh noon toot San Sonera rou re Asai aie ak i 786 ae aaa ‘ttre ees Ed or aNertieesee Ck Hinh 4.29: cira so iMPACT, bicn thi chon Initialize Chain [prensa many le O@a) O25#0 >> Tp Ate ap Conpenen imeyaey 3 Conant cnet nd renter ia! (pero peatpcaicopriardl Cal Ce) inh 430: cia 38 iMPACT, gn cfc file céu hinh 8. Cir sé Assign New Configuration File sé xudt hign (hinh 4.31). chon file “top_level.bit”, va click Open. Digu nay lién két file top_level.bit v6i xe3s500e. 19etn: me ay Cott Woon Cae | be ‘inh 4.31; cia s6 iMPACT, gin file céu hinh cho xe3e5000 J Soe Dopornaness mnths Set OF PROnt ee ce! ———— ICs 2 re inh 432: cia s6 iMPACT. hp hi thsi yéu cfu c6 gin SPI hay BPI PROM hay khéng. 209, 10. 1 12. 13. 14. MOL thong bio “ This device support attached flash PROMs. Do you want to altach an SPI or BPI PROM this device?” sé xuat hién (hinh 4.32). Digu nay chua can cho thiét ké nay. Click No. Cir sb Assign New Configuration File sé xuit hign tré lai (hinh 4,33), Trong trang hop nay, Click Bypass. Ditu nay dim bio bé qua xef04s. Hinh 433: ota s6 IMPACT, b6 qua xef40s Cita sé Assign New Configuration File sé xuat hign lan nita (hinh 4,34), Lai Click Bypass. Didu nay dam bao bé qua xe2c64a, Cita sé Device Programming Properties - Device 1 Programming Properties s& xuat hign (hinh 4.35). Click OK. Cita sé IMPACT sé xuat hign nhu 6 hinh 4.36. Click yao chip xe3eS00e (hinh 4.37) va chon Program. Churong trinh bay gid’ sé duge tai vio bing Spartan-3E. Sau khi tai xong, mt théng bao sé xudt hign “Program Succeeded” (hinh 4.38). Ta c6 thé thye hign chay timg. thao te eta chyong trinh bing céch click vao timg Available Operations are: Program, Get Device ID, Get Device Signature/Usercode, Read Device Status, One 21Step SVF, One Step XSVF cia cita sé IMPACT Procceses. Mdi Operation thinh cong s& c6 thong bio thinh céng (Program Successfully, Readldcode Successfully). Hinh 4.34: cia s6 iMPACT, b6 qua xe2e64a ‘inh 4.35: cia s6 iMPACT. hop hoi thoai Device Programming Properties 22Tee tat Ven Opewtons Guan Ong _Wingon rip Ove) xcoxneae Hinh 4.38; eta sb IMPACT, sau khi tai tph cOng chuong tinh vio bing Spartan-3E4.3.9. Chay chong trinh trén bang Spartan-3E. __ Bang Spartan-3E starter kit sau khi tai chuong trinh chi ra 6 hinh 4.39. Hign thi trén LCD. 6 thé khée nhur chi ra 6 hinh nay trong qué trinh chay chwong trinh, Trén bing BTN_North BTN_East ‘sw3,sw2,swi,swo | | L03,L02,L01,L00 ‘inh 4.39: Bing Spartan-3E véi chuomg trinh dang chay Bay gi’ chuong trinh cé thé dugc kiém tra trén bang Spartan-3E starter kit. Néu chyong. trinh hoat déng 16t thi contact xoay (é gitta cde mit BTN) khong e6 téc dung. Voi cde nit chuyén mach SWO-3, vi tri bat Ién trén 1a vi tri bat (on). LED LDO phai sang khi hoc la SWO hoge SW1 6 ON. LED LD1 sé phai sing khi ho3c SW2 hode SW3 6 ON. Ca 3 LEDs: LD0. LD1 vi LD2 sé cing sing khi (SWO ho3e SW1) vi (SW2 hoe SW3) la ON. Cudi cing LED LD3 sé phai sing khi nit BTN_East hoac nit BTN_North duge an xudng (cdc nit nay ty nha). Doing a post-fit timing simulation in Xilinx ISE WebPACK This is a brief description on how to create a post-fit timing simulation using Xilinx ISE WebPACK (using screen shots from version 9.1i).. 24In contrast to simple behavioral simulations, the post-fit simulation takes into account the delays introduced by signal runtimes on the chip. It therefore requires that you choose the same chip variant (especially concerning timing) which you would like to use in your final design. Preparing the Simulation Input For the simulation, we first have to create the input "stimulus" waveforms to be sent into the programmable logic device. The simulator will read in these and compute the expected output lines (as well as any internal connections). Therefore, we need to add a new "test bench waveform" source to the project: I will call the file clock_test_bench: 25@ Elle Edit View Project Source Process Add Tools Od aa [Sx oaxloal IPS 2r3ly 2d ‘Sources for: [Synthesis/impleme =] F S]USBUNIProg ® [od ae Bh Add Source. ‘Add Copy of Source. Partition Eorce » Toggle Paths Broperties, O/ZODAIE © Select the entire branch | Fejimplementation Constraints File []User Document [¥) Verilog Module Elle name: [W\Veniog Test Fixture VHDL Module (QVHOL Library Location [P]VHOL Package a) VHDL Test Bench [ok jest bonen Fromeworgang/aonreniTsiindUSBUNPY see F Add to project More Info. = 26‘After this, keep pressing Next and finally click on Finish and you will see a dialog to set up the fundamental characteristics: Assign Check Assign Inputs Outputs Inputs Wait To Wait To Check | Assign - [Clock Information © Single Clock © Multiple Clocks © Combinatorial (or intemal clock) F-Combinatorial Timing Information Inputs are assigned, outputs are decoded then checked. A delay between inputs and outputs avoids ‘assignmentichecking conflicts, Check Outputs [6250 ps After inputs are Assigned Assign Inputs [6250 ps After Outputs are Checked [-Siobal Signals | iniat Length of Test Bench: [2000000] ps | F csr PGA) Time Scale: [ps =] High for inttat [700000 a i ro = For CPLDs without a main clock, use "Combinatorial (or internal clock)". The two times on the right are the most important: If you would like to be able to supply a clock signal with frequency ‘Jf, you have to choose the check outputs and assign inputs time 1/4). For example, choose 6.25ns (6250ps) for a 40MHz clock. To be precise, the sum of both times (check outputs plus assign inputs) defines the minimum time interval between changes in input lines, A clock line at frequeney f changes its state every 1/(2/) seconds, and keeping the “check” and "assign" times equally large results in 1/(4f). For additional granularity, you can make these times even smaller, of course, Note: When changing the time scale, be sure to keep the GSR timing so that is stays 100ns (unless you know what you are doing). 27‘Now you can create the desired simulation input by clicking on the eyan-colored bars in all input signal traces. Note: In order to see the waveform in the source file tree on the left, you have to choose Sources for: Post-Fit Simulation, Pitre ew re trrereeir ee etee it [Hi Eile Edit View Project Source Process Test Bench Simulation Window Help inter eee er Opaa[Sxoax VIZ Axx #[ Alas 8 0 Ol] F [low af at el | OC Oe Se IS #2} &S(2-8[NO/OABRS ALFA: PACA ed a Sources for [Post-Fit Simulation =I] aS 6 106 206 306 406 506 606 7 BJUSBUnIProg TT En En in 2h xo95"xI-** Mtxmein 0 ‘[E)elock_test_bench (clock tes] AN osc_in o ti (WaIbt (netgenvstimain_tmesie Hivos = 2 Bl aata_. 8.. (enzzX Bnh04 Viaat.. Oo Vaat. o Se Baat. °° eh 1|____] = Viaat.. Oo 21g Sourefeg Snapd i Libra] => Sym] Meat othe Baat. fee eee MN ITT Viaat. Oo a Add Existing Sou Vaat. o oa Create New Source /-[B] View Generated Test Bench [Add Test Bench To Project vo Xilinx ISE Simulator Bimainsch | [ij clock test benchibw home/wol fgang/elekt ronik/xilinx/ ProjectMgmt - "/home/wolfgang/elektronik/xilinx/USEUniProg/main.ngr" line 0 line 0 =f aywarn Bran Running Fuse « ‘Uni Prog/main. vmé g)Wamings J Tet shet J i Findin Files | [Sim Console - clock_test_bench 28Running the Simulation The simulation input is now set up. In order to perform the actual simulation, double Simulate Post-Fit Model in the Processes window. After a while (don't get impatient!!), you will see the simulation result: 29Fae Seo Bx @ oer ae xe Sources for [Post-Fit Simulation =| [USBUNIProg Ch xcosrxl-** =. [2}elock_test_bench (clock tes JUT - main (neigenvtivn [Wa (netgenstivmain_imesir [| __] fep Snap] Lor] TW clock _test_ bench - clock te: Bitag_ciock @Kdata_bus [7:0] Bout 2omriz @data_busSinout$reg (7:0 lose in Bern in « > TO i > 5 [1000 Pum CL roorao Giro Aion) EProcesses | [Ej Sim Hierarchy mainsch =Ifrs_=] [_Gijctock test_benchibw jew Project Source Process Test Bench Simulation Window Help PAX Salas 5 ool] F wlio w OA/BS A [i simulation Console | Errors j\ Wamings rat snen 1% Find in Files [Hj Sim Console - clock_test_bench Some notes: 30lick on Simulate Post- eps as required and When you change something in the source schematic and doubl. Fit Model, then ISE is clever enough to go through all the synthe re-do the simulation, It seems that if you change something in the input waveform, you have to re-run Simulate Post-Fit Model to get new simulation results. The most important buttons are the blue ones to the left of the 1000 ns input in the screen shot.