1.

Consider the unpipelined processor, assume that it has a 2ns clock cycle and that
it uses 4 cycles for ALU operations and branches and 5 cycles for memory
operations. Assume the the relative frequencies of these operations are 40%,20% and
40% respectively. Suppose that due to clock skew and setup, pipelining the
processor adds 0.2ns of overhead to the clock. Ignoring any latency impact, how
much speedup in the instruction execution rate will we gain from a pipeline?
a)3.5 times
=b)4 times
c) 4.4 times
d) 5 times

2.A pipeline has a speed up factor 8.5 and has efficiency 80% how many stages does
the pipe has?
=a)11 stages
b) 12 stages
c)13 stages
d)14 stages

3.A 4 stage pipeline takes 2ns,4 ns, 1ns, 6ns. while 8 stage pipeline takes
3ns/stage. Ignore the over head. which of the following statement is true for
executing 250 instructions.
=a)4-stage pipeline operates 76% efficiency of the 8 stage pipeline.
b)8-stage pipeline operates 79% efficiency of the 4 stage pipeline.c)4-stage
pipeline is twice faster than that of 6 stage pipeline.
d)4-stage pipeline is twice faster than that of 9 stage pipeline.