3

flip-flops ,
, ,
.

, :
Latch flip-flop
NAND NOR.

.
flip-flops.

flip-flops
flip-flops
.
flip-flop IEEE / ANSI.
flip-flops.

.

.
,
. 1

1
 3

.
.

flip-flop,
. , ,
,
,
.
flip-flops ( FF).
2a
flip-flop. , Q
. Q FF,
FF.
FF, Q

.

2
 3

(a) (b)

2a,2b FF .

FF
2b. 1
(set) .
1 FF set ( 1).
0
(clear) (reset).
FF 0 FF
.
2a FF 1
.

FF. FF
latch (bistable multivibrator)
.

Flip-Flop NAND

FFs
NAND NOR. NAND ,
latch NAND latch.
3(). NAND -
NAND-1
NAND-2, . ,
Q FF.
, .
FF: SET

3
 3

Q 1 RESET
Q 0. SET RESET
1,
0
0.
(SET,RESET) 1
FF
, Q 1
0 . Q
0 1 3a
1
0 1
1 0
. SET
0 Q 1
1
0
0 ( 4a).
1
Q 1 0 ( 4b).
RESET 0
( 5b) 1 Q
0 ( 5a).
Q 1 0
( 3b)
SET,RESET.

3a,3b 1

4
 3

4a,4b
SET.

5a,5b H
RESET.

SET,RESET 0
1
1
.
FF .
FF NAND
6a 6b .

5
 3

6a,6b. a. S-R FF b.

FF NAND
7a,7b NAND OR
.

7a,7b FF NAND .

8a,8b S-R FF
NAND.

8a S-R FF

6
 3

8b S-R FF
. (Debounce)

Flip-Flop NOR

S-R FF NOR
9a, 9b 9c.
NOR

Q
. FF
(active high)
( 9c)
0.

FF (SET,RESET) 1.

NAND .

9a,9b,9c a. FF. b. . c. FF

7
 3

S-R NOR

Q= = Q = .S+ .Q

S-R FF NOR 10

10. S-R FF NOR.

S-R FF
1 NAND 0 NOR

, ,
, . ,
FF
, FF
.

,
,
,
(set,reset) , ,
.

8
 3

,

.
,

.

.

, 10% 90%
HIGH , 10a.
(leading edge)
(trailing edge).
() ,
50% HIGH .
10b .

10a,10b a.s b.

9
 3

Flip-flops

. ,

.

.
,

(clock).
, 11.
,
( )
. (
) 11.
0 1,
(Positive Going Transition PGT)
1 0, (Negative Going
Transition NGT).
.
(
),
.

. ,

.
flip-flops (clocked flip-flops)
,
( ).

10
 3

11. a. b.

.
PGT PGT NGT
NGT.
( / ) () ,
11(b).
1
( / ),
(F) . Hertz.
hertz (1 Hz 1 ).

flip-flops

FFs
. FFs,

.
1. FFs
CLK, CK, CP. CLK,
12. FFs,
CLK ,

11
 3

CLK. FFs ,
.
12a CLK

(PGT)
. 12b CLK

(GT).
.

12a,12b. a, b. .

2. FFs
,
.
Q
. ,
CLK.
.
, FF 12a
Q
(PGT) . ,
12b
(NGT) .
3. ,
FF

12
 3

CLK. FF
CLK .

(Setup and hold times)

FF

CLK.
13 FF
(PGT).
,
CLK,

. ICs
(min)

CLK.
,
CLK,
. ICs

(min). , FF
.

13. a. b.

13
 3

, FF
,
()
(min) ,
(min) .
ICs FF
nanosecond. 5 50
ns, 0 10 ns.
50% .

, , ,
FFs
CLK.

FF S-R (Set-Reset)

14a SR flip-flop
. FFs

0 1. S R
FF FF
NOR , FF
( ) PGT .
14b FF
( ) PGT CLK
S R.
.
( ) CLK.
Q PGT.
ICs
(Data Sheets).
14c
SR flip-flop.

14
 3

,
:
1. 0 Q
0 .
2. PGT ( a), S
R , FF
Q=0 =0
3. PGT ( c),
S 1, R
0. , FF 1
( ).
4.
( e), S=0 R=1 FF
0.
5. 1
S=1 R=0 .
6. S=1 R=0
1
.
7. S=1 R=1
.

15
 3

14a,14b,14c a.. b. . c.
- .

0 1 ( )
.
15 FF .

.

16
 3

15. S-R FF .

S-R FF 16 .

16.

1. Nand FF 3 4
2. 1
2
3. . (edge
detector)

17
.
17a
17b .

17
 3

17a,17b. a. b. .

FFs J-K

18a JK flip-flop
( ). J K
FF S-R FF
Q
S-R FF
S-R FF
1. J-K 1

. toggle mode
Q = . ,

18a 18b.

18
 3

18a,18b. a. J-K FF , , b. -
clock.

19 J-K FF
,
.

19. J-K FF

- J-K FF
20

19
 3

20. - J-K FF NAND.

D FF.

21a
D flip-flop . SR JK flip-flops,
flip-flop D,
. D flip-flop : Q
D
() CLK. , D
flip-flop
PGT. 21b
.
Q 1.
PGT a, D 0
, Q 0. D
a b,
Q. Q 0 a.
PGT b, Q 1
D 1 .
1 Q
c Q 0,
D 0 . , Q
D

20
 3

PGTs d, e, f g.
Q 1, D
1.
, Q
.
D
PGT.
- D flip-flop
, Q
D NGT CLK.
- D flip-flop
CLK.

21a,b. - D flip-flop. a. . b.
, .

21
 3

D flip-flop J-K flip-flop

- D flip-flop
JK flip-flop,
22 D,
Q D
.
S-R flip-flop D flip-flop.

22. D FF J-K FF.

D FFs
.
23
flip-flops
flip-flops.
.

8 bits .

22
 3

23. 3 bits
- D FF.

D FF (Transparent Latch)

- D flip-flop
( ),
(latch) D FF
, D latch latch
transparent latch 24.
FF NAND,
NAND 1 2
.
( EN) ,
Q
- D filp-flop.

23
 3

24. D flip-flop Latch. a . b, c.

T FF.

FF J-K FF
J K 1.
CLK. To FF D FF
D .

FFs

flip-flops , S, R, J, K, D
.
FF
CLK. ,

FF. FFs

.
1 0
, .
,

24
 3

,
FF 0 1.
25 JK flip-flop
0,
FF.
FF.

25. J-K FF preset clear. .

IEEE/ANSI

26a IEEE / ANSI -

JK flip-flop .
CLK -
FF (NGT). IEEE / ANSI,

. ,
"C" . IEEE / ANSI
"C"
.
active-low, .
IEEE / ANSI "S" "R"
SET RESET,
PRESET CLEAR, . 26b
IEEE / ANSI IC 74LS TTL

25
 3

. 74LS112 -- JK
flip-flop Preset Clear.

26a,26b. a. - J-K FF b. J-K FF

IEEE/ANSI

27a,27b. a. - D FF b. D FF
IEEE/ANSI

26
 3

Flip-flops

flip-flops


.
IC flip-flop
TTL CMOS.

(Setup and hold times)

(Propagation Delays)

FF,

. 28

CLK. 50%
.

FF (PRESET CLEAR).

,
.

27
 3

28. FF

T IC flip-flops
100 ns.
,
Q. FF
.

CLK
FF .
FF FF, FFs (part
number) . , 7470 JK flip-flop IC
FFs
20-35 MHz. 20 MHz.
,

7470 FF 20 MHz

. 20
MHz, , .

28
 3

high low

CLK ,
, (L)

(H).
29a.
.

.

29a,29b. a. high low. b.

Preset Clear.

(Preset Clear)
FF.
29b (L)
.

FF,
( ) .

, FF .

FF. ' ,

29
 3

ICs .
, <= 50 nsec TTL
<=200ns CMOS .

TTL CMOS .

ICs

,

FF. , ICs:

1
FFs .
,
, . 1
.

30
 3

1. FFs
- FFs.
2. 74HC CMOS
TTL . 74C
74HC.

FF.

, FF
FF, FFs
.
. 30,
J
FFs CLK.

30.

FFs.
FF

31
 3

.
FF .

74LS74.

TTL.
D FFs, Preset Clear.

31a,b,c.

31a. FF 31b.

31c.

74LS76

J-K FF, master-slave, .

Preset Clear.
32a,b,c.

32
 3

32a FF 32b.

32c. .

FFs
,
2.

33
 3

2. FF.

3. FFs.

34
 3

:
. 5V.
. 2 20Hz.
. .
.
.
. .TTL 74LS00 1.
. 74LS74 1
. 74LS76 1
. 1 2
. Dip-Switch

1, S-R FF NAND.
.

35
 3

, S - R
Q.

S R Q
0 0
0 1
1 0
1 1

. .

2. D FF.

. .

36
 3

. D 0 1
CLK
TTL 1KHz.

D Q
0
1

. D FF FF
. CLK FF
TTL 1KHz. Q
.

37
 3

.
.

38
 3

3. J-K FF -

. J-K FF.
CLK TTL
1KHz. Q
.

.
.

39
 3

4. .

. 33b FF
33a. Q = 0 .
Q.

33a 33b

. Q Q=0.
Q FF 34a.

34a. 34b.

40
 3

. Q FF 35a EN D
35b.

35a. 35b

. 1 Q=0.
Q
1 CLK 7474 ;

41
 3

42