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VHDL Tieng Viet
VHDL Tieng Viet
Trang
Mc lc.................................................................................................................- 1 -
Danh mc hnh:...................................................................................................- 3 -
Danh mc bng:...................................................................................................- 5 -
Chng 1: Gii thiu...........................................................................................- 6 -
1.1. Gii thiu v VHDL.............................................................................- 6 -
1.2. Gii thiu cng ngh (v ng dng) thit k mch bng VHDL.....- 7 -
1.2.1 ng dng ca cng ngh thit k mch bng VHDL....................- 7 -
1.2.2 Quy trinh thit k mch bng VHDL.............................................- 7 -
1.2.3. Cng c EDA.................................................................................- 8 -
1.2.4. Chuyn m VHDL vo mch.........................................................- 9 -
Chng 2. Cu trc m.....................................................................................- 12 -
2.1. Cc n v VHDL c bn..................................................................- 12 -
2.2. Khai bo Library...............................................................................- 12 -
2.3. Entity ( thc th)................................................................................- 14 -
2.4. ARCHITECTURE ( cu trc)..........................................................- 14 -
2.5. Cc v d m u...............................................................................- 17 -
Chng 3: Kiu d liu.....................................................................................- 20 -
3.1. Cc kiu d liu tin nh ngha.......................................................- 20 -
3.2. Cc kiu d liu ngi dng nh ngha.........................................- 23 -
3.3. Cc kiu con (Subtypes)....................................................................- 23 -
3.4. Mng (Arrays)....................................................................................- 24 -
3.5. Mng cng ( Port Array)...................................................................- 27 -
3.6. Kiu bn ghi (Records)......................................................................- 28 -
3.7. Kiu d liu c du v khng du ( Signed and Unsigned)...........- 28 -
3.8. Chuyn i d liu.............................................................................- 29 -
3.9. Tm tt.....................................................................................................- 31 -
3.10. Cc v d................................................................................................- 31 -
Chng 4: Ton t v thuc tnh.....................................................................- 36 -
4.1. Ton t................................................................................................- 36 -
4.1.1 Ton t gn..................................................................................- 36 -
4.1.2 Ton t Logic...............................................................................- 36 -
4.1.3 Ton t ton hc..........................................................................- 36 -
4.1.4 Ton t so snh............................................................................- 37 -
4.1.5 Ton t dch.................................................................................- 37 -
4.2. Thuc tnh..........................................................................................- 37 -
4.1.1. Thuc tnh d liu........................................................................- 37 -
4.1.2. Thuc tnh tn hiu.......................................................................- 38 -
4.3. Thuc tnh c nh ngha bi ngi dng..................................- 38 -
4.4. Chng ton t.....................................................................................- 38 -
4.5. GENERIC...........................................................................................- 39 -
4.6. V d.........................................................................................................- 39 -
Chng 5: M song song...................................................................................- 44 -
5.1. Song song v tun t.........................................................................- 44 -
5.1.1. Mch t hp v mch dy............................................................- 44 -
5.1.2. M song song v m tun t........................................................- 44 -
5.2. S dng cc ton t...........................................................................- 45 -
5.3. Mnh WHEN.................................................................................- 46 -
0
5.4. GENERATE.......................................................................................- 52 -
5.5. BLOCK...............................................................................................- 53 -
5.5.1. Simple BLOCK............................................................................- 53 -
5.5.2. Guarded BLOCK.........................................................................- 54 -
Chng 6: M tun t.......................................................................................- 56 -
6.1. PROCESS...........................................................................................- 56 -
6.2. Signals v Variables...........................................................................- 57 -
6.3. IF..........................................................................................................- 57 -
6.4. WAIT...................................................................................................- 59 -
6.5. CASE...................................................................................................- 62 -
6.6. LOOP..................................................................................................- 66 -
6.7. Bad Clocking......................................................................................- 71 -
6.8. S dng m tun t thit k cc mch t hp...........................- 73 -
Chng 7: Signal v Variable...........................................................................- 76 -
7.1. CONSTANT........................................................................................- 76 -
7.2. SIGNAL..............................................................................................- 76 -
7.3. VARIABLE.........................................................................................- 78 -
7.4. S thanh ghi........................................................................................- 84 -
Chng 8: My trng thi................................................................................- 93 -
8.1. Gii thiu............................................................................................- 93 -
8.2. Thit k theo kiu 1 (thit k theo m hnh may moore)...............- 94 -
8.3. Thit k kiu 2..................................................................................- 100 -
8.4. Kiu m ho: t nh phn sang Onehot.........................................- 110 -
Chng 9: Thit k thm cc mch...............................................................- 112 -
9.1. Barrel Shifter....................................................................................- 112 -
9.2. B so snh khng du v c du.....................................................- 114 -
9.3. B cng Carry Ripple v b cng Carry Look Ahead.................- 116 -
9.4. B chia du chm tnh.....................................................................- 120 -
9.5. B iu khin my bn hng..........................................................- 123 -
9.6. B nhn d liu ni tip..................................................................- 126 -
9.7. B chuyn song song thnh ni tip...............................................- 128 -
9.8. Tr chi trn led 7 thanh................................................................- 129 -
9.9. B pht tn hiu................................................................................- 132 -
9.10. Thit k b nh............................................................................- 134 -
Ti liu tham kho:.........................................................................................- 140 -
Phn cng cng vic:.......................................................................................- 140 -
1
Danh mc hnh:
Trang
2
Hnh 6.4b.1. Kt qu m phng...............................................................- 61 -
Hnh 6.5a.1. Kt qu m phng...............................................................- 64 -
Hnh 6.5b.1. B m 2 ch s thp phn................................................- 64 -
Hnh 6.5b.2. Kt qu m phng...............................................................- 65 -
Hnh 6.6a.1. B cng c nh 8 bit khng du.........................................- 67 -
Hnh 6.6a.2. Kt qu m phng...............................................................- 67 -
Hnh 6.6b.1. B dich n gin.................................................................- 69 -
Hnh 6.6b.2. Kt qu m phng...............................................................- 69 -
Hnh 6.6c.1. Kt qu m phng...............................................................- 70 -
Hnh 6.7a.1. RAM....................................................................................- 72 -
Hnh 6.7a.2. Kt qu m phng...............................................................- 72 -
Hnh 6.8a.1. Mch t hp sai v cc bng tht.......................................- 74 -
Hnh 6.8a.2. Kt qu m phng...............................................................- 74 -
Hnh 7.2a.1. Kt qu m phng...............................................................- 77 -
Hnh 7.3a.1. Kt qu m phng...............................................................- 78 -
Hnh 7.3b.1. B dn knh 4-1..................................................................- 79 -
Hnh 7.3b.2. Kt qu m phng cch 1 v 2...........................................- 81 -
Hnh 7.3c.1. DFF.....................................................................................- 81 -
Hnh 7.3c.2. Kt qu m phng cch 1 v 2............................................- 83 -
Hnh 7.3d.1. B chia tn..........................................................................- 83 -
Hnh 7.3d.2. Kt qu m phng...............................................................- 83 -
Hnh 7.4a.1. Cc mch suy ra t m ca cch 1 v 2.............................- 85 -
Hnh 7.4a.2. Kt qu m phng cch 1 v 2...........................................- 85 -
Hnh 7.4b.1. B m 0 7.......................................................................- 87 -
Hnh 7.4b.2. Kt qu m phng cch 1 v 2...........................................- 88 -
Hnh 7.4c.1. Thanh ghi dch 4 cp..........................................................- 88 -
Hnh 7.4c.2. Kt qu m phng cch 1, 2, v 3.......................................- 90 -
Hnh 7.4d.1. Thanh ghi dch 4 bit............................................................- 90 -
Hnh 7.4d.2. Kt qu m phng...............................................................- 92 -
Hnh 8.1 S my trng thi................................................................- 93 -
Hnh 8.2. S trng thi ca b m BCD...........................................- 97 -
Hnh 8.3. Kt qu m phng ca b m BCD.......................................- 99 -
Hnh 8.4. My trng thi ca v d 8.2....................................................- 99 -
Hnh 8.5. Kt qu m phng cho v d 8.2............................................- 100 -
Hnh 8.6.1 S mch kiu 1 - Hnh 8.6.2. S mch kiu 2...........- 101 -
Hnh 8.7.Kt qu m phng cho v d 8.3.............................................- 103 -
Hnh 8.8. S trng thi ca b pht hin chui...............................- 104 -
Hnh 8.9.Kt qu m phng cho b on nhn xu..............................- 105 -
Hnh 8.10.a. S nguyn l hot ng ca TLC................................- 105 -
Hnh 8.10.b. hnh trng thi ca TLC.............................................- 106 -
Hnh 8.11.a. Kt qu m phng TLC ch hd bnh thng.............- 108 -
Hnh 8.11.b. Kt qu m phng TLC ch kim tra........................- 108 -
Hnh 8.12.Dng tn hiu cn to...........................................................- 108 -
Hnh 8.13.Kt qu m phng cho v d 8.6...........................................- 110 -
Hnh 9.1. B dch barrel........................................................................- 112 -
Hnh 9.2.Kt qu m phng cho b dch barrel....................................- 114 -
Hnh 9.3.M hnh ca b so snh........................................................- 114 -
Hnh 9.4. Kt qu m phng b so snh c du....................................- 115 -
Hnh 9.5.1.Kt qu b so snh khng du 1..........................................- 115 -
Hnh 9.5.2. Kt qu ca b so snh khng du2...................................- 116 -
3
Hnh 9.6. S b cng ripple carry....................................................- 117 -
Hnh 9.7. Kt qu m phng cho b cng ripple carry.........................- 117 -
Hnh 9.8.1. S b cng carry look ahead..........................................- 118 -
Hnh 9.8.2. Kt qu m phng cho b cng carry look ahead...............- 119 -
Hnh 9.9. Thut ton chia......................................................................- 120 -
Hnh 9.10.1. Kt qu m phng b chia................................................- 121 -
Hnh 9.10.2.Kt qu m phong b chia th 2........................................- 122 -
Hnh 9.11. hnh trng thi ca b iu khin my bn hng...........- 123 -
Hnh 9.12.Kt qu m phng b iu khin my bn hng...................- 126 -
Hnh 9.13. S b nhn d liu ni tip.............................................- 126 -
Hnh 9.14.Kt qu m phng b nhn d liu.......................................- 128 -
Hnh 9.15.B chuyn song song thnh ni tip.....................................- 128 -
Hnh 9.16.Kt qu m phng cho b chuyn song song thnh ni tip - 129 -
Hnh 9.17. S ca SSD.....................................................................- 130 -
Hnh 9.18. hnh trng thi...............................................................- 130 -
Hnh 9.19. Kt qu m phng cho tr chi trn SSD............................- 132 -
Hnh 9.20 Hnh dng sng cn pht......................................................- 132 -
Hnh 9.2.1. Kt qu m phng to sng................................................- 133 -
Hnh 9.22Kt qu m phng to sng theo phng php truyn thng- 134 -
Hnh 9.23.S ca ROM.....................................................................- 135 -
Hnh 9.24. Kt qu m phng thit k ROM.........................................- 135 -
Hnh 9.25. RAM vi ng d liu tch ri..........................................- 136 -
Hnh 9.26Kt qu m phng RAM c ng d liu vo ra khc nhau.- 137
-
Hnh 9.27. RAM vi ng d liu chung.............................................- 137 -
Danh mc bng:
Trang
4
Chng 1: Gii thiu
1.1. Gii thiu v VHDL
VHDL cho php thit k bng nhiu phng php v d phng php
thit k t trn xung, hay t di ln da vo cc th vin sn c. VHDL cng
h tr cho nhiu loi cng c xy dng mch nh s dng cng ngh ng b
hay khng ng b, s dng ma trn lp trnh c hay s dng mng ngu
nhin.
5
tng hp mch khc nhau tu thuc cng ngh ch to phn cng mi ra i n
c th c p dng ngay cho cc h thng thit k.
- Th t l kh nng m t m rng:
1.2. Gii thiu cng ngh (v ng dng) thit k mch bng VHDL.
6
Nh cp trn, mt trong s ln cc ng dng ca VHDL l ch to
cc mch hoc h thng trong thit b c th lp trnh c (PLD hoc FPGA)
hoc trong ASIC. Vic ch tao ra vi mch s c chia thnh 3 giai on nh
sau:
- Giai on 1:
- Giai on 3:
7
1.2.3. Cng c EDA.
8
Hnh 1.3. M thit k b cng
9
hnh (b) v hnh (c) ( ). Cn nu mc ch cng ngh l
ASIC, th chng ta c th s dng hnh (d). Hnh D s dng cng ngh CMOS
vi cc tng transistor v cc mt n ph.
Bt c mt ci mch no c tao ra t m, th nhng thao tc ca n s
lun lun c kim tra mc thit k, nh ta ch ra hnh 1. Tt nhin,
chng ta cng c th kim tra n tng vt l, nhng sau nhng thay i l
rt tai hi.
Hnh di y l m phng kt qu ca on chng trnh vit trn
cho mch b cng y hnh 1.3.
10
Chng 2. Cu trc m
Trong chng ny, chng ta m t cc phn c bn c cha c cc on
Code nh ca VHDL: cc khai bo LIBRARY, ENTITY v ARCHITECTURE.
LIBRARY library_name;
USE library_name.package_name.package_parts;
11
Hnh 2.2: Cc phn c bn ca mt Library
Cc khai bo nh sau:
LIBRARY ieee; -- Du chm phy (;) ch th
USE ieee.std_logic_1164.all;-- kt ca mt cu lnh
LIBRARY work;
USE work.all;
12
2.3. Entity ( thc th).
ENTITY entity_name IS
PORT (
port_name : signal_mode signal_type;
port_name : signal_mode signal_type;
...);
END entity_name;
13
Nh thy trn, mt cu trc c 2 phn: phn khai bo ( chc nng), ni
cc tn hiu v cc hng c khai bo, v phn m (code - t BEGIN tr
xung).
V d: Xt tr li cng NAND ca hnh 2.4
ARCHITECTURE myarch OF nand_gate IS
BEGIN
x <= a NAND b;
END myarch;
14
+ M t kin trc theo m hnh cu trc:
ENTITY rsff IS
PORT( r : IN std_logic;
s : IN std_logic;
q : OUT std_logic;
qb : OUT std_logic);
END rsff;
ARCHITECTURE kien_truc OF rsff IS
COMPONENT nand -- nh ngha cng nand
GENERIC(delay : time);
PORT(a : IN std_logic;
b : IN std_logic;
c : OUT std_logic);
END COMPONENT;
BEGIN
u1: nand -- ci t u1 l thnh phn nand
GENERIC MAP(5 ns) -- gi tr delay c th thay i
values
PORT MAP(s, qb, q); -- bn I/O cho thnh phn
u2: nand -- thit lp u2 l thnh phn nand
15
GENERIC MAP(5 ns)
PORT MAP(q, r, qb);
END kien_truc;
V d2:
Architecture arc_mach_cong of mach_cong is
Component Xor
Port( X,Y : in bit ; Z, T : out bit);
End component;
Component And
Port(L,M :input ;N,P : out bit );
End component;
Begin
G1 : Xor port map (A,B,Sum);
G2 : And port map (A, B, C);
End arc_mach_cong;
2.5. Cc v d m u.
16
Hnh 2.5.b. S ca DFF khng ng b
1 ---------------------------------------
2 LIBRARY ieee;
3 USE ieee.std_logic_1164.all;
4 ---------------------------------------
5 ENTITY dff IS
6 PORT ( d, clk, rst: IN STD_LOGIC;
7 q: OUT STD_LOGIC);
8 END dff;
9 ---------------------------------------
10 ARCHITECTURE behavior OF dff IS
11 BEGIN
12 PROCESS (rst, clk)
13 BEGIN
14 IF (rst='1') THEN
15 q <= '0';
16 ELSIF (clk'EVENT AND clk='1') THEN
17 q <= d;
18 END IF;
19 END PROCESS;
20 END behavior;
21 ---------------------------------------
17
Hnh 2.6 m phng kt qu t v d 2.1, th c th c gii thch d
dng. Ct u tin cho bit tn ca tn hiu, nh c inh ngha trong
ENTITY. N cng cho bit ch ( hng) ca tn hiu, lu rng cc mi tn
ng vi rst, d v clk hng vo trong, y l pha input, cn q hng ra ngoi
tng ng vi pha output. Ct th hai cha gi tr ca mi tn hiu v tr
tng ng vi ni con tr tr ti. Trong trng hp hin ti, con tr 0ns v
tn hiu nhn gi tr (1,0,0,0). Ct th 3 cho thy s m phng ca ton b qu
trnh. Cc tn hiu vo (rst, d, clk) c th c chn mt cch t do v b m
phng s xc nh tn hiu ng ra tng ng.
18
Chng 3: Kiu d liu
vit m VHDL mt cch hiu qu, tht cn thit bit rng cc kiu
d liu no c cho php, lm th no nh r v s dng chng. Trong
chng ny, tt c cc kiu d liu c bn s c m t.
Gi std_logic_signed v std_logic_unsigned
ca th vin ieee: Cha cc hm cho php hat ng vi d liu
STD_LOGIC_VECTOR c thc hin khi m kiu d liu l SIGNED
hc UNSIGNED.
+ STD_LOGIC ( v STD_LOGIC_VECTOR):
H logic 8 gi tr sau y c gii tiu trong chun IEEE 1164:
19
X khng xc nh ( bt buc)
0 mc thp ( bt buc)
1 mc cao ( bt buc)
Z tr khng cao
W khng xc nh (yu)
L mc thp ( yu)
H mc cao ( yu)
- khng quan tm
V d:
SIGNAL x: STD_LOGIC;
-- x c khai bo nh mt k t s ( v hng), tn hiu thuc
kiu STD_LOGIC
SIGNAL y: STD_LOGIC_VECTOR (3 DOWNTO 0) := "0001";
-- y c khai bo nh mt vector 4-bit, vi bit bn tri cng l
-- MSB. Gi tr khi u ca y l "0001". Lu
-- rng ton t ":=" c s dng thit lp gi tr khi u.
20
Character literals: k t ASCII n hoc mt chui cc k t nh th
SIGNED v UNSIGNED: cc kiu d liu c nh ngha trong gi
std_logic_arith ca th vin ieee. Chng c hnh thc ging nh
STD_LOGIC_VECTOR, nhng ngai tr cc ton t s hc, m tiu
biu l kiu d liu INTEGER
Cc v d:
x0 <= '0'; -- bit, std_logic, or std_ulogic value '0'
x1 <= "00011111"; -- bit_vector, std_logic_vector,
-- std_ulogic_vector, signed, or unsigned
x2 <= "0001_1111"; -- ng gch di cho php d hnh dung
hn
x3 <= "101111" -- biu din nh phn ca s thp phn 47
x4 <= B"101111" -- nh trn
x5 <= O"57" -- biu din bt phn ca s thp phn 47
x6 <= X"2F" -- biu din s thp lc phn ca s thp
phn 47
n <= 1200; -- s nguyn
m <= 1_200; -- s nguyn, cho php gch di
IF ready THEN... -- Logic, thc hin nu ready=TRUE
y <= 1.2E-5; -- real, not synthesizable
q <= d after 10 ns; -- physical, not synthesizable
21
3.2. Cc kiu d liu ngi dng nh ngha.
VHDL cng cho php ngi dng t nh ngha cc kiu d liu. Hai
loi kiu d liu ngi dng nh ngha c ch ra di y bao gm integer
v enumerated.
Kiu integer ngi dng nh ngha:
TYPE integer IS RANGE -2147483647 TO +2147483647;
-- Thc ra kiu ny c nh ngha trc bi kiu INTEGER.
TYPE natural IS RANGE 0 TO +2147483647;
-- Thc ra kiu ny c nh ngha trc bi kiu
NATURAL.
TYPE my_integer IS RANGE -32 TO 32;
-- Mt tp con cc s integer m ngi dng nh ngha.
TYPE student_grade IS RANGE 0 TO 100;
-- Mt tp con cc s nguyn hoc s t nhin ngi dng nh
ngha.
_ Cc kiu m ngi dng inh ngha:
TYPE bit IS ('0', '1');
-- c nh ngha trc bi kiu BIT
TYPE my_logic IS ('0', '1', 'Z');
-- Mt tp con ca std_logic m ngi dng nh ngha
TYPE bit_vector IS ARRAY (NATURAL RANGE <>) OF BIT;
-- c nh ngha trc bi BIT_VECTOR.
-- RANGE <> c s dng ch th rng cc mc.khng gii
hn.
-- NATURAL RANGE <>, on the other hand, indicates that the
only
-- restriction is that the range must fall within the NATURAL
-- range.
TYPE state IS (idle, forward, backward, stop);
-- Mt kiu d liu , in hnh ca cc my trng thi hu hn.
TYPE color IS (red, green, blue, white);
-- Kiu d liu lit k khc.
Vic m ha cc kiu lit k c thc hin mt cch tun t v t
ng.
V d: Cho kiu mu nh trn, m ha cn 2 bit ( c 4 trng thi),
bt u 00 c gn cho trng thi u tin ( red), 01 c gn cho trng
thi th hai (green), 10 k tip (blue) v cui cng l trng thi 11 (while).
22
php, chng ch c cho php trong trng hp gia mt kiu con v kiu c
s tng ng vi n.
V d: kiu d liu sau y nhn c cc kiu d liu c gii thiu
trong cc v d phn trc.
23
Hnh 3.1: Minh ha scalar (a), 1D (b), 1Dx1D (c), v 2D (d)
Nh c th thy, khng h c nh ngha trc mng 2D hoc 1Dx1D,
m khi cn thit, cn phi c ch nh bi ngi dng. lm nh vy, mt
kiu mi (new TYPE) cn phi c nh ngha u tin, sau l tn hiu mi
(new SIGNAL), new VARIABLE hc CONSTANT c th c khai bo s
dng kiu d liu . C php di y s c dng:
ch nh mt kiu mng mi:
TYPE type_name IS ARRAY (specification) OF data_type;
to s dng kiu mng mi:
SIGNAL signal_name: type_name [:= initial_value];
Trong c php trn, mt SIGNAL c khai bo. Tuy nhin n cng
c th l mt CONSTANT hoc mt VARIABLE. Gia tr khi to ty chn.
* V d mng 1Dx1D:
* V d mng 2D:
24
... :=('0','0','0','1') -- for 1D array
... :=(('0','1','1','1'), ('1','1','1','0')); -- for 1Dx1D or-- 2D array
25
w(1,5 DOWNTO 1)<=v(2)(4 DOWNTO 0);-- illegal (type mismatch)
------- Package:
-------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
----------------------------
PACKAGE my_data_types IS
CONSTANT b: INTEGER := 7;
26
TYPE vector_array IS ARRAY (NATURAL RANGE <>)
OF
STD_LOGIC_VECTOR(b DOWNTO 0);
END my_data_types;
----------------------------------------------
V d:
SIGNAL x: SIGNED (7 DOWNTO 0);
SIGNAL y: UNSIGNED (0 TO 3);
* V d:
Cc php ton hp l v khng hp l i vi kiu d liu
signed/unsigned:
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all; -- gi cn thit
thm vo
...
27
SIGNAL a: IN SIGNED (7 DOWNTO 0);
SIGNAL b: IN SIGNED (7 DOWNTO 0);
SIGNAL x: OUT SIGNED (7 DOWNTO 0);
...
v <= a + b; -- hp l (php ton s hc
OK)
w <= a AND b; -- khng hp l (php ton logic
khng OK)
LIBRARY ieee;
USE ieee.std_logic_1164.all; -- khng thm gi i
hi
...
SIGNAL a: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL b: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL x: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
...
v <= a + b; -- khng hp l (php
ton s hc khng OK)
w <= a AND b; -- hp l (php ton logic OK)
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all; -- bao gm gi thm
vo
...
SIGNAL a: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL b: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL x: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
...
v <= a + b; -- hp l (php ton s hc
OK), khng du
w <= a AND b; -- hp l (php ton logic OK).
VHDL khng cho php cc php ton trc tip ( s hc, logic, ) tc
ng ln cc d liu khc kiu nhau. Do , thng l rt cn thit i vi vic
chuyn i d liu t mt kiu ny sang mt kiu khc. iu ny c th c
thc hin trong hai cch c bn: hoc chng ta vit mt t code cho iu ,
hoc chng ta gi mt FUNCTION t mt gi c nh ngha trc m n
cho php thc hin cc php bin i cho ta.
Nu d liu c quan h ng ( ngha l 2 ton hng c cng kiu c
s, bt chp ang c khai bo thuc v hai kiu lp khc nhau), th
std_logic_1164 ca th vin ieee cung cp cc hm chuyn i d thc hin.
28
TYPE long IS INTEGER RANGE -100 TO 100;
TYPE short IS INTEGER RANGE -10 TO 10;
SIGNAL x : short;
SIGNAL y : long;
...
y <= 2*x + 5; -- li, khng ph hp kiu
y <= long(2*x + 5); -- OK, kt qu c chuyn i
thnh kiu long
* V d: chuyn i d liu:
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
...
SIGNAL a: IN UNSIGNED (7 DOWNTO 0);
SIGNAL b: IN UNSIGNED (7 DOWNTO 0);
SIGNAL y: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
...
y <= CONV_STD_LOGIC_VECTOR ((a+b), 8);
-- Php ton hp l: a+b c chuyn i t UNSIGNED
thnh mt
-- gi tr 8-bit STD_LOGIC_VECTOR, sau gn cho y.
29
3.9. Tm tt.
3.10. Cc v d.
30
y(0) <= x(0); -- same types (STD_LOGIC), correct indexing
z(7) <= x(5); -- same types (STD_LOGIC), correct indexing
b <= v(3); -- same types (BIT), correct indexing
w1(0,0) <= x(3); -- same types (STD_LOGIC), correct indexing
Table 3.2
Synthesizable data types.
Data types Synthesizable values
BIT, BIT_VECTOR 0, 1
STD_LOGIC, STD_LOGIC_VECTOR X, 0, 1, Z (resolved)
STD_ULOGIC, STD_ULOGIC_VECTOR X, 0, 1, Z (unresolved)
BOOLEAN True, False
NATURAL From 0 to 2, 147, 483, 647
INTEGER From _2,147,483,647 to 2,147,483,647
SIGNED From _2,147,483,647 to 2,147,483,647
UNSIGNED From 0 to 2,147,483,647
User-defined integer type Subset of INTEGER
User-defined enumerated type Collection enumerated by user
SUBTYPE Subset of any type (pre- or user-defined)
ARRAY Single-type collection of any type above
RECORD Multiple-type collection of any types above
Data Types 39
TLFeBOOK
w1(2,5) <= y(7); -- same types (STD_LOGIC), correct indexing
w2(0)(0) <= x(2); -- same types (STD_LOGIC), correct indexing
w2(2)(5) <= y(7); -- same types (STD_LOGIC), correct indexing
w1(2,5) <= w2(3)(7); -- same types (STD_LOGIC), correct indexing
------- Illegal scalar assignments: --------------------
b <= a; -- type mismatch (BIT x STD_LOGIC)
w1(0)(2) <= x(2); -- index of w1 must be 2D
w2(2,0) <= a; -- index of w2 must be 1Dx1D
------- Legal vector assignments: ----------------------
x <= "11111110";
y <= ('1','1','1','1','1','1','0','Z');
z <= "11111" & "000";
x <= (OTHERS => '1');
y <= (7 =>'0', 1 =>'0', OTHERS => '1');
z <= y;
y(2 DOWNTO 0) <= z(6 DOWNTO 4);
w2(0)(7 DOWNTO 0) <= "11110000";
w3(2) <= y;
z <= w3(1);
z(5 DOWNTO 0) <= w3(1)(2 TO 7);
w3(1) <= "00000000";
w3(1) <= (OTHERS => '0');
w2 <= ((OTHERS=>'0'),(OTHERS=>'0'),(OTHERS=>'0'),(OTHERS=>'0'));
w3 <= ("11111100", ('0','0','0','0','Z','Z','Z','Z',),
(OTHERS=>'0'), (OTHERS=>'0'));
w1 <= ((OTHERS=>'Z'), "11110000" ,"11110000", (OTHERS=>'0'));
------ Illegal array assignments: ----------------------
x <= y; -- type mismatch
31
y(5 TO 7) <= z(6 DOWNTO 0); -- wrong direction of y
w1 <= (OTHERS => '1'); -- w1 is a 2D array
w1(0, 7 DOWNTO 0) <="11111111"; -- w1 is a 2D array
w2 <= (OTHERS => 'Z'); -- w2 is a 1Dx1D array
w2(0, 7 DOWNTO 0) <= "11110000"; -- index should be 1Dx1D
-- Example of data type independent array initialization:
FOR i IN 0 TO 3 LOOP
FOR j IN 7 DOWNTO 0 LOOP
x(j) <= '0';
y(j) <= '0'
40 Chapter 3
TLFeBOOK
z(j) <= '0';
w1(i,j) <= '0';
w2(i)(j) <= '0';
w3(i)(j) <= '0';
END LOOP;
END LOOP;
---------------------------------------------------------
* V d 3.2: Bit n v bit vector
32
BEGIN
x <= a AND b;
END and2
Code 2:
33
tt c cc tn hiu c kiu d liu SIGNED, trong khi gii php th hai u ra
c kiu INTEGER. Lu trong gii php th hai c mt hm chuyn i
(conversion function) c s dng dng 13, kiu ca (a+b) ph hp vi
kiu ca tng. Lu cn bao gm c gi std_logic_arith (dng 4 ca mi gii
php), c m t kiu d liu SIGNED. Nh li rng mt gi tr SIGNED c
m t ging nh mt vector, ngha l, tng t nh STD_LOGIC_VECTOR,
khng ging INTEGER.
Code:
----------------------------------------------------
1 ----- Solution 1: in/out=SIGNED ----------
2 LIBRARY ieee;
3 USE ieee.std_logic_1164.all;
4 USE ieee.std_logic_arith.all;
5 ------------------------------------------
6 ENTITY adder1 IS
7 PORT ( a, b : IN SIGNED (3 DOWNTO 0);
8 sum : OUT SIGNED (4 DOWNTO 0));
9 END adder1;
10 ------------------------------------------
11 ARCHITECTURE adder1 OF adder1 IS
12 BEGIN
13 sum <= a + b;
14 END adder1;
15 ------------------------------------------
------------------------------------------------
1 ------ Solution 2: out=INTEGER -----------
2 LIBRARY ieee;
3 USE ieee.std_logic_1164.all;
4 USE ieee.std_logic_arith.all;
5 ------------------------------------------
6 ENTITY adder2 IS
7 PORT ( a, b : IN SIGNED (3 DOWNTO 0);
8 sum : OUT INTEGER RANGE -16 TO 15);
9 END adder2;
10 ------------------------------------------
11 ARCHITECTURE adder2 OF adder2 IS
12 BEGIN
13 sum <= CONV_INTEGER(a + b);
14 END adder2;
15 ------------------------------------------
34
Chng 4: Ton t v thuc tnh.
4.1. Ton t.
35
* Ton t nhn.
/ Ton t chia.
** Ton t ly m.
MOD Php chia ly phn nguyn.
REM Php chia ly phn d.
ABS Php ly gi tr tuyt i.
36
Nu tn hiu c kiu lit k th:
dVAL(pos) Tr v gi tr ti pos.
dPOS(val) Tr v v tr c gi tr l val.
dLEFTOF(value) Tr v gi tr v tr bn tri ca value.
dVAL(row,colum) Tr v gi tr mt v tr c bit.
Vi d: y l v d vi tn hiu ng h.
IF (clk'EVENT AND clk='1')...
IF (NOT clk'STABLE AND clk='1')...
WAIT UNTIL (clk'EVENT AND clk='1');
IF RISING_EDGE(clk)...
Trong
+ attribute_type l kiu d liu.
+ Class : SIGNAL, TYPE, FUNCTION.
V d :
ATTRIBUTE number_of_inputs: INTEGER;
ATTRIBUTE number_of_inputs OF nand3: SIGNAL IS 3;
37
Cng ging nh cc thuc tnh c nh ngha bi ngi dng. Trong
VHDL ta cng c th xy dng chng cc ton t ton hc. xy dng chng
cc ton t ny ta cn phi ch r loi d liu tham gia. V d nh ton t +
trn ch p dng cho cc loi d liu cng kiu s.By gi ta xy dng ton t
+ dng cng mt s INTEGER vi mt BIT.
4.5. GENERIC.
4.6. V d.
38
Hnh 4.1. B m ho cho v d 4.1
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY decoder IS
PORT ( ena : IN STD_LOGIC;
sel : IN STD_LOGIC_VECTOR (2 DOWNTO
0);
x : OUT STD_LOGIC_VECTOR (7 DOWNTO 0));
END decoder;
39
Hnh sau y m t kt qu hot ng ca b gii m trn.
40
END parity;
Trong on m trn chng ta s dng mt mnh GENERIC nh
ngha n =7. Khi tt c cc ln n xut hin n u c gi tr l 7.
Kt qu ca mch c biu din bi hnh sau. Khi u vo input =00000000
th u ra output =0. Khi input =00000001 th u ra output = 1 v s u
vo l 1 l mt s l.
V d 3: Parity Generator
ENTITY parity_gen IS
GENERIC (n : INTEGER := 7);
PORT ( input: IN BIT_VECTOR (n-1 DOWNTO 0);
output: OUT BIT_VECTOR (n DOWNTO 0));
END parity_gen;
41
Kt qu:
50 100 150 200 250 300 350 400 450 500 ns
input 00 01 02 03 04 05
output 00 81 82 03 84 05
42
Chng 5: M song song
5.1. Song song v tun t.
43
l cc khi ln WHEN v GENERATE. Bn cnh , cc php gn dng cc
ton t c s dng to cc mch t hp. Cui cng mt loi khi ln c
bit c gi l BLOCK s c s dng.
V d : B dn knh 4 -1.
44
---------------------------------------------
ARCHITECTURE pure_logic OF mux IS
BEGIN
y <= (a AND NOT s1 AND NOT s0) OR
(b AND NOT s1 AND s0) OR
(c AND s1 AND NOT s0) OR
(d AND s1 AND s0);
END pure_logic;
Kt qa m phng.
s0
s1
V d:
------ With WHEN/ELSE
-------------------------
outp <= "000" WHEN (inp='0' OR reset='1') ELSE
"001" WHEN ctl='1' ELSE
"010";
---- With WITH/SELECT/WHEN
--------------------
WITH control SELECT
output <= "000" WHEN reset,
45
"111" WHEN set,
UNAFFECTED WHEN OTHERS;
V d 1: B dn knh 4 -1.
46
WITH sel SELECT
y <= a WHEN "00",
b WHEN "01",
c WHEN "10",
d WHEN OTHERS;
END mux2;
--------------------------------------------
V d 2: B m 3 trng thi.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
----------------------------------------------
ENTITY tri_state IS
PORT ( ena: IN STD_LOGIC;
input: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
output: OUT STD_LOGIC_VECTOR (7 DOWNTO
0));
END tri_state;
----------------------------------------------
ARCHITECTURE tri_state OF tri_state IS
BEGIN
output <= input WHEN (ena='0') ELSE
(OTHERS => 'Z');
END tri_state;
----------------------------------------------
Kt qu m phng
ena
input 01 00 01 00
output 01 00 ZZ 01 ZZ
47
V d 3: Encoder.
48
"100" WHEN "00010000",
"101" WHEN "00100000",
"110" WHEN "01000000",
"111" WHEN "10000000",
"ZZZ" WHEN OTHERS;
END encoder2;
---------------------------------------------
Kt qu m phng:
100 200 300 400 500 600 700 800 900 1000 ns
x 00 01 02 03 04 05 06 07 08 09 0A 0B
y Z 0 1 Z 2 Z 3 Z
V d 4: ALU.
49
M ngun thc hin m phng:
----------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
----------------------------------------------
ENTITY ALU IS
PORT (a, b: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
sel: IN STD_LOGIC_VECTOR (3 DOWNTO 0);
cin: IN STD_LOGIC;
y: OUT STD_LOGIC_VECTOR (7 DOWNTO 0));
END ALU;
----------------------------------------------
ARCHITECTURE dataflow OF ALU IS
SIGNAL arith, logic: STD_LOGIC_VECTOR (7
DOWNTO 0);
BEGIN
----- Arithmetic unit: ------
WITH sel(2 DOWNTO 0) SELECT
arith <= a WHEN "000",
a+1 WHEN "001",
a-1 WHEN "010",
b WHEN "011",
b+1 WHEN "100",
b-1 WHEN "101",
a+b WHEN "110",
a+b+cin WHEN OTHERS;
----- Logic unit: -----------
WITH sel(2 DOWNTO 0) SELECT
logic <= NOT a WHEN "000",
NOT b WHEN "001",
a AND b WHEN "010",
a OR b WHEN "011",
a NAND b WHEN "100",
a NOR b WHEN "101",
a XOR b WHEN "110",
NOT (a XOR b) WHEN OTHERS;
-------- Mux: ---------------
WITH sel(3) SELECT
y <= arith WHEN '0',
logic WHEN OTHERS;
END dataflow;
----------------------------------------------
Kt qu m phng.
50 100 150 200 250 300 350 400 450 500 ns
a 00 01 02 03 04 05
arith 00 02 02 04 03 05
b 00 01 02 03 04 05
cin
logic FF FE FD FC 04 05
sel 0 1 0 1 2 3
y 00 02 02 04 03 05
50
5.4. GENERATE.
51
PORT ( inp: IN STD_LOGIC_VECTOR (3 DOWNTO 0);
sel: IN INTEGER RANGE 0 TO 4;
outp: OUT STD_LOGIC_VECTOR (7 DOWNTO 0));
END shifter;
------------------------------------------------
ARCHITECTURE shifter OF shifter IS
SUBTYPE vector IS STD_LOGIC_VECTOR (7 DOWNTO 0);
TYPE matrix IS ARRAY (4 DOWNTO 0) OF vector;
SIGNAL row: matrix;
BEGIN
row(0) <= "0000" & inp;
G1: FOR i IN 1 TO 4 GENERATE
row(i) <= row(i-1)(6 DOWNTO 0) & '0';
END GENERATE;
outp <= row(sel);
END shifter;
Kt qu m phng:
inp 0 1 0 0
outp 00 01 02 03 04
sel 0 1 2 3 4
5.5. BLOCK.
Khi lnh BLOCK cho php t mt khi lnh song song vo mt on,
iu gip cho cc on lnh d c v d qun l hn. Cu trc ca chng
nh sau:
label: BLOCK
[declarative part]
BEGIN
(concurrent statements)
END BLOCK label;
Cc khi lnh BLOCK t lin tip nhau nh v d sau:
------------------------
ARCHITECTURE example ...
BEGIN
...
block1: BLOCK
BEGIN
52
...
END BLOCK block1
...
block2: BLOCK
BEGIN
...
END BLOCK block2;
...
END example;
------------------------
V d:
b1: BLOCK
SIGNAL a: STD_
BEGIN
a <= input_sig
END BLOCK b1;
53
-------------------------------
ARCHITECTURE latch OF latch IS
BEGIN
b1: BLOCK (clk='1')
BEGIN
q <= GUARDED d;
END BLOCK b1;
END latch;
-------------------------------
Kt qu m phng
100 200 300 400 500 600 700 800 900 1000 ns
clk
100 200 300 400 500 600 700 800 900 1000 ns
clk
rst
54
Chng 6: M tun t
6.1. PROCESS
C php:
V d 6.1a:
rst
clk
library IEEE;
use IEEE.STD_LOGIC_1164.all;
55
entity DFF is
Port(d,clk,rst:in std_logic;
q:out std_logic);
end DFF;
6.3. IF.
C php:
56
END IF;
V d:
V d 6.3a:
clk
digit 0 1 2 3 4 5 6 7 8 9
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY counter IS
PORT (clk : IN STD_LOGIC;
digit : OUT INTEGER RANGE 0 TO 9);
END counter;
57
V d 6.3b:
clk
rst
internal U ? ? ? C 6 3 1 0
ENTITY shiftreg IS
GENERIC (n: INTEGER := 4); -- # of stages
PORT (d, clk, rst: IN STD_LOGIC;
q: OUT STD_LOGIC);
END shiftreg;
6.4. WAIT.
58
C php:
V d:
Thanh ghi 8 bit vi tn hiu reset ng b
V d:
Thanh ghi 8 bit vi tn hiu reset khng ng b
PROCESS
BEGIN
WAIT ON clk, rst;
IF (rst='1') THEN
output <= "00000000";
ELSIF (clk'EVENT AND clk='1') THEN
output <= input;
END IF;
END PROCESS;
59
V d 6.4a:
DFF vi tn hiu reset khng ng b
5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 ns
rst
clk
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity DFF is
Port(d,clk,rst:in std_logic;
q:out std_logic);
end DFF;
V d 6.4b:
B m mt ch s thp phn 0 9 0
10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 160 ns
clk
digit 0 1 2 3 4 5 6 7 8 9
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY counter IS
PORT (clk : IN STD_LOGIC;
digit : OUT INTEGER RANGE 0 TO 9);
END counter;
60
VARIABLE temp : INTEGER RANGE 0 TO 10;
BEGIN
WAIT UNTIL (clk'EVENT AND clk='1');
temp := temp + 1;
IF (temp=10) THEN
temp := 0;
END IF;
digit <= temp;
END PROCESS;
END counter;
6.5. CASE.
C php:
CASE identifier IS
WHEN value => assignments;
WHEN value => assignments;
...
END CASE;
V d:
CASE control IS
WHEN "00" => x<=a; y<=b;
WHEN "01" => x<=b; y<=c;
WHEN OTHERS => x<="0000"; y<="ZZZZ";
END CASE;
WHEN CASE
Kiu lnh ng thi Tun t
S dng Ch ngoi PROCESS, Ch trong PROCESS,
FUNCTION, hoc FUNCTION, hoc
61
PROCEDURE PROCEDURE
Tt c s hon v phi C vi C
c kim tra WITH/SELECT/WHEN
S php gn ln nht 1 Bt k
cho mi kim tra
T kho khng kch UNAFFECTED NULL
hot
Bng 6.1. So snh gia WHEN v CASE
V d:
Vi WHEN:
Vi CASE:
CASE sel IS
WHEN "000" => x<=a;
WHEN "001" => x<=b;
WHEN "010" => x<=c;
WHEN OTHERS => NULL;
END CASE;
V d:
B dn knh MUX 4-1
Vi IF:
Vi CASE:
CASE sel IS
WHEN "00" => x<=a;
WHEN "01" => x<=b;
WHEN "10" => x<=c;
WHEN OTHERS => x<=d;
END CASE;
62
V d 6.5a:
DFF vi tn hiu reset khng ng b
5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 ns
rst
clk
V d 6.5b:
B m hai ch s thp phn 0 99 0, u ra l 2 LED 7 thanh
63
20 40 60 80 100 120 140 160 180 200 220 240 260 280 300 ns
reset
clk
temp1 0 1 0 1 0 1 2 3 4 0 1
temp2 0
digit1 7E 30 7E 30 7E 30 6D 79 33 7E 30
digit2 7E
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY counter IS
PORT (clk, reset : IN STD_LOGIC;
digit1, digit2 : OUT STD_LOGIC_VECTOR (6 DOWNTO 0));
END counter;
64
WHEN 1 => digit2 <= "0110000"; --30
WHEN 2 => digit2 <= "1101101"; --6D
WHEN 3 => digit2 <= "1111001"; --79
WHEN 4 => digit2 <= "0110011"; --33
WHEN 5 => digit2 <= "1011011"; --5B
WHEN 6 => digit2 <= "1011111"; --5F
WHEN 7 => digit2 <= "1110000"; --70
WHEN 8 => digit2 <= "1111111"; --7F
WHEN 9 => digit2 <= "1111011"; --7B
WHEN OTHERS => NULL;
END CASE;
END PROCESS;
END counter;
6.6. LOOP.
C php:
V d:
Vi FOR/LOOP:
FOR i IN 0 TO 5 LOOP
x(i) <= enable AND w(i+2);
y(0, i) <= w(i);
END LOOP;
65
Mt c im quan trng ca FOR/LOOP (tng t to vi
GENERATE) l gii hn ti thiu phi l tnh. Do , mt khai bo kiu FOR
i IN 0 TO choice LOOP, vi choice l mt tham s u vo (khng tnh),
khng kt hp tng qut c.
V d:
Vi WHILE/LOOP
V d:
Vi EXIT
V d:
Vi NEXT
FOR i IN 0 TO 15 LOOP
NEXT WHEN i=skip; -- jumps to next iteration
(...)
END LOOP;
V d 6.6a:
B cng c nh 8 bit khng du.
cin
a 92 40 04 31 86 C6 32
b 24 81 09 63 0D 8D 65
s B7 C2 0D 94 93 53 97
cout
66
Mi phn t ca s l mt b cng y .
sj = aj XOR bj XOR cj
cj1 = (aj AND bj) OR (aj AND cj) OR (bj AND cj)
Cch 1:
Dng Generic vi cc VECTOR
ENTITY adder IS
GENERIC (length : INTEGER := 8);
PORT ( a, b: IN STD_LOGIC_VECTOR (length-1 DOWNTO 0);
cin: IN STD_LOGIC;
s: OUT STD_LOGIC_VECTOR (length-1 DOWNTO 0);
cout: OUT STD_LOGIC);
END adder;
Cch 2:
Dng non-generic vi cc INTEGER
ENTITY adder IS
PORT ( a, b: IN INTEGER RANGE 0 TO 255;
c0: IN STD_LOGIC;
s: OUT INTEGER RANGE 0 TO 255;
c8: OUT STD_LOGIC);
END adder;
67
BEGIN
IF (c0='1') THEN temp:=1;
ELSE temp:=0;
END IF;
temp := a + b + temp;
IF (temp > 255) THEN
c8 <= '1';
temp := temp; ---256
ELSE c8 <= '0';
END IF;
s <= temp;
END PROCESS;
END adder;
V d 6.6b:
B dch n gin: dch vector u vo (kch thc 8) 0 hoc 1 v
pha tri. Khi dch, bit LSB phi c in 0. Nu shift = 0 th outp = inp; nu
shift = 1 th outp(0) = 0 v outp(i) = inp(i-1) vi 1 i 7.
inp 00 14 28 3C 50 64 78
shift 0 1
outp 00 14 28 3C A0 C8 F0
68
USE ieee.std_logic_1164.all;
ENTITY barrel IS
GENERIC (n: INTEGER := 8);
PORT ( inp: IN STD_LOGIC_VECTOR (n-1 DOWNTO 0);
shift: IN INTEGER RANGE 0 TO 1;
outp: OUT STD_LOGIC_VECTOR (n-1 DOWNTO 0));
END barrel;
V d 6.6c:
B m s s 0 ca mt vector nh phn, bt u t bn tri
50 100 150 200 250 300 350 400 450 500 550 600 ns
data 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D
zeros 8 7 6 5 4
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY LeadingZeros IS
PORT ( data: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
zeros: OUT INTEGER RANGE 0 TO 8);
END LeadingZeros;
69
END PROCESS;
END behavior;
V d:
B m phi c tng ti mi s chuyn tip ca tn hiu clock (sn
dng cng sn dng)
PROCESS (clk)
BEGIN
IF (clk'EVENT AND clk='1') THEN
counter <= counter + 1;
ELSIF(clk'EVENT AND clk='0') THEN
counter <= counter + 1;
END IF;
...
END PROCESS;
PROCESS (clk)
BEGIN
IF (clk'EVENT) THEN
counter := counter + 1;
END IF;
...
END PROCESS;
70
PROCESS (clk)
BEGIN
counter := counter + 1;
...
END PROCESS;
PROCESS (clk)
BEGIN
IF (clk'EVENT AND clk='1') THEN
x <= d;
END IF;
END PROCESS;
PROCESS (clk)
BEGIN
IF (clk'EVENT AND clk='0') THEN
y <= d;
END IF;
END PROCESS;
V d 6.7a:
RAM (Random Acess Memory), dung lng 16 t nh x 8 bit
wr_ena
clk
addr 3 4 5 2 3 4 5
data_in 32 33 34 35 36 37 38
data_out UU 32 UU 33 UU 34 UU 32 33 34
71
wr_ena c xc nhn, ti sn dng tip theo ca clk, vector c mt ti
data_in phi c lu tr ti a ch c m t bi addr. u ra, data_out,
bng cch x l khc, phi hin th lin tc d liu chn bi addr.
Khi wr_ena mc thp, q c ni vi u vo ca flip-flop, v d c
m, v vy khng c d liu mi s c ghi vo b nh. Khi wr_ena tr v
mc cao, d c ni vi u vo ca thanh ghi, v vy ti sn dng tip theo
ca clk, d s ghi gi tr lin trc.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY ram IS
GENERIC ( bits: INTEGER := 8;-- # of bits per word
words: INTEGER := 16);--#of words in the mem
PORT ( wr_ena, clk: IN STD_LOGIC;
addr: IN INTEGER RANGE 0 TO words-1;
data_in: IN STD_LOGIC_VECTOR (bits-1 DOWNTO 0);
data_out: OUT STD_LOGIC_VECTOR (bits-1 DOWNTO 0));
END ram;
72
V d 6.8a:
Thit k mch t hp sai
sel 0 3 1
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY example IS
PORT (a, b, c, d: IN STD_LOGIC;
sel: IN INTEGER RANGE 0 TO 3;
x, y: OUT STD_LOGIC);
END example;
73
END PROCESS;
END example;
74
Chng 7: Signal v Variable
VHDL cung cp hai i tng gii quyt cc gi tr d liu khng
tnh (non-static): SIGNAL v VARIABLE. N cn cung cp cc cch thit
lp cc gi tr mc nh (static): CONSTANT v GENERIC.
CONSTANT v GENERIC c th l ton cc v c th c s dng
trong c kiu m, ng thi hoc tun t. VARIABLE l cc b, ch c th
c s dng bn trong mt phn ca m tun t (trong PROCESS,
FUNCTION, hoc PROCEDURE).
7.1. CONSTANT.
C php:
V d:
7.2. SIGNAL.
C php:
V d:
75
Khai bo ca SIGNAL c th c to ra cc ch ging nhau nh l
khai bo CONSTANT.
Kha cnh quan trng ca SIGNAl, khi s dng bn trong mt phn ca
m tun t (PROCESS), s cp nht n khng tc th. Gi tr mi ca khng
nn c i c c trc khi kt thc PROCESS, FUNCTION, hoc
PROCEDURE tng ng.
Php ton gn cho SIGNAL l <= (count <= 35;). Gi tr khi to
khng th tng hp c, ch c xt khi m phng.
Kha cnh khc nh hng n kt qu khi nhiu php gn c to
cng SIGNAL. Trnh bin dch c th thng bo v thot s tng hp, hoc c
th suy ra mch sai (bng cch ch xt php gn cui cng). Do , vic xt lp
cc gi tr khi to, nn c thc hin vi VARIABLE.
V d 7.2a:
din 00 01 02 03 04 05 06
temp 0 1 2 3 4 5 6
ones 0 1 2 3 4 5
ENTITY count_ones IS
PORT ( din: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
ones: OUT INTEGER RANGE 0 TO 8);
END count_ones;
76
7.3. VARIABLE
C php:
V d:
V d 7.3a:
B m s s 1 ca mt vector nh phn
Khi cp nht bin l tc th, gi tr khi to c thit lp chnh xc v
khng c thng bo no v nhiu php gn do trnh bin dch.
50 100 150 200 250 300 350 400 450 500 550 600 ns
din 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D
ones 0 1 2 1 2 3 1 2 3 2 3
ENTITY count_ones IS
PORT ( din: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
ones: OUT INTEGER RANGE 0 TO 8);
END count_ones;
ARCHITECTURE ok OF count_ones IS
BEGIN
PROCESS (din)
VARIABLE temp: INTEGER RANGE 0 TO 8;
BEGIN
temp := 0;
77
FOR i IN 0 TO 7 LOOP
IF (din(i)='1') THEN
temp := temp + 1;
END IF;
END LOOP;
ones <= temp;
END PROCESS;
END ok;
SIGNAL VARIABLE
Php gn <= :=
Tnh nng Biu din s kt ni cc Biu din thng tin cc
mch (cc dy) b
Phm vi C th l ton cc (trn Cc b (ch trong
ton b m) PROCESS,
FUNCTION, hay
PROCEDURE tng
ng)
Hot ng Cp nht khng tc th Cp nht tc th (gi tr
trong m tun t (gi tr mi c th c s
mi ch c th dng lc dng trong dng lnh
kt thc PROCESS, tip theo ca m)
FUNCTION, hay
PROCEDURE)
S dng Trong PACKAGE, Ch trong m tun t,
ENTITY, hay trong PROCESS,
ARCHITECTURE. FUNCTION, hay
Trong ENTITY, tt c PROCEDURE
cc PORT l cc
SIGNAL mc nh
78
Cch 1:
S dng SIGNAL (khng ng)
ENTITY mux IS
PORT ( a, b, c, d, s0, s1: IN STD_LOGIC;
y: OUT STD_LOGIC);
END mux;
Cch 2:
S dng VARIABLE (ng)
ENTITY mux IS
PORT ( a, b, c, d, s0, s1: IN STD_LOGIC;
y: OUT STD_LOGIC);
END mux;
ARCHITECTURE ok OF mux IS
BEGIN
PROCESS (a, b, c, d, s0, s1)
VARIABLE sel : INTEGER RANGE 0 TO 3;
BEGIN
sel := 0;
IF (s0='1') THEN sel := sel + 1;
END IF;
IF (s1='1') THEN sel := sel + 2;
END IF;
CASE sel IS
79
WHEN 0 => y<=a;
WHEN 1 => y<=b;
WHEN 2 => y<=c;
WHEN 3 => y<=d;
END CASE;
END PROCESS;
END ok;
s0
s1
50 100 150 200 250 300 350 400 450 500 550 600 ns
s0
s1
80
Cch 1:
Khng ng
ENTITY dff IS
PORT ( d, clk: IN STD_LOGIC;
q: BUFFER STD_LOGIC;
qbar: OUT STD_LOGIC);
END dff;
Cch 2:
ng
ENTITY dff IS
PORT ( d, clk: IN STD_LOGIC;
q: BUFFER STD_LOGIC;
qbar: OUT STD_LOGIC);
END dff;
ARCHITECTURE ok OF dff IS
BEGIN
PROCESS (clk)
BEGIN
IF (clk'EVENT AND clk='1') THEN
q <= d;
END IF;
END PROCESS;
qbar <= NOT q;
END ok;
81
Trong cch 2, thay qbar<=NOT q (dng 30) bn ngoi PROCESS, do
php tnh nh mt biu thc ng thi ng.
50 100 150 200 250 300 350 400 450 500 550 600 ns
clk
qbar
50 100 150 200 250 300 350 400 450 500 550 600 ns
clk
qbar
V d 7.3d:
B chia tn, chia tn s clock bi 6.
clk
count1 0 1 2 3 4 5 6 7
count2 0 1 2 3 4
out1
out2
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY freq_divider IS
PORT ( clk : IN STD_LOGIC;
out1, out2 : BUFFER STD_LOGIC);
END freq_divider;
82
PROCESS (clk)
VARIABLE count2 : INTEGER RANGE 0 TO 7;
BEGIN
IF (clk'EVENT AND clk='1') THEN
count1 <= count1 + 1;
count2 := count2 + 1;
IF (count1 = 7 ) THEN
out1 <= NOT out1;
count1 <= 0;
END IF;
IF (count2 = 7 ) THEN
out2 <= NOT out2;
count2 := 0;
END IF;
END IF;
END PROCESS;
END example;
V d:
Trong PROCESS, output1 v output2 u s c lu tr (suy ra cc
flip-flop), bi v c hai u c gn ti s chuyn tip ca tn hiu khc (clk).
PROCESS (clk)
BEGIN
IF (clk'EVENT AND clk='1') THEN
output1 <= temp; -- output1 stored
output2 <= a; -- output2 stored
END IF;
END PROCESS;
83
PROCESS (clk)
BEGIN
IF (clk'EVENT AND clk='1') THEN
output1 <= temp; -- output1 stored
END IF;
output2 <= a; -- output2 not stored
END PROCESS;
PROCESS (clk)
VARIABLE temp: BIT;
BEGIN
IF (clk'EVENT AND clk='1') THEN
temp <= a;
END IF;
x <= temp; -- temp causes x to be stored
END PROCESS;
V d 7.4a:
DFF vi q v qbar
Cch 1 c 2 php gn SIGNAL ng b (dng 16-17), v vy 2 flip-flop
s c sinh. Cch 2 c mt trong cc php gn l ng b, vic tng hp s
lun suy ra ch mt flip-flop
clk
qbar
50 100 150 200 250 300 350 400 450 500 550 600 ns
clk
qbar
84
Cch 1:
Sinh hai DFF
ENTITY dff IS
PORT ( d, clk: IN STD_LOGIC;
q: BUFFER STD_LOGIC;
qbar: OUT STD_LOGIC);
END dff;
Cch 2:
Sinh mt DFF
ENTITY dff IS
PORT ( d, clk: IN STD_LOGIC;
q: BUFFER STD_LOGIC;
qbar: OUT STD_LOGIC);
END dff;
85
V d 7.4b:
B m 0 - 7
Hnh 7.4b.1. B m 0 7
Cch 1:
Mt php gn VARIABLE ng b c tao ra (dng 14-15). Mt
VARIABLE c th sinh cc thanh ghi bi v php gn ca n (dng 15) ti s
chuyn tip ca tn hiu khc (clk, dng 14) v gi tr ca n khng ri
PROCESS (dng 17).
Cch 2:
Mt php gn SIGNAL ng b xy ra (dng 13-14). Ch s dng cc
SIGNAL. Ch , khi khng c tn hiu ph c s dng, count cn c khai
bo nh kiu BUFFER (dng 14), bi v n c gn mt gi tr v cng c
c (s dng) ni ti (dng 14). Mt SIGNAL, ging nh mt VARIABLE, c
th cng c tng khi s dng trong m tun t.
86
ARCHITECTURE counter OF counter IS
BEGIN
PROCESS (clk, rst)
BEGIN
IF (rst='1') THEN
count <= 0;
ELSIF (clk'EVENT AND clk='1') THEN
count <= count + 1;
END IF;
END PROCESS;
END counter;
rst
clk
count 0 1 2 3 4 5 6 7
50 100 150 200 250 300 350 400 450 500 550 600 ns
rst
clk
count 0 1 2 3 4 5 6 7
V d 7.4c:
Thanh ghi dch 4 cp
Cch 1:
3 VARIABLE c s dng (a, b, v c, dng 10). Tuy nhin cc bin
c s dng trc cc gi tr c gn cho chng (o ngc th t, bt u
vi dout, dng 13, v kt thc vi din, dng 16). Kt qu l, cc flip-flop s
c suy ra, lu tr cc gi tr t php chy lin trc ca PROCESS.
87
ARCHITECTURE shift OF shift IS
BEGIN
PROCESS (clk)
VARIABLE a, b, c: BIT;
BEGIN
IF (clk'EVENT AND clk='1') THEN
dout <= c;
c := b;
b := a;
a := din;
END IF;
END PROCESS;
END shift;
Cch 2:
Cc bin c thay th bi cc SIGNAL (dng 8), v cc php gn c
to ra trong th t trc tip (t din-dout, dng 13-16). Khi cc php gn tn
hiu ti s chuyn tip tn hiu khc sinh cc thanh ghi, mch ng s c suy
ra.
Cch 3:
Cc bin ging nhau ca cch 1 b chim, nhng trong th t trc
tip (t din-dout, dng 13-16). Tuy nhin, mt php gn cho mt bin l tc th,
v khi cc bin ang c s dng trong th t trc tip (sau khi cc gi tr va
c gn cho chng), dng 13-15 thnh 1 dng, tng ng vi c:=din. Gi
tr ca c ri PROCESS trong dng tip theo (dng 16), khi mt php gn tn
hiu (dout <= c) xy ra ti s chuyn tip ca clk. Do , mt thanh ghi s
c suy ra t cch 3, nn khng to kt qu mch chnh xc.
88
dout: OUT BIT);
END shift;
din
clk
dout
50 100 150 200 250 300 350 400 450 500 550 600 ns
din
clk
dout
50 100 150 200 250 300 350 400 450 500 550 600 ns
din
clk
dout
V d 7.4d:
Thanh ghi dch 4 bit
89
Bit ra (q) phi l 4 sn clock dng sau bit vo (d). Reset phi l
khng ng b, xo tt c cc u ra flip-flop v 0 khi kch hot.
Cch 1:
S dng mt SIGNAL sinh cc flip-flop. Cc thanh ghi c to bi
v mt php gn cho mt tn hiu c to ra ti s chuyn tip ca tn hiu
khc (dng 17-18).
ENTITY shiftreg IS
PORT ( d, clk, rst: IN STD_LOGIC;
q: OUT STD_LOGIC);
END shiftreg;
Cch 2:
S dng mt VARIABLE. Php gn ti s chuyn tip ca tn hiu khc
c to ra cho mt bin (dng 17-18), nhng khi gi tr ca n ri PROCESS
(n c chuyn n mt port trong dng 20), n cng suy ra cc thanh ghi.
ENTITY shiftreg IS
PORT ( d, clk, rst: IN STD_LOGIC;
q: OUT STD_LOGIC);
END shiftreg;
90
ELSIF (clk'EVENT AND clk='1') THEN
internal := d & internal(3 DOWNTO 1);
END IF;
q <= internal(0);
END PROCESS;
END behavior;
clk
rst
internal 0 1 0 1 0 1 0 1 0
91
Chng 8: My trng thi
Mt thit k mch s c th c chia lm 2 thnh phn: b x l d
liu v b iu khin. Mi quan h gia b iu khin v b x l d liu trong
mch c biu din
My trng thi hu hn (FSM) l mt cng ngh m hnh ho c bit
cho cc mch logic tun t. M hnh c th rt c gip trong thit k
ca nhng loi h thng no , c bit l cc thao tc ca nhng h thng
theo khun dng tun t hon ton xc nh.
X - Tp hp cc tn hiu vo ca tmat:
92
X = { x1(t),,xn(t)}
Tp cc tn hiu ra ca tmat:
Y = {y1(t),,ym(t)}
Tp hp cc trng thi ca tmat:
S = {s1(t),,ss(t)}
Hm (s, x) hm chuyn trng thi ca tmat
Hm (s,x) hm u ra ca tmat.
93
Thit k phn mch dy:
94
IF (input = ...) THEN
output <= <value>;
nx_state <= state2;
ELSE ...
END IF;
WHEN state2 =>
IF (input = ...) THEN
output <= <value>;
nx_state <= state2;
ELSE ...
END IF;
...
END CASE;
END PROCESS;
95
END IF;
WHEN state1 =>
IF (input = ...) THEN
output <= <value>;
nx_state <= state2;
ELSE ...
END IF;
WHEN state2 =>
IF (input = ...) THEN
output <= <value>;
nx_state <= state3;
ELSE ...
END IF;
...
END CASE;
END PROCESS;
END <arch_name>;
V d 8.1: B m BCD
Mt b m l mt v d ca my Moore, u ra ch ph thuc vo kt
qu ca trng thi hin ti. Ging nh mt mch thanh ghi v mt mch dy
n gin. thit k mch ny, chng ta c th dng phng php thng
thng nh nhng phn mch mch t hp, nhng y ta s dng phng
php FSM.
Gi s ta cn thit k b m modul 10. Nh vy chng ta s cn c mt
may c 10 trang thi. Cc trng thi y c gi l zero, one,,nine.
hnh trng thi ca my c cho nh sau:
96
M thit k s nh sau:
-------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
-------------------------------------------------
ENTITY counterBCD IS
PORT ( clk, rst: IN STD_LOGIC;
count: OUT STD_LOGIC_VECTOR (3 DOWNTO 0));
END counterBCD;
-------------------------------------------------
ARCHITECTURE state_machine OF counterBCD IS
TYPE state IS (zero, one, two, three, four,
five, six, seven, eight, nine);
SIGNAL pr_state, nx_state: state;
BEGIN
------------- Phan mach day: -----------------
PROCESS (rst, clk)
BEGIN
IF (rst='1') THEN
pr_state <= zero;
ELSIF (clk'EVENT AND clk='1') THEN
pr_state <= nx_state;
END IF;
END PROCESS;
------------- Phan mach to hop: -----------------
PROCESS (pr_state)
BEGIN
CASE pr_state IS
WHEN zero =>
count <= "0000";
nx_state <= one;
WHEN one =>
count <= "0001";
nx_state <= two;
WHEN two =>
count <= "0010";
nx_state <= three;
WHEN three =>
count <= "0011";
nx_state <= four;
WHEN four =>
count <= "0100";
nx_state <= five;
WHEN five =>
count <= "0101";
nx_state <= six;
WHEN six =>
count <= "0110";
nx_state <= seven;
WHEN seven =>
count <= "0111";
nx_state <= eight;
WHEN eight =>
97
count <= "1000";
nx_state <= nine;
WHEN nine =>
count <= "1001";
nx_state <= zero;
END CASE;
END PROCESS;
END state_machine;
-------------------------------------------------
M phng kt qu:
M thit k s nh sau:
-------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
----------------------------------------------
ENTITY vd_FSM IS
PORT ( a, b, d, clk, rst: IN BIT;
x: OUT BIT);
END vd_FSM;
----------------------------------------------
ARCHITECTURE state_machine OF vd_FSM IS
98
TYPE state IS (stateA, stateB);
SIGNAL pr_state, nx_state: state;
BEGIN
---------- Phan mach day: ----------------------
PROCESS (rst, clk)
BEGIN
IF (rst='1') THEN
pr_state <= stateA;
ELSIF (clk'EVENT AND clk='1') THEN
pr_state <= nx_state;
END IF;
END PROCESS;
---------- Phan mach to hop: -----------------
PROCESS (a, b, d, pr_state)
BEGIN
CASE pr_state IS
WHEN stateA =>
x <= a;
IF (d='1') THEN nx_state <= stateB;
ELSE nx_state <= stateA;
END IF;
WHEN stateB =>
x <= b;
IF (d='1') THEN nx_state <= stateA;
ELSE nx_state <= stateB;
END IF;
END CASE;
END PROCESS;
END state_machine;
----------------------------------------------
Kt qu m phng:
99
Trong nhiu ng dng, tn hiu c yu cu l ng b, th u ra s
ch cp nht khi thay i sn clock. to ra my ng b Mealy, u ra phi
c lu tr tt, nh trong hnh 8.6.2
LIBRARY ieee;
USE ieee.std_logic_1164.all;
-------------------------------------------------------
ENTITY <ent_name> IS
PORT (input: IN <data_type>;
reset, clock: IN STD_LOGIC;
output: OUT <data_type>);
END <ent_name>;
-------------------------------------------------------
ARCHITECTURE <arch_name> OF <ent_name> IS
TYPE states IS (state0, state1, state2, state3, ...);
---------- Phan mach to hop: --------------------------
SIGNAL pr_state, nx_state: states;
PROCESS (pr_state)
SIGNAL temp: <data_type>;
BEGIN
BEGIN
CASE pr_state IS
---------- Phan mach day: --------------------------
PROCESS (reset, clock)
WHEN state0 =>
BEGIN
temp <= <value>;
IF (reset='1') THEN
IF (condition) THEN nx_state <= state1;
pr_state <= state0;
...
ELSIF (clock'EVENT AND clock='1') THEN
END IF;
output <= temp;
WHEN state1 =>
pr_state <= nx_state;
temp <= <value>;
END IF;
IF (condition) THEN nx_state <= state2;
END PROCESS;
...
END IF;
WHEN state2 =>
temp <= <value>;
IF (condition) THEN nx_state <= state3;
...
END IF;
...
END CASE; 100
END PROCESS;
END <arch_name>;
So snh khun mu ca thit k kiu 2 vi thit k kiu 1, chng ta thy
ch c mt s khc nhau duy nht, l xut hin tn hiu trung gian temp. Tn
hiu ny s c tc dng lu tr u ra ca my. Ch cho cc gi tr chuyn
thnh u ra khi khi c s thay i s kin clock.
V d 8.3:
Chng ta s nhn li thit k ca v d 8.2. Tuy nhin y chng ta
mun u ra l ng b (ch thay i khi c s kin thay i clock). V vy
trong v d ny chng ta s thit k theo kiu 2.
----------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
----------------------------------------------
ENTITY VD_FSM2 IS
PORT ( a, b, d, clk, rst: IN BIT;
x: OUT BIT);
END VD_FSM2;
----------------------------------------------
ARCHITECTURE VD_FSM2 OF VD_FSM2 IS
TYPE state IS (stateA, stateB);
SIGNAL pr_state, nx_state: state;
SIGNAL temp: BIT;
BEGIN
----- Phan mach day: ----------------------
PROCESS (rst, clk)
BEGIN
IF (rst='1') THEN
101
pr_state <= stateA;
ELSIF (clk'EVENT AND clk='1') THEN
x <= temp;
pr_state <= nx_state;
END IF;
END PROCESS;
---------- Phan mach to hop: -----------------
PROCESS (a, b, d, pr_state)
BEGIN
CASE pr_state IS
WHEN stateA =>
temp <= a;
IF (d='1') THEN nx_state <= stateB;
ELSE nx_state <= stateA;
END IF;
WHEN stateB =>
temp <= b;
IF (d='1') THEN nx_state <= stateA;
ELSE nx_state <= stateB;
END IF;
END CASE;
END PROCESS;
END VD_FSM2;
----------------------------------------------
102
Hnh 8.8. S trng thi ca b pht hin chui
M ca my c thit k nh sau:
----------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
----------------------------------------------
ENTITY Bo_doan_xau IS
PORT ( d, clk, rst: IN BIT;
q: OUT BIT);
END Bo_doan_xau;
--------------------------------------------
ARCHITECTURE state_machine OF Bo_doan_xau IS
TYPE state IS (zero, one, two, three);
SIGNAL pr_state, nx_state: state;
BEGIN
--------- Phan mach day: --------------------
PROCESS (rst, clk)
BEGIN
IF (rst='1') THEN
pr_state <= zero;
ELSIF (clk'EVENT AND clk='1') THEN
pr_state <= nx_state;
END IF;
END PROCESS;
---------- Phan mach to hop: ---------------
PROCESS (d, pr_state)
BEGIN
CASE pr_state IS
WHEN zero =>
q <= '0';
IF (d='1') THEN nx_state <= one;
ELSE nx_state <= zero;
END IF;
WHEN one =>
q <= '0';
IF (d='1') THEN nx_state <= two;
ELSE nx_state <= zero;
END IF;
WHEN two =>
103
q <= '0';
IF (d='1') THEN nx_state <= three;
ELSE nx_state <= zero;
END IF;
WHEN three =>
q <= '1';
IF (d='0') THEN nx_state <= zero;
ELSE nx_state <= three;
END IF;
END CASE;
END PROCESS;
END state_machine;
--------------------------------------------
Kt qu m phng s nh sau:
104
Hnh 8.10.b. hnh trng thi ca TLC
------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
ENTITY Bodk_den_giao_thong IS
PORT ( clk, stby, test: IN STD_LOGIC;
r1, r2, y1, y2, g1, g2: OUT STD_LOGIC);
END Bodk_den_giao_thong;
-------------------------------------------------
ARCHITECTURE state_machine_be OF Bodk_den_giao_thong IS
CONSTANT timeMAX : INTEGER := 2700;
CONSTANT timeRG : INTEGER := 1800;
CONSTANT timeRY : INTEGER := 300;
CONSTANT timeGR : INTEGER := 2700;
CONSTANT timeYR : INTEGER := 300;
CONSTANT timeTEST : INTEGER := 60;
TYPE state IS (RG, RY, GR, YR, YY);
SIGNAL pr_state, nx_state: state;
SIGNAL time : INTEGER RANGE 0 TO timeMAX;
BEGIN
-------------Phan mach day: ----
PROCESS (clk, stby)
VARIABLE count : INTEGER RANGE 0 TO timeMAX;
BEGIN
IF (stby='1') THEN
pr_state <= YY;
count := 0;
105
ELSIF (clk'EVENT AND clk='1') THEN
count := count + 1;
IF (count = time) THEN
pr_state <= nx_state;
count := 0;
END IF;
END IF;
END PROCESS;
----------- Phan mach to hop: ----
PROCESS (pr_state, test)
BEGIN
CASE pr_state IS
WHEN RG =>
r1<='1';r2<='0';y1<='0'; y2<='0'; g1<='0'; g2<='1';
nx_state <= RY;
IF (test='0') THEN time <= timeRG;
ELSE time <= timeTEST;
END IF;
WHEN RY =>
r1<='1';r2<='0';y1<='0';y2<='1';g1<='0'; g2<='0';
nx_state <= GR;
IF (test='0') THEN time <= timeRY;
ELSE time <= timeTEST;
END IF;
WHEN GR =>
r1<='0';r2<='1';y1<='0';y2<='0';g1<='1'; g2<='0';
nx_state <= YR;
IF (test='0') THEN time <= timeGR;
ELSE time <= timeTEST;
END IF;
WHEN YR =>
r1<='0';r2<='1';y1<='1'; y2<='0'; g1<='0'; g2<='0';
nx_state <= RG;
IF (test='0') THEN time <= timeYR;
ELSE time <= timeTEST;
END IF;
WHEN YY =>
r1<='0';r2<='0';y1<='1'; y2<='1'; g1<='0'; g2<='0';
nx_state <= RY;
END CASE;
END PROCESS;
END state_machine_be;
----------------------------------------------------
Nh ta thy, s lng Flip-flop dng thc hin mch l 15 ci: 3
ci cho lu tr trng thi hin ti, 12 ci cn li cho b m.
c th d dng thy kt qu m phng, y ta thc hin gim thi gian
thc t i 100 ln.
Kt qu m phng c ch ra trong hnh di y:
+ ch hot ng bnh thng (stby = 0, test = 0):
106
Hnh 8.11.a. Kt qu m phng TLC ch hd bnh thng
+ ch kim tra:
107
M chng trnh:
-----------------------------------------
ENTITY Bo_phat_tin_hieu IS
PORT ( clk: IN BIT;
outp: OUT BIT);
END Bo_phat_tin_hieu;
-----------------------------------------
ARCHITECTURE state_machine OF Bo_phat_tin_hieu IS
TYPE state IS (one, two, three);
SIGNAL pr_state1, nx_state1: state;
SIGNAL pr_state2, nx_state2: state;
SIGNAL out1, out2: BIT;
BEGIN
----- Phan mach day cua may 1: ---
PROCESS(clk)
BEGIN
IF (clk'EVENT AND clk='1') THEN
pr_state1 <= nx_state1;
END IF;
END PROCESS;
----- Phan mach day cua may 2: ---
PROCESS(clk)
BEGIN
IF (clk'EVENT AND clk='0') THEN
pr_state2 <= nx_state2;
END IF;
END PROCESS;
---- Phan mach to hop cua may 1: -----
PROCESS (pr_state1)
BEGIN
CASE pr_state1 IS
WHEN one =>
out1 <= '0';
nx_state1 <= two;
WHEN two =>
out1 <= '1';
nx_state1 <= three;
WHEN three =>
out1 <= '1';
nx_state1 <= one;
END CASE;
END PROCESS;
---- Phan macpt hop cua may 2: -----
PROCESS (pr_state2)
BEGIN
CASE pr_state2 IS
WHEN one =>
out2 <= '1';
nx_state2 <= two;
WHEN two =>
out2 <= '0';
nx_state2 <= three;
WHEN three =>
out2 <= '1';
nx_state2 <= one;
108
END CASE;
END PROCESS;
outp <= out1 AND out2;
END state_machine;
------------------------------------------
Kt qu m phng:
109
Vi 8 trng thi ca my ny th s lng flip-flop c yu cu ng
vi cc kiu m ho s bng:
+ 3 (=log28), ng vi kiu m ho nh phn.
+ 5 ( n(n-1)/2= 8 => n = 5 ), ng vi kiu m ho twohot
+ 8, ng vi kiu m ho onehot.
110
Chng 9: Thit k thm cc mch
Phn ny chng ta s trnh by cc mch sau:
+ Barrel shifter
+ B so snh khng du v c du.
+ B cng
+ B chia du chm tnh.
+ B iu khin my bn hng.
+ B nhn d liu ni tip.
+ B chuyn i song song sang ni tip.
+ SSD
+ B pht tn hiu
+ B nh
111
M thit k s nh sau:
---------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
---------------------------------------------
ENTITY barrel IS
PORT ( inp: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
shift: IN STD_LOGIC_VECTOR (2 DOWNTO 0);
outp: OUT STD_LOGIC_VECTOR (7 DOWNTO 0));
END barrel;
---------------------------------------------
ARCHITECTURE behavior OF barrel IS
BEGIN
PROCESS (inp, shift)
VARIABLE temp1: STD_LOGIC_VECTOR (7 DOWNTO 0);
VARIABLE temp2: STD_LOGIC_VECTOR (7 DOWNTO 0);
BEGIN
---- Bo dich thu nhat -----
IF (shift(0)='0') THEN
temp1 := inp;
ELSE
temp1(0) := '0';
FOR i IN 1 TO inp'HIGH LOOP
temp1(i) := inp(i-1);
END LOOP;
END IF;
---- Bo dich thu 2 -----
IF (shift(1)='0') THEN
temp2 := temp1;
ELSE
FOR i IN 0 TO 1 LOOP
temp2(i) := '0';
END LOOP;
FOR i IN 2 TO inp'HIGH LOOP
temp2(i) := temp1(i-2);
END LOOP;
END IF;
---- Bo dich thu 3 -----
IF (shift(2)='0') THEN
outp <= temp2;
ELSE
FOR i IN 0 TO 3 LOOP
outp(i) <= '0';
END LOOP;
FOR i IN 4 TO inp'HIGH LOOP
outp(i) <= temp2(i-4);
END LOOP;
END IF;
END PROCESS;
END behavior;
---------------------------------------------
112
Kt qu m phng:
B so snh c du:
lm vic vi s c du hoc s khng du th chng ta u phi khai
bo gi std_logic_arith (c th chng ta s thy trong on m di y).
113
----------------------------------------
Kt qu m phng:
B so snh khng du 1:
Phn m VHDL sau y l bn sao ca phn m c trnh by ( b
so snh khng du).
Kt qu:
114
B so snh khng du 2:
B so snh khng du c th cng c thc hin vi
STD_LOGIC_VECTORS, trong trng hp ny khng cn thit phi khai bo
std_logic_arith.
M thit k s nh sau:
115
Hnh 9.6. S b cng ripple carry
Trn s ta c th thy, vi mi bit, mt n v b cng y s
c thc hin. Bng tht ca b cng y c ch ra bn cnh s ,
trong a, b l cc bt u vo, cin l bit nh vo, s l bit tng, cout l bit nh
ra. T bng tht ta d dng tnh c:
s = a xor b xor cin
cout = (a and b) xor (a and cin) xor (b xor cin)
T cng thc trn ta xy dng chng trnh VHDL nh sau ( y
chng ta c th p dng cho bt k s lng u vo no):
LIBRARY ieee;
USE ieee.std_logic_1164.all;
---------------------------------------------
ENTITY Bo_cong_carry_ripple IS
GENERIC (n: INTEGER := 4);
PORT ( a, b: IN STD_LOGIC_VECTOR (n-1 DOWNTO 0);
cin: IN STD_LOGIC;
s: OUT STD_LOGIC_VECTOR (n-1 DOWNTO 0);
cout: OUT STD_LOGIC);
END Bo_cong_carry_ripple;
---------------------------------------------
ARCHITECTURE arc OF Bo_cong_carry_ripple IS
SIGNAL c: STD_LOGIC_VECTOR (n DOWNTO 0);
BEGIN
c(0) <= cin;
G1: FOR i IN 0 TO n-1 GENERATE
s(i) <= a(i) XOR b(i) XOR c(i);
c(i+1) <= (a(i) AND b(i)) OR
(a(i) AND c(i)) OR
(b(i) AND c(i));
END GENERATE;
cout <= c(n);
END arc;
---------------------------------------------
Kt qu m phng:
116
+ B cng carry look ahead:
T cng thc tnh trn, chng ta vit chng trnh thit k b cng carry
look ahead 4 bit nh sau:
---------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
---------------------------------------------
ENTITY Bo_cong_carry_look_ahead IS
PORT ( a, b: IN STD_LOGIC_VECTOR (3 DOWNTO 0);
117
cin: IN STD_LOGIC;
s: OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
cout: OUT STD_LOGIC);
END Bo_cong_carry_look_ahead;
---------------------------------------------
ARCHITECTURE Bo_cong_carry_look_ahead OF
Bo_cong_carry_look_ahead IS
SIGNAL c: STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL p: STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL g: STD_LOGIC_VECTOR (3 DOWNTO 0);
BEGIN
---- PGU: ---------------------------------
G1: FOR i IN 0 TO 3 GENERATE
p(i) <= a(i) XOR b(i);
g(i) <= a(i) AND b(i);
s(i) <= p(i) XOR c(i);
END GENERATE;
---- CLAU: --------------------------------
c(0) <= cin;
c(1) <= (cin AND p(0)) OR
g(0);
c(2) <= (cin AND p(0) AND p(1)) OR
(g(0) AND p(1)) OR
g(1);
c(3) <= (cin AND p(0) AND p(1) AND p(2)) OR
(g(0) AND p(1) AND p(2)) OR
(g(1) AND p(2)) OR g(2);
c(4) <= (cin AND p(0) AND p(1) AND p(2) AND p(3)) OR
(g(0) AND p(1) AND p(2) AND p(3)) OR
(g(1) AND p(2) AND p(3)) OR
(g(2) AND p(3)) OR g(3);
cout <= c(4);
END Bo_cong_carry_look_ahead;
---------------------------------------------
Kt qu m phng:
118
9.4. B chia du chm tnh.
119
--------------------------------------------------
ARCHITECTURE arc OF Bo_chia IS
BEGIN
PROCESS (a, b)
VARIABLE temp1: INTEGER RANGE 0 TO 15;
VARIABLE temp2: INTEGER RANGE 0 TO 15;
BEGIN
----- Khoi tao va bat loi: -------
temp1 := a;
temp2 := b;
IF (b=0) THEN err <= '1';
ELSE err <= '0';
END IF;
----- y(3): ---------------------------
IF (temp1 >= temp2 * 8) THEN
y(3) <= '1';
temp1 := temp1 - temp2*8;
ELSE y(3) <= '0';
END IF;
----- y(2): ---------------------------
IF (temp1 >= temp2 * 4) THEN
y(2) <= '1';
temp1 := temp1 - temp2 * 4;
ELSE y(2) <= '0';
END IF;
----- y(1): ---------------------------
IF (temp1 >= temp2 * 2) THEN
y(1) <= '1';
temp1 := temp1 - temp2 * 2;
ELSE y(1) <= '0';
END IF;
----- y(0): ---------------------------
IF (temp1 >= temp2) THEN
y(0) <= '1';
temp1 := temp1 - temp2;
ELSE y(0) <= '0';
END IF;
----- Phan du: ----------------------
rest <= temp1;
END PROCESS;
END arc;
--------------------------------------------------
Kt qu m phng:
120
Thit k theo phng php 2:
121
9.5. B iu khin my bn hng.
122
chuyn ti trng thi 35, l 1 trng thi m 1 dime c tr li v 1 candy
bar c phn pht. C 3 trng thi to ra chu trnh kp, l t 1 thanh ko
c phn pht v my tr li trng thi 0. Bi ton ny s c chia thnh 2
phn:
+ Trong phn u: din mo c bn lin quan n thit k b iu khin
my bn hng (nh trong hnh 9.11) .
M thit k s nh sau:
------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
------------------------------------------------------
ENTITY Bo_dieu_khien_may_bh IS
PORT ( clk, rst: IN STD_LOGIC;
nickel_in, dime_in, quarter_in: IN BOOLEAN;
candy_out, nickel_out, dime_out: OUT STD_LOGIC);
END Bo_dieu_khien_may_bh;
------------------------------------------------------
ARCHITECTURE state_machine OF Bo_dieu_khien_may_bh IS
TYPE state IS (st0, st5, st10, st15, st20, st25,
st30, st35, st40, st45);
SIGNAL present_state, next_state: STATE;
BEGIN
---- Lower section of the FSM (Sec. 8.2): ---------
PROCESS (rst, clk)
BEGIN
IF (rst='1') THEN
present_state <= st0;
ELSIF (clk'EVENT AND clk='1') THEN
present_state <= next_state;
END IF;
END PROCESS;
---- Upper section of the FSM (Sec. 8.2): ---------
PROCESS (present_state, nickel_in, dime_in, quarter_in)
BEGIN
CASE present_state IS
WHEN st0 =>
candy_out <= '0';
nickel_out <= '0';
dime_out <= '0';
IF (nickel_in) THEN next_state <= st5;
ELSIF (dime_in) THEN next_state <= st10;
ELSIF (quarter_in) THEN next_state <= st25;
ELSE next_state <= st0;
END IF;
WHEN st5 =>
candy_out <= '0';
nickel_out <= '0';
dime_out <= '0';
IF (nickel_in) THEN next_state <= st10;
ELSIF (dime_in) THEN next_state <= st15;
123
ELSIF (quarter_in) THEN next_state <= st30;
ELSE next_state <= st5;
END IF;
WHEN st10 =>
candy_out <= '0';
nickel_out <= '0';
dime_out <= '0';
IF (nickel_in) THEN next_state <= st15;
ELSIF (dime_in) THEN next_state <= st20;
ELSIF (quarter_in) THEN next_state <= st35;
ELSE next_state <= st10;
END IF;
WHEN st15 =>
candy_out <= '0';
nickel_out <= '0';
dime_out <= '0';
IF (nickel_in) THEN next_state <= st20;
ELSIF (dime_in) THEN next_state <= st25;
ELSIF (quarter_in) THEN next_state <= st40;
ELSE next_state <= st15;
END IF;
WHEN st20 =>
candy_out <= '0';
nickel_out <= '0';
dime_out <= '0';
IF (nickel_in) THEN next_state <= st25;
ELSIF (dime_in) THEN next_state <= st30;
ELSIF (quarter_in) THEN next_state <= st45;
ELSE next_state <= st20;
END IF;
WHEN st25 =>
candy_out <= '1';
nickel_out <= '0';
dime_out <= '0';
next_state <= st0;
WHEN st30 =>
candy_out <= '1';
nickel_out <= '1';
dime_out <= '0';
next_state <= st0;
WHEN st35 =>
candy_out <= '1';
nickel_out <= '0';
dime_out <= '1';
next_state <= st0;
WHEN st40 =>
candy_out <= '0';
nickel_out <= '1';
dime_out <= '0';
next_state <= st35;
WHEN st45 =>
candy_out <= '0';
nickel_out <= '0';
dime_out <= '1';
next_state <= st35;
END CASE;
END PROCESS;
END state_machine;
------------------------------------------------------
124
Kt qu m phng:
125
err, data_valid: OUT BIT);
END Bo_nhan_du_lieu_nt;
---------------------------------------------
ARCHITECTURE arc OF Bo_nhan_du_lieu_nt IS
BEGIN
PROCESS (rst, clk)
VARIABLE count: INTEGER RANGE 0 TO 10;
VARIABLE reg: BIT_VECTOR (10 DOWNTO 0);
VARIABLE temp : BIT;
BEGIN
IF (rst='1') THEN
count:=0;
reg := (reg'RANGE => '0');
temp := '0';
err <= '0';
data_valid <= '0';
ELSIF (clk'EVENT AND clk='1') THEN
IF (reg(0)='0' AND din='1') THEN
reg(0) := '1';
ELSIF (reg(0)='1') THEN
count := count + 1;
IF (count < 10) THEN
reg(count) := din;
ELSIF (count = 10) THEN
temp := (reg(1) XOR reg(2) XOR reg(3) XOR
reg(4) XOR reg(5) XOR reg(6) XOR
reg(7) XOR reg(8)) OR NOT reg(9);
err <= temp;
count := 0;
reg(0) := din;
IF (temp = '0') THEN
data_valid <= '1';
data <= reg(7 DOWNTO 1);
END IF;
END IF;
END IF;
END IF;
END PROCESS;
END arc;
-------------------------------------------------
Kt qu m phng:
126
Hnh 9.14.Kt qu m phng b nhn d liu
Trong :
+ d(7:0) l vector d liu gi i
+ dout l u ra thc t.
+ clk: u vo ca xung clock
+ load: u vo xc nhn
Vector d c lu tr ng b trong thanh ghi dch reg. Khi load
trng thi cao th d liu c np vo thanh ghi dch theo th t bit MSB l
bt gn u ra nht, v u ra l d(7). Mi khi load tr li 0 th bit tip theo
c xut hin ti u ra ca mi sn dng ca xung ng h. Sau khi tt c
8 bit c gi i, u ra tr li mc thp cho n ln chuyn i tip theo.
127
M thit k nh sau:
LIBRARY ieee;
USE ieee.std_logic_1164.all;
-------------------------------------------------
ENTITY Bo_chuyen_dl_ss_nt IS
PORT ( d: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
clk, load: IN STD_LOGIC;
dout: OUT STD_LOGIC);
END Bo_chuyen_dl_ss_nt;
-------------------------------------------------
ARCHITECTURE Bo_chuyen_dl_ss_nt OF Bo_chuyen_dl_ss_nt IS
SIGNAL reg: STD_LOGIC_VECTOR (7 DOWNTO 0);
BEGIN
PROCESS (clk)
BEGIN
IF (clk'EVENT AND clk='1') THEN
IF (load='1') THEN reg <= d;
ELSE reg <= reg(6 DOWNTO 0) & '0';
END IF;
END IF;
END PROCESS;
dout <= reg(7);
END Bo_chuyen_dl_ss_nt;
-------------------------------------------------
Kt qu m phng:
128
Hnh 9.17. S ca SSD
Mch ca chng ta s to ra mt s chuyn ng lin tc theo chiu kim
ng h ca cc on SSD. ng thi n cn to ra s dch chuyn chng lp
gia cc thanh k nhau. Chng ta c th biu din quy trnh ca n nh sau:
a->ab->b->bc->c->cd->d->de->e->ef->f->fa->a.
129
CONSTANT time2: INTEGER := 2; -- Gia tri thuc te hien thi is
30
TYPE states IS (a, ab, b, bc, c, cd, d, de, e, ef, f, fa);
SIGNAL present_state, next_state: STATES;
SIGNAL count: INTEGER RANGE 0 TO 5;
SIGNAL flip: BIT;
BEGIN
------- Phan mach day cua arc : ------------
PROCESS (clk, stop)
BEGIN
IF (stop='1') THEN
present_state <= a;
ELSIF (clk'EVENT AND clk='1') THEN
IF ((flip='1' AND count=time1) OR
(flip='0' AND count=time2)) THEN
count <= 0;
present_state <= next_state;
ELSE count <= count + 1;
END IF;
END IF;
END PROCESS;
------- Phan mach to hop: ------------
PROCESS (present_state)
BEGIN
CASE present_state IS
WHEN a =>
dout <= "1000000"; -- Decimal 64
flip<='1';
next_state <= ab;
WHEN ab =>
dout <= "1100000"; -- Decimal 96
flip<='0';
next_state <= b;
WHEN b =>
dout <= "0100000"; -- Decimal 32
flip<='1';
next_state <= bc;
WHEN bc =>
dout <= "0110000"; -- Decimal 48
flip<='0';
next_state <= c;
WHEN c =>
dout <= "0010000"; -- Decimal 16
flip<='1';
next_state <= cd;
WHEN cd =>
dout <= "0011000"; -- Decimal 24
flip<='0';
next_state <= d;
WHEN d =>
dout <= "0001000"; -- Decimal 8
flip<='1';
next_state <= de;
WHEN de =>
dout <= "0001100"; -- Decimal 12
flip<='0';
130
next_state <= e;
WHEN e =>
dout <= "0000100"; -- Decimal 4
flip<='1';
next_state <= ef;
WHEN ef =>
dout <= "0000110"; -- Decimal 6
flip<='0';
next_state <= f;
WHEN f =>
dout <= "0000010"; -- Decimal 2
flip<='1';
next_state <= fa;
WHEN fa =>
dout <= "1000010"; -- Decimal 66
flip<='0';
next_state <= a;
END CASE;
END PROCESS;
END arc;
--------------------------------------------------------
Kt qu m phng:
131
Tn hiu ca hnh 9.20 c th c m hnh nh mt FSM 8 trng thi.
S dng b m t 0 n 7. Chng ta c th thit lp mt sng bng 0 khi
bin m = 0 ( xung th nht) v bng 1 khi bin m = 1 (xung th hai),
vvnh trong hnh 9.20. thc thi c b to sng ny th yu cu 4
flip-flop: trong c 3 ci lu tr s m (3 bit), mt ci lu tr sng (1
bit ). thit k b to sng ny, chng ta thit k theo kiu 2, c th s nh
sau:
-----------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
-----------------------------------------------------
ENTITY Bo_phat_tin_hieu IS
PORT (clk: IN STD_LOGIC;
wave: OUT STD_LOGIC);
END Bo_phat_tin_hieu;
-----------------------------------------------------
ARCHITECTURE arc OF Bo_phat_tin_hieu IS
TYPE states IS (zero, one, two, three, four, five, six,
seven);
SIGNAL present_state, next_state: STATES;
SIGNAL temp: STD_LOGIC;
BEGIN
--- Phan mach day: ---
PROCESS (clk)
BEGIN
IF (clk'EVENT AND clk='1') THEN
present_state <= next_state;
wave <= temp;
END IF;
END PROCESS;
--- Phan mach to hop: ---
PROCESS (present_state)
BEGIN
CASE present_state IS
WHEN zero => temp<='0'; next_state <= one;
WHEN one => temp<='1'; next_state <= two;
WHEN two => temp<='0'; next_state <= three;
WHEN three => temp<='1'; next_state <= four;
WHEN four => temp<='1'; next_state <= five;
WHEN five => temp<='1'; next_state <= six;
WHEN six => temp<='0'; next_state <= seven;
WHEN seven => temp<='0'; next_state <= zero;
END CASE;
END PROCESS;
END arc;
-----------------------------------------------------
Kt qu m phng:
132
Phng php truyn thng:
Chng ta thit k b pht tn hiu theo phng php truyn thng vi
cu lnh IF nh sau:
---------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
---------------------------------------
ENTITY Bo_phat_tin_hieu2 IS
PORT (clk: IN BIT;
wave: OUT BIT);
END Bo_phat_tin_hieu2;
---------------------------------------
ARCHITECTURE arc OF Bo_phat_tin_hieu2 IS
BEGIN
PROCESS
VARIABLE count: INTEGER RANGE 0 TO 7;
BEGIN
WAIT UNTIL (clk'EVENT AND clk='1');
CASE count IS
WHEN 0 => wave <= '0';
WHEN 1 => wave <= '1';
WHEN 2 => wave <= '0';
WHEN 3 => wave <= '1';
WHEN 4 => wave <= '1';
WHEN 5 => wave <= '1';
WHEN 6 => wave <= '0';
WHEN 7 => wave <= '0';
END CASE;
if count = 7 then
count := 0;
else
count := count + 1;
end if ;
END PROCESS;
END arc;
---------------------------------------
Kt qu m phng:
133
ROM (Read Only Memory): B nh ch c v ghi: S ca ROM
c ch ra trong hnh 9.23. V ROM l b nh ch c, khng c tn hiu
clock, chn cho php ghi, n ch c tn hiu vo bus a ch v tn hiu ra l bus
d liu.
134
Hnh 9.25. RAM vi ng d liu tch ri
135
Kt qu m phng:
M thit k s nh sau:
-------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
-------------------------------------------------
ENTITY ramc IS
GENERIC ( bits: INTEGER := 8; -- # of bits per word
words: INTEGER := 16); -- # of words in the
-- memory
PORT ( clk, wr_ena: IN STD_LOGIC;
addr: IN INTEGER RANGE 0 TO words-1;
bidir: INOUT STD_LOGIC_VECTOR (bits-1 DOWNTO 0));
END ramc;
-------------------------------------------------
ARCHITECTURE arc OF ramc IS
TYPE vector_array IS ARRAY (0 TO words-1) OF
STD_LOGIC_VECTOR (bits-1 DOWNTO 0);
SIGNAL memory: vector_array;
136
BEGIN
PROCESS (clk, wr_ena)
BEGIN
IF (wr_ena='0') THEN
bidir <= memory(addr);
ELSE
bidir <= (OTHERS => 'Z');
IF (clk'EVENT AND clk='1') THEN
memory(addr) <= bidir;
END IF;
END IF;
END PROCESS;
END arc;
-------------------------------------------------
Kt lun
137
Ngy ny vic ng dng VHDL trong vic thit k mch v chp ngy
cang nhiu. Cng ngh ny ang l xu hng ca thi i, n gin v n
khng ch tiu tn t v tin bc m n cn gip cho chng ta n gin trong
vic thit k phn cng.
Trn y, chng ta trnh by mt cch khi qut v phng php thit
k cc mch. Nhng mch c bn nht c chng ta thit k mt cch chi
tit, hon thin. y l c s cho nhng thit k ln hn v phn cng, thit
k cc ng dng cho cc FPGA, ASIC.
138