BP vszeizs oob4ens sl ; INTEL CORP {UP/PRPHLS? 12e D 80286 THVT HE High Performance Microprocessor with Memory Management and Protection (80286-12, 80286-10, 80286-8) tm High Pertormance Processor (Up to six m Two 8086 Upward Compatible times 8086) praing Modes: = "8086 Heal Address Mode ws Large Accovtes Phyctoal Protected Virtual Address Mode =1aigabyte Virtual per Task ws Range of Clock ten tu integrated Memory Management, Four 12-5, MIs fos SY imtegraremory Protection and Support — 20, for C0206 10 for val temery ana ‘Operating ee ees High Bandwidth Bus intrtace 1 Somplate System Development (12.5 Megabyte/Sec) Development Software: Assembler, im Industry Standard 0.8. Support: PL/M, Pascal, FORTRAN, and System utiities = In-Cireult-Emulator (ICET™-266) m Avaliable In 68 Pin Ceramic LOC (Ceadiess Chip Carrier), PGA (Pin Grit ‘Array), and PLCC (Plastic Leaded Chip ‘= Optional Processor Extension: High Performance 80-bit Carrier) Packages Numeric Data Processor (Gen Paani Ses, Or #23189) “The 60286 i an advanced, high-performance microprocessor with specaly optimized capabities for multiple ree oo tasking ayatoms, Tho 60286 has bultin memory protection that supports opsrating system and User an ion as well aa program and data privacy within tasks. A 12 MHz 60286 provides si tes oF more a Mpput ian the stanaara® Miz 6086, Tha 60288 includes memory managoment capabites that map 299 {One agabyte of virtual address space per task ino 2 bytes (16 megabytes) of physical memory “The 60286 ts upward compatible with 8086 and 88 sofware, Using 8088 real address moda, the 80206 is TBject vodo sompatbla with existing 8086 88 sofware. n protected vtual adress mode, tho 80286 s ouce blest cone ol with 8086, 68 software and may require upgrading to uso virtual addrosses supported by the Fees ee negrated momary management and protection mechanism. Beth modes operate at fll 80268 per- formance and execute a superset of the €026 and 88 instructions. ‘Tne 20286 provides special operations to suppor the efficient implementation and execution of operating 2a Prcuanple one instruction can end execution of one task, sav is stato, switch toa now task load FO ule of tho now task, The 60289 also supports vitual memory systems by roving & ot present exception and rostrtabe instructions YEN and ME-00S are tadomars of Most Cor. inca tadorark a Bl Labs or ATT Figure 1, 80206 Internal Block Diagramintel J vsen2s couse ff 80286 PENTEL CORP {UP/PRPHLS? 42e 7 T-49-17-16 ‘Component Pad Vews—As vowod tam underside of mr mounted on to board ‘0 of to PC aid, Pe. Board Views—Ae vowed from the component a fadedatadetecssa? IN. signa must not bo connected Figure 2.80286 Pin Configuration 92intel BE ve20125 couuee0 af 80286 INTEL CORP {UP/PRPHLS? LE D-T-49-17-16 ‘The folowing pin function descriptions are forthe 80286 microprocessor: ‘Table 1.Pin Description Symbol Tyee ‘Name ae Function uk “SYSTEM CLOCK proves ho fundamental ring for A0888 asta, is divided by wo eS enseobse to goerte he prooenar lock. Tho ral Gey Avo ccc ree thontaad oan enteral eck genarator by a COW i HIGH Waneonon tho RESET oa DiaDo DATA BUS input data rng many, 70, an toup ackrowledgp ead ls ina deta rng merry and VO witocyels. The data buss ecine HIGH and oat to ‘State OFF drag bus hd acknowodge Fea-he “ADDRESS BUS oct physical emery a7d1/O pont adress, ADTs LOW whon daa {Rrottensionedon pins yan Aea-Ag we LOW Gurg\/O vans. Tho aceoss bs fs ‘eve igi and ots otal OFF dung bus hol exknowedge ‘BUS HIGH ENABLE rccatosransler or data cn th upor be ofthe data bus Diao lg oented device assgradto teu ihe data os would neal se se on eip ole tance, BHE acive LOW and fost 0st OFF cing bushot aceraniodge. ‘BRE ana Av encodings BE Vaive | Aovatue Funcion | ° | Wordwvansor ° {| Bytovanster on upper al of ta bus Oy5-D) 5 | Bho aneter on ower hat of ata bus (07-0) 1 $__ | witeoreeceu {BUS GYGLE STATUS indicates ion of bus cyl and, long wah M7 and GOO BE Ssenes te pe tbs eye, no buss iva, sat whenever ono oF oth a LOW. Bass Sb ar geite LOW andes o3 tale OFF dug bus hls acknowedge [cena wis [SE 105295 Bus Cycle Statue Detinivon Ed ‘ue Cyl nated Tnjeptacknowioooe in nt oar Wileat cour Nona nota satus ck eat = t banal ls shutdown Memory aa toad 300 0 None nota statis oye wir cour Vo reed owe Nona nota status ecto Memon rtuction rd cH wi TWENORY VO SELECT dings memory accos fom V0 access. THIGH dung Ty 0 aor te sraal/ shutdown cyto sn proves. LOM. an VO eye ran nar sametfcbge cles nprostens, WT foal o-stale OFF dig bua hed acknowledge. Cod ‘CODETINTERRUPT ACKNOWLEDGE dinghies Isrucon fet cycles kom memary Sera jee. Also daerquehes ntorup acknowledge eyes ram V0 oye. CODY AaB RanS to tte oF ering bus hold achoogo. stings th sae as MZ. | toex ‘BUS LOCK nal het oer syeiom bus maser. oto gain conta othe ayer ree ek ea ands tlemg tus ejl, The LOCK sigarmay be aca expiity pases eet weten rt of atomatcaty by 60286 hardware dung Mmery KCHG on coca. ntl sexed or cosrgtr able acces, LOCKsacbve LOW end fea or sate OFF doing bs ai ckrowedne, BUS READY tring e bus cyl. us cys ove onendod wihow Ht clined By READY LOW READY Is an seve LOY cynctnonovs nou rung set an ls Pre flaivsto its atom dockbe met fo" carer operation READY is nore dung shal ackrowledo, 33J voesars cower sf 0286 INTEL CORP {UP/PRPHLS} U2 D_T-49-17-16 ‘Table 1.Pin Description (Continued) ‘Symbal Tee Name end Futon 7 Ow rv ‘BUS HOLD REQUEST AND HOLD ACKNOWLEDGE contra omerahip of inne ° {ha 80206 oe! bus. The HOLD input allows actor oe! bs mest 0 ‘equal conto oth locals When contol grand, te 0208 wl Boat : Usbusciversto2-stte OFF ond then atvalo LDA. tus enering tho bas tt actnomloggeconauon. he ca us wi roman gered 0 ‘oquesting maser uns HOLD Dacor nace wh ess the 90206 Conaway HILDA and vgaring cool fe oa! us. Ts tries the fs fot eckrowleapeconstion HOLD maybe asyetvonovs to hosts ‘ole Thess sgnalo are acive HIGH, wie 7 TNTERAUPT AEQUEST requsts ho 60286 o suependiscoren roarer | {reeuton and somos a pending extra equest narupl requests are ‘masked wnonever te orapt orale nth lag words lore When {ha 00206 renponds fo an htoruptroquest performs wo trun chnomlodge bus eyes torend an 8th orp vector at os ource of th terap To sur progam ntarupton, NTR mustremein atte ul ro frtrerupt acknowoogo oj compet. NTA s Saelod at ne bagoning ot each processor eycl and must ecive HIGH ‘Ties two proceso jes bstore the carter nsucion ends in odar0 herp! before the net siicton IRs ot sonst, aclve HIGH, and fay be seypcronous to the sstom cock, < oo 7 TWON-MASKABLE INTERRUPT REQUEST Fitts Ue 00205 whan ‘Sromatysueled voto value o No erupt exnowedge oc [evtonmes The rtorupt net tin tne 60265 a wor doa Fut Nl inputis acl HIGH may bo asyeconous fo the system (Sek, en is ogo iggeres ator! syntoniaton. Fox prope fecognton the putin nave Been pono LOW for atest our sysiom (Soak eyes endvemain HIGH for atfent few eye cock yes ‘PROCESSOR EXTENSION OPERANO REQUEST AND ACKNOWLEDGE ° ond ine momery management an potooton copa ofthe 00206 1 {rocesor manson, The PERE put requests tha 20206 opt a ‘ns oprand ane: procaseor xtnsion. Ta PEACK output siga's {huprecossorontasion wan the request prad is boing ented. PERco' achve GH and foals Wo Sstale OFF dng bus Pod ymchvenaus to th system lock PERCR s PERE ERK sd T ‘PROCESSOR EXTENSION BUSY AWD ERROR indeate the operating ERROR 1 Coton of procosor etanion othe 60286 An acte BUSY nut slops oa8e rege nacaton en WAIT an some ESC nection unt BUSY becomes ctve ph). The C0208 maybe erupted whe waling for Sncomo hasive Av abe ERROR mp causes ra 602861 ‘ovo procossorxtosion strap whon oxoclng WAT or some ESC [etc These np are actvo LOW and maybe asynchongus 1 ho ‘yotom lek, Thess pul have aeral pup resists 8INTEL CORP 20% (2Vcapaciormutt bo connect btwoon spn ad round This capcior er the output of ‘hoirtemal ubsbate bias gnarter Amana OCteahage ren of pA 'tlowad tog tho capsctor. For eoraetopuratin ol tho 0026, the subetrat as generator mis charge tis cepacor ot operating vollage The cpactorearpeup tina Imiisoconds (max) ater Vor and CLK reach tha apecieg AC ans OC faramelor, RESET may be applodto grovel spun etry by the CPL ‘hing tis bime. Arh to, 80266 proaonsar cock can “ynetvorzed to anor lock pusing ESE LOM sytvoncus othe ck nove: {HUD is eny Low it HOLD I hactve (Low osi INTEL” CORP {UP/PREHLS? FUNCTIONAL DESCRIPTION Introduction ‘The 80266 san advanced, high-pertormane micro- processor with epecaly optimized capabilioe for ‘ultpio sor and mull-asking syetame, Depending (on the application, a 12 MHz 60286's pertormance stor than tho standard § MHz 2086's, wile providing compat softwaro empaty wih nas 6089, 88, and 106 family of U's. ‘The 80206 operates in two modes: 8086 real a dross mode and protected viral address: mode. Both modes exocute a superset ofthe 8088 and 86 Instuction set {In 8086 real address mode programs use rel ‘resses with up to one megabyte of address space, Programs use vitual addresses in protected vidual ddrass mode, also called protected mode, In pro- fected mode, tho 60286 CPU automatically maps 1 ‘igabyte of vitual addresses: por task inlo @ 16 ‘megebyle real address space, This mode also pro. vides mamor protection to aolaatho operating system and ensuro privacy of each tasks’ programs ata. Both modes provide tho eame base ine ruction set, registers, and addressing modes. ‘Tho following Functional Description describes fist, tho base £0226 architecture” common to. both ‘odes, second, 8086 roal adress mode, and thd, protected mod, 80286 BASE ARCHITECTURE ‘The 8086, 88, 188, and 286 CPU family all contain the samo basic set of registers, instructions, and Bi vsei7s oowwes off soe UAE D~T-49-17-16 ‘adéressing modes. The 80286 processor is upward ‘compat with the 8086, 8088, and 80186 CPU's, Register Set ‘Tho 80286 base architecture has fiteen registrs as, shown in Figure 3. These registrs are grouped into ‘he following four catogore General Registers: Eight 16:bt general purpose feaistes used to contain arthmetc and logical op ands, Four of these (AX, BX, CX, and DX) can bo Used ether in thoi one as 16-3t words or spl Into pairs of soparate 8-8 rogisters, Four 16-bit special purpose Tegiators select, at any given time, the eogments of ‘memory tht ar immediately addressable or code, stack, and data, (For usage, refer to Memory Organ zal ‘Segment Registrs ‘Base and Index Registers: Four of tho gonoral pu asters may also be used to determina offset ‘addresses of oporands in memory. These registers ‘may contsin base addresses or Indexes to paricular locations within a segment. The adcrossing mode determines the specie registers used for operand address calulations, ‘Statue and Control Registers: Tho 3 16-bit spocil Purpose rogistrs In figure 3A record or control oer {ain aspects of tho 80286 processor stato including the Instron Pointer, which contains the ofset ack ‘tess of the next saquontal instruction fo be exacot od aeraintel seate INT*: CORP {UP/PRPHLS} waaur7s aowwees Of 22E DP =7-49-17-16 Figure da. Status 3nd Control Reglater Bit Functions ‘Table 2. Flage Word Bit Functions. Flags Word Description a ‘The Flags word (Flags) records speci Pietra Position | Name ie Meare resutotigca andartmete newetons [PS aoe tno. 2 8 and) arcane creation ary orto cares oer Gin eats wine guonoperang mode (ts oe ei hd'0), Mags oa Toth ropa. The uncton of he F | Ramee settee fag bats genta 80 acces 7 [FT lence tom bacon ibe Eonar cose Instruction Set Se 3 [iF | 2orohagSartnatn Tho suction ets dvided into sven catogoin: oF og—Sei Bin ars stole avoumrogeaerng | |_| Sodan fmerbulton, cowel Wanse, gh lve etvs Serie, Steal ont end procosorconvak hese cetegorce |_| wt ge fumnotued gute 7 row FS teat : ‘ergo an orate ema seg oa ‘An 80286 instruction can roerence 2270, on negative runber (excusing 2 ‘operands; ere an operand resides in 8 reg of ‘otherwise mani tho ntuclon tel, ori memory. Zerooperandin- : = stusore (og. NOP end FLT) ao vualy ono bye | © | TF | Saastprieg Oncor ion. Gnecpeand revuctore (oa, NC and DES) Secieostoncase ee trois to bs long bul some ae encoded a Stata ae do ant Siyene be Oneoperen etucions may ele: | —g—{—-—y seuss ee treo 8 rogeler or memory locaton. Two-eperand persicracereta tenses Inoatins porn tho foowng ai ype uc eeitoratstc aera can fon operation coved gehts Wo] OF | reson rg Rag t Rogier nce aoe Bere hontot Ceaing DE emer needle o Regitr orintent —Momory to Mornory —Ragister to Mamory Immediate to Memory a7DB s826175 oneunas aq intel 20206 CORP {UP/PRPHLS} L2E D-T-49-17-16 “wo-operand instuctons (09. MOV and ADD) ae Miagtes cages Of Mansytomeney [a5 peralon aro proved by o epoca Case f sting ‘atuctone fecunng ono io tweo bytes, Forder [ACS | Addy woah cary tuted iratcton one ang encoding far to tho [INC | — terenen sor wordy Inetctonsotsummayettond of fis document, [Asx | Ast aus or ation For detaed oporaton and usage of cach insruc. | O88 | Secnatutraton En, so aponedn of S000 Poweanmere Rel SUBTRACTION ‘ance Man (Orr No. 21048), Bs] bate ono GENERAL PURPOSE 308 | Settee ows bao 67 ow ie arn ‘eC__| — Docranom awed 7st Puch wed oi wick NEG | Hoga bo woe ror er of ck CGvP | — Gon cr wor USA | —Pushalropaos onc AAs | —Asciaguster sbrdion POPA op roger tomick a OI 56H Enchange eo HULTIPLCATION sar Tiana ToL [Mtl or worse TRRUTOUTPUT TUL | — nog eyo word W inp ove fad ——| AC ait ay [our abate cr wed DiIOn ‘RODRESS OBJECT DAY [ory end ied Te ‘ondectvoadons TOW | — oe dn i cr wed i dot ng BS aio —| ASG anton ies doin sng ES GoW | Gomer ower C Fie TaANGrER CHO | —Comor wod ts dotionad Tae ond A garage Figure ab. Arithmetic instructions Fg Sire ght es. PUSH hag oro ck Toaeals OFF ep ag ack + [RTF red Figur 4, Daa Tranter ntrctons| AN [ ant ovr OR] ne oon oer Ts Tio baa waaay xR | "tscui o” tor word ins in wed sg Test | “tet boomers ours Gaps o wo ata SHIFTS ours Corpse o word srg HEAL Sa anne ope oa SAS Seay or wed tig SHA] Stiga hte Lo0s Ceeacatate Saft] shit artimete righty od S108 Sinwiyi ood rg ROTATES ie fost FOL | Roa armed EPETREPE | Rept wi mine FoR | Rott iis ovo TEDNORERG[ Resestonioratoqalratzne | [AGL | Folate can etiecr wid GR | Rot oop any hyo word Figure 4c, String Instructions Figure 4d, hitt/Rotate Logical Instructions 28Pp ezeis oousuee 99 80286 INTEL CORP {UP/PRPHLS? LE D-7-49-17-16 ~"GoNTIONAL TRANGFERS ‘WNGONDTIOWAL TRANSFERS ANGE | Jump abovernot below vorequl | — CALL ‘Caproesdre IAE/NG— | — Jump ebove or equtnatboiow | _ RET etum fom accede IB/ANAE | — Jump below/not above or eaul_| _ IMP ume IBE/INA™ | “Junpilow or egal above © unpiteary TTERATION CONTROLS EAE Sump equals JG/NLE | —Jumpitesterretossorequal | LOOP Loop i JQE/INL | — Jump i pester or equations WOOREROORE Lop equal ame “HLINGE —[ dp fess/ot greater noc equal | LOOPNE/LOOPRE | Loop ot equl/natzo : JLEVING | — Jowpfies or eque/ot greater cod in Heiter OX = 0 ING supe INET | — Jowpitnt equal 206 NTERRUPTS, INO Sump fot ver INP/IPO | _ Jonpit ot prtypey od cu Inert NS: ump fet sn INTO, inp raion ra Sump foveriow ET neropt rota {IPAIPE | — Joni partypey oer B im tsign Figure 4 Program Transfer instructions FLAG OPERATIONS Memory Organization se Seteae tea Memory is organized as sot of variable ongth s09- ee Ges cary tog ments, Each sogmant naar contiguous. so: (CC | Component x fag, ‘uence of up 164K (216) G2 bytes. Momory lo S10 a recon fag atddrossed using a two component aderess (a point- ‘cw Gie Sreaion n ‘0 that consists of a 16-bit sogmont selector, and a a ee Je-bioflset. The segment selacor indicates the de- sired sogmont in memory. The offot component in (Gu | — Goorin ons og + ates tho dasrod bye adoss within the segment. EXTERNAL SYNCHRONIZATION Hct Hal uniter es ‘WAIT | — Wat tor BUSY ntact E50 Excpe wonensonroeisor | sserpooren Loox Leck bs sing next insuton THO OPERATION ae Tar ——[— nooperaton | EXEGUTION ENVIRONMENT CONTROL sce |) ree TSW Load mechine sta word SEW machin ua word Figure df. Processor Control instructions eR | Female 4 4 a — BOUND | Dele ves ose rcibd ge oss Figure 4g, High Level Instructions Figure 5. Two Component Address8028 INTEL CORP {UP/PRPHLS} yeaea7s ooente? © 6 VED. T-49-17-16 ‘Table a. Segment Register Selection Rules Temory ‘Segment Register Tipe Segment Reterance Needed eed Selection Rule Traction Geaaics) ‘Aukemawi naire prloich ‘Slack ‘Stack 68) ‘Al slack pushes and pope. Ary meneny erence wiiavuses BP fs bese regi, Tooele ‘Baa 5) ‘Al data earoncos excpl whan lave To iackor ‘rg dosinaton ‘Eernal Gebaj bata | 60a ES) ‘Aenale dala sent and dovinaton of ting operaion ‘Al instructions that adéress operands in. memory ‘must speciy the sogmant and th oftet. For speed land compact instruction encoding, segment selec- tors aro Usual stored in tho high spood segment registers. An instruction need specity only the de- Sted sogmont ragistar and an offset fn ordor toa ‘ress a momory operand. [Most instructions need not explicitly specity which ‘segment register I Used, The correct segment reg- is automaticaly chosen according to the rules ff Table 8. These res follow the way programs are ‘witen (soe Figura 6) a8 independent modules that equi areas for coda and dats, stack and access to external data areas. ‘Special segment override instuction prefixes allow the impli segment rogistor solacton rules to bo ‘overidden for spacial cases. The stack, data, and fxtra segments may coincide for simple programs. ‘To access operands nat residing in ane ofthe four immediately avaiable segments, a full 2-0 point ‘ora naw segment selacior must be loaded. “Tho 80286 provides @ total of eight addressing moses for Instructions fo specly operands. Two ad- ‘ressing modos. aro provided for instructions that ‘perato‘onrogitar or inmediato operands: Reglater Operand Mode: Tho operand is loc ‘0d mn one of th 8 oF 16-bit gonoral registers. Immediate Operand Mode: The oporand is in- ‘cided inthe Instruction. ‘Six modes are provided to specty th location of an ‘operand Iva memory segment. A memory operand fadéress consists of two" 16-11 components: s69- Tent selotor and offset. Tho segment selector is Supplied by a gogment rgistor either imply cho- sen by the addrescing mode or explcily chosen by regment override profi. The offal is calculated by summing any combination of the following three dross olomonts: tho dleplacement (an 8 or 16:bi immediate val- ‘us contained inthe instruction) the base (contents of either the BX or BP base rogistrs) 340 Figure 6, Segmented Memory Helps ‘Structure Software the Index (conten of either tho St or OI index registers) ‘Any cary out from the 16-bit addon is ignoced Elght-it isplacomonts are sign oxtonded 10 16-bit values. Combinations of these three address elements de- fin ho ab memory arssng aes, devcbed Direct Mode: The operand’soffsot is contained in the instruction as an 6 or 16 dsplacoment ele- ment Reglater indirect Mode: Th operands offset sin ‘one of the ragsters SI, 0, BX, or BP. ‘Based Mode: The oporand'soffst is tho sum of an 8 or 16-01 dplaoement and the conten ofa baso rogstor (BX or BP)i INTEL CORP Hi} Sopmant 1 Wiese | W= 0. Data sogmant may not be witon i. » W= 4 _Datasogmentnay be witen i. aa z FrseaabiG) | E= 1 Code Segment Desir pe i riomingt@) | C= 4 sagront ray ony be execu Ce \when GOL =DPL and CPL Tomas mehangod. 1 Pesdabie(R) Code sepnant may notbo road FL 1__Codesepentmay bo read o ‘AecoseadTA) | A= 0 Sogmont has ot been access. ‘A= Segment elector hes boon taded into sogmont reper riod slot teat neuctona, Figure 11, Code and Data Segment Descriptor Formats 34188028 INTEL CORP {UP/PRPHLS? Code and data (including stack date) are stored in two typos of segments: code segments and data, ‘segments. Both iypes are denied and defined by opment doserplors (S = 1). Code segments aro Idontied by the exocutablo (E) bit eot to 1 in tho ‘descriptor access rights byte. The access ghs byte ‘of both code and data sogment descriptor typos hhavo three fields In common: present (P) bit, Do- scrptorPrviloge Lovel (OPL), and accossad (A) bt IVP = 0, any altompted uso of this sogment wi ‘causo a not present exception. DPL species tho priioge level of the segment descriptor. DPL con- frols when the descipior may be used by a task (ater to privilege lecussion below). The AD shows ‘whathar the sogment has been previously accessed {or usage profiing, a necessly for vitual memory systoms. The CPU will always Set this bt when ac- essing the descripter. Data segments (S = 1, E = 0) may be alther road- cnly of read-write as controled by the W bit of tho fccess rights byte. Read-only (W = 0) dala sog- Imants may not be weiten into. Data sogmonts may determined by the Expan- segment descriptor is interpreted cferenty depending on the ED bit (600 Figure 11). ‘A code sogment ($= 1, E = 1) may bo oxocute- ‘only of exeeute/foad a8 determined by the lead. ablo (A) Bi Codo sogmonts may nover bo writin into and executo-only coda sogmonts (R= 0) may ‘ot bo read. A code sogmont may also have an at ule cad conforming (CA contarming cose sea. ‘mant may be shared by programs Uh Gitoront Pvtope level, fhe GPL ofe soning ode segment defines the range of pivlage levels fat which the sagment may be executed (eer to piv- jogo discussion below). The mit eld entifes tho last byte ofa code segment. ‘SYSTEM SEGMENT DESCRIPTORS (6 ~ TYPE ~ 1-3) In addon to code and data sogmont dosciptors, tho protactad mode 60286 datines System Sogmont Doseritors. Those descripors dotino spectal sys tom data segments which contain a tablo of doscrp- {ors (Local Descriptor Table Descriptor or sogmonts which contain the execution sala of a task (Ta State Segment Descriptor) Figure 12 givos the formats forthe special systom dala sogmant descripors. The descriptors contain a 24-bit base adaross of tho sogmant and a 16-i fin i The access byte detinas tho ype of doserptr, Is Slate and prviege lve. The desriptor contant valid and the segment i in pisical IP = 0, the segment is aot va ‘only usod in Task Stato Segment descriptors a Indicates tho priviogo lovel at which the doscrip- aa? Ne2bl75 OobuL34 3 ff VE D —T-49-17-16 tor may be used (669 Privilege). Since the Local Oo scriptor Table descriptor may only bo used by a apo cial privleged instruction, the DPL ld isnot used. Bit 4 of tho access byte ls 0 to Indicate tht itis a system control descriptor. The type field species ‘he descriptor type as Indcated in Figure 12. System Segment Descriptor “hat on st 0 compet a 4008, System Segment Descriptor Flelds Name | Vale Description TYPE | 1 | Avalabi Task State Soran TES) 2 | Leal Deserpoe Tai 5 _| Suny Task State Sogmont TSS) P| 0 | Descrisiorcontnis ar nt valid 4 _| Dosergtor contents ere vad DPL_| 0-3 | Desorptor Privo Lovet "BASE | 24-bit | Beas Adore of speci sytem data umber | Segmeortin eat memory Timi | s63t | Otset ot st bein segment umber Figure 12. System Segment Descriptor Format GATE DESCRIPTORS (S = 0, TYPE = 4-7) Gates are used to control access to enty points within the target code segment. Tho gato dase tors are cal gates, task gatos, interrupt gatos and trap gates. Gates provide a level of indirection twoon the source. and destination of the contol transfor This ndraction allows tho CPU to automat cally pertorm protection checks and contol onty point ‘of the destination. Call gates aro usod to ‘change privioge levels (see Privioge) task gatos ‘79 Used to perform a task switch, and interrupt and {rap gales aro used to spect interupt service rou tines. The intorupt gate disables interupls (resets |F) while the trap gate does not. Descriptor “tbo ft or conse wih 8068 Ge a ce)intel a T-49-17-16 —— INTEL CORP UP/PRPHLS 12e p ate Descriptor Feide spor prvieg lve! and specs when thie do- a Serplor may bo Used by a task (ear Io prviope ae discussion below). Bit 4 must equal 0 to indicate a 4 | alae Systom cont doserplor. Tho typo Noid epectos we | § ihe doseptor ype as ncicaled in Figure 13. ; - 4 ‘SEGMENT DESCRIPTOR CACHE REGISTERS Assan! cil aa assed ‘ {ach ofthe four eogment gator (C5, $5, ‘Segment pure are automatically loaded bao (cached) info a sopmont doserpiorcacho rogitor wor {Figure 14) whonover ho asodltod Sogmont roi: coun torts loaded wi a solocter. Only sogmont dose. 0-31 | procedures stack. Only used tors may be loaded into segment descriptor cache \ieat pe ‘ogistors. Onco loaded, al foterences to tat 200 Sessoonetaaicow | ert manay vo he che denon rns 7 ssn | sonencan imunstor | Non intend of reaccoting the degre. The ESTIMATION 3688 | Tapaat) Serptor cache rogstore aro nol vibe to programe. Salecortothetaetask | No instructions it to store thle contonta: They state segment Task@sto)_| Gry change whan ‘DESTINATION | 6DE | Er por wan Orrcr™ | feet | ents Sapna SELECTOR FIELDS Figure 13. Gate Descriptor Format Figure 13 shows the format of the gate descriptors. ‘The descriptor contains a destination pointer that points to the descriptor ofthe target sogmant and {he entypeint offset. The destination solactor In an Intorupt gate, Wap gat, and cal gate must reer toa ‘code segment descriptor. These gate descriptors ‘contain the entry point Io prevent a program trom Constructing and using an legal enty point. Teck {gatos may only role to a task siato sogment. Since {ask gatos invoke a task swt, the destination of- set fs not used in the task gate. Exception 13 s generated when the gatos usod a destination selector dogs not ota to tho correct do- script ype. The word count ili usod in tho call {gate descriptor o indicate the numbor of paramotors (0-31 words) to be automatically copied from the Callor's stack to tho stack of tho called routine when ‘a contol transfer changes privilege lovels. The word Count fild isnot used by any other gate descriptor. 0888 byte format isthe samo forall gato do- irs. P = 1 indeatos tha tho gato contents are ‘indicates the contonts ar not valid and renced. DPL is the do: ‘causos exception 11 itt Bss20n7s owas sf [A protected moda soletor has tvoe fds: descrip for entry index, local oF global descriptor tablo Inc Calor (1), and solactor privloge (RPL) a8 shown in Figure 18. Those folds solect one of two memory basod tables of descriptors, select the appropriata {abo ontry and alow highspood testing of tho solac- {ors privogo atirbute (rotor to privioge dcussion below),intel INTEL CORP {UP/PRPHLS} LOCAL AND GLOBAL DESCRIPTOR TABL* + ‘Two tables of descriptor, called descriptor tabios Contain al desciptors accessibia by a task at ary {von ime. A dascrptor tables a linear array of up {10.6192 descriptors. Tho upper 19 bis of the selec {or value are an inex into a descriptor tablo. Each {ablo has a 24-bit base register to locate the descrip. {or table in physical momnry and a 16-bit role tor that confine descripior access tothe dofnod rn. Its ofthe table as shown in Figure 16. A rostrtablo ‘exception (13) wil occur an attempt is made to ‘ference a descriptor outside the tae init, (One table, called the Global Descripiar tabla (GOT), Contains descriptors avaiable fo all tacks, The other table, called the Local Desciplor Table (LOT), com tains deserptors that can be private to.8 task. Each task may have its own private LOT. Tho GOT may ontan all descriptor types except ntorupt and ap descriptors. The LOT may contain only segment, {ask gato, and cal gate descriptors. A segment cam ot be accessed by a task i ls segmont descriptor ‘does not exist in ether descriptor table a the time of 7 Figure 16. Local nd Global Descriptor Table Definition ‘Tho LGDT and LLDT instuctons load the base and limit ofthe global and local descriptor tables. LGOT ‘and LLDT are privleged,b. thoy may only be exe- uted by tusted programs operating at level 0. The {GOT instructon loads asi byte fad containing the ‘16-bit abi init and 24-bit physical base address of {he Global Descriptor Table as shown in Figure 17. ‘Tho LOT instruction ioads a selector which refers 102 Local Descripior Tablo daserptor containing the lh 3.19 Pp vsze7s cous 2h LE D ~T-49-17-16 bbase address and li for an LOT, as shown in Fig ue 12 80286 "Mtn st 0 congas in oe Figure 17. Global Descriptor Table and interrupt Descriptor Table Data Type INTERRUPT DESCRIPTOR TABLE The protected mode 80286 has a thd descriptor lable, called the Interupt Descriptor Table (OT) (00 Figure 18), used to dofine up to 256 intertupte, I may contain only task gatos, intorupt gates and {rap gates. Tho [DT (Inrupt Boscrptor Table) has 24-bit physical base and 16:1 mit register in the GPU. The privileged LIDT instuction loads these ‘egjstors with a six byte value of idonteal form to that of the LGDT instuoton (eee Figure 17 and Pr tected Mode inta Figu lerupt Descriptor Table Definition Feterences to DT ontres aro made via INT instru. tions, external intorupt vectors, or exceptions, The {DT must be at loast 256 byt In size to allocate space for al rosorved interrupts Privilege ‘The 60286 has a four-level hierarchical privloge sy tom which contois he use of prvlegéd instructions nd secess to descriptors (and thor associated seq ments) within a task: Fourvel privioge, as shown in Figure 19, fs an extension of the user/supervisor ‘mad commonly found in milcomputars. The prvi lege levels are rumborod 0 through 2. Level 0 is thointel INTEL CORP {UP/PRPHLS? ‘most privlogad level. Priviego loves provide protec tion within task. (Tasks are isolated by providing private LOT's for each task) Operating systom rou- fines, interrupt handlers, and other system sotware can be included and protected within the vitual ad {098 space of each task using the four levels of priviloge. Each task in the sysiom has a separate Stack for each offs privilege levels. “Tasks. descriptors, and solectors havo a privioge level attabute that dotormines whether tho Gosctp- {or may be used, Task priviago affects the use of Instructions and descriptors. Doscrptor and soloctor privioge ony effect access tothe descriptor. TASK PRIVILEGE ‘A task always executes atone of the four privilege lovols. Tho task prvioge level at any specific instant 'scallad the Current Prisiogo Lovo! (CPL) and is de- fined by the lower two bits of tho CS register. PL. cannot change during executon in a single code Sogmont. A task's CPL may oly be changed by con- two ransters through gate descriptors toa new code segment (See Contol Transler). Tasks bogin exo- cuiing atthe CPL value speciid by the code sog- ‘ont selector within TSS when tho task I inated ‘laa task switch operation (See Figur 20). task ‘executing at Love O can access all data segments ‘olined in the GOT and the task's LOT and is con Sore the most trusted love. A task executing @ {Loval'3 has the most restcted accoss to ta and is ‘considered the laast trusted love. DESCRIPTOR PRIVILEGE Descriptor privieg (s,specied by the Descriptor Piivilage Lovel (OPL) fed of the descriptor access byte. DPL spectis the least trusted task privlogo: lave (CPL) at which a task may access the descr 3920 Bp weenr7s owes? of 90286 U2E D ~T-49-17-16 tor. Descriptors with DPL.~ 0 are the most protect- ed. Only tasks. executing at privioge level 0 (CPL = 0) may access thom. Descriptors with DPL. = 3 ere the least protected (18. havo the least re- stricted access) since tasks can access thom whan GPL = 0, 1, 2, 03 This tule apples to all descrp- tors, oxcopt LOT descriptors. SELECTOR PRIVILEGE ‘Soloctor priviogo fs spected by the Requostad Priv- oval (APL) fl n tho least sigificant two bis ‘ofa selector. Selector APL may establish a less ‘rusted prviogo lavel than the current privilege lovel {or the use of a selector. This lavel is callad tho tack’ effective privioge level (EPL). APL can only luce the scope ofa task’ acooss to data with this ctr. A task’s effective privilege Is the rumaic ‘maximum of RPL and GPL. A sslocter with RPL = 0 imposes no additional resiriction on Its uso wi selector wih RPL = 3 can only refer to sogmonts at Privilege Lovel 3 rogardiess of tho task’s CPL. APL. 's gonorally used to verty that pointer parameters passed toa more trusted procoduro aro not alowed fo use data ata more prvleged lave than the caller (ofr to pointer testing instructions), Descriptor Access and Privilege Validation Dotermining tho ability of a task to accoss a seg. ‘mant involves tho type of sogmant to bo accossad the instruction used, the typeof descriptor used and CCPL, RPL, and UPL, The to base ypee of segment accesses are control transfor (scloctors load into (63) and data (selectors loaded into DS, ES or SS). DATA SEGMENT ACCESS Instruction that load eolectors into OS and ES must rotor toa data sogmont descriptor or roadable code sogment descriptor. Tho CPL of tho task and tho PL of the selector must bo the samo as or moro privileged (numerically equal tor lowor tha) than the descriptor DPL. In gonoral, a task can only oss data sogmonis atthe samo or less pilogod lovols than the CPL or RPL (whichever ls numoricelly ighod) to prevent a program trom accossing data cannot be trusad to se. ‘An exception to the rule Is a readable conforming ode segment. This type of code segment can be reac from any privilege lev cocks fall (0.9. DPL is numerically 1 tho privintel “INTEL CORP {UP/PRPHLS} sciptor r excite on cae sognor excopon 9 sea Fe Satna ebeentecoptcn 1 Cones Instone that oes sls nto SS must tert Gua pment once wtb a So. eae 80 Setar ge SPL ard RPL mst raat OPC A ter Sot yes 8 pidape ‘Balclaon'al couse copia ot pout (a cans oncopbon 12 CONTROL TRANSFER, Four typos of control transfor cén occur when a se- Factors loaded into CS by a contol transfer opere- tion (e90 Table 10). Each vansfer type can only 00- ‘url the operation which loaded the selector rote fences the correct descriptor type. Any violation of these descriptor usage res (@.. JMP through a call ‘gale of RET to a Task Stato Segment wil cause ‘exception 13. ‘Tho ability to roferonce a descriptor for control trans- forts also eubjoct to rules of privioge. A CALL or JUMP ‘nstuction may only reerence a code seg- ‘mont descriptor with DPL equal to the task CPL ora ‘conforming eegmant wilh OPL of equal or greater privilege than CPL. Tho RPL of the solactor used to foferonce the code descriptor must havo as much prvloge as CPL. FRET and IRET instructions may only reference code ‘sogmant doscriptors with descriptor privilege to or loss privoged than tho task CPL. The. loaded into CS isthe return address frm the slack. ‘After the roturn, the selector APL Is tho task’s now (GPL. CPL changes, the old stack pointer ls popped after the return accross. \Whon a JMP or CALL reterences a Task Stato Sog- ‘mant descriptor, the descriptor OPL, must be the ‘Samo or loss priviogod than the task’s CPL. Fefer- ‘able 10. Descriptor Types Used for Control Trank J ve2er7s couse of 20206 v2E D ~T-49-17-16 ‘ono0 to a valid Task Stato Segment descriptor caus- ‘08a task avitch (09 Task Switch Operation) Rfor- ‘once fo a Task Slale Segmont descriptor at amore ‘rvioged lovel than the task’s CPL generates ox- ‘option 13. When an instructon or interupt references a gate ‘descriptor, the gato DPL must have the same or less privilege than the task GPL. I OPL is ata more priv- foged lovel than CPL, exocoption 13 occurs. I tho dstination selector contained In tho gato roter- ‘ances a code sogment descriptor, the code s03- ‘ant descriptor DPL must bo the same or more priv- llogad than tho task CPL. If not, Exception 13 isis ‘ued. After the control tansfor, the cod segment scripts DPL is the task’s new CPL. Ifthe dest= ation selector in tho gato references a task stato Sogment, a task switch is automaticaly performed (Geo Task Switch Operation). “Tho privilege rues on control transfer require: = JMP oF CALL direct to a cade segment (code ‘segment descrpten cen only be to @ conforming sogment with OPL of equal or greater privilege than GPL of @ non-conforming sogmont at the samo prilogo tovel. = intorupts within the task or calls that may ‘change priviogo levels, can ony vansfor contol through a gato atthe samo or a loss privileged level than GPL to a code sogmont a tho same oF ‘meta prvloged fval than GPL. — return instructions that don't ewitch tasks can ‘only return contol to @ cade segment al tho ‘same or fs prveged level. = task switch can bo porformed by a cal, jump or Interupt which referencas either a task gato or {ask stato sogment atthe samo or los privlogod love Control Transter Type Operation 7 teranend_| "rable Treat fbn tse igs oval TH, CALL FET, RET” | Code Sognant | GOTT Inorsogmentio tho sare oir pvogeTovainaraat | CALL GsiGaie | Goraor witntaskmay ngs CPL inemptinaiucion, | Trapor oF Ssemlon, extemal | Inrapt totraot Seta Trerogment oa ower pion vel Chagos wok GF) RET. RET” eon Seqrort | GOTROT CALL MP Tasks] GOT Segment mae CALL sorb rer Ireroptinatucton, | yay fe Ercopton Exam | TekGste r inert TAT (Rested Took Bt of fag word = 0 “NT sted Task tot Fag werd) = tintel sone INTEL CORP {UP/PRPHLS} PRIVILEGE LEVEL CHANGES ‘Any contr transfer that changes CPL within the task, causes a change of stacks as part of tho oper aon nial values of SS:5P for privage lavas 0,1, and 2 are kept in tho task slate eogment (afer to ‘Task Switch Operation). During a JMP or CALL con- trol transfer, the new stack pointes loaded into the 'SS and SP rogstors and the previous stack pointer {is pushed onto tho naw stack. Whon roturring to the original privioge level, ts stack Is restored as part ofthe RET of IRET instruc: tion oporation. For subroutine cals that pass param ‘ters onthe stack and cross privilege levels, a fixed ‘number of words, as spec In the gate, ae cop fad from the previous stack othe curant stack. The inter-sogmont RET Instruction with a stack adjust ‘ment valuo wil cnecty restore tho previous stack Pointer upen return. Protection “The 80286 includes mochanisms to protect exical instructions that affect he CPU execution stato (6.9. HLT) and code or data segments from improper us. ‘age. Thoso protection mechanisms are grouped into three forme Restcted usage of segments (2.9. no write a lowed to read-only data sogmont). The only sog- ‘ments avaiable for use are dotinad by desorip- tors in the Local Deseiptor Table (LOT) and Global Descriptor Tablo (GON). Rosticted access to sogmanis via the rules of priviogo and doscriptor usage. Privieged instructons ot operations that may only bo executed at conan privlage levels as ce- tormined by the CPL and 1/0 Privege Level GOPL). The IOPL is defined by bts 14 and 13 of tha fag word. “These checks are performed for all instructions and ccan be spilt into three categories: segment toad checks (Table 11), oporand reference checks (Tabla 12), and priviogod instuction checks (Tablo 12). ‘Any Violation ofthe rules shown wil result in an ex: ‘ception. A not present oxcepton related othe stack ‘segment causes exception 12. ‘The IRET and POPF instructions do not perform ‘some oftheir dofned functions f CPL isnot of suff. cient privlego (numorcaly small enough). Procisay these aro: * The IF bits not changed i GPL > 1OPL. * The IOPL ied of tho tag word i not changed if LF. No excoptions or other indiation are given when ‘these conditions occur. 322 J ve2en75 oonue3s 2B 6 aee p —T-49-17-16 Table 11 ‘Segment Register Load Checks Error Description oe Descriptor abe a oxcoodod 3 ‘Segmant dseptor not gresent Terie Prvige rs veiatod 19 Invalé dose seen ype ag ‘ontrgisterioad. gt ony aa sgmntoadto Special Contol decor load to DS. ES, $8 —Bxcsul only segmont load to 5.5 85 Bata segmnttoasiocs ‘TRoad/esocuo code sopmeont fondo SS 0 ‘Table 12. Operand Reference Checks Error Description reeion| umber Wits code sagmant 8 Fed rom exacit-ony code ‘ment 2 oad data sogrrent Segment ecsedes! Nore: ‘Cary out noo calelatons i nord ‘Table 18. Privlloged instruction Checks ‘Exception Number i2erts Error Description ‘GPL A O when oxoeutg he folowing Setvctons UOT, LOT LOOT, LTR, LuSW, crs.ntr ‘GL > IOPL whon exoang the fol Towing avuctoe TNS, IN OUTS, OUT, ST, CU, Lock ny EXCEPTIONS “The 60286 detects soveral types of excpions and interups, in protected mode (00 Table 14) Most ‘are restartabie after the exceptional condition is a: ‘moved. Interrupt handlers for most exceptions can ‘oad an ertor code, pushed on the stack afar the return addres, that Wentiies the selector Involved (Oi none) The return address normaly point to the faling instruction, including al eading profixes. Fors processor extension segment overtun exception, {he retum aderess will not pot at the ESC instruc: tion that caused the exception; however, the proces. may contain the aderase of8 INTEL CORP {UP/PRPHLS? 02 ey | VEE D “T-49-17-16 ‘Table 14, Protected Mode Exceptions Return aways | Error Invert Adarone rare Vector Function oat 3 | Daskiooxcapton detected 5 | Procesoretasion sogmontoverun 10 | ad ase atata sagan 11 | Sogmentnotprocert 12 | Staacsagmant overun or stack sepmen nat reset 13 __|_ Gover protecton nove: 1 When a PUSHA or PPA Instuckon atmpt to wrap ecund i vel not ho resale because stack grant wrap aur enol ps Saved SP being efi 000004, coon FFFEL, FERN, 22 Thoso encoplons ideals ¢Woleton ‘ndor thse condtons ‘These excoptions indicate @ violation to privlogo ‘ules or usage rules has occurred. Rasta If goner- ly not attempted undor those conditions. All those chacks are performed for all instructions ‘and can be spi into tree categories: sogment load ‘checks (Table 11), operand retorence checks (Tablo 12), and privileged instruction checks (Table 13) ‘Any violation ofthe rules shown wil resul in an ox: Ception, A not present exception causes exception Wor 12 and is restartablo, Special Operations ‘TASK SWITCH OPERATION “Tho 00286 provides a bultin task ewitch operation hich saves th ent 80286 execution state (regis. tors, address space, and a link to tha previous task), Yoads a new execution stato, and commences exe: cetion inthe new task. Uko gates, tho task switch operation is invoked by exbeuting an inor-seqment IMP or CALL Instruction which refers 10. @. Task State Segment (TSS) or task gato daseriptr inthe GOT or LDT. An INT nInstuction, oxcoption, or ox. ternal interupt may also invoke tho task switch op- ration by selecting a task gate descriptor in tho ae sociated IDT descriptor entry ‘The TSS descriptor points at a segment (soe Figure 20) containing the entre 80286 exccution state Wile task gate descriptor containe a TSS selector. Tho fit eld ofthe descriptor must bo > 00284), Each task must have a TSS associated with it, The current TSS is ientiiod by @ special register In the 80286 called the Task Fagister (TR). Ths rogistor Contains a selector rfering to the task state seg ‘ment descriptor that detinos the currant TSS. A Nd. on bese and limit registr assoclatod with TA are loaded whenever THis loaded wih @ new selector. 29 1 prvioge nes or Usage rues has occured. Restate gener ot atime ‘The IRET instruction is used to rotu contol tothe task that called the curent task of wes Interupted Bit 14 jn the flag rogistor called tha Nostod Task {(N7) Bit tcontrols the function ofthe IRET instruc: tion i NT ="0, the IRET Instruction performs the ‘regular current task by popping values off th stac when NT = 1, IRET performs’ a task switch opera: tion back to tho previous task Whon a CALL, JMP, or INT instucton iniates @ {ask switch, the old (oxcopt for case of JMP) and ‘new TSS wil be marked busy and the back ink fold ofthe new TSS soto the old TSS selector. The NT. bit of the now task Is sat by CALL or INT inated {ask switches, An intorpt that does not cause @ task switch wil clear NT” NT may also be set oF cared by POPF or IRET instuctons, ‘Tho task state segmont is marked busy by changing tho desciptor ype field trom Type 110 Typo &. Use of a solector that references a busy task stato seg. ‘ment causes Exception 13, PROCESSOR EXTENSION CONTEXT SWITCHING ‘Tho context of a processor extension (such as tho {80287 numerics processor is not changed by {ask switch operation. A processor extension con. {ext ngod only be changed wien a dtferont task at tompts to use the processor extension (which sti Contains the context of a provious task). The 60206 ‘otocts the fst uso of a procossor entonsion attr @ task switch by causing tho processor extension not present exception (7). The interupt handler may ‘hen decide whether a contaxt change is necessary Whenever the 80286 switchos tasks, sets the Task ‘Switched (TS) bit of the MSW. TS indicates that @ processor extension context may belong to a dior tent task than tho current one, The processor exton- sion not presont exception (7) wil oceur when tempting to execute an ESC or WAIT Instruction i ‘TS=1 anda processor extension fs present (> inmsw,PB sozur7s oowweay of intel soa INTEL CORP TOP. 15, The IF tld ofthe fag word isnot updated it CPL >'TOPL, The IOPL Meld Is updated only tf cre 6, 16. Any violation of privilege rules 8 applied tothe selector operand do not cause a protection ception; rather, the Instruction does not return & Fosult and the 200 fag Is cleared. 17.11 the starting adéross of the memory operand llates a segment limi, or an Ievald acooss attompted, a general protection exception (13) ‘Wil cour bofor tho ESC instruction fs execut- fd, A stack sogment overrun exception (12) wil ‘cour I tho stack Int le violated by the opor- fand’s staring adaross. Ifa sogment ft vo. lated during an attomptad data transfor thon a Bracessor extension sagment overrun exception (@) occurs. 18, Tho destination of an INT, JMP, CALL, RET oF IRET Instucton must be in the datind Im of a ‘code sogment ora general protection exception (43) wil occur.| © Wi sa20175 coun i 4 intel 28 al INTEL CORP {UP/PRPHLS} WE D—749-17-16 ‘80286 INSTRUCTION SET SUMMARY forte heen wa fa lo jwmaneroroaa ——_[o08rrw gum wie tals Joma tregerinenoy wa} ae [oa |e free torer ale ayer (ovessoe| aariw [ean] « fa fate ‘ome (ioecorw | esrew [wen] lee vormaneywugronnur [1000120 [onto im sae |r | oan unde omiecteresy wfale nn eine Font antares etaneveie we fae | ar | ow a ir B16 fpronttese Pde es]. “ fesse ele for-comate a 5c “ tot a|a “ ATTA AL sls ° LossAtorgar eye ino tes nfo |e | ems a [eo0r08 Jog ve) tie) a» fan foe | ems ‘Stato walneal Pomona 8, see 947| JJ vs2er7s coves 3 intel 0206 INTEL CORP {UP/PRPHLS} L2E D—T+49-17-16 (80286 INSTRUCTION SET SUMMARY (Continued) TATRATER me otis fle ote thes rie afoajelo ealnamenywthregertoainer [000004w | mosrag im] afar lade fromsumiovessareamey [100000e"[mosooe vm] cain _[aintewnet]] ar | ax | 2 | frees acme a] mena wg hae a lar fa] eo Jeredatstoronirinonoy — Creaveoew[meotovin] dee [asuten=cil] a7 | arr | 2 ° Jprsatonconier alos Pier mmery ar far tala pose aya = eae atl jssinniivineny (ia0oers eeisive| an —Jamivecal] ar | ar | 2 | bremediate om accurulatr [corosvow] ona [ cuaew=1 2 . [ocmtmommeone (Gnesi a wl |e| Jotitooniteneny [100eeee] aati] am —Tawme=a| ar | ar | | 0 Jrmntaitomsceeie a}a hepeevneney, ar tom [a | o Pee af mony rege ww |aw [a |e ta egaary afar tele jentintnny [osttorwlecti vel ae Jamal) ew | ww | 2 | fr aoc aya (Ea =Chaga on atrfele Jan Asc achat tora a a ppad~oncnt vata afta iintel INTEL CORP {UP/PRPHLS} 180286 INSTRUCTION SET SUMMARY (Continued) BB so20175 cous 5 U2E D—T-49-17-16 a tot oni ore fonenon row at "ra aa one has aster tie 2h =O ean put sats ese = erate ure py s jur-hnwernertons: [1iisbate fox val ce tion insects nine” [601001 owing “val aon [data] Boee Seen Bee Boeo ‘Slade wea nde rari rol wane m8 SOHNE. 3.49intel a B va2er75 Oouuee? 27 ff INTEL CORP <{UP/PRPHLS} Lae p-T-49-17-16 £80286 INSTRUCTION SET SUMMARY (Continued) oe) armntveiionte — (rannes [eat vm war fale froma tvasteanary ee les Jrosantoaimisr oe fesr-anttincon tage faster tote ro a}o [rsroneeeme (fever [eesooe vel ae [antes] w tale weetintnuniecomine — (insojoce] au —Tomte=a] af Pein dregs ier er far [oa | mmestotorogeurnanony afar je] e faransieceer (scerro+] — sen [estas] ae : yrs dest far lal e lamcuntmnninnny -(4058080%[mattsovn| am Tawixsi]} ar | ar | 2 | o frveso scams Og = [iors [esioroa) aw lar lals ete efale recone brs efale 0st Crerersiw] fale Lott UN elas siabintton A a fe] o feheamt boned = Conners) PTE ee ear] pure-ovearersooroer fariesiie] eh ef oe] Perosny ence en (ivvaers Trviearon] te |e | a |e sete | sem] an | ao tein | som | ae | ae ten | sem | oe | oe arn | sem | ae | ae © ftzeots Ternennoe | OT Pace Pee |e rey ste | eel foes faeintef 802% INTEL CORP {UP/PRPHLS} (00286 INSTRUCTION SET SUMMARY (Continued) Bp yeze175 conuees wa V2E D—T-49-17-16 few nat (iiwioooT ape Dawe J] ore | orm |e | ow finery Cosisis [asoro on] remtem|temsten| an | aa pat Caner] aa wim foam | oa | sues otetd Wode Oy reetitervegmet toners sien eave Yaenpeeareeasaanpioeteme wnat prea CiaaaTemor wa) ote | toom | arte |e tt ne rama “catsanepaenr see ‘ccna area ropes ain \arpetoenvetyocpoet san erator rem | tem * 11101001] aaptow | dapign rm em u wearmeoy ibs (14184 [et 90_ ta} remuient|remiieme| a | ae “Via cel gata to saa prog ive * atm erie ine ean Crease Tecior a) watery | ovsew | anew | 2 fesse ned ar ny ete Vuarpenccospasind leasssa tom | osm [oe | a sosediginneiiose tem | onem |e] ane wen | am | 2 lansse puceymessioiemnaioosr [ssonio1e | cane [anus ]| tem 2 [anus nda 4 Tesnetsaogeee ssn euuee ostres intel ta INTEL CORP {UP/PRPHLS} Ata WSTAUCTON HET SUMMARY Cet B vs2e175 cones of 12E D—T-49-17-16 comes fete ei tes fro toneton coon ferocTawarin eo laie-amoercenone tomas | rome . Lasmat-sey sect a ramee | rome * fusro-aee erent romeo | rome UA pellet oad tana | tomes lecind=deg enn he tons | rome " Lares sets on roma | rome . = mpm remors | remo * naimyensin remo | rma * [mene —sey onto renee | rome . [naioe-sepcneatnarpeee ees tomes | rome * |auesa-ses senior tenes | tener * [noe -dopen nate! eed tomas | rome |nossk-sop nner tones | rome |nrno= sence tana | rome lose set eon tana | tone [ns sponser rome | rome * f.ooP=toopcxtnes omen \ieceeen 1. Leorn2cre- sos rca sonar | sonore " Lsontancome-uysde sen (a11e000e [a] net (nee * . sem aa emacs eas im | ore sone | eet &Bp ve20175 conuez0 ol intel 80286 “INTEL CORP {UP/PRPHLS} (80296 INSTRUCTION SET SUMMARY (Continued) VRE D—T-49-17-16 —— sas te a wept co visas Segre a. ae Jeter arom | tem | 24 fasstaasnce [Protected ode On: = bel foo sera Gm) YY a EE a ones. x crane allo Paced : tye — Caos] tf oe ee ae oe aa oma i: — i]s : s|s a jel “ on nog anwar [anasaia) = P| a 3= Proceaser Extension aps ‘mod hh of aor | seo arr nthe peered eoretoutanie oc T=Lost gebe dneor tie gwar [eocotits | 09000004 [maso1 wal | mt ne | ae. oa Sloe gotalgeneilorsttrapni [9000111 100000001 [nesad in} | 11° we a * r-ininnaeecewnnen fooueisi ooo laaicanl| w | we [a | ae) cone [aso Teonaneey oscar |e | we | ta | celeb nie a : Seman wiv |x | ae = Store foal deere abe regia "I a3 Ry soregaterimameny ~ [eosetrts [oe0e0ee9 Trosoao en} ae fr ° ‘Soted ana cata aos not avcablin 008 98 womans 383ee SINTEL CORP {UP/PRPHLS} BL vazeizs aowue7a off 0286 32E D-7-49-17-16 (80286 INSTRUCTION SET SUMMARY (Continued) fuss tnt ear ane wot ‘evegiconeny lane once ie fst-toteedenina rouge Jarred pet tomogram [renner non UTR Local ask roger i es Tee sooo 1 Sora tak ogee tS — ; : emvogetnony 8 { [seen va] Wenn ver otucsa gre one [eonerts1 T cossoete Treen va}: 2 (ecoorrts | oavooave | maizeivn’}. ‘Shaded oes dal evans nt ween 46,68 momo. 354J es2e17s oouunre of 80286 INTEL CORP {UP/PRPHLS} U2E D—T-49-17-16 REG fs assigned according tothe following table: Seema $6 (w = 1) eBIt(w = 0) ‘To Etfoctve Address (EA) of he mamory oporand 000" AX 000" AL Is computed according tothe mod and /m els: ot ox oor ot O10 OF it mad = 11 thon rma rated as @ REG fold ont ae aisiion ifmed = 00 than DISP = 0°, dsplow and cisphigh aes aaa are abeont 101. BP wor cH ifmod = 01 then ISP = dspow slgn-extonded to oi st 110. OH 18 bite, isphigh is absont woo) tt BH if mod = 10:hen DISP = cep-high: lepiow {frm =,000 thon EA = (BX) + (S) + DISP it1/m = 001 then EA = (BX) + (0) + DISP rf = 010 thon EA = (BP) * (S) + DISP item = O11 thon EA = (BP) + (Ol) + DISP Helm = 100 thon EA = (8) + DISP lcm = 104 then EA = (0) + DISP lef = 110 thon EA = (BP) + DISP* item = 111 then EA = (8X) + DISP DISP folows 2nd byte of instructon (before data it required) ‘exept mod = anda = 10.900 EO dep pow ‘SEGMENT OVERRIDE PREFIX oot 1 19] 0g essigned according othe folowing: ‘Segment reg Register 0 ES nt | ce 8s. i 100] 256 ‘Tho physical adarasses of all operands adrossod by the BP register are computed using the SS sog- ‘ant register. The physical addresses of the dost- ration operands of the sing primitive operations (those addressed by the DI register) are computed using tho ES segment, which may not be overidden. DATA SHEET REVISION REVIEW ‘The following Ist represents key difrances be: ‘woon this and th -012 dala shoot. Ploaso reviow this summary careful. 1. Speccations fr the 6 MHz version of the part have been deleted, Intl no longer manufactares an 602886. 2. The system dagrams (Figures 31 and 92) have been modiied. Tho ecu which dives the RES Input of the 826254 has boon moditiod ln odor to ‘tow the 820284 to coroctly ganorato a systom sot signal. See tho 820284 data shoot (Order No, 210883) for further information.