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HT68F20/HT68F30/HT68F40/HT68F50/HT68F60

Enhanced I/O Flash Type MCU 8-Bit MCU with EEPROM

Technical Document
· Application Note
- HA0075E MCU Reset and Oscillator Circuits Application Note

Features
CPU Features Peripheral Features
· Operating Voltage: · Flash Program Memory: 1K´14 ~ 12K´16
fSYS= 8MHz: 2.2V~5.5V · RAM Data Memory: 64´8 ~ 576´8
fSYS= 12MHz: 2.7V~5.5V · EEPROM Memory: 32´8~256´8
fSYS= 20MHz: 4.5V~5.5V
· Watchdog Timer function
· Up to 0.2ms instruction cycle with 20MHz system
· Up to 50 bidirectional I/O lines
clock at VDD=5V
· Software controlled 4-SCOM lines LCD driver with
· Power down and wake-up functions to reduce power
consumption 1/2 bias
· · Multiple pin-shared external interrupts
Five oscillators:
External Crystal - HXT · Multiple Timer Module for time measure, input
External 32.768kHz Crystal - LXT capture, compare match output, PWM output or
External RC - ERC single pulse output function
Internal RC - HIRC · Serial Interfaces Module - SIM for SPI or I2C
Internal 32kHz RC - LIRC · Dual Comparator functions
· Multi-mode operation: NORMAL, SLOW, IDLE and · Dual Time-Base functions for generation of fixed time
SLEEP interrupt signals
· Fully integrated internal 4MHz, 8MHz and 12MHz · Low voltage reset function
oscillator requires no external components · Low voltage detect function
· All instructions executed in one or two instruction · Wide range of available package types
cycles
· Table read instructions
· 63 powerful instructions
· Up to 12-level subroutine nesting
· Bit manipulation instruction

General Description
The HT68FXX series of devices are Flash Memory I/O A full choice of HXT, LXT, ERC, HIRC and LIRC oscilla-
type 8-bit high performance RISC architecture tor functions are provided including a fully integrated
microcontrollers. Offering users the convenience of Flash system oscillator which requires no external compo-
Memory multi-programming features, these devices also nents for its implementation. The ability to operate and
include a wide range of functions and features. Other switch dynamically between a range of operating
memory includes an area of RAM Data Memory as well as modes using different clock sources gives users the
an area of EEPROM memory for storage of non-volatile ability to optimise microcontroller operation and mini-
data such as serial numbers, calibration data etc. mise power consumption.
Multiple and extremely flexible Timer Modules provide The inclusion of flexible I/O programming features,
timing, pulse generation and PWM generation func- Time-Base functions along with many other features en-
tions. Analog features include dual comparator func- sure that the devices will find excellent use in applica-
tions. Communication with the outside world is catered tions such as electronic metering, environmental
for by including fully integrated SPI or I2C interface func- monitoring, handheld instruments, household appli-
tions, two popular interfaces which provide designers ances, electronically controlled tools, motor driving in
with a means of easy communication with external pe- addition to many others.
ripheral hardware. Protective features such as an inter-
nal Watchdog Timer, Low Voltage Reset and Low
Voltage Detector coupled with excellent noise immunity
and ESD protection ensure that reliable operation is
maintained in hostile electrical environments.

Rev. 1.00 1 November 3, 2009

HT68F20/HT68F30/HT68F40/HT68F50/HT68F60

Selection Table
Most features are common to all devices, the main feature distinguishing them are Memory capacity, I/O count, TM
features, stack capacity and package types. The following table summarises the main features of each device.

Program Data Data Ext. Timer Interface
Part No. VDD I/O 2 Stack Package
Memory Memory EEPROM Interrupt Module (SPI/I C)

2.2V~ 10-bit CTM´1, 16DIP/NSOP/SSOP
HT68F20* 1K´14 64´8 32´8 18 2 Ö 4
5.5V 10-bit STM´1 20DIP/SOP/SSOP

16DIP/NSOP/SSOP
2.2V~ 10-bit CTM´1,
HT68F30 2K´14 96´8 64´8 22 2 Ö 4 20DIP/SOP/SSOP
5.5V 10-bit ETM´1
24SKDIP/SOP/SSOP

10-bit CTM´1, 24/28SKDIP/SOP/SSOP
2.2V~
HT68F40 4K´15 192´8 128´8 42 2 10-bit ETM´1, Ö 8 44QFP, 32/40/48QFN
5.5V
16-bit STM´1 48SSOP

10-bit CTM´2, 28SKDIP/SOP/SSOP
2.2V~
HT68F50 8K´16 384´8 256´8 42 2 10-bit ETM´1, Ö 8 44QFP, 40/48QFN
5.5V
16-bit STM´1 48SSOP

10-bit CTMx2,
2.2V~ 44/52QFP, 40/48QFN
HT68F60* 12K´16 576´8 256´8 50 4 10-bit ETMx1, Ö 12
5.5V 48SSOP
16-bit STMx1

Note: ²*² Under development, available in 1Q, 2010
As devices exist in more than one package format, the table reflects the situation for the package with the most
pins.

L o w W a tc h d o g
V o lta g e T im e r
D e te c t

R e s e t
L o w
V o lta g e C ir c u it
R e s e t
8 - b it
R IS C In te rru p t
M C U C o n tr o lle r
C o re
F la s h /E E P R O M S ta c k
E R C /H X T
P r o g r a m m in g
O s c illa to r
C ir c u itr y ( IS P )

H IR C L IR C /L X T
F la s h E E P R O M R A M
P ro g ra m D a ta T B 0 /T B 1 D a ta O s c illa to r O s c illa to r
M e m o ry M e m o ry M e m o ry

C o m p a ra to rs

I/O S IM T M 0 T M 1 T M n

Block Diagram

Rev. 1.00 2 November 3, 2009

HT68F20/HT68F30/HT68F40/HT68F50/HT68F60

Pin Assignment
P A 0 /C 0 X /T P 0 _ 0 1 2 0 P A 1 /T P 1 _ 0
V S S 2 1 9 P A 2 /T C K 0 /C 0 +
P A 0 /C 0 X /T P 0 _ 0 1 1 6 P A 1 /T P 1 _ 0 P B 4 /X T 2 3 1 8 P A 3 /IN T 0 /C 0 -
V S S 2 1 5 P A 2 /T C K 0 /C 0 + P B 3 /X T 1 4 1 7 P A 4 /IN T 1 /T C K 1
P B 4 /X T 2 3 1 4 P A 3 /IN T 0 /C 0 - P B 2 /O S C 2 5 1 6 P A 5 /C 1 X /S D O
P B 3 /X T 1 4 1 3 P A 4 /IN T 1 /T C K 1 P B 1 /O S C 1 6 1 5 P A 6 /S D I/S D A
P B 2 /O S C 2 5 1 2 P A 5 /C 1 X /S D O V D D 7 1 4 P A 7 /S C K /S C L
P B 1 /O S C 1 6 1 1 P A 6 /S D I/S D A P B 0 /R E S 8 1 3 P B 5 /S C S
V D D 7 1 0 P A 7 /S C K /S C L P C 1 /S C O M 1 9 1 2 P C 2 /P C K /C 1 + /S C O M 2
P B 0 /R E S 8 9 P B 5 /S C S P C 0 /T P 1 _ 1 /S C O M 0 1 0 1 1 P C 3 /P IN T /C 1 -/S C O M 3

H T 6 8 F 2 0 H T 6 8 F 2 0
1 6 D IP -A /N S O P -A /S S O P -A 2 0 D IP -A /S O P -A /S S O P -A

P A 0 /C 0 X /T P 0 _ 0 1 2 0 P A 1 /T P 1 A
V S S 2 1 9 P A 2 /T C K 0 /C 0 +
P A 0 /C 0 X /T P 0 _ 0 1 1 6 P A 1 /T P 1 A P B 4 /X T 2 3 1 8 P A 3 /IN T 0 /C 0 -
V S S 2 1 5 P A 2 /T C K 0 /C 0 + P B 3 /X T 1 4 1 7 P A 4 /IN T 1 /T C K 1
P B 4 /X T 2 3 1 4 P A 3 /IN T 0 /C 0 - P B 2 /O S C 2 5 1 6 P A 5 /C 1 X /S D O
P B 3 /X T 1 4 1 3 P A 4 /IN T 1 /T C K 1 P B 1 /O S C 1 6 1 5 P A 6 /S D I/S D A
P B 2 /O S C 2 5 1 2 P A 5 /C 1 X /S D O V D D 7 1 4 P A 7 /S C K /S C L
P B 1 /O S C 1 6 1 1 P A 6 /S D I/S D A P B 0 /R E S 8 1 3 P B 5 /S C S
V D D 7 1 0 P A 7 /S C K /S C L P C 1 /T P 1 B _ 1 /[S D O ]/S C O M 1 9 1 2 P C 2 /P C K /C 1 +
P B 0 /R E S 8 9 P B 5 /S C S P C 0 /T P 1 B _ 0 /[S D I/S D A ]/S C O M 0 1 0 1 1 P C 3 /P IN T /C 1 -

H T 6 8 F 3 0 H T 6 8 F 3 0
1 6 D IP -A /N S O P -A /S S O P -A 2 0 D IP -A /S O P -A /S S O P -A

P A 0 /C 0 X /T P 0 _ 0 1 2 4 P A 1 /T P 1 A
V S S 2 2 3 P A 2 /T C K 0 /C 0 +
P B 4 /X T 2 3 2 2 P A 3 /IN T 0 /C 0 -
P B 3 /X T 1 4 2 1 P A 4 /IN T 1 /T C K 1
P B 2 /O S C 2 5 2 0 P A 5 /C 1 X /S D O
P B 1 /O S C 1 6 1 9 P A 6 /S D I/S D A
V D D 7 1 8 P A 7 /S C K /S C L
P B 0 /R E S 8 1 7 P B 5 /S C S
P C 1 /T P 1 B _ 1 /[S D O ]/S C O M 1 9 1 6 P C 2 /P C K /C 1 +
P C 0 /T P 1 B _ 0 /[S D I/S D A ]/S C O M 0 1 0 1 5 P C 3 /P IN T /C 1 -
P C 7 /[S C K /S C L ]/S C O M 3 1 1 1 4 P C 4 /[P IN T ]
P C 6 /[S C S ]/S C O M 2 1 2 1 3 P C 5 /T P 0 _ 1 /[P C K ]

H T 6 8 F 3 0
2 4 S K D IP -A /S O P -A /S S O P -A
P A 0 /C 0 X /T P 0 _ 0 1 2 8 P A 1 /T P 1 A
V S S 2 2 7 P A 2 /T C K 0 /C 0 +
P A 0 /C 0 X /T P 0 _ 0 1 2 4 P A 1 /T P 1 A P B 4 /X T 2 3 2 6 P A 3 /IN T 0 /C 0 -
V S S 2 2 3 P A 2 /T C K 0 /C 0 + P B 3 /X T 1 4 2 5 P A 4 /IN T 1 /T C K 1
P B 4 /X T 2 3 2 2 P A 3 /IN T 0 /C 0 - P B 2 /O S C 2 5 2 4 P A 5 /C 1 X /S D O
P B 3 /X T 1 4 2 1 P A 4 /IN T 1 /T C K 1 P B 1 /O S C 1 6 2 3 P A 6 /S D I/S D A
P B 2 /O S C 2 5 2 0 P A 5 /C 1 X /S D O V D D 7 2 2 P A 7 /S C K /S C L
P B 1 /O S C 1 6 1 9 P A 6 /S D I/S D A P B 0 /R E S 8 2 1 P B 5 /S C S
V D D 7 1 8 P A 7 /S C K /S C L P C 1 /T P 1 B _ 1 /S C O M 1 9 2 0 P C 2 /T C K 2 /P C K /C 1 +
P B 0 /R E S 8 1 7 P B 5 /S C S P C 0 /T P 1 B _ 0 /S C O M 0 1 0 1 9 P C 3 /P IN T /T P 2 _ 0 /C 1 -
P C 1 /T P 1 B _ 1 /S C O M 1 9 1 6 P C 2 /T C K 2 /P C K /C 1 + P C 7 /[T P 1 A ]/S C O M 3 1 1 1 8 P C 4 /[IN T 0 ]/[P IN T ]/T P 2 _ 1
P C 0 /T P 1 B _ 0 /S C O M 0 1 0 1 5 P C 3 /P IN T /T P 2 _ 0 /C 1 - P C 6 /[T P 0 _ 0 ]/S C O M 2 1 2 1 7 P C 5 /[IN T 1 ]/T P 0 _ 1 /T P 1 B _ 2 /[P C K ]
P C 7 /[T P 1 A ]/S C O M 3 1 1 1 4 P C 4 /[IN T 0 ]/[P IN T ]/T P 2 _ 1 P D 3 /[T C K 1 ]/[S D O ] 1 3 1 6 P D 0 /[T C K 2 ]/[S C S ]
P C 6 /[T P 0 _ 0 ]/S C O M 2 1 2 1 3 P C 5 /[IN T 1 ]/T P 0 _ 1 /T P 1 B _ 2 /[P C K ] P D 2 /[T C K 0 ]/[S D I/S D A ] 1 4 1 5 P D 1 /[T P 2 _ 0 ]/[S D O ]/[S C K /S C L ]

H T 6 8 F 4 0 H T 6 8 F 4 0
2 4 S K D IP -A /S O P -A /S S O P -A 2 8 S K D IP -A /S O P -A /S S O P -A

Note: 1. Bracketed pin names indicate non-default pinout remapping locations.
2. If the pin-shared pin functions have multiple outputs simultaneously, its pin names at the right side of the
²/² sign can be used for higher priority.

Rev. 1.00 3 November 3, 2009

HT68F20/HT68F30/HT68F40/HT68F50/HT68F60

P C 5 /[IN T 1 ]/T P 0 _ 1 /T P 1 B _ 2 /[P C

P D 1 /[T P 2 _ 0 ]/[S D O ]/[S C K /S C
P C 5 /[IN T 1 ]/T P 0

P C 4 /[IN T 0 ]/[P IN T ]/T P 2
P C 4 /[IN

P C 3 /P IN T /T P 2 _ 0 /C
P C 2 /T C K 2 /P C K /C
P C 3

P D 0 /[T C K 2 ]/[S C
P C

P D 6 /[S C K /S C
P B 7 /[S D I/S D
_ 1 /T P 1 B _
2 /T C K 2 /P

T 0 ]/[P IN T
/P IN T /T P
P A 5 /C

P A 7 /S
P A 6 /S

P B 6 /[S D

P D 7 /[S C
P
1 X /S D O

C K /S C L
B 5 /S C S

2 _ 0 /C 1 -
C K /C 1 +

]/T P 2 _ 1
2 /[P C K ]
D I/S D A

1 +

_ 1
O ]

S ]
A ]

K ]
S ]

1 -
L ]

L ]
4 0 3 9 3 8 3 7 3 6 3 5 3 4 3 3 3 2 3 1
3 2 3 1 3 0 2 9 2 8 2 7 2 6 2 5 P B 5 /S C S 1 3 0 P D 2 /[T C K 0 ]/[S D I/S D A ]
P A 4 /IN T 1 /T C K 1 1 2 4 P D 0 /[T C K 2 ]/[S C S ] P A 7 /S C K /S C L 2 2 9 P D 3 /[T C K 1 ]/[S D O ]
P A 3 /IN T 0 /C 0 - 2 2 3 P D 1 /[T P 2 _ 0 ]/[S D O ]/[S C K /S C L ] P A 6 /S D I/S D A 3 2 8 P D 4 /[T P 2 _ 1 ]
P A 2 /T C K 0 /C 0 + 3 2 2 P D 2 /[T C K 0 ]/[S D I/S D A ] P A 5 /C 1 X /S D O 4 2 7 P D 5 /[T P 0 _ 1 ]
P A 1 /T P 1 A 4 H T 6 8 F 4 0 2 1 P D 3 /[T C K 1 ]/[S D O ] P A 4 /IN T 1 /T C K 1 5 H T 6 8 F 4 0 2 6 P C 6 /[T P 0 _ 0 ]/S C O M 2
P A 0 /C 0 X /T P 0 _ 0 5 3 2 Q F N -A 2 0 P C 6 /[T P 0 _ 0 ]/S C O M 2 P A 3 /IN T 0 /C 0 - 6 4 0 Q F N -A 2 5 P C 7 /[T P 1 A ]/S C O M 3
P F 1 /[C 1 X ] 6 1 9 P C 7 /[T P 1 A ]/S C O M 3 P A 2 /T C K 0 /C 0 + 7 2 4 P C 0 /T P 1 B _ 0 /S C O M 0
P F 0 /[C 0 X ] 7 1 8 P C 0 /T P 1 B _ 0 /S C O M 0 P A 1 /T P 1 A 8 2 3 P C 1 /T P 1 B _ 1 /S C O M 1
P E 7 /[IN T 1 ] 8 1 7 P C 1 /T P 1 B _ 1 /S C O M 1 P A 0 /C 0 X /T P 0 _ 0 9 2 2 P E 4 /[T P 1 B _ 2 ]
9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 P F 1 /[C 1 X ] 1 0 2 1 P E 5
1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0
P E 6
V S S
P B 4
P B 3
P B 2
P B 1
V D D
P B 0

P F 0
P E 7
P E 6
V S S
P B 4
P B 3
P B 2
P B 1
V D D
P B 0
/[IN T 0 ]

/X T
/X T
/O S
/O S

/R E S

/[C 0 X ]
/[IN T 1 ]
/[IN T 0 ]

/X T
/X T
/O S
/O S

/R E S
2
1
C 2
C 1

2
1
C 2
C 1
P C 5 /[IN T 1 ]/T P 0 _ 1 /T P 1 B _ 2 /[P C
P A 0 /C 0 X /T P 0 _ 0 P A 1 /T P 1 A

P D 1 /[T P 2 _ 0 ]/[S D O ]/[S C K /S C
1 4 8
P F 1 /[C 1 X ] 2 4 7 P A 2 /T C K 0 /C 0 +

P C 4 /[IN T 0 ]/[P IN T ]/T P 2
P F 0 /[C 0 X ] 3 4 6 P A 3 /IN T 0 /C 0 -

P D 2 /[T C K 0 ]/[S D I/S D
P C 3 /P IN T /T P 2 _ 0 /C
P C 2 /T C K 2 /P C K /C
P E 7 /[IN T 1 ] 4 4 5 P A 4 /IN T 1 /T C K 1

P D 0 /[T C K 2 ]/[S C
P E 6 /[IN T 0 ] 5 4 4 P A 5 /C 1 X /S D O

P D 6 /[S C K /S C
P B 7 /[S D I/S D
V S S 6 4 3 P A 6 /S D I/S D A

P B 6 /[S D

P D 7 /[S C
P B 4 /X T 2 7 4 2 P A 7 /S C K /S C L
P B 3 /X T 1 8 4 1 P B 5 /S C S
P B 2 /O S C 2 9 4 0 P B 6 /[S D O ]

1 +

_ 1
O ]
A ]

K ]
S ]

A ]
S ]

1 -
L ]

L ]
P B 1 /O S C 1 1 0 3 9 P B 7 /[S D I/S D A ]
V D D P D 6 /[S C K /S C L ] 4 4 4 3 4 2 4 1 4 0 3 9 3 8 3 7 3 6 3 5 3 4
1 1 3 8 P B 5 /S C S 1 3 3 P D 3 /[T C K 1 ]/[S D O ]
P B 0 /R E S 1 2 3 7 P D 7 /[S C S ] P A 7 /S C K /S C L 2 3 2 P D 4 /[T P 2 _ 1 ]
P E 5 1 3 3 6 P C 4 /[IN T 0 ]/[P IN T ]/T P 2 _ 1 P A 6 /S D I/S D A 3 3 1 P D 5 /[T P 0 _ 1 ]
P A 5 /C 1 X /S D O 4 3 0 P E 0
P E 4 /[T P 1 B _ 2 ] 1 4 3 5 N C 5
P A 4 /IN T 1 /T C K 1 2 9 P E 1
P C 1 /T P 1 B _ 1 /S C O M 1 3 4 N C H T 6 8 F 4 0
1 5 P A 3 /IN T 0 /C 0 - 6 2 8 P E 2
7
4 4 Q F P -A
P C 0 /T P 1 B _ 0 /S C O M 0 1 6 3 3 N C P A 2 /T C K 0 /C 0 + 2 7 P E 3
P A 1 /T P 1 A 8 2 6 P C 6 /[T P 0 _ 0 ]/S C O M 2
N C 1 7 3 2 P C 2 /T C K 2 /P C K /C 1 +
P A 0 /C 0 X /T P 0 _ 0 9 2 5 P C 7 /[T P 1 A ]/S C O M 3
P C 7 /[T P 1 A ]/S C O M 3 1 8 3 1 P C 3 /P IN T /T P 2 _ 0 /C 1 - P F 1 /[C 1 X ] 1 0 2 4 P C 0 /T P 1 B _ 0 /S C O M 0
P C 6 /[T P 0 _ 0 ]/S C O M 2 1 9 3 0 P C 5 /[IN T 1 ]/T P 0 _ 1 /T P 1 B _ 2 /[P C K ] P F 0 /[C 0 X ] 1 1 2 3 P C 1 /T P 1 B _ 1 /S C O M 1
1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2
P E 3 2 0 2 9 P D 0 /[T C K 2 ]/[S C S ]
P E 2 2 8 P D 1 /[T P 2 _ 0 ]/[S D O ]/[S C K /S C L ]
P E 7
P E 6
V S S
P B 4
P B 3
P B 2
P B 1
V D D
P B 0
P E 5
P E 4

2 1
P E 1 2 2 2 7 P D 2 /[T C K 0 ]/[S D I/S D A ]
/[IN T 1 ]
/[IN T 0 ]

/X T
/X T
/O S
/O S

/R E S

/[T P 1 B _ 2 ]

P E 0 2 3 2 6 P D 3 /[T C K 1 ]/[S D O ]
2
1
C 2
C 1

P D 5 /[T P 0 _ 1 ] 2 4 2 5 P D 4 /[T P 2 _ 1 ]

H T 6 8 F 4 0
4 8 S S O P -A
P C 5 /[IN T 1 ]/T P 0

P D 1 /[T P 2 _ 0 ]/[S D O ]/[S C K /S C
P C 4 /[IN

P D 2 /[T C K 0 ]/[S D I/S D
P C 3
P C

P D 0 /[T C K 2 ]/[S C
_ 1 /T P 1 B _ 2 /[P C
2 /T C K 2 /P C K /C

T 0 ]/[P IN T ]/T P 2
/P IN T /T P 2 _ 0 /C
P D 6 /[S C K /S C
P B 7 /[S D I/S D
P B 6 /[S D

P D 7 /[S C

N
1 +

_ 1
O ]
A ]

S ]

A ]
S ]

K ]
1 -
L ]

L ]
C

4 8 4 7 4 6 4 5 4 4 4 3 4 2 4 1 4 0 3 9 3 8 3 7
N C 1 3 6 P D 3 /[T C K 1 ]/[S D O ]
P B 5 /S C S 2 3 5 P D 4 /[T P 2 _ 1 ]
P A 7 /S C K /S C L 3 3 4 P D 5 /[T P 0 _ 1 ]
P A 6 /S D I/S D A 4 3 3 P E 0
P A 5 /C 1 X /S D O 5 3 2 P E 1
P A 4 /IN T 1 /T C K 1 6 H T 6 8 F 4 0 3 1 P E 2
P A 3 /IN T 0 C 0 - 7 4 8 Q F N -A 3 0 P E 3
P A 2 /T C K 0 /C 0 + 8 2 9 P C 6 /[T P 0 _ 0 ]/S C O M 2
P A 1 /T P 1 A 9 2 8 P C 7 /[T P 1 A ]/S C O M 3
P A 0 /C 0 X /T P 0 _ 0 1 0 2 7 N C
N C 1 1 2 6 P C 0 /T P 1 B _ 0 /S C O M 0
P F 1 /[C 1 X ] 1 2 2 5 P C 1 /T P 1 B _ 1 /S C O M 1
1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4
P F 0
P E 7
P E 6
V S S
P B 4
P B 3
P B 2
P B 1
V D D
P B 0
P E 5
P E 4
/[C 0 X ]
/[IN T 1 ]
/[IN T 0 ]

/X T
/X T
/O S
/O S

/R E S

/[T P 1 B _ 2 ]
2
1
C 2
C 1

Note: 1. Bracketed pin names indicate non-default pinout remapping locations.
2. If the pin-shared pin functions have multiple outputs simultaneously, its pin names at the right side of the
²/² sign can be used for higher priority.

Rev. 1.00 4 November 3, 2009

1. If the pin-shared pin functions have multiple outputs simultaneously. 6 4 0 Q F N -A 2 5 P C 7 /[T P 1 A ]/S C O M 3 P A 2 /T C K 0 /C 0 + 7 2 4 P C 0 /T P 1 B _ 0 /S C O M 0 P C 6 /[T P 0 _ 0 ]/S C O M 2 1 2 1 7 P C 5 /[IN T 1 ]/T P 0 _ 1 /T P 1 B _ 2 /[P C K ] P A 1 /T P 1 A 8 2 3 P C 1 /T P 1 B _ 1 /S C O M 1 P D 3 /[T C K 1 ]/T P 3 _ 0 /[S D O ] 1 3 1 6 P D 0 /[T C K 2 ]/T P 3 _ 1 /[S C S ] P A 0 /C 0 X /T P 0 _ 0 9 2 2 P E 4 /[T P 1 B _ 2 ] P D 2 /[T C K 0 ]/[S D I/S D A ] 1 4 1 5 P D 1 /[T P 2 _ 0 ]/[S D O ]/[S C K /S C L ] P F 1 /[C 1 X ] 1 0 2 1 P E 5 /[T P 3 _ 0 ] 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 H T 6 8 F 5 0 P F 0 P E 7 P E 6 V S S P B 4 P B 3 P B 2 P B 1 V D D P B 0 2 8 S K D IP -A /S O P -A /S S O P -A /[C 0 X ] /[IN T 1 ] /[IN T 0 ] /X T /X T /O S /O S /R E S 2 1 C 2 C 1 P C 5 /[IN T P A 0 /C 0 X /T P 0 _ 0 1 4 8 P A 1 /T P 1 A P C 4 /[IN P D 1 /[T P F 1 /[C 1 X ] 2 4 7 P A 2 /T C K 0 /C 0 + P P F 0 /[C 0 X ] 3 4 6 P A 3 /IN T 0 /C 0 - 1 D P T ]/T P 0 _ 1 /T P 1 B _ 2 /[P C P D 2 /[T C K 0 ]/[S D I/S D 0 /[T C K 2 ]/T P 3 _ 1 /[S C 2 _ 0 ]/[S D O ]/[S C K /S C 0 ]/[P IN T ]/T C K 3 /T P 2 P E 7 /[IN T 1 ] P A 4 /IN T 1 /T C K 1 P C 3 /P IN T /T P 2 _ 0 /C 4 4 5 P C 2 /T C K 2 /P C K /C P E 6 /[IN T 0 ] 5 4 4 P A 5 /C 1 X /S D O P D 6 /[S C K /S C P B 7 /[S D I/S D V S S 6 4 3 P A 6 /S D I/S D A P B 4 /X T 2 7 4 2 P A 7 /S C K /S C L P B 6 /[S D P D 7 /[S C P B 3 /X T 1 8 4 1 P B 5 /S C S P B 2 /O S C 2 9 4 0 P B 6 /[S D O ] 1 + _ 1 O ] A ] S ] A ] S ] K ] 1 - L ] L ] P B 1 /O S C 1 1 0 3 9 P B 7 /[S D I/S D A ] V D D 1 1 3 8 P D 6 /[S C K /S C L ] 4 4 4 3 4 2 4 1 4 0 3 9 3 8 3 7 3 6 3 5 3 4 P B 5 /S C S 1 3 3 P D 3 /[T C K 1 ]/T P 3 _ 0 /[S D O ] P B 0 /R E S 1 2 3 7 P D 7 /[S C S ] P A 7 /S C K /S C L 2 3 2 P D 4 /[T P 2 _ 1 ] P E 5 /[T P 3 _ 0 ] 1 3 3 6 P C 4 /[IN T 0 ]/[P IN T ]/T P 2 _ 1 P A 6 /S D I/S D A 3 3 1 P D 5 /[T P 0 _ 1 ] P E 4 /[T P 1 B _ 2 ] 1 4 3 5 N C P A 5 /C 1 X /S D O 4 3 0 P E 0 P A 4 /IN T 1 /T C K 1 5 2 9 P E 1 P C 1 /T P 1 B _ 1 /S C O M 1 1 5 3 4 N C H T 6 8 F 5 0 P A 3 /IN T 0 /C 0 . its pin names at the right side of the ²/² sign can be used for higher priority. 6 2 8 P E 2 P C 0 /T P 1 B _ 0 /S C O M 0 1 6 3 3 N C 7 4 4 Q F P -A P A 2 /T C K 0 /C 0 + 2 7 P E 3 /[T P 3 _ 1 ] N C 1 7 3 2 P C 2 /T C K 2 /P C K /C 1 + P A 1 /T P 1 A 8 2 6 P C 6 /[T P 0 _ 0 ]/S C O M 2 P C 7 /[T P 1 A ]/S C O M 3 P C 3 /P IN T /T P 2 _ 0 /C 1 . 2.00 5 November 3. P A 4 /IN T 1 /T C K 1 5 H T 6 8 F 5 0 2 6 P C 6 /[T P 0 _ 0 ]/S C O M 2 P C 7 /[T P 1 A ]/S C O M 3 1 1 1 8 P C 4 /[IN T 0 ]/[P IN T ]/T C K 3 /T P 2 _ 1 P A 3 /IN T 0 /C 0 . 7 4 8 Q F N -A 3 0 P E 3 /[T P 3 _ 1 ] P A 2 /T C K 0 /C 0 + 8 2 9 P C 6 /[T P 0 _ 0 ]/S C O M 2 P A 1 /T P 1 A 9 2 8 P C 7 /[T P 1 A ]/S C O M 3 P A 0 /C 0 X /T P 0 _ 0 1 0 2 7 N C N C 1 1 2 6 P C 0 /T P 1 B _ 0 /S C O M 0 P F 1 /[C 1 X ] 1 2 2 5 P C 1 /T P 1 B _ 1 /S C O M 1 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 P F 0 P E 7 P E 6 V S S P B 4 P B 3 P B 2 P B 1 V D D P B 0 P E 5 P E 4 /[C 0 X ] /[IN T 1 ] /[IN T 0 ] /X T /X T /O S /O S /R E S /[T P 3 _ 0 ] /[T P 1 B _ 2 ] 2 1 C 2 C 1 Note: 1. HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 P C 5 /[IN T P C 4 /[IN P D 1 /[T P 1 D P T ]/T P 0 _ 1 /T P 1 B _ 2 /[P C 2 _ 0 ]/[S D O ]/[S C K /S C 0 /[T C K 2 ]/T P 3 _ 1 /[S C 0 ]/[P IN T ]/T C K 3 /T P 2 P C 3 /P IN T /T P 2 _ 0 /C P C 2 /T C K 2 /P C K /C P A 0 /C 0 X /T P 0 _ 0 1 2 8 P A 1 /T P 1 A P D 6 /[S C K /S C P B 7 /[S D I/S D V S S 2 2 7 P A 2 /T C K 0 /C 0 + P B 6 /[S D P D 7 /[S C P B 4 /X T 2 3 2 6 P A 3 /IN T 0 /C 0 - P B 3 /X T 1 4 2 5 P A 4 /IN T 1 /T C K 1 1 + _ 1 O ] P B 2 /O S C 2 5 2 4 P A 5 /C 1 X /S D O S ] A ] S ] K ] 1 - L ] L ] P B 1 /O S C 1 6 2 3 P A 6 /S D I/S D A 4 0 3 9 3 8 3 7 3 6 3 5 3 4 3 3 3 2 3 1 V D D 7 2 2 P A 7 /S C K /S C L P B 5 /S C S 1 3 0 P D 2 /[T C K 0 ]/[S D I/S D A ] P B 0 /R E S 8 2 1 P B 5 /S C S P A 7 /S C K /S C L 2 2 9 P D 3 /[T C K 1 ]/T P 3 _ 0 /[S D O ] P A 6 /S D I/S D A 3 2 8 P D 4 /[T P 2 _ 1 ] P C 1 /T P 1 B _ 1 /S C O M 1 9 2 0 P C 2 /T C K 2 /P C K /C 1 + 4 2 7 P D 5 /[T P 0 _ 1 ] P A 5 /C 1 X /S D O P C 0 /T P 1 B _ 0 /S C O M 0 1 0 1 9 P C 3 /P IN T /T P 2 _ 0 /C 1 . P A 0 /C 0 X /T P 0 _ 0 9 2 5 P C 7 /[T P 1 A ]/S C O M 3 1 8 3 1 P F 1 /[C 1 X ] 1 0 2 4 P C 0 /T P 1 B _ 0 /S C O M 0 P C 6 /[T P 0 _ 0 ]/S C O M 2 1 9 3 0 P C 5 /[IN T 1 ]/T P 0 _ 1 /T P 1 B _ 2 /[P C K ] P F 0 /[C 0 X ] 1 1 2 3 P C 1 /T P 1 B _ 1 /S C O M 1 P E 3 /[T P 3 _ 1 ] 2 9 P D 0 /[T C K 2 ]/[S C S ] 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 0 P E 2 2 1 2 8 P D 1 /[T P 2 _ 0 ]/[S D O ]/[S C K /S C L ] P E 7 P E 6 V S S P B 4 P B 3 P B 2 P B 1 V D D P B 0 P E 5 P E 4 P E 1 2 2 2 7 P D 2 /[T C K 0 ]/[S D I/S D A ] /[IN T 1 ] /[IN T 0 ] /X T /X T /O S /O S /R E S /[T P 3 _ 0 ] /[T P 1 B _ 2 ] P E 0 2 3 2 6 P D 3 /[T C K 1 ]/[S D O ] 2 1 C 2 C 1 P D 5 /[T P 0 _ 1 ] 2 4 2 5 P D 4 /[T P 2 _ 1 ] H T 6 8 F 5 0 P C 5 /[IN T 1 ]/T P 0 _ 1 /T P 1 B _ 2 /[P C 4 8 S S O P -A P C 4 /[IN T 0 ]/[P IN T ]/T C K 3 /T P 2 P D 1 /[T P 2 _ 0 ]/[S D O ]/[S C K /S C P D 0 /[T C K 2 ]/T P 3 _ 1 /[S C P D 2 /[T C K 0 ]/[S D I/S D P C 3 /P IN T /T P 2 _ 0 /C P C 2 /T C K 2 /P C K /C P D 6 /[S C K /S C P B 7 /[S D I/S D P B 6 /[S D P D 7 /[S C N 1 + _ 1 O ] A ] S ] A ] S ] K ] 1 - L ] L ] C 4 8 4 7 4 6 4 5 4 4 4 3 4 2 4 1 4 0 3 9 3 8 3 7 N C 1 3 6 P D 3 /[T C K 1 ]/T P 3 _ 0 /[S D O ] P B 5 /S C S 2 3 5 P D 4 /[T P 2 _ 1 ] P A 7 /S C K /S C L 3 3 4 P D 5 /[T P 0 _ 1 ] P A 6 /S D I/S D A 4 3 3 P E 0 P A 5 /C 1 X /S D O 5 3 2 P E 1 P A 4 /IN T 1 /T C K 1 6 H T 6 8 F 5 0 3 1 P E 2 P A 3 /IN T 0 /C 0 . 2009 . Rev. Bracketed pin names indicate non-default pinout remapping locations.

2. HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 P C 5 /IN T 3 /[IN T P C 5 /IN T 3 /[IN T P C 4 /IN T 2 /[IN P C 4 /IN T 2 /[IN P D 1 /[T P D 1 /[T P P 1 D P T 1 D P ]/T P 0 _ 1 /T P 1 B _ 2 /[P C T P D 2 /[T C K 0 ]/[S D I/S D 0 /[T C K 2 ]/T P 3 _ 1 /[S C 2 _ 0 ]/[S D O ]/[S C K /S C 0 ]/[P IN T ]/T C K 3 /T P 2 ]/T P 0 _ 1 /T P 1 B _ 2 /[P C 0 /[T C K 2 ]/T P 3 _ 1 /[S C 2 _ 0 ]/[S D O ]/[S C K /S C P C 3 /P IN T /T P 2 _ 0 /C 0 ]/[P IN T ]/T C K 3 /T P 2 P C 2 /T C K 2 /P C K /C P C 3 /P IN T /T P 2 _ 0 /C P C 2 /T C K 2 /P C K /C P D 6 /[S C K /S C P B 7 /[S D I/S D P D 6 /[S C K /S C P B 7 /[S D I/S D P B 6 /[S D P D 7 /[S C P B 6 /[S D P D 7 /[S C 1 + _ 1 O ] S ] A ] A ] S ] K ] 1 - L ] L ] 1 + _ 1 O ] A ] K ] S ] S ] 1 - L ] L ] 4 0 3 9 3 8 3 7 3 6 3 5 3 4 3 3 3 2 3 1 4 4 4 3 4 2 4 1 4 0 3 9 3 8 3 7 3 6 3 5 3 4 1 3 0 P D 2 /[T C K 0 ]/[S D I/S D A ] P B 5 /S C S 1 3 3 P D 3 /[T C K 1 ]/T P 3 _ 0 /[S D O ]/[S C K /S C L ] P B 5 /S C S 2 2 9 P D 3 /[T C K 1 ]/T P 3 _ 0 /[S D O ]/[S C K /S C L ] P A 7 /S C K /S C L 2 3 2 P D 4 /[T P 2 _ 1 ] P A 7 /S C K /S C L 3 2 8 P D 4 /[T P 2 _ 1 ] P A 6 /S D I/S D A 3 3 1 P D 5 /[T P 0 _ 1 ] P A 6 /S D I/S D A 4 2 7 P D 5 /[T P 0 _ 1 ] P A 5 /C 1 X /S D O 4 3 0 P E 0 /[IN T 0 ] P A 5 /C 1 X /S D O 5 P A 4 /IN T 1 /T C K 1 5 2 9 P E 1 /[IN T 1 ] P A 4 /IN T 1 /T C K 1 H T 6 8 F 6 0 2 6 P C 6 /[T P 0 _ 0 ]/S C O M 2 H T 6 8 F 6 0 6 4 0 Q F N -A 2 5 P C 7 /[T P 1 A ]/S C O M 3 P A 3 /IN T 0 /C 0 . 1 3 3 6 P E 2 /[IN T 2 ] P A 4 /IN T 1 /T C K 1 6 H T 6 8 F 6 0 3 1 P E 2 /[IN T 2 ] P A 2 /T C K 0 /C 0 + 1 4 3 5 P E 3 /[T P 3 _ 1 ] P A 3 /IN T 0 /C 0 . Rev. Bracketed pin names indicate non-default pinout remapping locations. 7 4 8 Q F N -A 3 0 P E 3 /[T P 3 _ 1 ] P A 1 /T P 1 A 1 5 3 4 P G 1 /[C 1 X ] P A 2 /T C K 0 /C 0 + 8 2 9 P C 6 /[T P 0 _ 0 ]/S C O M 2 P A 1 /T P 1 A 9 2 8 P C 7 /[T P 1 A ]/S C O M 3 P A 0 /C 0 X /T P 0 _ 0 1 6 3 3 P C 6 /[T P 0 _ 0 ]/S C O M 2 P A 0 /C 0 X /T P 0 _ 0 1 0 2 7 N C P F 1 /[C 1 X ] 1 7 3 2 P C 7 /[T P 1 A ]/S C O M 3 N C 1 1 2 6 P C 0 /T P 1 B _ 0 /S C O M 0 P F 0 /[C 0 X ] 1 8 3 1 P C 0 /T P 1 B _ 0 /S C O M 0 P F 1 /[C 1 X ] 1 2 2 5 P C 1 /T P 1 B _ 1 /S C O M 1 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 P E 7 /[IN T 1 ] 1 9 3 0 P C 1 /T P 1 B _ 1 /S C O M 1 P E 6 /[IN T 0 ] 2 0 2 9 P E 4 /[T P 1 B _ 2 ] P F 0 P E 7 P E 6 V S S P B 4 P B 3 P B 2 P B 1 V D D P B 0 P E 5 P E 4 V S S 2 1 2 8 P E 5 /[T P 3 _ 0 ] /[C 0 X ] /[IN T 1 ] /[IN T 0 ] /X T /X T /O S /O S /R E S /[T P 3 _ 0 ] /[T P 1 B _ 2 ] P B 4 /X T 2 2 2 2 7 P B 0 /R E S 2 1 C 2 C 1 P B 3 /X T 1 2 3 2 6 V D D P B 2 /O S C 2 2 4 2 5 P B 1 /O S C 1 P C 5 /IN T 3 /[IN T P C 4 /IN T 2 /[IN H T 6 8 F 6 0 4 8 S S O P -A P D 1 /[T P 1 D P T ]/T P 0 _ 1 /T P 1 B _ 2 /[P C P D 2 /[T C K 0 ]/[S D I/S D 0 /[T C K 2 ]/T P 3 _ 1 /[S C 2 _ 0 ]/[S D O ]/[S C K /S C 0 ]/[P IN T ]/T C K 3 /T P 2 P C 3 /P IN T /T P 2 _ 0 /C P C 2 /T C K 2 /P C K /C P D 6 /[S C K /S C P B 7 /[S D I/S D P B 6 /[S D P D 7 /[S C P P F 4 F 5 1 + _ 1 O ] S ] A ] A ] S ] K ] 1 - L ] L ] 5 2 5 1 5 0 4 9 4 8 4 7 4 6 4 5 4 4 4 3 4 2 4 1 4 0 P F 3 1 3 9 P D 3 /[T C K 1 ]/T P 3 _ 0 /[S D O ]/[S C K /S C L ] P F 2 2 3 8 P D 4 /[T P 2 _ 1 ] P B 5 /S C S 3 3 7 P D 5 /[T P 0 _ 1 ] P A 7 /S C K /S C L 4 3 6 P E 0 /[IN T 0 ] P A 6 /S D I/S D A 5 3 5 P E 1 /[IN T 1 ] P A 5 /C 1 X /S D O 6 3 4 P E 2 /[IN T 2 ] P A 4 /IN T 1 /T C K 1 7 H T 6 8 F 6 0 3 3 P E 3 /[T P 3 _ 1 ] 5 2 Q F P -A P A 3 /IN T 0 /C 0 . 8 3 2 P F 6 P A 2 /T C K 0 /C 0 + 9 3 1 P F 7 P A 1 /T P 1 A 1 0 3 0 P G 0 /[C 0 X ] P A 0 /C 0 X /T P 0 _ 0 1 1 2 9 P G 1 /[C 1 X ] P F 1 /[C 1 X ] 1 2 2 8 P C 6 /[T P 0 _ 0 ]/S C O M 2 P F 0 /[C 0 X ] 1 3 2 7 P C 7 /[T P 1 A ]/S C O M 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 P E 7 P E 6 V S S P B 4 P B 3 P B 2 P B 1 V D D P B 0 P E 5 P E 4 P C 1 P C 0 /[IN T 1 ] /[IN T 0 ] /X T /X T /O S /O S /R E /[T P /[T P /T P /T P 2 1 1 B 1 B S C 2 C 1 3 _ 1 B _ 1 /S C O M 1 _ 0 /S C O M 0 0 ] _ 2 ] Note: 1. its pin names at the right side of the ²/² sign can be used for higher priority. 6 2 8 P E 2 /[IN T 2 ] P A 3 /IN T 0 /C 0 . 2009 .00 6 November 3. 1. 4 4 Q F P -A 7 P A 2 /T C K 0 /C 0 + 7 2 7 P E 3 /[T P 3 _ 1 ] P A 2 /T C K 0 /C 0 + 2 4 P C 0 /T P 1 B _ 0 /S C O M 0 8 2 3 P C 1 /T P 1 B _ 1 /S C O M 1 P A 1 /T P 1 A 8 2 6 P C 6 /[T P 0 _ 0 ]/S C O M 2 P A 1 /T P 1 A 9 2 2 P E 4 /[T P 1 B _ 2 ] P A 0 /C 0 X /T P 0 _ 0 9 2 5 P C 7 /[T P 1 A ]/S C O M 3 P A 0 /C 0 X /T P 0 _ 0 1 0 2 1 P E 5 /[T P 3 _ 0 ] P F 1 /[C 1 X ] 1 0 2 4 P C 0 /T P 1 B _ 0 /S C O M 0 P F 1 /[C 1 X ] 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 P F 0 /[C 0 X ] 1 1 2 3 P C 1 /T P 1 B _ 1 /S C O M 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 P F 0 P E 7 P E 6 V S S P B 4 P B 3 P B 2 P B 1 V D D P B 0 P E 7 P E 6 V S S P B 4 P B 3 P B 2 P B 1 V D D P B 0 P E 5 P E 4 /[C 0 X ] /[IN T 1 ] /[IN T 0 ] /X T /X T /O S /O S /R E S /[IN T 1 ] /[IN T 0 ] /X T /X T /O S /O S /R E S /[T P 3 _ 0 ] /[T P 1 B _ 2 ] 2 1 C 2 C 1 2 1 C 2 C 1 P C 5 /IN T 3 /[IN T 1 ]/T P 0 _ 1 /T P 1 B _ 2 /[P C P C 4 /IN T 2 /[IN T 0 ]/[P IN T ]/T C K 3 /T P 2 P D 1 /[T P 2 _ 0 ]/[S D O ]/[S C K /S C P D 0 /[T C K 2 ]/T P 3 _ 1 /[S C N C 1 4 8 P C 2 /T C K 2 /P C K /C 1 + P D 2 /[T C K 0 ]/[S D I/S D N C 2 4 7 P C 3 /P IN T /T P 2 _ 0 /C 1 - P C 3 /P IN T /T P 2 _ 0 /C P C 2 /T C K 2 /P C K /C P D 7 /[S C S ] 3 4 6 P C 4 /IN T 2 /[IN T 0 ]/[P IN T ]/T C K 3 /T P 2 _ 1 P D 6 /[S C K /S C P B 7 /[S D I/S D P D 6 /[S C K /S C L ] 4 4 5 P C 5 /IN T 3 /[IN T 1 ]/T P 0 _ 1 /T P 1 B _ 2 /[P C K ] P B 7 /[S D I/S D A ] 5 4 4 P D 0 /[T C K 2 ]/T P 3 _ 1 /[S C S ] P B 6 /[S D P D 7 /[S C P B 6 /[S D O ] 6 4 3 P D 1 /[T P 2 _ 0 ]/[S D O ]/[S C K /S C L ] P F 2 7 4 2 P D 2 /[T C K 0 ]/[S D I/S D A ] N 1 + _ 1 O ] A ] S ] K ] S ] A ] 1 - L ] L ] C P B 5 /S C S /V R E F 8 4 1 P D 3 /[T C K 1 ]/T P 3 _ 0 /[S D O ]/[S C K /S C L ] P A 7 /S C K /S C L 9 4 0 P D 4 /[T P 2 _ 1 ] 4 8 4 7 4 6 4 5 4 4 4 3 4 2 4 1 4 0 3 9 3 8 3 7 N C 1 3 6 P D 3 /[T C K 1 ]/T P 3 _ 0 /[S D O ]/[S C K /S C L ] P A 6 /S D I/S D A 1 0 3 9 P D 5 /[T P 0 _ 1 ] P D 4 /[T P 2 _ 1 ] P B 5 /S C S 2 3 5 P A 5 /C 1 X /S D O 1 1 3 8 P E 0 /[IN T 0 ] P A 7 /S C K /S C L 3 3 4 P D 5 /[T P 0 _ 1 ] P A 4 /IN T 1 /T C K 1 1 2 3 7 P E 1 /[IN T 1 ] P A 6 /S D I/S D A 4 3 3 P E 0 /[IN T 0 ] P A 5 /C 1 X /S D O 5 3 2 P E 1 /[IN T 1 ] P A 3 /IN T 0 /C 0 . If the pin-shared pin functions have multiple outputs simultaneously.

C1+ Comparator 0.00 7 November 3. PA.1 etc. 1. PC1. TP1_1 TM1 I/O TMPC0 ST CMOS PA1. PA.0. 1 input AN ¾ PA2. not all of the above listed pins may be present on package types with smaller numbers of pins. 1 input AN ¾ PA3. Comparator 0. 2009 . however the details behind how each pin is configured is contained in other sections of the datasheet. which refer to the digital I/O function of the pins. However these Port pins are also shared with other function such as the Serial Port pins etc. PA4 PINT Peripheral Interrupt ¾ ST ¾ PC3 PCK Peripheral Clock output ¾ ¾ CMOS PC2 SDI SPI Data input ¾ ST ¾ PA6 SDO SPI Data output ¾ ¾ CMOS PA5 SCS SPI Slave Select ¾ ST CMOS PB5 SCK SPI Serial Clock ¾ ST CMOS PA7 SCL 2 I C Clock ¾ ST NMOS PA7 SDA 2 I C Data ¾ ST NMOS PA6 SCOM0~SCOM3 SCOM0~SCOM3 SCOMC ¾ SCOM PC0. C1. INT1 Ext. CO: Configuration option. C1X Comparator 0. The function of each pin is listed in the following table. Interrupt 0. HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 Pin Description With the exception of the power pins.g. PC3 CP0C C0+. all pins on these devices can be referenced by their Port name. PA4 TP0_0 TM0 I/O TMPC0 ST CMOS PA0 TP1_0. PC3 OSC1 HXT/ERC pin CO HXT ¾ PB1 OSC2 HXT pin CO ¾ HXT PB2 XT1 LXT pin CO LXT ¾ PB3 XT2 LXT pin CO ¾ LXT PB4 RES Reset input CO ST ¾ PB0 VDD Power supply ¾ PWR ¾ ¾ VSS Ground ¾ PWR ¾ ¾ Note: I/T: Input type. PA5 TCK0. 1 output ¾ CMOS PA0. PC2 CP1C C0X. PC0 INT0. PC2. TCK1 TM0. NMOS: NMOS output SCOM: Software controlled LCD COM. TM1 input ¾ ST ¾ PA2. ST: Schmitt Trigger input CMOS: CMOS output. Rev. O/T: Output type OP: Optional by configuration option (CO) or register option PWR: Power. e. HT68F20 Pin Name Function OP I/T O/T Pin-Shared Mapping PAWU PA0~PA7 Port A ST CMOS ¾ PAPU PB0~PB5 Port B PBPU ST CMOS ¾ PC0~PC3 Port C PCPU ST CMOS ¾ C0-. AN: Analog input pin HXT: High frequency crystal oscillator LXT: Low frequency crystal oscillator As the Pin Description Summary table applies to the package type with the most pins. 1 ¾ ST ¾ PA3.

PC1 INT0. PC3 CP0C C0+. TM1 input ¾ ST ¾ PA2. PA4 PINT Peripheral Interrupt PRM0 ST ¾ PC3 or PC4 PCK Peripheral Clock output PRM0 ¾ CMOS PC2 or PC5 SDI SPI Data input PRM0 ST ¾ PA6 or PC0 SDO SPI Data output PRM0 ¾ CMOS PA5 or PC1 SCS SPI Slave Select PRM0 ST CMOS PB5 or PC6 SCK SPI Serial Clock PRM0 ST CMOS PA7 or PC7 2 SCL I C Clock PRM0 ST NMOS PA7 or PC7 2 SDA I C Data PRM0 ST NMOS PA6 or PC0 SCOM0~SCOM3 SCOM0~SCOM3 SCOMC ¾ SCOM PC0. C1X Comparator 0. C1. INT1 Ext. PA4 TP0_0. TCK1 TM0. PC5 TP1A TM1 I/O TMPC0 ST CMOS PA1 TP1B_0. PC6. 1 output ¾ CMOS PA0. not all of the above listed pins may be present on package types with smaller numbers of pins. 1. O/T: Output type OP: Optional by configuration option (CO) or register option PWR: Power. 1 input AN ¾ PA3. Interrupt 0. 1 ¾ ST ¾ PA3. AN: Analog input pin HXT: High frequency crystal oscillator LXT: Low frequency crystal oscillator As the Pin Description Summary table applies to the package type with the most pins. ST: Schmitt Trigger input CMOS: CMOS output. TP1B_1 TM1 I/O TMPC0 ST CMOS PC0. 1 input AN ¾ PA2. TP0_1 TM0 I/O TMPC0 ST CMOS PA0. C1+ Comparator 0. PC2 CP1C C0X. Comparator 0. PA5 TCK0. HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68F30 Pin Name Function OP I/T O/T Pin-Shared Mapping PAWU PA0~PA7 Port A ST CMOS ¾ PAPU PB0~PB5 Port B PBPU ST CMOS ¾ PC0~PC7 Port C PCPU ST CMOS ¾ C0-. Rev. NMOS: NMOS output SCOM: Software controlled LCD COM. PC1.00 8 November 3. 2009 . PC7 OSC1 HXT/ERC pin CO HXT ¾ PB1 OSC2 HXT pin CO ¾ HXT PB2 XT1 LXT pin CO LXT ¾ PB3 XT2 LXT pin CO ¾ LXT PB4 RES Reset input CO ST ¾ PB0 VDD Power supply ¾ PWR ¾ ¾ VSS Ground ¾ PWR ¾ ¾ Note: I/T: Input type. CO: Configuration option.

00 9 November 3. 2009 . PC4 or PD1. PA4. 1 input AN ¾ PA3. PE7 PINT Peripheral Interrupt PRM0 ST ¾ PC3 or PC4 PCK Peripheral Clock output PRM0 ¾ CMOS PC2 or PC5 SDI SPI Data input PRM0 ST ¾ PA6 or PD2 or PB7 SDO SPI Data output PRM0 ¾ CMOS PA5 or PD3 or PB6 SCS SPI Slave Select PRM0 ST CMOS PB5 or PD0 or PD7 SCK SPI Serial Clock PRM0 ST CMOS PA7 or PD1 or PD6 2 SCL I C Clock PRM0 ST NMOS PA7 or PD1 or PD6 2 SDA I C Data PRM0 ST NMOS PA6 or PD2 or PB7 SCOM0~SCOM3 SCOM0~SCOM3 SCOMC ¾ SCOM PC0. PC5 or INT0. HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68F40 Pin Name Function OP I/T O/T Pin-Shared Mapping PAWU PA0~PA7 Port A ST CMOS ¾ PAPU PB0~PB7 Port B PBPU ST CMOS ¾ PC0~PC7 Port C PCPU ST CMOS ¾ PD0~PD7 Port D PDPU ST CMOS ¾ PE0~PE7 Port E PEPU ST CMOS ¾ PF0~PF1 Port F PFPU ST CMOS ¾ CP0C C0-. PC5 or PC6. 1 output CP1C ¾ CMOS PA0. Interrupt 0. PC1. C1X Comparator 0. PA5 or PF0. INT1 Ext. PC2 CP1C CP0C C0X. PC1. 1 PRM1 ST ¾ PE6. TP0_1 TM0 I/O ST CMOS PA0. PC7 OSC1 HXT/ERC pin CO HXT ¾ PB1 OSC2 HXT pin CO ¾ HXT PB2 XT1 LXT pin CO LXT ¾ PB3 XT2 LXT pin CO ¾ LXT PB4 RES Reset input CO ST ¾ PB0 VDD Power supply ¾ PWR ¾ ¾ VSS Ground ¾ PWR ¾ ¾ Rev. PD5 PRM2 TMPC0 TP1A TM1 I/O ST CMOS PA1 or PC7 PRM2 TMPC0 PC0. Comparator 0. PC2 or TCK0~TCK2 TM0~TM2 input PRM1 ST ¾ PD2. 1. PA4 or PC4. PD4 PRM2 PA3. PE4 TMPC1 TP2_0. PC3 CP1C CP0C C0+. PC6. -. TP2_1 TM2 I/O ST CMOS PC3. C1. PF1 PRM0 PA2. PD3. C1+ Comparator 0. PC5 or TP1B_0~TP1B_2 TM1 I/O ST CMOS PRM2 -. 1 input AN ¾ PA2. PD0 TMPC0 TP0_0.

1 output CP1C ¾ CMOS PA0. PC2 CP1C CP0C C0X. 1 input AN ¾ PA3. - TMPC0 TP0_0. PC5 or PC6. PF1 PRM0 PA2. AN: Analog input pin HXT: High frequency crystal oscillator LXT: Low frequency crystal oscillator As the Pin Description Summary table applies to the package type with the most pins. HT68F50 Pin Name Function OP I/T O/T Pin-Shared Mapping PAWU PA0~PA7 Port A ST CMOS ¾ PAPU PB0~PB7 Port B PBPU ST CMOS ¾ PC0~PC7 Port C PCPU ST CMOS ¾ PD0~PD7 Port D PDPU ST CMOS ¾ PE0~PE7 Port E PEPU ST CMOS ¾ PF0~PF1 Port F PFPU ST CMOS ¾ CP0C C0-. PC4 or TCK0~TCK3 TM0~TM3 input PRM1 ST ¾ PD2.00 10 November 3. PE7 PINT Peripheral Interrupt PRM0 ST ¾ PC3 or PC4 PCK Peripheral Clock output PRM0 ¾ CMOS PC2 or PC5 SDI SPI Data input PRM0 ST ¾ PA6 or PD2 or PB7 SDO SPI Data output PRM0 ¾ CMOS PA5 or PD3 or PB6 SCS SPI Slave Select PRM0 ST CMOS PB5 or PD0 or PD7 SCK SPI Serial Clock PRM0 ST CMOS PA7 or PD1 or PD6 Rev. C1X Comparator 0. PD4 PRM2 TMPC1 TP3_0. not all of the above listed pins may be present on package types with smaller numbers of pins. PA4 or PC4. PC2. NMOS: NMOS output SCOM: Software controlled LCD COM. Interrupt 0. PC1. PD5 PRM2 TMPC0 TP1A TM1 I/O ST CMOS PA1 or PC7 PRM2 TMPC0 PC0. PD0. -. 1 input AN ¾ PA2. TP3_1 TM3 I/O ST CMOS PD3. C1. PD3. TP2_1 TM2 I/O ST CMOS PC3. 2009 . PA5 or PF0. PC5 or TP1B_0~TP1B_2 TM1 I/O ST CMOS PRM2 -. CO: Configuration option. PA4. PC3 CP1C CP0C C0+. C1+ Comparator 0. ST: Schmitt Trigger input CMOS: CMOS output. PC4 or PD1. PD0 or PE5. HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 Note: I/T: Input type. Comparator 0. TP0_1 TM0 I/O ST CMOS PA0. PE3 PRM2 PA3. PE4 TMPC1 TP2_0. INT1 Ext. O/T: Output type OP: Optional by configuration option (CO) or register option PWR: Power. PC5 or INT0. 1. 1 PRM1 ST ¾ PE6.

PC2. TP0_1 TM0 I/O ST CMOS PA0. O/T: Output type OP: Optional by configuration option (CO) or register option PWR: Power. C1+ Comparator 0. 1 input AN ¾ PA3. PG1 PRM0 PA2. PC4 or TCK0~TCK3 TM0~TM3 input PRM1 ST ¾ PD2. - TMPC0 TP0_0. 2009 . PC1. Comparator 0. not all of the above listed pins may be present on package types with smaller numbers of pins. ST: Schmitt Trigger input CMOS: CMOS output. PD3. PC5 or PC6. HT68F60 Pin Name Function OP I/T O/T Pin-Shared Mapping PAWU PA0~PA7 Port A ST CMOS ¾ PAPU PB0~PB7 Port B PBPU ST CMOS ¾ PC0~PC7 Port C PCPU ST CMOS ¾ PD0~PD7 Port D PDPU ST CMOS ¾ PE0~PE7 Port E PEPU ST CMOS ¾ PF0~PF7 Port F PFPU ST CMOS ¾ PG0~PG1 Port G PGPU ST CMOS ¾ CP0C C0-. PC2 CP1C CP0C PA0. 1 output CP1C ¾ CMOS PG0. PC6. PC3 CP1C CP0C C0+. C1X Comparator 0. PF1 or C0X. HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 Pin Name Function OP I/T O/T Pin-Shared Mapping 2 SCL I C Clock PRM0 ST NMOS PA7 or PD1 or PD6 2 SDA I C Data PRM0 ST NMOS PA6 or PD2 or PB7 SCOM0~SCOM3 SCOM0~SCOM3 SCOMC ¾ SCOM PC0.00 11 November 3. 1. CO: Configuration option. AN: Analog input pin HXT: High frequency crystal oscillator LXT: Low frequency crystal oscillator As the Pin Description Summary table applies to the package type with the most pins. PC7 OSC1 HXT/ERC pin CO HXT ¾ PB1 OSC2 HXT pin CO ¾ HXT PB2 XT1 LXT pin CO LXT ¾ PB3 XT2 LXT pin CO ¾ LXT PB4 RES Reset input CO ST ¾ PB0 VDD Power supply ¾ PWR ¾ ¾ VSS Ground ¾ PWR ¾ ¾ Note: I/T: Input type. NMOS: NMOS output SCOM: Software controlled LCD COM. PA4. PD5 PRM2 TMPC0 TP1A TM1 I/O ST CMOS PA1 or PC7 PRM2 Rev. PD0. PA5 or PF0. 1 input AN ¾ PA2. C1.

PA4. ST: Schmitt Trigger input CMOS: CMOS output. -. PC1. PC4. AN: Analog input pin HXT: High frequency crystal oscillator LXT: Low frequency crystal oscillator As the Pin Description Summary table applies to the package type with the most pins. PC5 or PC4. O/T: Output type OP: Optional by configuration option (CO) or register option PWR: Power. PC5. TP2_1 TM2 I/O ST CMOS PC3. - PINT Peripheral Interrupt PRM0 ST ¾ PC3 or PC4 PCK Peripheral Clock output PRM0 ¾ CMOS PC2 or PC5 SDI SPI Data input PRM0 ST ¾ PA6 or PD2 or PB7 PA5 or PD3 or PB6 or SDO SPI Data output PRM0 ¾ CMOS PD1 SCS SPI Slave Select PRM0 ST CMOS PB5 or PD0 or PD7 PA7 or PD1 or PD6 or SCK SPI Serial Clock PRM0 ST CMOS PD3 PA7 or PD1 or PD6 or SCL I2C Clock PRM0 ST NMOS PD3 SDA I2C Data PRM0 ST NMOS PA6 or PD2 or PB7 SCOM0~SCOM3 SCOM0~SCOM3 SCOMC ¾ SCOM PC0.or PE6. NMOS: NMOS output SCOM: Software controlled LCD COM. . or INT0~INT3 Ext. TP3_1 TM3 I/O ST CMOS PD3. PC6.00 12 November 3. PC7 OSC1 HXT/ERC pin CO HXT ¾ PB1 OSC2 HXT pin CO ¾ HXT PB2 XT1 LXT pin CO LXT ¾ PB3 XT2 LXT pin CO ¾ LXT PB4 RES Reset input CO ST ¾ PB0 VDD Power supply ¾ PWR ¾ ¾ VSS Ground ¾ PWR ¾ ¾ Note: I/T: Input type. Interrupt 0~3 PRM1 ST ¾ PE0. PE1. PC1. PD4 PRM2 TMPC1 TP3_0. not all of the above listed pins may be present on package types with smaller numbers of pins. 2009 . PD0 or PE5. PE4 TMPC1 TP2_0. -. CO: Configuration option. 1. HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 Pin Name Function OP I/T O/T Pin-Shared Mapping TMPC0 PC0. PE3 PRM2 PA3. PC4 or PD1. -. -. PE2. PE7. PC5 or TP1B_0~TP1B_2 TM1 I/O ST CMOS PRM2 -. Rev.

.. LIRC) WDT enable 5V ¾ 30 50 mA IDLE0 Mode Stanby Current 3V ¾ 1...0 mA WDT enable (HXT) Operating Current...... Typ... No load...00 13 November 3. ¾ 2................5 5...0 mA (HXT.9VDD ¾ VDD V Rev............-80mA Total Power Dissipation . ¾ 0........55 0........0 mA ISLEEP1 No load............. HIRC) fSYS=12MHz on 5V ¾ 1.. HIRC) 3V No load.4VDD V VIH2 Input High Voltage (RES) ¾ ¾ 0.......5 V 3V No load. HIRC) fSYS=20MHz 4.....6 2..3VDD V Input Pins except RES pin Input High Voltage for I/O Ports VIH1 ¾ ¾ 0. Max..... 3V No load.......0V Storage Temperature .7 mA Operating Current..7 ¾ 5....... ERC. 3V ¾ 1.5 3.2 ¾ 5.... Stresses exceeding the range specified under ²Absolute Maximum Ratings² may cause substantial damage to the device.. WDT disable (LXT and LIRC off) 5V ¾ ¾ 2 mA SLEEP1 Mode Stanby Current 3V ¾ 1......... Unit VDD Conditions fSYS=8MHz 2..5 3...VSS-0...3V to VDD+0.......5 mA Operating Current..7 1.2 3..........3V to VSS+6..80mA IOH Total.. fSYS=fL.......7VDD ¾ VDD V or Input Pins except RES pin VIL2 Input Low Voltage (RES) ¾ ¾ 0 ¾ 0. ERC.0 mA IDLE1 Mode Stanby Current 3V No load. WDT enable..... Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability..... WDT enable (LXT or LIRC on) 5V ¾ 2..30 2. fSYS=fH 5V WDT enable ¾ 3.......... HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 Absolute Maximum Ratings Supply Voltage ..0 mA Input Low Voltage for I/O Ports or VIL1 ¾ ¾ 0 ¾ 0.. ¾ 0.. fSYS=fH=12MHz....0 9..C..1 mA 5V WDT enable ¾ 1..-50°C to 125°C Input Voltage. fSYS=fH=20MHz...3 5...8 2............... fSYS=fH=4MHz. WDT enable (LXT or LIRC on) 5V ¾ 3....3 mA 5V WDT enable ¾ 5.5 V Operating Voltage VDD ¾ fSYS=12MHz 2.......5 ¾ 5........ fSYS=fH=8MHz.. ¾ 10 20 mA IDD3 fSYS=fL (LXT.83 mA IIDLE1 (HXT.0 mA IIDLE0 No load..... D.... Characteristics Ta=25°C Test Conditions Symbol Parameter Min. IDD2 Normal Mode........0 7.......VSS-0.........0 6....-40°C to 85°C IOL Total ...500mW Note: These are stress ratings only.............. 1. IDD1 Normal Mode...00 mA SLEEP0 Mode Stanby Current 3V ¾ ¾ 1 mA ISLEEP0 No load....3V Operating Temperature.......... fSYS=fH 5V ¾ 6.... ERC.. 2009 ..... Slow Mode.5 V (HXT.4 mA No load..

1.40 +5% V LVR Enable. VLVD=2.5 25. VLVD=3.70 +5% V VLVD LVD Voltage Level ¾ LVDEN=1.4V -5% 4. 4.10V option -5% 2.15V option -5% 3.3V -5% 3. 2.500 0. VLVD=3.7V -5% 2. 2.2V -5% 2.6V -5% 3.2mA 2.30 +5% V LVDEN=1. ISEL[1:0]=10 70 100 130 mA SCOMC. Max.5 V 3V IOH=-3.40 +5% V LVDEN=1.5 ¾ ¾ V Pull-high Resistance for I/O 3V 20 60 100 kW RPH ¾ Ports 5V 10 30 50 kW SCOMC.00 +5% V LVDEN=1.55 +5% V VLVR LVR Voltage Level ¾ LVR Enable.00 14 November 3. 3. VLVD=4. VLVD=2.3 V VOL Output Low Voltage I/O Port 5V IOL=20mA ¾ ¾ 0.0V -5% 2.20 +5% V LVDEN=1.5 mA SCOMC. ISEL[1:0]=00 17.0V -5% 3.0 32.55V option -5% 2. HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 Ta=25°C Test Conditions Symbol Parameter Min. VLVD=3.20V option -5% 4. ISEL[1:0]=01 35 50 65 mA ISCOM SCOM Operating Current 5V SCOMC.00 +5% V LVDEN=1.60 +5% V LVDEN=1.20 +5% V LVDEN=1.525 VDD Rev.4mA 4. VLVD=2. 2009 . Typ.10 +5% V LVR Enable. LVDEN=0 ¾ 60 90 mA Additional Power Consumption if ILV ¾ LVR disable. LVDEN=1 ¾ 90 135 mA 3V IOL=9mA ¾ ¾ 0. LVDEN=1 ¾ 75 115 mA LVR and LVD is Used LVR enable. VLVD=2.475 0.7 ¾ ¾ V VOH Output High Voltage I/O Port 5V IOH=-7.15 +5% V LVR Enable.4V -5% 2. ISEL[1:0]=11 140 200 260 mA VSCOM VDD/2 Voltage for LCD COM 5V No load 0. Unit VDD Conditions LVR Enable.

HT68F20/HT68F30/HT68F40/HT68F50/HT68F60

A.C. Characteristics Ta=25°C

Test Conditions
Symbol Parameter Min. Typ. Max. Unit
VDD Conditions
2.2V~5.5V DC ¾ 8 MHz
fCPU Operating Clock ¾ 2.7V~5.5V DC ¾ 12 MHz

4.5V~5.5V DC ¾ 20 MHz

2.2V~5.5V 0.4 ¾ 8 MHz
fSYS System Clock (HXT) ¾ 2.7V~5.5V 0.4 ¾ 12 MHz

4.5V~5.5V 0.4 ¾ 20 MHz

3V/5V Ta=25°C -2% 4 +2% MHz

3V/5V Ta=25°C -2% 8 +2% MHz

5V Ta=25°C -2% 12 +2% MHz

3V/5V Ta=0~70°C -5% 4 +5% MHz

3V/5V Ta=0~70°C -4% 8 +4% MHz

5V Ta=0~70°C -5% 12 +3% MHz
2.2V~
Ta=0~70°C -7% 4 +7% MHz
3.6V
3.0V~
Ta=0~70°C -5% 4 +9% MHz
5.5V
2.2V~
Ta=0~70°C -6% 8 +4% MHz
3.6V
System Clock
fHIRC
(HIRC) 3.0V~
Ta=0~70°C -4% 8 +9% MHz
5.5V
3.0V~
Ta=0~70°C -6% 12 +7% MHz
5.5V
2.2V~
Ta= -40°C~85°C -12% 4 +8% MHz
3.6V
3.0V~
Ta= -40°C~85°C -10% 4 +9% MHz
5.5V
2.2V~
Ta= -40°C~85°C -15% 8 +4% MHz
3.6V
3.0V~
Ta= -40°C~85°C -8% 8 +9% MHz
5.5V
3.0V~
Ta= -40°C~85°C -12% 12 +7% MHz
5.5V
5V Ta=25°C, R=120kW * -2% 8 +2% MHz

5V Ta=0~70°C, R=120kW * -5% 8 +6% MHz

Ta= -40°C~85°C,
5V -7% 8 +9% MHz
R=120kW *
fERC System Clock (ERC)
3.0V~ Ta= -40°C~85°C,
-9% 8 +10% MHz
5.5V R=120kW *

2.2V~ Ta= -40°C~85°C,
-15% 8 +10% MHz
5.5V R=120kW *
fLXT System Clock (LXT) ¾ ¾ ¾ 32.768 ¾ kHz

Rev. 1.00 15 November 3, 2009

HT68F20/HT68F30/HT68F40/HT68F50/HT68F60
Ta=25°C

Test Conditions
Symbol Parameter Min. Typ. Max. Unit
VDD Conditions
fLIRC System Clock (LIRC) 5V Ta=25°C -10% 32 +10% kHz
fTIMER Timer Input Pin Frequency ¾ ¾ ¾ ¾ 1 fSYS

tRES External Reset Low Pulse Width ¾ ¾ 1 ¾ ¾ ms
tINT Interrupt Pulse Width ¾ ¾ 1 ¾ ¾ tSYS

tLVR Low Voltage Width to Reset ¾ ¾ 120 240 480 ms
tLVD Low Voltage Width to Interrupt ¾ ¾ 20 45 90 ms
tLVDS LVDO stable time ¾ ¾ 15 ¾ ¾ ms
tBGS VBG Turn on Stable Time ¾ ¾ 200 ¾ ¾ ms
tEERD EEPROM Read Time ¾ ¾ ¾ 45 90 ms
tEEWR EEPROM Write Time ¾ ¾ ¾ 2 4 ms
fSYS=HXT or LXT ¾ 1024 ¾
System Start-up Timer Period
tSST ¾ fSYS=ERC or HIRC ¾ 15~16 ¾ tSYS
(Wake-up from HALT)
fSYS=LIRC OSC ¾ 1~2 ¾

Note: 1. tSYS=1/fSYS
2. * For fERC, as the resistor tolerance will influence the frequency a precision resistor is recommended.
3. To maintain the accuracy of the internal HIRC oscillator frequency, a 0.1mF decoupling capacitor should be
connected between VDD and VSS and located as close to the device as possible.

Comparator Electrical Characteristics Ta=25°C

Test Conditions
Symbol Parameter Min. Typ. Max. Unit
VDD Conditions
VCMP Comparator Operating Voltage ¾ ¾ 2.2 ¾ 5.5 V

3V ¾ ¾ 37 56 mA
ICMP Comparator Operating Current
5V ¾ ¾ 130 200 mA
VCMPOS Comparator Input Offset Voltage ¾ ¾ -10 ¾ 10 mV
VHYS Hysteresis Width ¾ ¾ 20 40 60 mV
Comparator Common Mode
VCM ¾ ¾ VSS ¾ VDD-1.4V V
Voltage Range
AOL Comparator Open Loop Gain ¾ ¾ 60 80 ¾ dB
With 100mV
tPD Comparator Response Time ¾ ¾ 370 560 ns
overdrive (Note)

Note: Measured with comparator one input pin at VCM = (VDD-1.4)/2 while the other pin input transition from VSS to
(VCM +100mV) or from VDD to (VCM -100mV).

Rev. 1.00 16 November 3, 2009

HT68F20/HT68F30/HT68F40/HT68F50/HT68F60

Power-on Reset Characteristics Ta=25°C

Test Conditions
Symbol Parameter Min. Typ. Max. Unit
VDD Conditions
VDD Start Voltage to Ensure
VPOR ¾ ¾ ¾ ¾ 100 mV
Power-on Reset
VDD Raising Rate to Ensure
RRVDD ¾ ¾ 0.035 ¾ ¾ V/ms
Power-on Reset
Minimum Time for VDD Stays at
tPOR ¾ ¾ 1 ¾ ¾ ms
VPOR to Ensure Power-on Reset

V D D

tP O R R R V D D

V P O R
T im e

Rev. 1.00 17 November 3, 2009

HT68F20/HT68F30/HT68F40/HT68F50/HT68F60

System Architecture
A key factor in the high-performance features of the ternally generated non-overlapping clocks, T1~T4. The
Holtek range of microcontrollers is attributed to their in- Program Counter is incremented at the beginning of the
ternal system architecture. The range of devices take T1 clock during which time a new instruction is fetched.
advantage of the usual features found within RISC The remaining T2~T4 clocks carry out the decoding and
microcontrollers providing increased speed of operation execution functions. In this way, one T1~T4 clock cycle
and enhanced performance. The pipelining scheme is forms one instruction cycle. Although the fetching and
implemented in such a way that instruction fetching and execution of instructions takes place in consecutive in-
instruction execution are overlapped, hence instructions struction cycles, the pipelining structure of the
are effectively executed in one cycle, with the exception microcontroller ensures that instructions are effectively
of branch or call instructions. An 8-bit wide ALU is used executed in one instruction cycle. The exception to this
in practically all instruction set operations, which carries are instructions where the contents of the Program
out arithmetic operations, logic operations, rotation, in- Counter are changed, such as subroutine calls or
crement, decrement, branch decisions, etc. The internal jumps, in which case the instruction will take one more
data path is simplified by moving data through the Accu- instruction cycle to execute.
mulator and the ALU. Certain internal registers are im-
For instructions involving branches, such as jump or call
plemented in the Data Memory and can be directly or instructions, two machine cycles are required to com-
indirectly addressed. The simple addressing methods of
plete instruction execution. An extra cycle is required as
these registers along with additional architectural fea-
the program takes one cycle to first obtain the actual
tures ensure that a minimum of external components is
jump or call address and then another cycle to actually
required to provide a functional I/O control system with
execute the branch. The requirement for this extra cycle
maximum reliability and flexibility. This makes the de-
should be taken into account by programmers in timing
vice suitable for low-cost, high-volume production for
sensitive applications.
controller applications.

Clocking and Pipelining
The main system clock, derived from either a HXT, LXT,
HIRC, LIRC or ERC oscillator is subdivided into four in-

fS Y S
(S y s te m C lo c k )

P h a s e C lo c k T 1

P h a s e C lo c k T 2

P h a s e C lo c k T 3

P h a s e C lo c k T 4

P ro g ra m C o u n te r P C P C + 1 P C + 2

F e tc h In s t. (P C )
P ip e lin in g
E x e c u te In s t. (P C -1 ) F e tc h In s t. (P C + 1 )
E x e c u te In s t. (P C ) F e tc h In s t. (P C + 2 )
E x e c u te In s t. (P C + 1 )

System Clocking and Pipelining

1 M O V A ,[1 2 H ] F e tc h In s t. 1 E x e c u te In s t. 1
2 C A L L D E L A Y F e tc h In s t. 2 E x e c u te In s t. 2
3 C P L [1 2 H ] F e tc h In s t. 3 F lu s h P ip e lin e
4 : F e tc h In s t. 6 E x e c u te In s t. 6
5 : F e tc h In s t. 7
6 D E L A Y : N O P

Instruction Fetching

Rev. 1.00 18 November 3, 2009

non-consecutive Program Memory address. As these ALU calculation or oper- also be noted that a dummy cycle will be inserted. the ALU receives related in- this low byte is available for manipulation. DEC ther readable nor writeable. required address into the Program Counter. RLA. is available for The arithmetic-logic unit or ALU is a critical area of the program control and is a readable and writeable register. overflow. S ta c k L e v e l 2 rect instruction is obtained. For condi- P ro g ra m C o u n te r tional skip instructions. the Stack Pointer will point to the top of the stack. During program execution. RL. however. DAA save the contents of the Program Counter only. known as the Program Counter Low Regis. RETI gram Counter are pushed onto the stack. as only microcontroller data bus. interrupt or reset. After a device reset. dated to reflect these changes. the Program Counter is used the interrupt request flag will be recorded but the ac- to keep track of the address of the next instruction to be knowledge signal will be inhibited. CALL. a CALL subroutine in- lower 8 bits. struction can still be executed which will result in a stack ter. RRC. JMP. the contents of the Pro- SIZA. non-consecutive addresses such as a jump instruction. XOR. ORM. space. the first Program Counter save in microcontroller manages program control by loading the the stack will be lost. RET or RETI. The acti. etc. the interrupt time an instruction is executed except for instructions. At a subroutine call or · Branch decision. The ALU supports the following functions: Stack · Arithmetic operations: ADD.ALU Program Counter Low register or PCL. which has already been fetched during the present instruction execution. Only the However. known as the Arithmetic and Logic Unit . when the stack is full. the status register will be correspondingly up- so an extra cycle is needed to pre-fetch. Connected to the main gram jump can be executed directly. SBCM. INC. signaled by a return instruction. will be serviced. ations of the instruction set. ADCM. RRCA. ations may result in carry. PC8 HT68F30 PC10~PC8 Device Stack Levels HT68F40 PC11~PC8 PCL7~PCL0 HT68F20/HT68F30 4 HT68F50 PC12~PC8 HT68F40/HT68F50 8 HT68F60 PC13~PC8 HT68F60 12 Program Counter The lower byte of the Program Counter. RET. borrow or other status ulating the PCL register may cause program branching. RLC vated level is indexed by the Stack Pointer. Manip. This feature prevents stack overflow al- such as ²JMP² or ²CALL² that demand a jump to a lowing the programmer to use the structure more easily. ANDM. 2009 . logical operations after which the result will be placed in tions. a subroutine call. stack has multiple levels depending upon the device XORM. changes. SUBM. RLCA. RR. CPL. microcontroller that carries out arithmetic and logic oper- By transferring data directly into this register. SIZ. SZA.00 19 November 3. The · Logic operations: AND. HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 Program Counter If the stack is full and an enabled interrupt takes place.. DECA. ADC. Precautions should be taken to avoid such cases which might cause unpredictable program When executing instructions requiring jumps to branching. OR. SDZA. once the condition has been met. the jumps are struction codes and performs the required arithmetic or limited to the present page of memory. and is nei- · Increment and Decrement INCA. When such program jumps are executed it should the specified register. SBC. by RET or RETI. are directly addressable by the application program. the If the stack is overflow. and is neither readable nor writeable. SZ. CPLA and is neither part of the data nor part of the program · Rotation RRA. ADDM. that is 256 loca. Rev. S ta c k S ta c k L e v e l 3 P ro g ra m P o in te r M e m o ry Program Counter Device Program Counter PCL Register B o tto m o f S ta c k S ta c k L e v e l N High Byte HT68F20 PC9. the next instruction. At the end of a subroutine or an interrupt routine. SNZ. SDZ. It is automatically incremented by one each Pointer is decremented. When the Stack executed. is dis. T o p o f S ta c k S ta c k L e v e l 1 carded and a dummy cycle takes its place while the cor. interrupt acknowledge signal. 1. This is a special part of the memory which is used to SUB. the Program Counter is re- stored to its previous value from the stack. a short pro.

byte will be read as ²0². This example uses raw table data lo- jump to this location and begin execution. table data is defined and retrieved from the ation. first be setup by placing the address of the look up data cation on the same device. Any unused bits in this transferred higher order dressed by a separate table pointer register. The location 000H is The following example shows how the table pointer and reserved for use by the device reset for program initialis. allowing the user the convenience of code modifi. certain locations are re- served for the reset and interrupts. Bank 0 and Bank 1. look-up table. is ad- register. When the instruction is executed. cated in the Program Memory which is stored there us- H T 6 8 F 2 0 H T 6 8 F 3 0 H T 6 8 F 4 0 H T 6 8 F 5 0 H T 6 8 F 6 0 0 0 0 0 H R e s e t R e s e t R e s e t R e s e t R e s e t 0 0 0 4 H In te rru p t In te rru p t In te rru p t In te rru p t In te rru p t 0 0 2 C H V e c to r V e c to r V e c to r V e c to r V e c to r 0 0 3 C H 0 3 F F H 1 4 b its B a n k 0 0 7 F F H 1 4 b its 0 F F F H 1 5 b its 1 F F F H 1 6 b its 1 F F F H 1 6 b its 2 0 0 0 H B a n k 1 2 F F F H Program Memory Structure Rev. After a device reset is initiated. To use the look-up table. the table pointer must times. HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 Flash Program Memory The Program Memory is the location where the user Look-up Table code or program is stored. these Flash devices offer users the TBHP. Device Capacity Banks The accompanying diagram illustrates the addressing HT68F20 1K´14 0 data flow of the look-up table. The higher order table data byte from the tion and interrupt entries. R e g is te r T B L H R e g is te r lected using Bit 5 of the BP Register. table informa- the instruction. respectively. After setting up the table pointer. For this device series the Any location within the Program Memory can be defined Program Memory is Flash type. The required Bank is se. 2009 . 1 The HT68F60 has its Program Memory divided into two U s e r S e le c te d Banks. These registers define the total address of the flexibility to conveniently debug and develop their appli. 1. By using the appropriate to be retrieved in the table pointer register. the lower order table The Program Memory has a capacity of 1K´14 bits to byte from the Program Memory will be transferred to the 12K´16 bits.00 20 November 3. Table data. H ig h B y te L o w B y te Special Vectors Table Program Example Within the Program Memory. HT68F30 2K´14 0 P ro g ra m M e m o ry L a s t p a g e o r HT68F40 0 A d d re s s 4K´15 T B H P R e g is te r D a ta HT68F50 8K´16 0 1 4 ~ 1 6 b its T B L P R e g is te r HT68F60 12K´16 0. which can be Program Memory will be transferred to the TBLH special setup in any location within the Program Memory. the program will microcontroller. cations while also offering a means of field programming and updating. TBLP and programming tools. the table data can be retrieved from the Program Memory using the Structure ²TABRD[m]² or ²TABRDL[m]² instructions. The Program Memory is addressed by the user defined Data Memory register [m] as specified in Program Counter and also contains data. which means it can be as a look-up table where programmers can store fixed programmed and re-programmed a large number of data.

Data is downloaded and uploaded serially on instructions should be avoided. This enables product manufac- page. The value at this ORG As an additional convenience. initialise low table pointer .06h . The high byte of and re-insertion of the device. initialise high table pointer tbhp. HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 ing the ORG statement. is referenced mov a. the table data which in this case is equal to zero will be MCU Programming Function transferred to the TBLH register automatically when the Pins ²TABRD [m]² instruction is executed. poses. However. 00Eh. register tempreg2 : : org 700h .07h . 2009 . The table pointer is setup here to have an ini. The technical details regarding the main routine table-read instructions.a . In Circuit Programming During the programming process the RES pin will be held low by the programmer disabling the normal opera- The provision of Flash type Program Memory provides tion of the microcontroller and taking control of the PA0 the user with a means of convenient and easy upgrades and PA2 I/O pins for data and clock programming pur- and modifications to their programs on the same device. As a rule it is both be programmed serially in-circuit using this 5-wire recommended that simultaneous use of the table read interface. This provides manufacturers with HT68F30. The user must there take care to ensure that no other outputs are connected to these two pins. temporary register #2 : : mov a. temporary register #1 tempreg2 db ? . 00Ch. 01Bh : : Rev. 00Dh. and then programming or upgrading the address ²706H² or 6 locations after the start of the last program at a later stage. example the data ²1AH² is transferred to tempreg1 and data ²0FH² to . memory address ²706H² transferred to tempreg1 and TBLH dec tblp . Note that the value for the table pointer is refer. in situations a single pin with an additional line for the clock.00 21 November 3. 01Ah. reduce value of table pointer by one tabrd tempreg2 . Holtek has provided a statement is ²700H² which refers to the start address of means of programming the microcontroller in-circuit us- the last page within the 2K Program Memory of the ing a 5-pin interface. the Interrupt Service Routines may change the value of the TBLH and subsequently cause The Program Memory and EEPROM data memory can errors if used again by the main routine. 1. Note that all table in-circuit programming of the devices are beyond the related instructions require two instruction cycles to scope of this document and will be supplied in supple- complete their operation. the inter- ditional lines are required for the power supply and one rupts should be disabled prior to the execution of any line for the reset. turers to easily keep their manufactured products sup- enced to the first address of the present page if the plied with the latest program releases without removal ²TABRD [m]² instruction is being used. transfers value in table referenced by table pointer data at program .a : : tabrd tempreg1 . the possibility of manufacturing their circuit boards com- tial value of ²06H². transfers value in table referenced by table pointer data at program . If using the table VSS Ground read instructions. 00Fh. This will ensure that the first data plete with a programmed or un-programmed read from the data table will be at the Program Memory microcontroller. · Table Read Program Example tempreg1 db ? . PA0 Serial Data Input/Output Because the TBLH register is a read-only register and PA2 Serial Clock cannot be restored. Two ad- where simultaneous use cannot be avoided. sets initial address of program memory dc 00Ah. mentary literature. 00Bh. care should be taken to ensure its RES Device Reset protection if both the main routine and Interrupt Service VDD Power Supply Routine use table read instructions. memory address ²705H² transferred to tempreg2 and TBLH in this .note that this address mov tblp.

00 22 November 3. 1 1 H IN T C 1 4 1 H E E A 1 2 H IN T C 2 4 2 H E E D formation is stored. The resistance of * must be greater than 1kW or the capacitance B a n k 0 . 1 0 H IN T C 0 4 0 H U n u s e d E E C ternal memory and is the location where temporary in. 1 E H P B C 4 E H T M 1 A H lation. however. 1 F H P C P U 4 F H U n u s e d 2 0 H P C 5 0 H U n u s e d 2 1 H P C C 5 1 H U n u s e d 2 2 H U n u s e d 5 2 H U n u s e d 2 3 H U n u s e d 5 3 H U n u s e d 2 4 H U n u s e d 5 4 H U n u s e d 2 5 H U n u s e d 5 5 H U n u s e d 2 6 H U n u s e d 5 6 H U n u s e d 2 7 H U n u s e d 5 7 H U n u s e d 2 8 H U n u s e d 5 8 H U n u s e d 2 9 H U n u s e d 5 9 H U n u s e d 2 A H U n u s e d 5 A H U n u s e d 2 B H U n u s e d 5 B H U n u s e d 2 C H U n u s e d 5 C H U n u s e d 2 D H U n u s e d 5 D H U n u s e d 2 E H U n u s e d 5 E H S C O M C 2 F H U n u s e d 5 F H U n u s e d HT68F20 Special Purpose Data Memory Rev. 2009 . 1 C H P B P U 4 C H T M 1 D H 1 D H P B 4 D H T M 1 A L trol. 1 8 H P A W U 4 8 H T M 1 C 0 1 9 H P A P U 4 9 H T M 1 C 1 Here are located registers which are necessary for cor. known as the Special Function Data Memory. 1. 1 A H P A 4 A H U n u s e d rect operation of the device. the first of these is an area of 1 7 H U n u s e d 4 7 H U n u s e d RAM. HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 W r ite r C o n n e c to r M C U P r o g r a m m in g S ig n a ls P in s Device Capacity Banks 0: 60H~7FH W r ite r _ V D D V D D HT68F20 64´8 1: 60H~7FH 0: 60H~7FH R E S R E S HT68F30 1: 60H~7FH 96´8 2: 60H~7FH D A T A D A T A 0: 80H~FFH HT68F40 192´8 1: 80H~BFH C L K C L K 0: 80H~FFH HT68F50 384´8 1: 80H~FFH W r ite r _ V S S V S S 2: 80H~FFH 0: 80H~FFH * * * 1: 80H~FFH HT68F60 576´8 2: 80H~FFH 3: 80H~FFH T o o th e r C ir c u it 4: 80H~FFH Note: * may be resistor or capacitor. 1 3 H U n u s e d 4 3 H T M P C 0 1 4 H M F I0 4 4 H U n u s e d Structure 1 5 H M F I1 4 5 H U n u s e d 1 6 H M F I2 4 6 H U n u s e d Divided into two sections. some remain protected from user manipu. Many of these registers can 1 B H P A C 4 B H T M 1 D L be read from and written to directly under program con. 1 B a n k 0 B a n k 1 of * must be less than 1nF. 0 0 H IA R 0 3 0 H U n u s e d 0 1 H M P 0 3 1 H U n u s e d 0 2 H IA R 1 3 2 H U n u s e d 0 3 H M P 1 3 3 H U n u s e d Programmer Pin MCU Pins 0 4 H B P C P 0 C 3 4 H RES PB0 0 5 H A C C 3 5 H C P 1 C 0 6 H P C L 3 6 H S IM C 0 DATA PA0 0 7 H T B L P 3 7 H S IM C 1 0 8 H T B L H 3 8 H S IM D CLK PA2 0 9 H T B H P 3 9 H S IM A /S IM C 2 0 A H S T A T U S 3 A H T M 0 C 0 Programmer and MCU Pins 0 B H S M O D 3 B H T M 0 C 1 0 C H L V D C 3 C H T M 0 D L 0 D H IN T E G 3 D H T M 0 D H RAM Data Memory 0 E H W D T C 3 E H T M 0 A L 0 F H T B C 3 F H T M 0 A H The Data Memory is a volatile area of 8-bit wide RAM in.

00 23 November 3. 1. 1 B a n k 0 B a n k 1 0 0 H IA R 0 3 0 H U n u s e d 0 0 H IA R 0 4 0 H U n u s e d E E C 0 1 H M P 0 3 1 H U n u s e d 0 1 H M P 0 4 1 H E E A 0 2 H IA R 1 3 2 H U n u s e d 0 2 H IA R 1 4 2 H E E D 0 3 H M P 1 3 3 H U n u s e d 0 3 H M P 1 4 3 H T M P C 0 0 4 H B P 3 4 H C P 0 C 0 4 H B P 4 4 H T M P C 1 0 5 H A C C 3 5 H C P 1 C 0 5 H A C C 4 5 H P R M 0 0 6 H P C L 3 6 H S IM C 0 0 6 H P C L 4 6 H P R M 1 0 7 H T B L P 3 7 H S IM C 1 0 7 H T B L P 4 7 H P R M 2 0 8 H T B L H 3 8 H S IM D 0 8 H T B L H 4 8 H T M 1 C 0 0 9 H T B H P 3 9 H S IM A /S IM C 2 0 9 H T B H P 4 9 H T M 1 C 1 0 A H S T A T U S 3 A H T M 0 C 0 0 A H S T A T U S 4 A H T M 1 C 2 0 B H S M O D 3 B H T M 0 C 1 0 B H S M O D 4 B H T M 1 D L 0 C H L V D C 3 C H T M 0 D L 0 C H L V D C 4 C H T M 1 D H 0 D H IN T E G 3 D H T M 0 D H 0 D H IN T E G 4 D H T M 1 A L 0 E H W D T C 3 E H T M 0 A L 0 E H W D T C 4 E H T M 1 A H 0 F H T B C 3 F H T M 0 A H 0 F H T B C 4 F H T M 1 B L 1 0 H IN T C 0 4 0 H U n u s e d E E C 1 0 H IN T C 0 5 0 H T M 1 B H 1 1 H IN T C 1 4 1 H E E A 1 1 H IN T C 1 5 1 H T M 2 C 0 1 2 H IN T C 2 4 2 H E E D 1 2 H IN T C 2 5 2 H T M 2 C 1 1 3 H U n u s e d 4 3 H T M P C 0 1 3 H U n u s e d 5 3 H T M 2 D L 1 4 H M F I0 4 4 H U n u s e d 1 4 H M F I0 5 4 H T M 2 D H 1 5 H M F I1 4 5 H P R M 0 1 5 H M F I1 5 5 H T M 2 A L 1 6 H M F I2 4 6 H U n u s e d 1 6 H M F I2 5 6 H T M 2 A H 1 7 H U n u s e d 4 7 H U n u s e d 1 7 H U n u s e d 5 7 H T M 2 R P 1 8 H P A W U 4 8 H T M 1 C 0 1 8 H P A W U 5 8 H U n u s e d 1 9 H P A P U 4 9 H T M 1 C 1 1 9 H P A P U 5 9 H U n u s e d 1 A H P A 4 A H T M 1 C 2 1 A H P A 5 A H U n u s e d 1 B H P A C 4 B H T M 1 D L 1 B H P A C 5 B H U n u s e d 1 C H P B P U 4 C H T M 1 D H 1 C H P B P U 5 C H U n u s e d 1 D H P B 4 D H T M 1 A L 1 D H P B 5 D H U n u s e d 1 E H P B C 4 E H T M 1 A H 1 E H P B C 5 E H S C O M C 1 F H P C P U 4 F H T M 1 B L 1 F H P C P U 5 F H U n u s e d 2 0 H P C 5 0 H T M 1 B H 2 0 H P C 6 0 H U n u s e d 2 1 H P C C 5 1 H U n u s e d 2 1 H P C C 6 1 H U n u s e d 2 2 H U n u s e d 5 2 H U n u s e d 2 2 H P D P U 6 2 H U n u s e d 2 3 H U n u s e d 5 3 H U n u s e d 2 3 H P D 6 3 H U n u s e d 2 4 H U n u s e d 5 4 H U n u s e d 2 4 H P D C 6 4 H U n u s e d 2 5 H U n u s e d 5 5 H U n u s e d 2 5 H P E P U 6 5 H U n u s e d 2 6 H U n u s e d 5 6 H U n u s e d 2 6 H P E 6 6 H U n u s e d 2 7 H U n u s e d 5 7 H U n u s e d 2 7 H P E C 6 7 H U n u s e d 2 8 H U n u s e d 5 8 H U n u s e d 2 8 H P F P U 6 8 H U n u s e d 2 9 H U n u s e d 5 9 H U n u s e d 2 9 H P F 6 9 H U n u s e d 2 A H U n u s e d 5 A H U n u s e d 2 A H P F C 6 A H U n u s e d 2 B H U n u s e d 5 B H U n u s e d 2 B H U n u s e d 6 B H U n u s e d 2 C H U n u s e d 5 C H U n u s e d 2 C H U n u s e d 6 C H U n u s e d 2 D H U n u s e d 5 D H U n u s e d 2 D H U n u s e d 6 D H U n u s e d 2 E H U n u s e d 5 E H S C O M C 2 E H U n u s e d 6 E H U n u s e d 2 F H U n u s e d 5 F H U n u s e d 2 F H U n u s e d 6 F H U n u s e d 3 0 H U n u s e d 7 0 H U n u s e d HT68F30 Special Purpose Data Memory 3 1 H U n u s e d 7 1 H U n u s e d 3 2 H U n u s e d 7 2 H U n u s e d 3 3 H U n u s e d 7 3 H U n u s e d 3 4 H C P 0 C 7 4 H U n u s e d 3 5 H C P 1 C 7 5 H U n u s e d 3 6 H S IM C 0 7 6 H U n u s e d 3 7 H S IM C 1 7 7 H U n u s e d 3 8 H S IM D 7 8 H U n u s e d 3 9 H S IM A /S IM C 2 7 9 H U n u s e d 3 A H T M 0 C 0 7 A H U n u s e d 3 B H T M 0 C 1 7 B H U n u s e d 3 C H T M 0 D L 7 C H U n u s e d 3 D H T M 0 D H 7 D H U n u s e d 3 E H T M 0 A L 7 E H U n u s e d 3 F H T M 0 A H 7 F H U n u s e d HT68F40 Special Purpose Data Memory Rev. 2 B a n k 0 . 2009 . 2 B a n k 1 B a n k 0 . 1 . HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 B a n k 0 .

2009 .00 24 November 3. 4 B a n k 0 . 4 B a n k 1 0 0 H IA R 0 4 0 H U n u s e d E E C 0 0 H IA R 0 4 0 H U n u s e d E E C 0 1 H M P 0 4 1 H E E A 0 1 H M P 0 4 1 H E E A 0 2 H IA R 1 4 2 H E E D 0 2 H IA R 1 4 2 H E E D 0 3 H M P 1 4 3 H T M P C 0 0 3 H M P 1 4 3 H T M P C 0 0 4 H B P 4 4 H T M P C 1 0 4 H B P 4 4 H T M P C 1 0 5 H A C C 4 5 H P R M 0 0 5 H A C C 4 5 H P R M 0 0 6 H P C L 4 6 H P R M 1 0 6 H P C L 4 6 H P R M 1 0 7 H T B L P 4 7 H P R M 2 0 7 H T B L P 4 7 H P R M 2 0 8 H T B L H 4 8 H T M 1 C 0 0 8 H T B L H 4 8 H T M 1 C 0 0 9 H T B H P 4 9 H T M 1 C 1 0 9 H T B H P 4 9 H T M 1 C 1 0 A H S T A T U S 4 A H T M 1 C 2 0 A H S T A T U S 4 A H T M 1 C 2 0 B H S M O D 4 B H T M 1 D L 0 B H S M O D 4 B H T M 1 D L 0 C H L V D C 4 C H T M 1 D H 0 C H L V D C 4 C H T M 1 D H 0 D H IN T E G 4 D H T M 1 A L 0 D H IN T E G 4 D H T M 1 A L 0 E H W D T C 4 E H T M 1 A H 0 E H W D T C 4 E H T M 1 A H 0 F H T B C 4 F H T M 1 B L 0 F H T B C 4 F H T M 1 B L 1 0 H IN T C 0 5 0 H T M 1 B H 1 0 H IN T C 0 5 0 H T M 1 B H 1 1 H IN T C 1 5 1 H T M 2 C 0 1 1 H IN T C 1 5 1 H T M 2 C 0 1 2 H IN T C 2 5 2 H T M 2 C 1 1 2 H IN T C 2 5 2 H T M 2 C 1 1 3 H U n u s e d 5 3 H T M 2 D L 1 3 H IN T C 3 5 3 H T M 2 D L 1 4 H M F I0 5 4 H T M 2 D H 1 4 H M F I0 5 4 H T M 2 D H 1 5 H M F I1 5 5 H T M 2 A L 1 5 H M F I1 5 5 H T M 2 A L 1 6 H M F I2 5 6 H T M 2 A H 1 6 H M F I2 5 6 H T M 2 A H 1 7 H M F I3 5 7 H T M 2 R P 1 7 H M F I3 5 7 H T M 2 R P 1 8 H P A W U 5 8 H T M 3 C 0 1 8 H P A W U 5 8 H T M 3 C 0 1 9 H P A P U 5 9 H T M 3 C 1 1 9 H P A P U 5 9 H T M 3 C 1 1 A H P A 5 A H T M 3 D L 1 A H P A 5 A H T M 3 D L 1 B H P A C 5 B H T M 3 D H 1 B H P A C 5 B H T M 3 D H 1 C H P B P U 5 C H T M 3 A L 1 C H P B P U 5 C H T M 3 A L 1 D H P B 5 D H T M 3 A H 1 D H P B 5 D H T M 3 A H 1 E H P B C 5 E H S C O M C 1 E H P B C 5 E H S C O M C 1 F H P C P U 5 F H U n u s e d 1 F H P C P U 5 F H U n u s e d 2 0 H P C 6 0 H U n u s e d 2 0 H P C 6 0 HU n u s e d 2 1 H P C C 6 1 H U n u s e d 2 1 H P C C 6 1 HU n u s e d 2 2 H P D P U 6 2 H U n u s e d 2 2 H P D P U 6 2 HU n u s e d 2 3 H P D 6 3 H U n u s e d 2 3 H P D 6 3 HU n u s e d 2 4 H P D C 6 4 H U n u s e d 2 4 H P D C 6 4 HU n u s e d 2 5 H P E P U 6 5 H U n u s e d 2 5 H P E P U 6 5 HU n u s e d 2 6 H P E 6 6 H U n u s e d 2 6 H P E 6 6 H U n u s e d 2 7 H P E C 6 7 H U n u s e d 2 7 H P E C 6 7 H U n u s e d 2 8 H P F P U 6 8 H U n u s e d 2 8 H P F P U 6 8 H U n u s e d 2 9 H P F 6 9 H U n u s e d 2 9 H P F 6 9 H U n u s e d 2 A H P F C 6 A H U n u s e d 2 A H P F C 6 A H U n u s e d 2 B H U n u s e d 6 B H U n u s e d 2 B H P G P U 6 B H U n u s e d 2 C H U n u s e d 6 C H U n u s e d 2 C H P G 6 C H U n u s e d 2 D H U n u s e d 6 D H U n u s e d 2 D H P G C 6 D H U n u s e d 2 E H U n u s e d 6 E H U n u s e d 2 E H U n u s e d 6 E H U n u s e d 2 F H U n u s e d 6 F H U n u s e d 2 F H U n u s e d 6 F H U n u s e d 3 0 H U n u s e d 7 0 H U n u s e d 3 0 H U n u s e d 7 0 H U n u s e d 3 1 H U n u s e d 7 1 H U n u s e d 3 1 H U n u s e d 7 1 H U n u s e d 3 2 H U n u s e d 7 2 H U n u s e d 3 2 H U n u s e d 7 2 H U n u s e d 3 3 H U n u s e d 7 3 H U n u s e d 3 3 H U n u s e d 7 3 H U n u s e d 3 4 H C P 0 C 7 4 H U n u s e d 3 4 H C P 0 C 7 4 H U n u s e d 3 5 H C P 1 C 7 5 H U n u s e d 3 5 H C P 1 C 7 5 H U n u s e d 3 6 H S IM C 0 7 6 H U n u s e d 3 6 H S IM C 0 7 6 H U n u s e d 3 7 H S IM C 1 7 7 H U n u s e d 3 7 H S IM C 1 7 7 H U n u s e d 3 8 H S IM D 7 8 H U n u s e d 3 8 H S IM D 7 8 H U n u s e d 3 9 H S IM A /S IM C 2 7 9 H U n u s e d 3 9 H S IM A /S IM C 2 7 9 H U n u s e d 3 A H T M 0 C 0 7 A H U n u s e d 3 A H T M 0 C 0 7 A H U n u s e d 3 B H T M 0 C 1 7 B H U n u s e d 3 B H T M 0 C 1 7 B H U n u s e d 3 C H T M 0 D L 7 C H U n u s e d 3 C H T M 0 D L 7 C H U n u s e d 3 D H T M 0 D H 7 D H U n u s e d 3 D H T M 0 D H 7 D H U n u s e d 3 E H T M 0 A L 7 E H U n u s e d 3 E H T M 0 A L 7 E H U n u s e d 3 F H T M 0 A H 7 F H U n u s e d 3 F H T M 0 A H 7 F H U n u s e d HT68F50 Special Purpose Data Memory HT68F60 Special Purpose Data Memory Rev. 1. HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 B a n k 0 . 1 . 2 B a n k 1 B a n k 0 . 3 . 3 . 2 . 2 B a n k 0 . 1 . 2 .

increment memory pointer sdz block . together with Indirect eral registers require a separate description in this Addressing Register. Memory Pointers is not required to address the full ters.IAR0. a value of ²1² and Memory Pointers. MP0. however sev.section ¢data¢ adres1 db ? adres2 db ? adres3 db ? adres4 db ? block db ? code . When Special Function Register Description any operation to the relevant Indirect Addressing Regis- ters is carried out.a . not physically implemented. which is only accessible in Bank 1. do not actually physically exist as normal regis. Switching between the different Data Memory Two Memory Pointers. 2009 . must be addressed indirectly using MP1 and IAR1. dressing. no reference is made to specific RAM addresses. is the address specified by scribed in the relevant functional section. the structure of which depends upon the device and writing to the registers indirectly will result in no op- chosen. These Memory Pointers are physically imple- rect value. bit 7 of the space. Actions on the IAR0 and IAR1 registers will result in four Data Memory locations already defined as loca- no actual read or write operation to these registers but tions adres1 to adres4. The Special Purpose Data Memory registers eration. microcontroller is directed to. MP1 EEC register at address 40H. vided.section at 0 ¢code¢ org 00h start: mov a. Acting as a · Indirect Addressing Program Example data . will be returned. with the exception of the Memory Pointers . All locations within this area are read from any bank. Accumulator loaded with first RAM address mov mp0.00 25 November 3. the related Memory Pointer. setup size of block mov block. in contrast to direct memory ad. IAR0 and IAR1. 1. MP0 or MP1. pair.a mov a. known as MP0 and MP1 are pro- banks is achieved by setting the Bank Pointer to the cor. When bit 7 of the Memory Pointers for manipulation uses these Indirect Addressing Registers HT68F20 and HT68F30 devices is read. setup memory pointer with first RAM address loop: clr IAR0 . rather to the memory location specified by their corre- sponding Memory Pointers.MP0. As the Indirect Addressing Registers are and write accessible under program control. where the actual memory address is speci- The following example shows how to clear a section of fied. Direct Ad- Indirect Addressing Registers . The method of indirect addressing for RAM data memory space. IAR1 dressing can only be used with Bank 0. The start address of the Data Memory for all mented in the Data Memory and can be manipulated in devices is the address 00H. IAR0 and MP0 can together access data from Bank eral Purpose Data Memory. the same way as normal registers providing a conve- nient way with which to address and track data. are accessible in all banks. IAR0.offset adres1 . 0 while the IAR1 and MP1 register pair can access data eral purpose use. from Bank 0. check if last memory location has been cleared jmp loop continue: The important point to note here is that in the example shown above. while MP1 and IAR1 are used to access data from all banks according to BP register. are used to access data section. al. the actual address that the Most of the Special Function Register details will be de. which is reserved for gen. reading the Indirect Ad- The overall Data Memory is subdivided into several dressing Registers indirectly will return a result of ²00H² banks. HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 The second area of Data Memory is known as the Gen. all other Banks The Indirect Addressing Registers.04h . clear the data at address defined by MP0 inc mp0 . Note though having their locations in normal RAM register that for the HT68F20 and HT68F30 devices. Rev.

HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 Bank Pointer .00 26 November 3. It should be noted that the Special Function Depending upon which device is used. 2009 . the Data Memory bank remains during programming. Bit Device 7 6 5 4 3 2 1 0 HT68F20 ¾ ¾ ¾ ¾ ¾ ¾ ¾ DMBP0 HT68F40 HT68F30 ¾ ¾ ¾ ¾ ¾ ¾ DMBP1 DMBP0 HT68F50 HT68F60 ¾ ¾ PMBP0 ¾ ¾ DMBP2 DMBP1 DMBP0 BP Registers List · BP Register ¨ HT68F20/HT68F40 Bit 7 6 5 4 3 2 1 0 Name ¾ ¾ ¾ ¾ ¾ ¾ ¾ DMBP0 R/W ¾ ¾ ¾ ¾ ¾ ¾ ¾ R/W POR ¾ ¾ ¾ ¾ ¾ ¾ ¾ 0 Bit 7 ~ 1 Unimplemented. read as ²0² Bit 1 ~ 0 DMBP1. DMBP0: Select Data Memory Banks 00: Bank 0 01: Bank 1 10: Bank 2 11: Undefined Rev. As both the Program Memory and Data Memory share except for a WDT time-out reset in the Power Down the same Bank Pointer Register. Selecting which means that the Special Function Registers can be the required Program and Data Memory area is accessed from within any bank.BP unaffected. Data Memory are divided into several banks. Ac- while bits 0~2 are used to select Data Memory Banks cessing data from banks other than Bank 0 must be 0~4. The Data Memory is initialised to Bank 0 after a reset. read as ²0² Bit 0 DMBP0: Select Data Memory Banks 0: Bank 0 1: Bank 1 ¨ HT68F30/HT68F50 Bit 7 6 5 4 3 2 1 0 Name ¾ ¾ ¾ ¾ ¾ ¾ DMBP1 DMBP0 R/W ¾ ¾ ¾ ¾ ¾ ¾ R/W R/W POR ¾ ¾ ¾ ¾ ¾ ¾ 0 0 Bit 7 ~ 2 Unimplemented. Directly addressing the achieved using the Bank Pointer. implemented using Indirect addressing. in which case. care must be taken Mode. cessed irrespective of the value of the Bank Pointer. the Program and Data Memory is not affected by the bank selection. 1. Bit 5 of the Bank Data Memory will always result in Bank 0 being ac- Pointer is used to select Program Memory Bank 0 or 1.

Their value can be changed. ²HALT² or ²CLR WDT² instruction or during a system cation.ACC for example using the ²INC² or ²DEC² instructions. trol operation of the look-up table which is stored in the · AC is set if an operation results in a carry out of the Program Memory. it is necessary to do this by passing the data ment flags are used to record the status and operation of through the Accumulator as no direct transfer between the microcontroller. dummy cycle will be inserted. jumps within the current Program Memory page are per- The Z. power storage function of the Accumulator. Their value must be setup before any table read cleared. direct flag can be affected only by a system power-up. or no borrow from the high nib- and indicates the location where the table data is lo. Loading a value directly into this PCL register struction. note that a the latest operations. commands are executed.PCL other registers. In addition. al- The Accumulator is central to the operation of any lowing for easy table data pointing and reading. read as ²0² Bit 2 ~ 0 DMBP2 ~ DMBP0: Select Data Memory Banks 000: Bank 0 001: Bank 1 010: Bank 2 011: Bank 3 100: Bank 4 101~111: Undefined Accumulator . With the exception of the TO and PDF flags. for example. however. Program Memory Address is from 0000H ~ 1FFFH 1: Bank 1..00 27 November 3. This 8-bit register contains the zero flag (Z). as the register is only 8-bit wide. overflow flag (OV). the result of each calculation or logical operation such Status Register . By manipulating this register. 1.STATUS as addition. etc. the low will not change the TO or PDF flag. When such operations are used. C These three special function registers are used to con. only power-up.TBLP. two registers is permitted. OV. The Accumulator is the place stored after a table read data instruction has been exe- where all intermediate results from the ALU are stored. auxiliary carry flag (AC). opera- byte of the Program Counter is made accessible to pro. 2009 . The TO of the Data Memory. transferring data between one user defined register and These arithmetic/logical operation and system manage- another. ble into the low nibble in subtraction. to the Data Memory resulting in higher programming and timing overheads. · C is set if an operation results in a carry during an ad- Look-up Table Registers . otherwise AC is cated. time-out or by executing the ²CLR WDT² or ²HALT² in- mented. otherwise C is cleared. TBLH dition operation or if a borrow does not take place dur- ing a subtraction operation. TBLP and TBHP are the table pointer low nibbles in addition. Any data written into the status register To provide additional program control functions. read as ²0² Bit 5 PMBP0: Select Program Memory Banks 0: Bank 0. Note that the lower order table data byte is trans- Without the Accumulator it would be necessary to write ferred to a user defined location. carry flag Data transfer operations usually involve the temporary (C). subtraction. TBHP. when down flag (PDF). cuted. tions related to the status register may give different re- grammers by locating it within the Special Purpose area sults due to the different instruction operations. and watchdog time-out flag (TO). The PDF flag is affected only by executing the will cause a jump to the specified Program Memory lo. a WDT jumps to other program locations are easily imple. HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 ¨ HT68F60 Bit 7 6 5 4 3 2 1 0 Name ¾ ¾ PMBP0 ¾ ¾ DMBP2 DMBP1 DMBP0 R/W ¾ ¾ R/W ¾ ¾ R/W R/W R/W POR ¾ ¾ 0 ¾ ¾ 0 0 0 Bit 7 ~ 6 Unimplemented. Program Memory Address is from 2000H ~ 2FFFH Bit 4 ~ 3 Unimplemented. shift. TBLH is microcontroller and is closely related with operations the location where the high order byte of the table data is carried out by the ALU. is also affected by a rotate through carry instruction. bits in the status register can be altered by instructions like most Program Counter Low Register . AC and C flags generally reflect the status of mitted. Rev.

otherwise OV is cleared. or no borrow from the high nibble into the low nibble in subtraction Bit 0 C: Carry flag 0: no carry-out 1: an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation C is also affected by a rotate through carry instruction. 1. · STATUS Register Bit 7 6 5 4 3 2 1 0 Name ¾ ¾ TO PDF OV Z AC C R/W ¾ ¾ R R R/W R/W R/W R/W POR ¾ ¾ 0 0 x x x x ²x² unknown Bit 7. If the contents of est-order bit but not a carry out of the highest-order bit. on entering an interrupt sequence or execut- is zero. Bit 2 Z: Zero flag 0: The result of an arithmetic or logical operation is not zero 1: The result of an arithmetic or logical operation is zero Bit 1 AC: Auxiliary flag 0: no auxiliary carry 1: an operation results in a carry out of the low nibbles in addition. Bit 4 PDF: Power down flag 0: After power up or executing the ²CLR WDT² instruction 1: By executing the ²HALT² instruction Bit 3 OV: Overflow flag 0: no overflow 1: an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit or vice versa. ²CLR WDT² instruction. · TO is cleared by a system power-up or executing the ²CLR WDT² or ²HALT² instruction. pushed onto the stack automatically. precautions must be · PDF is cleared by a system power-up or executing the taken to correctly save it. 2009 . the status register will not be · OV is set if an operation results in a carry into the high. ing a subroutine call. PDF is set by executing the ²HALT² instruction.00 28 November 3. HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 · Z is set if the result of an arithmetic or logical operation In addition. can corrupt the status register. Rev. TO is set by a WDT time-out. otherwise Z is cleared. read as ²0² Bit 5 TO: Watchdog Time-Out flag 0: After power up or executing the ²CLR WDT² or ²HALT² instruction 1: A watchdog time-out occurred. the status registers are important and if the subroutine or vice versa. 6 Unimplemented.

is by its nature HT68F20 32´8 00H ~ 1FH a non-volatile form of re-programmable memory. IAR1. As both the EEA and EED registers are lo- EEPROM Data Memory Structure cated in Bank 0. system setup data or EEPROM Registers other product information to be stored directly within the Three registers control the overall operation of the inter- product microcontroller. These are the address reg- writing data to the EEPROM memory has been reduced ister. before any operations on the EEC register are executed. according to the device selected. with data retention even when its power supply is removed. The process of reading and nal EEPROM Data Memory. Unlike directly addressed directly and can only be read from or the Program Memory and RAM Data Memory. ter in Bank 0 and a single control register in Bank 1. cali- bration values. Read MP1 Memory Pointer must first be set to the value 40H and Write operations to the EEPROM are carried out in and the Bank Pointer register. a whole new HT68F40 128´8 00H ~ 7FH host of application possibilities are made available to the designer. The The EEPROM Data Memory capacity varies from 32x8 EEC register however. they can be directly accessed in the same was as any other Special Function Register. EEPROM. 1. 2009 . single byte operations using an address and data regis. HT68F30 64´8 00H ~ 3FH By incorporating this kind of data memory. HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 EEPROM Data Memory The device contains an area of internal EEPROM Data Memory. which stands for Electrically Eras. EEC. Because the EEC memory space and is therefore not directly addressable control register is located at address 40H in Bank 1. 01H. EEA. Device Capacity Address able Programmable Read Only Memory. register. cannot be to 256´8 bits. HT68F50/HT68F60 256´8 00H ~ FFH formation such as product identification numbers. BP. EED and a single control to a very trivial affair.00 29 November 3. the in the same way as the other types of memory. the data register. the written to indirectly using the MP1 Memory Pointer and EEPROM Data Memory is not directly mapped into Indirect Addressing Register. being located in Bank1. · EEPROM Register List ¨ HT68F20 Bit Name 7 6 5 4 3 2 1 0 EEA ¾ ¾ ¾ D4 D3 D2 D1 D0 EED D7 D6 D5 D4 D3 D2 D1 D0 EEC ¾ ¾ ¾ ¾ WREN WR RDEN RD ¨ HT68F30 Bit Name 7 6 5 4 3 2 1 0 EEA ¾ ¾ D5 D4 D3 D2 D1 D0 EED D7 D6 D5 D4 D3 D2 D1 D0 EEC ¾ ¾ ¾ ¾ WREN WR RDEN RD ¨ HT68F40 Bit Name 7 6 5 4 3 2 1 0 EEA ¾ D6 D5 D4 D3 D2 D1 D0 EED D7 D6 D5 D4 D3 D2 D1 D0 EEC ¾ ¾ ¾ ¾ WREN WR RDEN RD Rev. set to the value. The availability of EEPROM storage allows in. specific user data.

read as ²0² Bit 4 ~ 0 Data EEPROM address Data EEPROM address bit 4 ~ bit 0 ¨ HT68F30 Bit 7 6 5 4 3 2 1 0 Name ¾ ¾ D5 D4 D3 D2 D1 D0 R/W ¾ ¾ R/W R/W R/W R/W R/W R/W POR ¾ ¾ x x x x x x ²x² unknown Bit 7 ~ 6 Unimplemented. 1.00 30 November 3. 2009 . HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 ¨ HT68F50/HT68F60 Bit Name 7 6 5 4 3 2 1 0 EEA D7 D6 D5 D4 D3 D2 D1 D0 EED D7 D6 D5 D4 D3 D2 D1 D0 EEC ¾ ¾ ¾ ¾ WREN WR RDEN RD · EEA Register ¨ HT68F20 Bit 7 6 5 4 3 2 1 0 Name ¾ ¾ ¾ D4 D3 D2 D1 D0 R/W ¾ ¾ ¾ R/W R/W R/W R/W R/W POR ¾ ¾ ¾ x x x x x ²x² unknown Bit 7 ~ 5 Unimplemented. read as ²0² Bit 6 ~ 0 Data EEPROM address Data EEPROM address bit 6 ~ bit 0 ¨ HT68F50/HT68F60 Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR x x x x x x x x ²x² unknown Bit 7 ~ 0 Data EEPROM address Data EEPROM address bit 7 ~ bit 0 Rev. read as ²0² Bit 5 ~ 0 Data EEPROM address Data EEPROM address bit 5 ~ bit 0 ¨ HT68F40 Bit 7 6 5 4 3 2 1 0 Name ¾ D6 D5 D4 D3 D2 D1 D0 R/W ¾ R/W R/W R/W R/W R/W R/W R/W POR ¾ x x x x x x x ²x² unknown Bit 7 Unimplemented.

The application program can therefore poll the WR bit to de- Writing Data to the EEPROM termine when the write cycle has ended. microcontroller system clock. 2009 . Clearing this bit to zero will inhibit Data EEPROM read operations. Clearing this bit to zero will inhibit Data EEPROM write operations. Note: The WREN. Reading Data from the EEPROM ter and the data placed in the EED register. To write data to the EEPROM. Bit 1 RDEN: Data EEPROM Read Enable 0: Disable 1: Enable This is the Data EEPROM Read Enable Bit which must be set high before Data EEPROM read operations are carried out. Detecting when the write cycle has finished can be im- matically cleared to zero. RDEN and RD can not be set to ²1² at the same time in one instruction. cleared to zero by the microcontroller. Setting this bit high will have no effect if the RDEN has not first been set high. in the EEC register is now set high. the EEPROM write cycle is controlled using an internal If the RD bit in the EEC register is now set high. the WR bit will be automatically cuted. WR. a certain time will elapse ate a read operation if the RDEN bit has not been set. Setting the RD bit high will not initi. When the read cycle terminates. cle will then be initiated. When the write EED register until another read or write operation is exe. Bit 2 WR: EEPROM Write Control 0: Write cycle has finished 1: Activate a write cycle This is the Data EEPROM Write Control Bit and when set high by the application program will activate a write cycle. Setting this bit high will have no effect if the WREN has not first been set high. cycle terminates. This bit will be automatically reset to zero by the hardware after the read cycle has finished. The EEPROM address of the data to be written must then be placed in the EEA regis- Rev. read as ²0² Bit 3 WREN: Data EEPROM Write Enable 0: Disable 1: Enable This is the Data EEPROM Write Enable Bit which must be set high before Data EEPROM write operations are carried out. The data will remain in the ter or by using the EEPROM interrupt.00 31 November 3. This bit will be automatically reset to zero by the hardware after the write cycle has finished. the write enable bit. before the data will have been written into the EEPROM. the read enable bit. the RD bit will be auto. The WR and RD can not be set to ²1² at the same time. a read t i m e r w h o se o p e r a t i o n i s a syn ch r o n o u s t o cycle will be initiated. informing the termine when the data is valid for reading. user that the data has been written to the EEPROM. Bit 0 RD: EEPROM Read Control 0: Read cycle has finished 1: Activate a read cycle This is the Data EEPROM Read Control Bit and when set high by the application program will activate a read cycle. Setting the WR bit high will not able the read function. HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 · EEC Register Bit 7 6 5 4 3 2 1 0 Name ¾ ¾ ¾ ¾ WREN WR RDEN RD R/W ¾ ¾ ¾ ¾ R/W R/W R/W R/W POR ¾ ¾ ¾ ¾ 0 0 0 0 Bit 7 ~ 4 Unimplemented. The EEPROM address of the initiate a write cycle if the WREN bit has not been set. The application program can poll the RD bit to de. after which the data can be plemented either by polling the WR bit in the EEC regis- read from the EED register. in the EEC register must first be set high to en. WREN. If the WR bit To read data from the EEPROM. in the EEC register must first be set high to en- able the write function. As data to be read must then be placed in the EEA register. an internal write cy- RDEN. 1.

consideration might be EEPROM is contained within a Multi-function Interrupt. check for write cycle end JMP BACK CLR IAR1 . the EEPROM interrupt flag must be manually re- control register is located in Bank 1. enable write operations SET IAR1. A MOV A. As the EEPROM reset. move read data to register MOV READ_DATA. set RDEN bit.polling method MOV A. A SET IAR1. this adds a further set by the application program. A MOV A. enable read operations SET IAR1.2 . start Write Cycle . 040H . given in the application program to the checking of the the associated multi-function interrupt enable bit must validity of new write data by a simple read back process. When the interrupt is serviced Bank Pointer. disable EEPROM read/write CLR BP Rev. The mally cleared to zero as this would inhibit access to EEPROM interrupt must first be enabled by setting the Bank 1 where the EEPROM control register exist.0 . EEDATA . EEPROM vided in several ways.set RD bit BACK: SZ IAR1. However as the though certainly not necessary. MP1 points to EEC register MOV A. a jump to the associated Multi-function Inter- preventing any write operations. Also the Bank Pointer could be nor- an EEPROM write or read cycle has ended. Al- DEE bit in the relevant interrupt register. setup Bank Pointer MOV BP. which means that only the Multi-function interrupt flag will be automatically Data Memory Bank 0 will be selected. EEPROM_ADRES . tained in the Interrupt section.2 . will be reset to zero.3 . 01H .set WR bit BACK: SZ IAR1. When an EEPROM write cycle ends. Care must be taken that data is not inadvertently written to the EEPROM.polling method MOV A. During normal program operation. start Read Cycle . user defined data MOV EED. setup memory pointer MP1 MOV MP1. EEPROM_DATA . BP. 1. A ¨ Writing Data to the EEPROM . After the device is powered-on and Multi-function interrupts are enabled and the stack the Write Enable bit in the control register will be cleared is not full.00 32 November 3. also be set. MP1 points to EEC register MOV A. set WREN bit. check for read cycle end JMP BACK CLR IAR1 . A . disable EEPROM read/write CLR BP MOV A. A SET IAR1. 2009 . setup memory pointer MP1 MOV MP1. ensuring that Programming Considerations the Write Enable bit in the control register is cleared will safeguard against incorrect write operations. Also at power-on the rupt vector will take place. Protection can be enhanced by ensur- EEPROM Interrupt ing that the Write Enable bit is normally cleared to zero The EEPROM write or read interrupt is generated when when not writing.0 . More details can be ob- measure of protection against spurious write opera.1 . user defined address MOV EEA. A MOV A. tions. 040H . EEPROM_ADRES . HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 Write Protection DEF request flag and its associated multi-function inter- Protection against inadvertent write operation is pro. setup Bank Pointer MOV BP. If the global. 01H . the · Programming Examples ¨ Reading data from the EEPROM . rupt request flag will both be set. user defined address MOV EEA. A .

the device has the flexibility to optimize the perfor. With the capability of dy. The There are five methods of generating the system clock. The namically switching between fast and slow system two low speed oscillators are the internal 32kHz RC os- clock. while the opposite is of course true for the ceramic oscillator. External oscilla. as the system oscillator is implemented using the HLCLK bit and CKS2 ~ CKS0 bits in the SMOD register and as the system clock can be dynamically selected. CKS2~CKS0 bits Low Speed Oscillation fS UB Configuration Option Fast Wake-up from SLEEP Mode or IDLE Mode Control (for HXT only) System Clock Configurations Rev. higher frequency oscillators provide higher performance three high speed oscillators and two low speed oscilla- but carry with it the disadvantage of higher power re. cillator and the external 32. requiring no external Oscillator Types components. 8MHz or 12MHz RC oscillator. tors. High Speed Oscillation HXT fH ERC 6-stage Prescaler fH/2 HIRC fH /4 High Speed Oscillation fH/8 Configuration Option fH/16 Low Speed Oscillation fH/32 fH/64 LIRC fL fSY S LXT HLCLK. 2009 . a feature especially important in lecting whether the low or high speed oscillator is used power sensitive portable applications. The flexible features of the oscillator functions 400kHz~ OSC1/ ensure that the best optimisation can be achieved in External Crystal HXT 20MHz OSC2 terms of speed and power saving. HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 Oscillator Various oscillator options offer the user a wide range of functions according to their various application require.768kHz Speed Crystal XT2 the oscillators also provide clock sources for the Watch- Internal Low dog Timer and Time Base Interrupts. Pins ments.768kHz crystal oscillator. 8 or 12MHz ¾ Speed RC Oscillator Overview External Low XT1/ In addition to being the source of the main system clock LXT 32. the internal 4MHz. Internal High HIRC 4. All oscillator options System Clock Configurations are selected through the configuration options. are provided to form a wide range of both fast and slow system oscillators. Type Name Freq. 1. external RC network oscillator and lower frequency oscillators.00 33 November 3. Se- mance/power ratio. Oscillator selections and operation are selected through a combination of External RC ERC 8MHz OSC1 configuration options and registers. The high speed oscillators are the external crystal/ quirements. LIRC 32kHz ¾ Speed RC tors requiring some external components as well as fully integrated internal oscillators.

HIRC C 1 In te r n a l The internal RC oscillator is a fully integrated system os- O S C 1 O s c illa to r cillator requiring no external components. HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 The actual source clock used for each of the high speed termines the oscillation frequency.768kHz and requires a 32.ERC lation.768kHz Crystal System Oscillator is 4MHz 0pF 0pF one of the low frequency oscillator choices. it can be noted that with an external 120kW resistor connected and with a 5V voltage power supply External Crystal/ Ceramic Oscillator . across OSC1 and OSC2 will create the necessary V D D phase shift and feedback for oscillation. During power-up there is a time between OSC1 and VDD. to ensure oscillation. of the high frequency oscillator choices.768kHz crystal are necessary to provide oscil- External RC Oscillator .3V 2 . For applications where precise frequencies are Using the ERC oscillator only requires that a resistor. 8MHz or 12MHz will Crystal/Resonator Oscillator . crystal to be connected between pins XT1 and XT2. it may be neces- sary to add two small value capacitors.LXT 8MHz 0pF 0pF The External 32. the external and low speed oscillators is chosen via configuration capacitor has no influence over the frequency and is options. A lth o u g h n o t s h o w n O S C 1 /O S C 2 p in s h a v e a p a r a s itic c a p a c ita n c e o f a r o u n d 7 p F . The frequency of the slow speed or high speed connected for stability purposes only.HXT have a tolerance within 2%. essential. The internal C ir c u it R p R f RC oscillator has three fixed frequencies of either 4MHz. and a capacitor is connected delay associated with the LXT oscillator waiting for it to between OSC1 and ground. C 1 a n d C 2 a r e r e q u ir e d . which is se- 1MHz 100pF 100pF lected via configuration option. or 5V and at a temperature of 25°C degrees. For most crystal oscilla. The values of C1 and C2 should External RC Oscillator . 1. the oscillator will The External Crystal/ Ceramic System Oscillator is one have a frequency of 8MHz within a tolerance of 2%. C1 and C2. Device trimming during the manufacturing process and the inclusion of internal fre- T o in te r n a l quency compensation circuits are used to ensure that O S C 2 c ir c u its C 2 the influence of the power supply voltage.4MW. to be connected as shown for oscillation to occur. is connected facturing tolerances. the fixed oscillation frequency of 4MHz. providing a low cost oscilla- start-up. erence point. Internal RC Oscillator . 12MHz 0pF 0pF External 32. O S C 1 Using a ceramic resonator will usually require two small 4 7 0 p F value capacitors. As a result. Here only the OSC1 pin is used. R p is n o r m a lly n o t r e q u ir e d . as it requires no external Crystal Oscillator C1 and C2 Values pins for its operation. Device trimming system clock is also determined using the HLCLK bit during the manufacturing process and the inclusion of and CKS2 ~ CKS0 bits in the SMOD register. tem- speed and one low speed system oscillators.768kHz Crystal Oscillator . minimised. As a resistance/frequency ref- high or low speed oscillator. these components may be required to provide frequency compensation due to different crystal manu- with a value between 56kW and 2. for some crystal types R O S C and frequencies. 8MHz or 12MHz.HXT and temperature of 25°C degrees. without requir- ing external capacitors.00 34 November 3. It is not perature and process variations on the oscillation possible to choose a no-oscillator selection for either the frequency are minimised. It is only the external resistor that de- Rev. temperature and process variations on the oscillation frequency are N o te : 1 . which is shared with I/O lected via configuration option. the simple connection of a crystal pin. which is se. The Crystal Recommended Capacitor Values external resistor and capacitor components connected to the 32. at a power supply of either 3.ERC be selected in consultation with the crystal or resonator manufacturer¢s specification. tor configuration. I/O pins PB1 and PB2 are free for Crystal Frequency C1 C2 use as normal I/O pins. 2009 .768kHz Note: C1 and C2 values are for guidance only. This clock source has a fixed frequency of 32. However. C1 and C2. Note that if this internal sys- tem clock option is selected. pin PB1. Note that internal frequency compensation circuits are used to en- two oscillator selections must be made namely one high sure that the influence of the power supply voltage. leaving pin PB2 free for use as a normal I/O tor configurations.

the only difference is that it will take more 3 2 . of 5V and at a temperature of 25°C degrees. The ex- cleared to zero ensuring that the LXT oscillator is in the act values of C1 and C2 should be selected in consulta- Quick Start operating mode. to ensure oscillation and 1 Low-power accurate frequency generation. C 1 a n d C 2 a r e r e q u ir e d . in many microcontroller applications it may be nec. These are the Watchdog Timer and the Time Base Interrupts. no matter what condition the C ir c u it LXTLP bit is set to. 1. is required. tem- perature and process variations on the oscillation 32. with reduced current consumption. a typical frequency of 32kHz at 5V. at a power supply Note: 1. the microcontroller activity and to conserve power. consumption is only required during the LXT oscillator the XT1/XT2 pins can be used as normal I/O pins. How. Supplementary Oscillators The low speed oscillators. frequency oscillator choices. In the Quick Start Mode the tion with the crystal or resonator manufacturer¢s LXT oscillator will power up and stabilise quickly. 0 Quick Start However. the LXT oscillator will always func- R p In te rn a l R C tion normally. HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 When the microcontroller enters the SLEEP or IDLE LXT Oscillator Low Power Function Mode. C1 and C2 values are for guidance only. requiring no external External LXT Oscillator components for its implementation. C 1 In te r n a l X T 1 O s c illa to r It should be noted that. selection is executed using the LXTLP bit in the TBC essary to keep the internal timers operational even register. another clock. such as battery · If the LXT oscillator is used for any clock source. RP=5M~10MW is recommended. As a result. R p . in addition to providing a sys- tem clock source are also used to provide a clock source to two other device functions. when the microcontroller is in the SLEEP or IDLE Mode. for some crystals. oscillation frequency of 32kHz will have a tolerance 32. after the LXT oscillator has fully powered up it can Rp. which is selected via con- 2 . cation program sets the LXTLP bit high about 2 seconds after power-on. It is a fully integrated RC oscillator with p a r a s itic c a p a c ita n c e o f a r o u n d 7 p F .LIRC C 2 The Internal 32kHz System Oscillator is one of the low N o te : 1 . In power sensitive applications. must be provided.7 6 8 O s c illa to r k H z time to start up if in the Low-power mode. How- specification. The mode ever. the applications. Rev. it is therefore recommended that the appli- XT1/XT2 pins. Quick Start Mode and the Low Power Mode. where power consumption must be kept to 32. be placed into the Low-power mode by setting the Some configuration options determine if the XT1/XT2 LXTLP bit high. C1 and C2. Device trimming during the manufacturing process and the inclusion of LXT Oscillator C1 and C2 Values internal frequency compensation circuits are used to en- Crystal Frequency C1 C2 sure that the influence of the power supply voltage. start-up.768kHz 10pF 10pF frequency are minimised. the system clock is switched off to stop The LXT oscillator can function in one of two modes. ever. 2009 .00 35 November 3. A lth o u g h n o t s h o w n p in s h a v e a figuration option. the fixed 2. it is necessary to add After power on the LXTLP bit will be automatically two small value external capacitors. independent of the system LXTLP Bit LXT Mode clock. X T 2 T o in te r n a l c ir c u its Internal 32kHz Oscillator .768kHz Crystal Recommended Capacitor Values within 10%. The oscillator will continue to run but pins are used for the LXT oscillator or as I/O pins. To do this.768kHz crystal should be connected to the a minimum. as the higher current · If the LXT oscillator is not used for any clock source. The external parallel feedback resistor.

2009 . a clock sys- tem can be configured to obtain maximum application performance. Rev. using the HLCLK bit and CKS2~CKS0 bits in the SMOD conflicting requirements that are especially true in bat. If fL is se- speed clocks reduce current consumption. selected via a configuration option. By providing vide a substitute clock for the microcontroller just after a the user with a wide range of clock options using config. There are two additional internal clocks for the periph- mance/power ratio. CKS2~CKS0 bits Low Speed Oscillation fSUB Configuration Option Fast Wake-up from SLEEP Mode or IDLE Mode Control (for HXT only) fTB C fTB Time Base fSYS /4 TBCK fS UB fS WDT fSYS/ 4 Configuration Option System Clock Configurations Note: When the system clock source fSYS is switched to fL from fH. their microcontroller to achieve the best perfor. Thus there is no fH~fH/64 for peripheral circuit to use. The low speed system clock current consumption and of course vice-versa. ERC or HIRC oscillator. High Speed Oscillation HXT fH ERC 6-stage Prescaler fH /2 HIRC fH /4 High Speed Oscillation fH/8 Configuration Option fH/16 Low Speed Oscillation f H/32 fH /64 LIRC fL fS YS LXT HLCLK. the substitute clock. from either an HXT. fL. As Holtek lected then it can be sourced by either the LXT or LIRC has provided these devices with both high and low oscillators. selected via quired for high performance will by their nature increase a configuration option. wake-up has occurred to enable faster wake-up times. fTBC. or low frequency. register. selected The device has many different clock sources for both via configuration options. Each of these internal clocks are System Clocks sourced by either the LXT or LIRC oscillators. source. HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 Operating Modes and System Clocks P re s e n t d a y appl i c a t i ons r equi r e t ha t t h e i r The main system clock. fSUB. eral circuits. uration options and register programming. can come from either a high fre- microcontrollers have high performance but often still quency. and the Time Base clock. The fast clocks re. The fSUB clock is used to pro- the CPU and peripheral function operation. The high speed system clock can be sourced tery powered portable applications. the high speed oscillation will stop to conserve the power. lower source can be sourced from internal clock fL. 1. which is a divided version of the high them dynamically. The speed clock sources and the means to switch between other choice. and is selected demand that they consume as little power as possible. the user can optimise the operation of speed system oscillator has a range of fH/2~fH/64. fH.00 36 November 3.

each one with its own special character- Description Operation Mode CPU fSYS fSUB fS fTBC NORMAL Mode On fH~ fH/64 On On On SLOW Mode On fL On On On IDLE0 Mode Off Off On On/Off On IDLE1 Mode Off On On On On SLEEP0 Mode Off Off Off Off Off SLEEP1 Mode Off Off On On Off · NORMAL Mode to operate if the LVDEN is ²1² or the Watchdog Timer As the name suggests this is one of the main operat. tions operational such as the Watchdog Timer.00 37 November 3. The high speed oscillator will however first is low. 1. In the SLEEP0 mode the CPU will be continue to run. source comes from fSUB then fS will be on. 2009 . will either be on or off de- pending upon the fS clock source. and if the set to ²1². In the IDLE0 Mode the vided clock ratio reduces the operating current. either the LXT or the LIRC. There are two modes allowing normal operation of the TMs. Watchdog Timer clock. If the source is · SLOW Mode fSYS/4 then the fS clock will be off. The clock source used will be from one of the low speed oscillators. the actual inhibited from driving the CPU but some peripheral ratio being selected by the CKS2~LCKS0 and HLCLK functions will remain operational such as the Watch- bits in the SMOD register. fS. In this Mode the Watchdog Timer clock. In the IDLE1 Mode. the microcontroller. The remaining four modes. In the SLOW ister is high and the FSYSON bit in the WDTC register Mode. System Operation Modes SLEEP1. TMs tion is executed and when the IDLEN bit in the SMOD and SIM. Although a high speed os. the system oscillator will register is low. functions operational and where the system clock is · IDLE0 Mode provided by one of the high speed oscillators. it won¢t enter the SLEEP0 Mode. In the IDLE0 Mode. either the HXT. IDLE0 and IDLE1 Mode are used when the There are six different modes of operation for the microcontroller CPU is switched off to conserve power. the sys- cillator is used. and the fSUB and fS clocks will be stopped too. If the mode. function is enabled and if its clock source is chosen ing modes where the microcontroller has all of its via configuration option to come from the fSUB. This mode operates allowing the microcontroller to operate The IDLE0 Mode is entered when a HALT instruction normally with a clock source will come from one of the is executed and when the IDLEN bit in the SMOD reg- high speed oscillators. running the microcontroller at a di. If the LVDEN is source is fSYS/4 then the fS clock will be on. tem oscillator will be stopped. microcontroller. and this system oscillator may be high stopped. However the fSUB and fS clocks will continue Rev. mes from fSUB then fS will be on. · SLEEP1 Mode The SLEEP Mode is entered when an HALT instruc- tion is executed and when the IDLEN bit in the SMOD register is low. the fH is off. In the IDLE1 and the Watchdog Timer function is disabled. will be on. The fTBC clock is used performance and power requirements of the applica- as a source for the Time Base interrupt functions and for tion. speed or low speed system oscillator. The IDLE1 Mode is entered when an HALT instruction Running the microcontroller in this mode allows it to is executed and when the IDLEN bit in the SMOD reg- run with much lower operating currents. TMs and SIM. In the IDLE0 Mode the system oscillator will be be divided by a ratio ranging from 1 to 64. the NORMAL Mode and SLOW Mode. the SLEEP0. In the SLEEP1 mode the CPU will be stopped. fS. the LVDEN is must set to ²0². HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 Together with fSYS/4 it is also used as one of the clock istics and which can be chosen according to the specific sources for the Watchdog timer. dog Timer. In the IDLE1 Mode the system oscillator will be inhibited from driving the CPU but may continue to · SLEEP0 Mode provide a clock source to keep some peripheral func- The SLEEP Mode is entered when an HALT instruc. ates normally although now with a slower speed clock · IDLE1 Mode source. ERC or HIRC ister is high and the FSYSON bit in the WDTC register oscillators. and if the source co- This is also a mode where the microcontroller oper. is high.

Therefore this flag will always be read as ²1² by the application program after device power-on. the CPU and the system clock will all stop in IDLE0 mode. if FSYSON bit is high. 2009 . the fSUB clock source can be used as a temporary system clock to provide a faster wake up time as the fSUB clock is available. 1. which can be either the LXT or LIRC.00 38 November 3. In the IDLE1 Mode the CPU will stop running but the system clock will continue to keep the peripheral functions operational. The flag will be low when in the SLEEP or IDLE0 Mode but after a wake-up has occurred. HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 Control Register A single register. when a HALT instruction is executed the device will enter the IDLE Mode. · SMOD Register Bit 7 6 5 4 3 2 1 0 Name CKS2 CKS1 CKS0 FSTEN LTO HTO IDLEN HLCLK R/W R/W R/W R/W R/W R R R/W R/W POR 0 0 0 0 0 0 1 1 Bit 7~5 CKS2~CKS0: The system clock selection when HLCLK is ²0² 000: fL (fLXT or fLIRC) 001: fL (fLXT or fLIRC) 010: fH/64 011: fH/32 100: fH/16 101: fH/8 110: fH/4 111: fH/2 These three bits are used to select which clock is used as the system clock source. a divided version of the high speed system oscillator can also be chosen as the system clock source. If FSYSON bit is low. In addition to the system clock source. When the bit is high. the flag will change to a high level after 1024 clock cycles if the LXT oscillator is used and 1~2 clock cycles if the LIRC oscillator is used. Bit 0 HLCLK: system clock selection 0: fH/2 ~ fH/64 or fL 1: fH This bit is used to select if the fH clock or the fH/2 ~ fH/64 or fL clock is used as the system clock. This flag is cleared to ²0² by hardware when the device is powered on and then changes to a high level after the high speed system oscillator is stable. Bit 4 FSTEN: Fast Wake-up Control (only for HXT) 0: Disable 1: Enable This is the Fast Wake-up Control bit which determines if the fSUB clock source is initially used after the device wakes up. SMOD. If the bit is low the device will enter the SLEEP Mode when a HALT instruction is executed. The flag will be low when in the SLEEP0 Mode but after a wake-up has occurred. When the bit is high the fH clock will be selected and if low the fH/2 ~ fH/64 or fL clock will be selected. If this bit is high. the flag will change to a high level after 1024 clock cycles if the HXT oscillator is used and after 15~16 clock cycles if the ERC or HIRC oscillator is used. Rev. When system clock switches from the fH clock to the fL clock and the fH clock will be automatically switched off to conserve power. Bit 2 HTO: High speed system oscillator ready flag 0: Not ready 1: Ready This is the high speed system oscillator ready flag which indicates when the high speed system oscillator is stable. Bit 1 IDLEN: IDLE Mode control 0: Disable 1: Enable This is the IDLE Mode Control bit and determines what happens when the HALT instruction is executed. is used for overall control of the internal clocks within the device. Bit 3 LTO: Low speed system oscillator ready flag 0: Not ready 1: Ready This is the low speed system oscillator ready flag which indicates when the low speed system oscillator is stable after power on reset or a wake-up has occurred.

FSTEN will have no effect in mode. 1. where the system clock If the HXT oscillator is selected as the NORMAL Mode source to the device will be stopped. The and allow normal operation to resume. As the clock source for as the system oscillator then it will take 15~16 clock cy- the Fast Wake-up function is fSUB. The Fast Wake-up enable/dis- System FSTEN Wake-up Time Wake-up Time Wake-up Time Wake-up Time Oscillator Bit (SLEEP0 Mode) (SLEEP1 Mode) (IDLE0 Mode) (IDLE1 Mode) 0 1024 HXT cycles 1024 HXT cycles 1~2 HXT cycles HXT 1~2 fSUB cycles 1 1024 HXT cycles (System runs with fSUB first for 1024 HXT cycles 1~2 HXT cycles and then switches over to run with the HXT clock) ERC X 15~16 ERC cycles 15~16 ERC cycles 1~2 ERC cycles HIRC X 15~16 HIRC cycles 15~16 HIRC cycles 1~2 HIRC cycles LIRC X 1~2 LIRC cycles 1~2 LIRC cycles 1~2 LIRC cycles LXT X 1024 LTX cycles 1024 LXT cycles 1~2 LXT cycles Wake-Up Times Note that if the Watchdog Timer is disabled. at which Wake-up function is provided.00 39 November 3. the Fast Wake-up function has no effect because these cases. modes. porary clock to first drive the system until the original If the ERC or HIRC oscillators or LIRC oscillator is used system oscillator has stabilised. stabilise LIRC or LXT oscillator for the system to wake-up. HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 Fast Wake-up able function is controlled using the FSTEN bit in the To minimise power consumption the device can enter SMOD register. the fSUB clock is stopped. switch over to operating from the HXT oscillator. When the device is woken up from the SLEEP0 The Fast Wake-up bit. However when the system clock. point the HTO flag will switch high and the system will namely either the LXT or LIRC oscillator. which allows fSUB. then it will take one to two tSUB clock cycles of the time for the original system oscillator to restart. To ensure the system will then initially run under the fSUB clock source device is up and running as fast as possible a Fast until 1024 HXT clock cycles have elapsed. the Fast Wake-up cles of the ERC or HIRC or 1~2 cycles of the LIRC to function is only available in the SLEEP1 and IDLE0 wake up the system from the SLEEP or IDLE0 Mode. 2009 . and if the Fast Wake-up function is en- device is woken up again. to act as a tem. the SLEEP or IDLE0 Mode. it can take a considerable abled. ID L E 1 N O R M A L H A L T in s tr u c tio n is e x e c u te d fS Y S = f H ~ f H / 6 4 C P U s to p fH o n ID L E N = 1 C P U ru n F S Y S O N = 1 fS Y S o n fS Y S o n fT B C o n fT B C o n fS U B o n fS U B o n S L E E P 0 ID L E 0 H A L T in s tr u c tio n is e x e c u te d H A L T in s tr u c tio n is e x e c u te d fS Y S o ff C P U s to p C P U s to p ID L E N = 1 ID L E N = 0 F S Y S O N = 0 fT B C o ff fS Y S o ff fS U B o ff fT B C o n W D T & L V D o ff fS U B o n S L E E P 1 S L O W H A L T in s tr u c tio n is e x e c u te d fS Y S = fL fS Y S o ff fL o n C P U s to p C P U ru n ID L E N = 0 fS Y S o n fT B C o ff fT B C o n fS U B o n fS U B o n W D T o r L V D o n fH o ff Rev. then there will be no Fast Wake-up function available when the device wakes-up from the SLEEP0 Mode. which means that the LXT and LIRC are all both off.

1. When a HALT instruction is executed.00 40 November 3. eration of other internal functions such as the TMs and namically allowing the user to select the best perfor. The accompanying flowchart shows what hap- mance/power ratio for the present task in hand. stop running to conserve power. the high speed clock source will tored using the LTO bit in the SMOD register. When this happens it must be noted that the fH/16 and fH/64 internal clock N O R M A L M o d e C K S 2 ~ C K S 0 = 0 0 x B & H L C L K = 0 S L O W M o d e W D T a n d L V D a r e a ll o ff ID L E N = 0 H A L T in s tr u c tio n is e x e c u te d S L E E P 0 M o d e W D T o r L V D is o n ID L E N = 0 H A L T in s tr u c tio n is e x e c u te d S L E E P 1 M o d e ID L E N = 1 . to the clock source. the system clock can switch to run in the Mode and SLOW Mode is executed using the HLCLK bit SLOW Mode by set the HLCLK bit to ²0² and set the and CKS2~CKS0 bits in the SMOD register while Mode Switching from the NORMAL/SLOW Modes to the CKS2~CKS0 bits to ²000² or ²001² in the SMOD regis- SLEEP/IDLE Modes is executed via the HALT instruc. ter. and therefore consumes In simple terms. F S Y S O N = 1 H A L T in s tr u c tio n is e x e c u te d ID L E 1 M o d e Rev. The SLOW Mode is sourced from the LXT or the LIRC plies that clock source is switched from the high speed oscillators and therefore requires these oscillators to be clock source. this for certain operations which do not require high per- termined by the condition of the IDLEN bit in the SMOD formance and can subsequently reduce power con- register and FSYSON in the WDTC register. the SIM. which may affect the op- The device can switch between operating modes dy. This will then use the low speed system oscillator tion. 2009 . fH/2~fH/64 or fL. which uses the high speed system oscillator. which im. If stable before full mode switching occurs. Users may decide to do device enters the IDLE Mode or the SLEEP Mode is de. When running in the NORMAL Mode. performance can be executed using slower clocks thus NORMAL Mode to SLOW Mode Switching requiring less operating current and prolonging battery life in portable applications. sumption. fH. This is moni- the clock is from the fL. F S Y S O N = 0 H A L T in s tr u c tio n is e x e c u te d ID E L 0 M o d e ID L E N = 1 . Mode Switching between the NORMAL more power. In this pens when the device moves between the various oper- way microcontroller operations that do not require high ating modes. whether the which will consume less power. HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 Operating Mode Switching and Wake-up sources will also stop running. When the HLCLK bit switches to a low level.

When this instruction is executed under the condi- ²101². off. 1. where the high speed system oscillator tion in the application program with the IDLEN bit in is used.00 41 November 3. PDF. the · The system clock. 0 0 1 B a s H L C L K = 0 o r H L C L K = 1 N O R M A L M o d e W D T a n d L V D a r e a ll o ff ID L E N = 0 H A L T in s tr u c tio n is e x e c u te d S L E E P 0 M o d e W D T o r L V D is o n ID L E N = 0 H A L T in s tr u c tio n is e x e c u te d S L E E P 1 M o d e ID L E N = 1 . the following will occur: required for the high frequency clock to stabilise. As a certain amount of time will be tions described above. depends upon which high speed system oscillator type · The Data Memory contents and registers will maintain is used. · The I/O ports will maintain their present conditions. · In the status register. WDT clock and Time Base clock status of the HTO bit is checked. will be cleared. To switch back to the SLEEP0 Mode and that is to execute the ²HALT² instruc- NORMAL Mode. TO. The amount of time will be stopped and the application program will stop required for high speed system oscillator stabilization at the ²HALT² instruction. ²011². ²110² or ²111². Rev. but CKS2~CKS0 is set to ²010². ²100². their present condition. F S Y S O N = 1 H A L T in s tr u c tio n is e x e c u te d ID L E 1 M o d e SLOW Mode to NORMAL Mode Switching Entering the SLEEP0 Mode In SLOW Mode the system uses either the LXT or LIRC There is only one way for the device to enter the low speed system oscillator. the Power Down flag. 2009 . · The WDT will be cleared and stopped no matter if the WDT clock source originates from the fSUB clock or from the system clock. HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 S L O W M o d e C K S 2 ~ C K S 0 ¹ 0 0 0 B . the HLCLK bit should be set to ²1² or HLCLK bit SMOD register equal to ²0² and the WDT and LVD both is ²0². will be set and the Watchdog time-out flag. F S Y S O N = 0 H A L T in s tr u c tio n is e x e c u te d ID L E 0 M o d e ID L E N = 1 .

1. When this instruction is executed under the condi- account by the circuit designer if the power consumption tions described above. such as other CMOS inputs. PDF. HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 Entering the SLEEP1 Mode Entering the IDLE1 Mode There is only one way for the device to enter the There is only one way for the device to enter the IDLE1 SLEEP1 Mode and that is to execute the ²HALT² Mode and that is to execute the ²HALT² instruction in the instruction in the application program with the IDLEN bit application program with the IDLEN bit in SMOD register in SMOD register equal to ²0² and the WDT or LVD on. will be be set and the Watchdog time-out flag. will should be placed in a condition in which minimum cur- be set and the Watchdog time-out flag. · In the status register. any floating input pins could create internal oscillations · The Data Memory contents and registers will maintain and result in increased current consumption. 2009 . · The I/O ports will maintain their present conditions. Also note that additional standby current will also be required if the configuration options have enabled the LXT or LIRC oscillator. cleared. TO. if the sys- tem oscillator is from the high speed system oscillator. will be cleared. the Power Down flag. but the WDT or LVD will remain ²HALT² instruction. In the IDLE1 Mode the system oscillator is on. clock. PDF. the following will occur: conditions described above. TO. with the clock source coming from the fSUB clock. the following will occur: is to be minimised. but the must be connected to either a fixed high or low level as Time Base clock and fSUB clock will be on. applies to devices which have different package types. TO. All high-impedance input pins program will stop at the ²HALT² instruction. These must either be WDT clock source is selected to come from the fSUB setup as outputs or if setup as inputs must have clock and the WDT is enabled. which are con- nected to I/O pins. clock source originates from the system clock.00 42 November 3. · The WDT will be cleared and resume counting if the as there may be unbonbed pins. · The I/O ports will maintain their present conditions. These · In the status register. there are other considerations which must also be taken into to ²0². · The WDT will be cleared and resume counting if the · The WDT will be cleared and resume counting if the WDT is enabled regardless of the WDT clock source WDT clock source is selected to come from the fSUB which originates from the fSUB clock or from the system clock as the WDT is enabled. · The I/O ports will maintain their present conditions. which are setup as outputs. This also their present condition. the following will occur: · The system clock and Time Base clock will be · The system clock and Time Base clock and fSUB clock stopped and the application program will stop at the will be on and the application program will stop at the ²HALT² instruction. When this instruction is executed under the with described above. Care must also be taken with the loads. the Power Down flag. equal to ²1² and the FSYSON bit in WDTC register equal When this instruction is executed under the conditions to ²1². will be set and the Watchdog time-out flag. the Power Down flag. Special attention must be made to · The system clock will be stopped and the application the I/O pins on the device. their present condition. rent is drawn or connected only to external circuits that do not draw current. PDF. will · In the status register. the additional standby current will also be perhaps in the order of several hundred micro-amps Rev. · The Data Memory contents and registers will maintain · The Data Memory contents and registers will maintain their present condition. Entering the IDLE0 Mode Standby Current Considerations There is only one way for the device to enter the IDLE0 As the main reason for entering the SLEEP or IDLE Mode and that is to execute the ²HALT² instruction in the Mode is to keep the current consumption of the device application program with the IDLEN bit in SMOD register to as low a value as possible. The WDT will stop if its pull-high resistors connected. will be cleared. perhaps only in the order equal to ²1² and the FSYSON bit in WDTC register equal of several micro-amps except in the IDLE1 Mode.

the ac- executed. in which case the regular inter- rupt response takes place. the system. a Watchdog tor may not be stability if fSUB is from LXT oscillator. then two possible situations may occur. The Timer reset will be initiated. the wake-up function of the related interrupt will be disabled. and causes a wake-up that only resets the Program · There are peripheral functions. The PDF flag is cleared by a NORMAL Mode. the interrupt which woke-up the device will not be immediately serviced. If the system is woken up by an clock source is selected from fSUB. the clock source to the Each pin on Port A can be setup using the PAWU regis. When a Port A pin wake-up occurs. In this situation. up. the LXT oscilla- device is woken up by a WDT overflow. such as WDT. the system clock can Timer instructions and is set when executing the ²HALT² be switched to the LXT or LIRC oscillator after wake instruction.00 43 November 3. The TO flag is set if a WDT time-out occurs. The LXT oscillator is not ready yet when the first instruction is wake-up methods will initiate a reset operation. in which case the program will resume execution at the instruction following the ²HALT² instruction. for which the fSYS is used. · The on/off condition of fSUB and fS depends upon gram will resume execution at the instruction following whether the WDT is enabled or disabled as the WDT the ²HALT² instruction. if the system is woken up from the lows: SLEEP0 Mode and both the HXT and LXT oscillators · An external reset need to start-up from an off state. if the struction after HTO is ²1². HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 Wake-up Programming Considerations After the system enters the SLEEP or IDLE Mode. peripheral functions mentioned above will change ac- ter to permit a negative transition on the pin to wake-up cordingly. it can The HXT and LXT oscillators both use the same SST be woken up from one of various sources listed as fol. the high speed system oscillator If the system is woken up by an external reset. The first is where the related interrupt is disabled or the interrupt is enabled but the stack is full. the de. counter. TMs Counter and Stack Pointer. needs an SST period. · A system interrupt · If the device is woken up from the SLEEP0 Mode to · A WDT overflow the NORMAL Mode. At this time. Rev. The device will execute first in- vice will experience a full system reset. The LXT oscillator · An external falling edge on Port A uses the SST counter after HXT oscillator has finished its SST period. source is switched from fH to fL. Although both of these same situation occurs in the power-on state. but will rather be serviced later when the related interrupt is fi- nally enabled or when a stack level becomes free. If the system clock original status. For example. the pro. the other flags remain in their and SIM. tual source of the wake-up can be determined by exam- · If the device is woken up from the SLEEP1 Mode to ining the TO and PDF flags. The other situation is where the related interrupt is enabled and the stack is not full. and the system clock source is from system power-up or executing the clear Watchdog HXT oscillator and FSTEN is ²1². however. interrupt. 1. If an interrupt request flag is set high before entering the SLEEP or IDLE Mode. 2009 .

00 44 November 3. fS. The LXT oscillator is supplied by an ex- such as electrical noise. Bit 3 ~ 0 WDTEN3. clock period can vary with VDD. due to certain uncontrollable external events cess variations.768kHz crystal. ternal 32. WDTC register to obtain the required Watchdog Timer The fSUB clock can be sourced from either the LXT or time-out period. The Watchdog Watchdog Timer Clock Source Timer clock source can originate from its own internal The Watchdog Timer clock source is provided by the in. LIRC oscillator. WDTEN2. This reg- the WDTC register. again chosen via a configuration op- Watchdog Timer Control Register tion. 1. WS0 : WDT time-out period selection 000: 256/fS 001: 512/fS 010: 1024/fS 011: 2048/fS 100: 4096/fS 101: 8192/fS 110: 16384/fS 111: 32768/fS These three bits determine the division ratio of the Watchdog Timer source clock. the overall operation of the Watchdog Timer. It is divided ternal clock. it should be noted that this specified internal malfunctions or sequences from jumping to unknown lo. using the WS2~WS0 bits in the sources selected by configuration option: fSUB or fSYS/4. 2009 . The other Watchdog Timer clock source option is the fSYS/4 clock. The LIRC internal oscillator has an ister together with several configuration options control approximate period of 32kHz at a supply voltage of 5V. WDTEN1. WDTEN0 : WDT Software Control 1010: Disable Other: Enable Rev. · WDTC Register Bit 7 6 5 4 3 2 1 0 Name FSYSON WS2 WS1 WS0 WDTEN3 WDTEN2 WDTEN1 WDTEN0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 1 1 1 1 0 1 0 Bit 7 FSYSON: fSYS Control in IDLE Mode 0: Disable 1: Enable Bit 6 ~ 4 WS2. which in turn determines the timeout period. temperature and pro- cations. LIRC oscillators. HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 Watchdog Timer The Watchdog Timer is provided to prevent program However. WS1. The Watchdog Timer source clock is then subdi- vided by a ratio of 28 to 215 to give longer timeouts. which is in turn supplied by one of two by a value of 28 to 215. controls the required timeout actual value being chosen using the WS2~WS0 bits in period as well as the enable/disable operation. the LXT oscillator or fSYS/4. the A single register. WDTC.

In addition to a configuration op. clock source gle ²CLR WDT² instruction while the second is to use selection and clear instruction type are selected using the two commands ²CLR WDT1² and ²CLR WDT2². If the fSYS/4 clock is used as the Watchdog Timer WDT Enable xxxx Enable clock source. there are clear the WDT while for the second option. Some of the Watch. For systems that operate in noisy Watchdog Timer Enable/Disable Control environments. For configuration options. if ²CLR WDT1² is used to well as the configuration option being set to disable. However. with a 32. HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 Watchdog Timer Operation bit TO. or enters an end. Note Watchdog Timer. only the execution of a value of ²1010². and a minimum timeout of 7. To disable the Watchdog Timer. Mode. irrespective of the configu- Similarly after the ²CLR WDT2² instruction has been ex- ration enable/disable setting. only a successive ²CLR WDT1² instruction can it is recommended that they are set to a value of 0101 for clear the Watchdog Timer. Three methods has to strategically clear the Watchdog Timer before it can be adopted to clear the contents of the Watchdog overflows to prevent the Watchdog Timer from execut. the Watchdog Timer enabled. when a Watchdog Timer time-out occurs. this will give a maximum watchdog period of around 1 second for the 215 division WDT Configuration WDTEN3~ WDT ratio. in which case the Watchdog Timer clear the Watchdog Timer. third is via a HALT instruction. a Watchdog Timer time-out will initialise a device reset and set the status C L R W D T 1 F la g C le a r W D T T y p e C L R W D T 2 F la g C o n fig u r a tio n O p tio n 1 o r 2 In s tr u c tio n s C L R fS /2 8 fS Y S /4 M fS 8 . Note that if the Watchdog The maximum time out period is when the 215 division ra- Timer has been disabled. If the program malfunctions for whatever the Watchdog Timer software clear instructions and the reason. one of which must be chosen will overflow and reset the device. This is done using the clear watchdog in. both ²CLR also four bits.o u t C o n fig u r a tio n (2 8 /fS ~ 2 15/fS ) O p tio n C o n fig u r a tio n W S 2 ~ W S 0 O p tio n (fS /2 8 ~ fS /2 15) Watchdog Timer Rev.s ta g e D iv id e r W D T P r e s c a le r U L X T M fS U B X U L IR C X 8 -to -1 M U X W D T T im e . oscillator as its source clock. This means that in the ap. After power on these bits will have the value of 1010. the TO set when its timer overflows. If the Watchdog Timer is used ecuted. then the instruction clock is stopped and the Watchdog Timer may lose its WDT Disable 1010 Disable protecting purposes. the clear the Watchdog Timer. The first is an external hardware reset. a simple execution of ²CLR WDT² will tion to enable/disable the Watchdog Timer. bit in the status register will be set and only the Program plication program and during normal operation the user Counter and Stack Pointer will be reset. by configuration option. successive executions of this WDTEN3~WDTEN0 bits must also be set to a specific instruction will have no effect. it should be noted that when the system WDT Disable Except 1010 Enable enters the SLEEP or IDLE0 Mode. then any instruction relating to tio is selected. as that for this second option.00 45 November 3. maximum noise immunity. jumps to an unkown location. the first option. means a low level on the RES pin. if the system is in the SLEEP or IDLE The Watchdog Timer operates by providing a device re. Under normal program operation. WDTEN3~WDTEN0. which ing a reset. Any other values for these bits will keep ²CLR WDT2² instruction will clear the Watchdog Timer. using the fSUB clock source is strongly recommended. in the WDTC regis- WDT1² and ²CLR WDT2² must both be executed alter- ter to offer an additional enable/disable control of the nately to successfully clear the Watchdog Timer. the second is using structions. 2009 . 1.8ms for the 28 division Option WDTEN0 Bits ration. The first option is to use the sin- dog Timer options. such as enable/disable.768kHz LXT its operation will result in no operation. As an example. Timer. less loop. these clear instructions will not be executed in There are two methods of using software instructions to the correct manner.

af. the RES pin. The most important reset condition is after though the microcontroller has an internal RC reset power is first applied to the microcontroller. As well as ensuring that the Program added in environments where power line noise Memory begins execution from the first memory ad. some of the microcontroller registers remain pin should be kept as short as possible to minimise unchanged allowing the microcontroller to proceed with any stray noise interference. LVR.9 V D D R E S t RR SS TT DD ++ t SS SS TT In te rn a l R e s e t Note: tRSTD is power-on delay.0. enough or does not stabilise quickly at power-on. will be in a well defined state and ready internal reset function may be incapable of providing to execute the first program instruction. when the microcontroller is running. Al- parameters.00 46 November 3.0 1 m F * * operations result in different register conditions being V D D setup. the reset delay time tRSTD is invoked to provide In addition to the power-on reset. All types of reset 0 . known as a normal oper. typical time=100ms Power-On Reset Timing Chart Rev. normal operation after the reset line is allowed to return For applications that operate within an environment high. where more noise is present the Enhanced Reset Cir- cuit shown is recommended. function. value. Another type of reset is when the Watchdog Timer over- V D D flows and resets the microcontroller. HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 Reset and Initialisation A reset function is a fundamental part of any · RES Pin microcontroller ensuring that the device can be set to As the reset pin is shared with PB. V S S ternally: · Power-on Reset Note: ²*² It is recommended that this component is The most fundamental and unavoidable reset is the added for added ESD protection one that occurs after power is first applied to the ²**² It is recommended that this component is microcontroller. through events occurring both internally and ex. ternal reset circuit. similar to the RES reset 1 N 4 1 4 8 * 1 0 k W ~ is implemented in situations where the power supply 1 0 0 k W voltage falls below a certain threshold. normal operation of the microcontroller will be begin program execution from the lowest Program inhibited. a power-on reset also ensures that certain other registers are preset to known conditions. if the VDD power supply rise time is not fast internal circuitry will ensure that the microcontroller. For this reason it is recom- power-on reset. In this case. The abbreviation SST in the figures stands for System Start-up Timer. 1. 2009 . P B 0 /R E S 3 0 0 W * Reset Functions 0 . V D D 0 . whose additional time delay will ensure that the RES pin remains low for an extended period mences. situations may arise an extra delay time after which the microcontroller will where it is necessary to forcefully apply a reset condition begin normal operation. website. certain important internal registers will mended that an external RC network is connected to be set to defined states before the program com. the ter a short delay. Any wiring connected to the RES ation reset. to allow the power supply to stabilise. One example of this For most applications a resistor connected between is where after power has been applied and the VDD and the RES pin and a capacitor connected be- microcontroller is already running. is significant dress. During this time which will be reset to zero forcing the microcontroller to delay. the reset function some predetermined condition irrespective of outside must be selected using a configuration option. After this proper reset operation. All the External RES Circuit I/O port and port control registers will power up in a More information regarding external reset circuits is high condition ensuring that all pins will be first set to located in Application Note HA0075E on the Holtek inputs. In such a case. tween VSS and the RES pin will provide a suitable ex- fully pulled low. Another reset exists in the form of a Low Voltage Reset. After the RES line reaches a certain voltage Memory address. One of these registers is the Program Counter. the RES line is force. where a full reset.1 ~ 1 m F There are five ways in which a microcontroller reset can occur.

i. One of a WDT time-out reset during IDLE or SLEEP range of specified voltage values for VLVR can be se. If the supply reset flags are shown in the table: voltage of the device drops to within a range of TO PDF RESET Conditions 0. WDT counting W D T T im e . the Program Counter will reset to to the A. characteristics. typical time=100ms Stack Pointer will point to the top Stack Pointer of the stack WDT Time-out Reset during Normal Operation Timing Chart · Watchdog Time-out Reset during SLEEP or IDLE Mode The Watchdog time-out Reset during SLEEP or IDLE Mode is a little different from other kinds of reset. 1. The LVR includes the following specifications: For RES or LVR reset during NORMAL or a valid LVR signal. typical time=100ms The different types of reset described affect the reset RES Reset Timing Chart flags in different ways. In te rn a l R e s e t Reset Initial Conditions Note: tRSTD is power-on delay.9V~VLVR such as might occur when changing the bat- tery. Characteristics for tSST details. Note: tRSTD is power-on delay. the LVR will automatically reset the device inter. If the WDT time-out reset during NORMAL or 1 u low voltage state does not exceed tLVR.4 V D D tSST is 1024 clock for HXT or LXT. the LVR will ig. zero and program execution initiated from this point. The tSST is tR S T D + tS S T 1~2 clock for LIRC. These flags. 0 0 Power-on reset nally. typical time=100ms a power-on reset occurs.C. known as PDF and TO are located in the status register and are controlled · Low Voltage Reset . The R E S 0 . Refer case of other resets. which is selected via a configuration option. HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 Pulling the RES Pin low using external hardware will Program Counter and the Stack Pointer will be also execute a device reset. In this case. Interrupts All interrupts will be disabled tion is the same as a hardware RES pin reset except Clear after reset. such as the The microcontroller contains a low voltage reset circuit SLEEP or IDLE Mode function or Watchdog Timer. Note: The tSST is 15~16 clock cycles if the system 0 . L V R Note: ²u² stands for unchanged tR S T D + tS S T The following table indicates the way in which the vari- In te rn a l R e s e t ous components of the microcontroller are affected after Note: tRSTD is power-on delay. a voltage in the u u SLOW Mode operation range between 0. Low Voltage Reset Timing Chart Item Condition After RESET Program Counter Reset to zero · Watchdog Time-out Reset during Normal Operation The Watchdog time-out Reset during normal opera.. Most of the conditions remain unchanged except that the W D T T im e . 2009 . SLOW Mode operation nore it and will not perform a reset function.00 47 November 3. a low voltage.9V~VLVR must exist for greater than the value tLVR specified in the A. WDT begins that the Watchdog time-out flag TO will be set to ²1².e. as in the cleared to ²0² and the TO flag will be set to ²1².o u t Timer/Event Timer Counter will be turned off tR S T D + tS S T Counter In te rn a l R e s e t Input/Output Ports I/O ports will be setup as inputs.LVR by various microcontroller operations.C. 1 1 Mode operation lected using configuration options. The in order to monitor the supply voltage of the device.9 V D D clock source is provided by ERC or HIRC.o u t tS S T In te rn a l R e s e t WDT Time-out Reset during SLEEP or IDLE Timing Chart Rev.

0000 ---.0000 ---.--xx ---. it is important to know what condition the microcontroller is in after a particular reset occurs.uuuu PC ---. · HT68F20 Register Reset RES or LVR WDT Time-out WDT Time-out Register (Power-on) Reset (Normal Operation) (IDLE) MP0 -xxx xxxx -xxx xxxx -xxx xxxx -uuu uuuu MP1 -xxx xxxx -xxx xxxx -xxx xxxx -uuu uuuu BP ---. 2009 . uuuu uuu- Rev.--uu ---. Note that where more than one package type exists the table will reflect the situation for the larger package type. 1.0000 ---. The following table describes how each type of reset affects each of the microcontroller internal registers.uuuu PCC ---.--uu ---.0000 ---.1111 ---.1111 ---.---0 ---.---0 ---.uuuu CP0C 1000 0--1 1000 0--1 1000 0--1 uuuu u--u CP1C 1000 0--1 1000 0--1 1000 0--1 uuuu u--u SIMC0 1110 000. 1110 000.uuuu WDTC 0111 1010 0111 1010 0111 1010 uuuu uuuu TBC 0011 0111 0011 0111 0011 0111 uuuu uuuu INTC0 -000 0000 -000 0000 -000 0000 -uuu uuuu INTC1 0000 0000 0000 0000 0000 0000 uuuu uuuu INTC2 0000 0000 0000 0000 0000 0000 uuuu uuuu MFI0 --00 --00 --00 --00 --00 --00 --uu --uu MFI1 --00 --00 --00 --00 --00 --00 --uu --uu MFI2 0000 0000 0000 0000 0000 0000 uuuu uuuu PAWU 0000 0000 0000 0000 0000 0000 uuuu uuuu PAPU 0000 0000 0000 0000 0000 0000 uuuu uuuu PA 1111 1111 1111 1111 1111 1111 uuuu uuuu PAC 1111 1111 1111 1111 1111 1111 uuuu uuuu PBPU --00 0000 --00 0000 --00 0000 --uu uuuu PB --11 1111 --11 1111 --11 1111 --uu uuuu PBC --11 1111 --11 1111 --11 1111 --uu uuuu PCPU ---.1111 ---.--uu STATUS --00 xxxx --uu uuuu --1u uuuu --11 uuuu SMOD 0000 0011 0000 0011 0000 0011 uuuu uuuu LVDC --00 -000 --00 -000 --00 -000 --uu -uuu INTEG ---.1111 ---.0000 ---.00 48 November 3.1111 ---.1111 ---. HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 The different kinds of resets all affect the internal registers of the microcontroller in different ways.---u ACC xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu PCL 0000 0000 0000 0000 0000 0000 0000 0000 TBLP xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu TBLH --xx xxxx --uu uuuu --uu uuuu --uu uuuu TBHP ---. To ensure reliable continuation of normal program execution after a reset occurs. 1110 000.---0 ---.0000 ---.

--00 ---.--00 ---.--00 ---.--uu TM0AL 0000 0000 0000 0000 0000 0000 uuuu uuuu TM0AH ---.0000 ---.--00 ---.--00 ---.--00 ---.--uu EEA ---x xxxx ---x xxxx ---x xxxx ---0 0000 EED xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu EEC ---.--uu SCOMC 0000 0000 0000 0000 0000 0000 uuuu uuuu Note: ²u² stands for unchanged ²x² stands for unknown ²-² stands for unimplemented Rev. 1.0000 ---.uuuu TMPC0 --01 ---1 --01 ---1 --01 ---1 --uu ---u TM1C0 0000 0000 0000 0000 0000 0000 uuuu uuuu TM1C1 0000 0000 0000 0000 0000 0000 uuuu uuuu TM1DL 0000 0000 0000 0000 0000 0000 uuuu uuuu TM1DH ---.--00 ---.--uu TM1AL 0000 0000 0000 0000 0000 0000 uuuu uuuu TM1AH ---.--00 ---.--00 ---. 2009 .--00 ---.0000 ---.00 49 November 3.--00 ---. HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 Reset RES or LVR WDT Time-out WDT Time-out Register (Power-on) Reset (Normal Operation) (IDLE) SIMC1 1000 0001 1000 0001 1000 0001 uuuu uuuu SIMD xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu SIMA/SIMC2 0000 0000 0000 0000 0000 0000 uuuu uuuu TM0C0 0000 0000 0000 0000 0000 0000 uuuu uuuu TM0C1 0000 0000 0000 0000 0000 0000 uuuu uuuu TM0DL 0000 0000 0000 0000 0000 0000 uuuu uuuu TM0DH ---.--00 ---.

1. uuuu uuu- SIMC1 1000 0001 1000 0001 1000 0001 uuuu uuuu SIMD xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu SIMA/SIMC2 0000 0000 0000 0000 0000 0000 uuuu uuuu TM0C0 0000 0000 0000 0000 0000 0000 uuuu uuuu TM0C1 0000 0000 0000 0000 0000 0000 uuuu uuuu Rev.-uuu ---.0000 ---. 2009 . 1110 000.0000 ---.-uuu ---. HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 · HT68F30 Register Reset RES or LVR WDT Time-out WDT Time-out Register (Power-on) Reset (Normal Operation) (IDLE) MP0 -xxx xxxx -xxx xxxx -xxx xxxx -uuu uuuu MP1 -xxx xxxx -xxx xxxx -xxx xxxx -uuu uuuu BP ---.--00 ---.0000 ---.uuuu WDTC 0111 1010 0111 1010 0111 1010 uuuu uuuu TBC 0011 0111 0011 0111 0011 0111 uuuu uuuu INTC0 -000 0000 -000 0000 -000 0000 -uuu uuuu INTC1 0000 0000 0000 0000 0000 0000 uuuu uuuu INTC2 0000 0000 0000 0000 0000 0000 uuuu uuuu MFI0 --00 --00 --00 --00 --00 --00 --uu --uu MFI1 -000 -000 -000 -000 -000 -000 -uuu -uuu MFI2 0000 0000 0000 0000 0000 0000 uuuu uuuu PAWU 0000 0000 0000 0000 0000 0000 uuuu uuuu PAPU 0000 0000 0000 0000 0000 0000 uuuu uuuu PA 1111 1111 1111 1111 1111 1111 uuuu uuuu PAC 1111 1111 1111 1111 1111 1111 uuuu uuuu PBPU --00 0000 --00 0000 --00 0000 --uu uuuu PB --11 1111 --11 1111 --11 1111 --uu uuuu PBC --11 1111 --11 1111 --11 1111 --uu uuuu PCPU 0000 0000 0000 0000 0000 0000 uuuu uuuu PC 1111 1111 1111 1111 1111 1111 uuuu uuuu PCC 1111 1111 1111 1111 1111 1111 uuuu uuuu CP0C 1000 0--1 1000 0--1 1000 0--1 uuuu u--u CP1C 1000 0--1 1000 0--1 1000 0--1 uuuu u--u SIMC0 1110 000.--00 ---.--00 ---.-xxx ---.00 50 November 3.--uu ACC xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu PCL 0000 0000 0000 0000 0000 0000 0000 0000 TBLP xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu TBLH --xx xxxx --uu uuuu --uu uuuu --uu uuuu TBHP ---.-uuu STATUS --00 xxxx --uu uuuu --1u uuuu --11 uuuu SMOD 0000 0011 0000 0011 0000 0011 uuuu uuuu LVDC --00 -000 --00 -000 --00 -000 --uu -uuu INTEG ---. 1110 000.

0000 ---.00 51 November 3.--00 ---.--uu SCOMC 0000 0000 0000 0000 0000 0000 uuuu uuuu Note: ²u² stands for unchanged ²x² stands for unknown ²-² stands for unimplemented Rev.--00 ---.--00 ---.-000 ---.0000 ---.--00 ---.--uu TM1AL 0000 0000 0000 0000 0000 0000 uuuu uuuu TM1AH ---. 2009 .--00 ---.0000 ---. HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 Reset RES or LVR WDT Time-out WDT Time-out Register (Power-on) Reset (Normal Operation) (IDLE) TM0DL 0000 0000 0000 0000 0000 0000 uuuu uuuu TM0DH ---.--00 ---.--uu TM0AL 0000 0000 0000 0000 0000 0000 uuuu uuuu TM0AH ---.--00 ---.--00 ---.-000 ---.--00 ---.--uu TM1BL 0000 0000 0000 0000 0000 0000 uuuu uuuu TM1BH ---.--uu EEA --xx xxxx --xx xxxx --xx xxxx --uu uuuu EED xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu EEC ---.--00 ---.--00 ---.-uuu TM1C0 0000 0000 0000 0000 0000 0000 uuuu uuuu TM1C1 0000 0000 0000 0000 0000 0000 uuuu uuuu TM1C2 0000 0000 0000 0000 0000 0000 uuuu uuuu TM1DL 0000 0000 0000 0000 0000 0000 uuuu uuuu TM1DH ---.-000 ---.--00 ---.uuuu TMPC0 1-01 --01 1-01 --01 1-01 --01 u-uu --uu PRM0 ---.--00 ---.--00 ---.--00 ---. 1.

2009 .00 52 November 3.uuuu STATUS --00 xxxx --uu uuuu --1u uuuu --11 uuuu SMOD 0000 0011 0000 0011 0000 0011 uuuu uuuu LVDC --00 -000 --00 -000 --00 -000 --uu -uuu INTEG ---.--11 ---.xxxx ---.---0 ---.uuuu ---.--11 ---.--uu Rev.uuuu ---. 1.---u ACC xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu PCL 0000 0000 0000 0000 0000 0000 0000 0000 TBLP xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu TBLH -xxx xxxx -uuu uuuu -uuu uuuu -uuu uuuu TBHP ---.---0 ---.--00 ---.--00 ---.uuuu WDTC 0111 1010 0111 1010 0111 1010 uuuu uuuu TBC 0011 0111 0011 0111 0011 0111 uuuu uuuu INTC0 -000 0000 -000 0000 -000 0000 -uuu uuuu INTC1 0000 0000 0000 0000 0000 0000 uuuu uuuu INTC2 0000 0000 0000 0000 0000 0000 uuuu uuuu MFI0 0000 0000 0000 0000 0000 0000 uuuu uuuu MFI1 -000 -000 -000 -000 -000 -000 -uuu -uuu MFI2 0000 0000 0000 0000 0000 0000 uuuu uuuu PAWU 0000 0000 0000 0000 0000 0000 uuuu uuuu PAPU 0000 0000 0000 0000 0000 0000 uuuu uuuu PA 1111 1111 1111 1111 1111 1111 uuuu uuuu PAC 1111 1111 1111 1111 1111 1111 uuuu uuuu PBPU 0000 0000 0000 0000 0000 0000 uuuu uuuu PB 1111 1111 1111 1111 1111 1111 uuuu uuuu PBC 1111 1111 1111 1111 1111 1111 uuuu uuuu PCPU 0000 0000 0000 0000 0000 0000 uuuu uuuu PC 1111 1111 1111 1111 1111 1111 uuuu uuuu PCC 1111 1111 1111 1111 1111 1111 uuuu uuuu PDPU 0000 0000 0000 0000 0000 0000 uuuu uuuu PD 1111 1111 1111 1111 1111 1111 uuuu uuuu PDC 1111 1111 1111 1111 1111 1111 uuuu uuuu PEPU 0000 0000 0000 0000 0000 0000 uuuu uuuu PE 1111 1111 1111 1111 1111 1111 uuuu uuuu PEC 1111 1111 1111 1111 1111 1111 uuuu uuuu PFPU ---.--11 ---.--00 ---.--uu PFC ---.--uu PF ---.0000 ---.---0 ---.--11 ---.--11 ---.0000 ---.--11 ---. HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 · HT68F40 Register Reset RES or LVR WDT Time-out WDT Time-out Register (Power-on) Reset (Normal Operation) (IDLE) MP0 xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu MP1 xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu BP ---.0000 ---.

--00 ---.--00 ---.--00 ---.--uu EEA -xxx xxxx -xxx xxxx -xxx xxxx -uuu uuuu EED xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu EEC ---.--00 ---. uuuu uuu- SIMC1 1000 0001 1000 0001 1000 0001 uuuu uuuu SIMD xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu SIMA/SIMC2 0000 0000 0000 0000 0000 0000 uuuu uuuu TM0C0 0000 0000 0000 0000 0000 0000 uuuu uuuu TM0C1 0000 0000 0000 0000 0000 0000 uuuu uuuu TM0DL 0000 0000 0000 0000 0000 0000 uuuu uuuu TM0DH ---.0000 ---.--00 ---.--00 ---.0000 000.--00 ---.--01 ---. 0000 0--.00 53 November 3. 1110 000.--uu TM1AL 0000 0000 0000 0000 0000 0000 uuuu uuuu TM1AH ---. HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 Reset RES or LVR WDT Time-out WDT Time-out Register (Power-on) Reset (Normal Operation) (IDLE) CP0C 1000 0--1 1000 0--1 1000 0--1 uuuu u--u CP1C 1000 0--1 1000 0--1 1000 0--1 uuuu u--u SIMC0 1110 000.--01 ---. 2009 . 1. 0000 0--.--00 ---.--00 ---. uuuu u--- TM2C1 0000 0000 0000 0000 0000 0000 uuuu uuuu TM2DL 0000 0000 0000 0000 0000 0000 uuuu uuuu TM2DH 0000 0000 0000 0000 0000 0000 uuuu uuuu TM2AL 0000 0000 0000 0000 0000 0000 uuuu uuuu TM2AH 0000 0000 0000 0000 0000 0000 uuuu uuuu TM2RP 0000 0000 0000 0000 0000 0000 uuuu uuuu SCOMC 0000 0000 0000 0000 0000 0000 uuuu uuuu Note: ²u² stands for unchanged ²x² stands for unknown ²-² stands for unimplemented Rev.--00 ---.--00 ---.--00 ---.--uu TM2C0 0000 0--.0000 ---.--00 ---.--00 ---.--01 ---.uuuu TMPC0 1001 --01 1001 --01 1001 --01 uuuu --uu TMPC1 ---.--uu PRM0 -0-0 0000 -0-0 0000 -0-0 0000 -u-u uuuu PRM1 000.uuuu PRM2 --00 0000 --00 0000 --00 0000 --uu uuuu TM1C0 0000 0000 0000 0000 0000 0000 uuuu uuuu TM1C1 0000 0000 0000 0000 0000 0000 uuuu uuuu TM1C2 0000 0000 0000 0000 0000 0000 uuuu uuuu TM1DL 0000 0000 0000 0000 0000 0000 uuuu uuuu TM1DH ---.--uu TM0AL 0000 0000 0000 0000 0000 0000 uuuu uuuu TM0AH ---.0000 ---.--00 ---.0000 000.0000 uuu.--uu TM1BL 0000 0000 0000 0000 0000 0000 uuuu uuuu TM1BH ---. 1110 000.

--11 ---. HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 · HT68F50 Register Reset RES or LVR WDT Time-out WDT Time-out Register (Power-on) Reset (Normal Operation) (IDLE) MP0 xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu MP1 xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu BP ---. 1110 000. 2009 .--11 ---.--11 ---.uuuu WDTC 0111 1010 0111 1010 0111 1010 uuuu uuuu TBC 0011 0111 0011 0111 0011 0111 uuuu uuuu INTC0 -000 0000 -000 0000 -000 0000 -uuu uuuu INTC1 0000 0000 0000 0000 0000 0000 uuuu uuuu INTC2 0000 0000 0000 0000 0000 0000 uuuu uuuu MFI0 0000 0000 0000 0000 0000 0000 uuuu uuuu MFI1 -000 -000 -000 -000 -000 -000 -uuu -uuu MFI2 0000 0000 0000 0000 0000 0000 uuuu uuuu MFI3 --00 --00 --00 --00 --00 --00 --uu --uu PAWU 0000 0000 0000 0000 0000 0000 uuuu uuuu PAPU 0000 0000 0000 0000 0000 0000 uuuu uuuu PA 1111 1111 1111 1111 1111 1111 uuuu uuuu PAC 1111 1111 1111 1111 1111 1111 uuuu uuuu PBPU 0000 0000 0000 0000 0000 0000 uuuu uuuu PB 1111 1111 1111 1111 1111 1111 uuuu uuuu PBC 1111 1111 1111 1111 1111 1111 uuuu uuuu PCPU 0000 0000 0000 0000 0000 0000 uuuu uuuu PC 1111 1111 1111 1111 1111 1111 uuuu uuuu PCC 1111 1111 1111 1111 1111 1111 uuuu uuuu PDPU 0000 0000 0000 0000 0000 0000 uuuu uuuu PD 1111 1111 1111 1111 1111 1111 uuuu uuuu PDC 1111 1111 1111 1111 1111 1111 uuuu uuuu PEPU 0000 0000 0000 0000 0000 0000 uuuu uuuu PE 1111 1111 1111 1111 1111 1111 uuuu uuuu PEC 1111 1111 1111 1111 1111 1111 uuuu uuuu PFPU ---. uuuu uuu- Rev.--uu CP0C 1000 0--1 1000 0--1 1000 0--1 uuuu u--u CP1C 1000 0--1 1000 0--1 1000 0--1 uuuu u--u SIMC0 1110 000.--uu ACC xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu PCL 0000 0000 0000 0000 0000 0000 0000 0000 TBLP xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu TBLH xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu TBHP ---x xxxx ---u uuuu ---u uuuu ---u uuuu STATUS --00 xxxx --uu uuuu --1u uuuu --11 uuuu SMOD 0000 0011 0000 0011 0000 0011 uuuu uuuu LVDC --00 -000 --00 -000 --00 -000 --uu -uuu INTEG ---.--00 ---. 1.--00 ---.--00 ---.--00 ---.--00 ---.0000 ---.0000 ---. 1110 000.00 54 November 3.0000 ---.--00 ---.--11 ---.--11 ---.--uu PF ---.--uu PFC ---.--11 ---.

0000 000.--00 ---. 2009 .--00 ---.0000 uuu.--uu EEA xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu EED xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu EEC ---.--uu TM2C0 0000 0--. uuuu u--- TM2C1 0000 0000 0000 0000 0000 0000 uuuu uuuu TM2DL 0000 0000 0000 0000 0000 0000 uuuu uuuu TM2DH 0000 0000 0000 0000 0000 0000 uuuu uuuu TM2AL 0000 0000 0000 0000 0000 0000 uuuu uuuu TM2AH 0000 0000 0000 0000 0000 0000 uuuu uuuu TM2RP 0000 0000 0000 0000 0000 0000 uuuu uuuu TM3C0 0000 0000 0000 0000 0000 0000 uuuu uuuu TM3C1 0000 0000 0000 0000 0000 0000 uuuu uuuu TM3DL 0000 0000 0000 0000 0000 0000 uuuu uuuu TM3DH ---.--00 ---.0000 ---.--00 ---.--00 ---.--00 ---.--00 ---.--00 ---. 0000 0--.--uu TM1AL 0000 0000 0000 0000 0000 0000 uuuu uuuu TM1AH ---.--00 ---.00 55 November 3. 0000 0--.--00 ---.--uu SCOMC 0000 0000 0000 0000 0000 0000 uuuu uuuu Note: ²u² stands for unchanged ²x² stands for unknown ²-² stands for unimplemented Rev.0000 ---.--00 ---. 1.--00 ---.--00 ---.0000 ---.--00 ---.--uu TM1BL 0000 0000 0000 0000 0000 0000 uuuu uuuu TM1BH ---.--00 ---. HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 Reset RES or LVR WDT Time-out WDT Time-out Register (Power-on) Reset (Normal Operation) (IDLE) SIMC1 1000 0001 1000 0001 1000 0001 uuuu uuuu SIMD xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu SIMA/SIMC2 0000 0000 0000 0000 0000 0000 uuuu uuuu TM0C0 0000 0000 0000 0000 0000 0000 uuuu uuuu TM0C1 0000 0000 0000 0000 0000 0000 uuuu uuuu TM0DL 0000 0000 0000 0000 0000 0000 uuuu uuuu TM0DH ---.uuuu PRM2 0000 0000 0000 0000 0000 0000 uuuu uuuu TM1C0 0000 0000 0000 0000 0000 0000 uuuu uuuu TM1C1 0000 0000 0000 0000 0000 0000 uuuu uuuu TM1C2 0000 0000 0000 0000 0000 0000 uuuu uuuu TM1DL 0000 0000 0000 0000 0000 0000 uuuu uuuu TM1DH ---.--00 ---.--00 ---.--uu TM0AL 0000 0000 0000 0000 0000 0000 uuuu uuuu TM0AH ---.--00 ---.uuuu TMPC0 1001 --01 1001 --01 1001 --01 uuuu --uu TMPC1 --01 --01 --01 --01 --01 --01 --uu --uu PRM0 -0-0 0000 -0-0 0000 -0-0 0000 -u-u uuuu PRM1 000.--00 ---.--uu TM3AL 0000 0000 0000 0000 0000 0000 uuuu uuuu TM3AH ---.--00 ---.--00 ---.0000 000.

0 0 0 --u.00 56 November 3.--00 0000 0000 0000 0000 uuuu uuuu PG ---..--11 ---.-uuu ACC xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu PCL 0000 0000 0000 0000 0000 0000 0000 0000 TBLP xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu TBLH xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu TBHP --xx xxxx --uu uuuu --uu uuuu --uu uuuu STATUS --00 xxxx --uu uuuu --1u uuuu --11 uuuu SMOD 0000 0011 0000 0011 0000 0011 uuuu uuuu LVDC --00 -000 --00 -000 --00 -000 --uu -uuu INTEG 0000 0000 0000 0000 0000 0000 uuuu uuuu WDTC 0111 1010 0111 1010 0111 1010 uuuu uuuu TBC 0011 0111 0011 0111 0011 0111 uuuu uuuu INTC0 -000 0000 -000 0000 -000 0000 -uuu uuuu INTC1 0000 0000 0000 0000 0000 0000 uuuu uuuu INTC2 0000 0000 0000 0000 0000 0000 uuuu uuuu INTC3 0000 0000 0000 0000 0000 0000 uuuu uuuu MFI0 0000 0000 0000 0000 0000 0000 uuuu uuuu MFI1 -000 -000 -000 -000 -000 -000 -uuu -uuu MFI2 0000 0000 0000 0000 0000 0000 uuuu uuuu MFI3 --00 --00 --00 --00 --00 --00 --uu --uu PAWU 0000 0000 0000 0000 0000 0000 uuuu uuuu PAPU 0000 0000 0000 0000 0000 0000 uuuu uuuu PA 1111 1111 1111 1111 1111 1111 uuuu uuuu PAC 1111 1111 1111 1111 1111 1111 uuuu uuuu PBPU 0000 0000 0000 0000 0000 0000 uuuu uuuu PB 1111 1111 1111 1111 1111 1111 uuuu uuuu PBC 1111 1111 1111 1111 1111 1111 uuuu uuuu PCPU 0000 0000 0000 0000 0000 0000 uuuu uuuu PC 1111 1111 1111 1111 1111 1111 uuuu uuuu PCC 1111 1111 1111 1111 1111 1111 uuuu uuuu PDPU 0000 0000 0000 0000 0000 0000 uuuu uuuu PD 1111 1111 1111 1111 1111 1111 uuuu uuuu PDC 1111 1111 1111 1111 1111 1111 uuuu uuuu PEPU 0000 0000 0000 0000 0000 0000 uuuu uuuu PE 1111 1111 1111 1111 1111 1111 uuuu uuuu PEC 1111 1111 1111 1111 1111 1111 uuuu uuuu PFPU 0000 0000 0000 0000 0000 0000 uuuu uuuu PF 1111 1111 1111 1111 1111 1111 uuuu uuuu PFC 1111 1111 1111 1111 1111 1111 uuuu uuuu PGPU ---..0.--11 ---.0 0 0 .--uu Rev.--11 ---..0 0 0 .--11 ---.0.. 1.--11 ---.--11 ---. HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 · HT68F60 Register Reset RES or LVR WDT Time-out WDT Time-out Register (Power-on) Reset (Normal Operation) (IDLE) MP0 xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu MP1 xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu BP ..0. 2009 ..--uu PGC ---.

uuuu u--- TM2C1 0000 0000 0000 0000 0000 0000 uuuu uuuu TM2DL 0000 0000 0000 0000 0000 0000 uuuu uuuu TM2DH 0000 0000 0000 0000 0000 0000 uuuu uuuu TM2AL 0000 0000 0000 0000 0000 0000 uuuu uuuu TM2AH 0000 0000 0000 0000 0000 0000 uuuu uuuu TM2RP 0000 0000 0000 0000 0000 0000 uuuu uuuu TM3C0 0000 0000 0000 0000 0000 0000 uuuu uuuu TM3C1 0000 0000 0000 0000 0000 0000 uuuu uuuu TM3DL 0000 0000 0000 0000 0000 0000 uuuu uuuu TM3DH ---. uuuu uuu- SIMC1 1000 0001 1000 0001 1000 0001 uuuu uuuu SIMD xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu SIMA/SIMC2 0000 0000 0000 0000 0000 0000 uuuu uuuu TM0C0 0000 0000 0000 0000 0000 0000 uuuu uuuu TM0C1 0000 0000 0000 0000 0000 0000 uuuu uuuu TM0DL 0000 0000 0000 0000 0000 0000 uuuu uuuu TM0DH ---.--uu TM0AL 0000 0000 0000 0000 0000 0000 uuuu uuuu TM0AH ---.--00 ---.--00 ---. 1.--00 ---.--00 ---.--uu TM2C0 0000 0--. 2009 .--00 ---.--uu TM1AL 0000 0000 0000 0000 0000 0000 uuuu uuuu TM1AH ---.--00 ---.--00 ---. 0000 0--.uuuu TMPC0 1001 --01 1001 --01 1001 --01 uuuu --uu TMPC1 --01 --01 --01 --01 --01 --01 --uu --uu PRM0 0000 0000 0000 0000 0000 0000 uuuu uuuu PRM1 0000 0000 0000 0000 0000 0000 uuuu uuuu PRM2 0000 0000 0000 0000 0000 0000 uuuu uuuu TM1C0 0000 0000 0000 0000 0000 0000 uuuu uuuu TM1C1 0000 0000 0000 0000 0000 0000 uuuu uuuu TM1C2 0000 0000 0000 0000 0000 0000 uuuu uuuu TM1DL 0000 0000 0000 0000 0000 0000 uuuu uuuu TM1DH ---.--00 ---.--00 ---.--00 ---.0000 ---.--00 ---.--00 ---. 1110 000.--00 ---.00 57 November 3.--uu SCOMC 0000 0000 0000 0000 0000 0000 uuuu uuuu Note: ²u² stands for unchanged ²x² stands for unknown ²-² stands for unimplemented Rev.--00 ---.--uu EEA xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu EED xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu EEC ---.--00 ---.--00 ---.--00 ---.--uu TM1BL 0000 0000 0000 0000 0000 0000 uuuu uuuu TM1BH ---.--00 ---.0000 ---.--uu TM3AL 0000 0000 0000 0000 0000 0000 uuuu uuuu TM3AH ---.--00 ---. 1110 000.--00 ---.--00 ---. 0000 0--. HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 Reset RES or LVR WDT Time-out WDT Time-out Register (Power-on) Reset (Normal Operation) (IDLE) CP0C 1000 0--1 1000 0--1 1000 0--1 uuuu u--u CP1C 1000 0--1 1000 0--1 1000 0--1 uuuu u--u SIMC0 1110 000.0000 ---.

[m]². For input operation. pull-high selections for all ports and wake-up selections on certain pins. These I/O ports are mapped to the RAM Data Memory with specific addresses as shown in the Special Purpose Data Memory table. which means the inputs must be ready at the T2 rising edge of instruction ²MOV A. · I/O Register List ¨ HT68F20 Register Bit Name 7 6 5 4 3 2 1 0 PAWU D7 D6 D5 D4 D3 D2 D1 D0 PAPU D7 D6 D5 D4 D3 D2 D1 D0 PA D7 D6 D5 D4 D3 D2 D1 D0 PAC D7 D6 D5 D4 D3 D2 D1 D0 PBPU ¾ ¾ D5 D4 D3 D2 D1 D0 PB ¾ ¾ D5 D4 D3 D2 D1 D0 PBC ¾ ¾ D5 D4 D3 D2 D1 D0 PCPU ¾ ¾ ¾ ¾ D3 D2 D1 D0 PC ¾ ¾ ¾ ¾ D3 D2 D1 D0 PCC ¾ ¾ ¾ ¾ D3 D2 D1 D0 ¨ HT68F30 Register Bit Name 7 6 5 4 3 2 1 0 PAWU D7 D6 D5 D4 D3 D2 D1 D0 PAPU D7 D6 D5 D4 D3 D2 D1 D0 PA D7 D6 D5 D4 D3 D2 D1 D0 PAC D7 D6 D5 D4 D3 D2 D1 D0 PBPU ¾ ¾ D5 D4 D3 D2 D1 D0 PB ¾ ¾ D5 D4 D3 D2 D1 D0 PBC ¾ ¾ D5 D4 D3 D2 D1 D0 PCPU D7 D6 D5 D4 D3 D2 D1 D0 PC D7 D6 D5 D4 D3 D2 D1 D0 PCC D7 D6 D5 D4 D3 D2 D1 D0 Rev. 1. 2009 . where m denotes the port address. HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 Input/Output Ports Holtek microcontrollers offer considerable flexibility on their I/O ports. The device provides bidirectional input/output lines labeled with port names PA~PG. the user is provided with an I/O structure to meet the needs of a wide range of application possibilities. all the data is latched and remains unchanged until the output latch is rewritten. For output opera- tion.00 58 November 3. these ports are non-latching. With the input or output designation of every pin fully under user program control. All of these I/O ports can be used for input and output operations.

HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 ¨ HT68F40/HT68F50 Register Bit Name 7 6 5 4 3 2 1 0 PAWU D7 D6 D5 D4 D3 D2 D1 D0 PAPU D7 D6 D5 D4 D3 D2 D1 D0 PA D7 D6 D5 D4 D3 D2 D1 D0 PAC D7 D6 D5 D4 D3 D2 D1 D0 PBPU D7 D6 D5 D4 D3 D2 D1 D0 PB D7 D6 D5 D4 D3 D2 D1 D0 PBC D7 D6 D5 D4 D3 D2 D1 D0 PCPU D7 D6 D5 D4 D3 D2 D1 D0 PC D7 D6 D5 D4 D3 D2 D1 D0 PCC D7 D6 D5 D4 D3 D2 D1 D0 PDPU D7 D6 D5 D4 D3 D2 D1 D0 PD D7 D6 D5 D4 D3 D2 D1 D0 PDC D7 D6 D5 D4 D3 D2 D1 D0 PEPU D7 D6 D5 D4 D3 D2 D1 D0 PE D7 D6 D5 D4 D3 D2 D1 D0 PEC D7 D6 D5 D4 D3 D2 D1 D0 PFPU ¾ ¾ ¾ ¾ ¾ ¾ D1 D0 PF ¾ ¾ ¾ ¾ ¾ ¾ D1 D0 PFC ¾ ¾ ¾ ¾ ¾ ¾ D1 D0 Rev. 1. 2009 .00 59 November 3.

2009 .00 60 November 3. 1. HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 ¨ HT68F60 Register Bit Name 7 6 5 4 3 2 1 0 PAWU D7 D6 D5 D4 D3 D2 D1 D0 PAPU D7 D6 D5 D4 D3 D2 D1 D0 PA D7 D6 D5 D4 D3 D2 D1 D0 PAC D7 D6 D5 D4 D3 D2 D1 D0 PBPU D7 D6 D5 D4 D3 D2 D1 D0 PB D7 D6 D5 D4 D3 D2 D1 D0 PBC D7 D6 D5 D4 D3 D2 D1 D0 PCPU D7 D6 D5 D4 D3 D2 D1 D0 PC D7 D6 D5 D4 D3 D2 D1 D0 PCC D7 D6 D5 D4 D3 D2 D1 D0 PDPU D7 D6 D5 D4 D3 D2 D1 D0 PD D7 D6 D5 D4 D3 D2 D1 D0 PDC D7 D6 D5 D4 D3 D2 D1 D0 PEPU D7 D6 D5 D4 D3 D2 D1 D0 PE D7 D6 D5 D4 D3 D2 D1 D0 PEC D7 D6 D5 D4 D3 D2 D1 D0 PFPU D7 D6 D5 D4 D3 D2 D1 D0 PF D7 D6 D5 D4 D3 D2 D1 D0 PFC D7 D6 D5 D4 D3 D2 D1 D0 PGPU ¾ ¾ ¾ ¾ ¾ ¾ D1 D0 PG ¾ ¾ ¾ ¾ ¾ ¾ D1 D0 PGC ¾ ¾ ¾ ¾ ¾ ¾ D1 D0 Rev.

when configured as an input have the capability of being connected to an internal pull-high resistor. 1.00 61 November 3. To eliminate the need for these external resistors. all I/O pins. These pull-high resistors are selected using registers PAPU~PGPU. HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 Pull-high Resistors Many product applications require pull-high resistors for their switch inputs usually requiring the use of an external re- sistor. 2009 . and are implemented using weak PMOS transistors. · PAPU Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 · PBPU Register ¨ HT68F40/HT68F50/HT68F60 Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 · PCPU Register ¨ HT68F30/HT68F40/HT68F50/HT68F60 Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 · PDPU Register ¨ HT68F40/HT68F50/HT68F60 Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 · PEPU Register ¨ HT68F40/HT68F50/HT68F60 Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Rev.

read as ²0² Bit 5~0 PBPU: Port B bit 5 ~ bit 0 Pull-High Control 0: Disable 1: Enable · PCPU Register ¨ HT68F20 Bit 7 6 5 4 3 2 1 0 Name ¾ ¾ ¾ ¾ D3 D2 D1 D0 R/W ¾ ¾ ¾ ¾ R/W R/W R/W R/W POR ¾ ¾ ¾ ¾ 0 0 0 0 Bit 7~4 ²¾² Unimplemented. 1. 2009 .00 62 November 3. read as ²0² Bit 1~0 PFPU: Port F bit 1 ~ bit 0 Pull-High Control 0: Disable 1: Enable Rev. read as ²0² Bit 3~0 PCPU: Port C bit 3 ~ bit 0 Pull-High Control 0: Disable 1: Enable · PFPU Register ¨ HT68F40/HT68F50 Bit 7 6 5 4 3 2 1 0 Name ¾ ¾ ¾ ¾ ¾ ¾ D1 D0 R/W ¾ ¾ ¾ ¾ ¾ ¾ R/W R/W POR ¾ ¾ ¾ ¾ ¾ ¾ 0 0 Bit 7~2 ²¾² Unimplemented. HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 · PFPU Register ¨ HT68F60 Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0 I/O Port bit 7 ~ bit 0 Pull-High Control 0: Disable 1: Enable · PBPU Register ¨ HT68F20/HT68F30 Bit 7 6 5 4 3 2 1 0 Name ¾ ¾ D5 D4 D3 D2 D1 D0 R/W ¾ ¾ R/W R/W R/W R/W R/W R/W POR ¾ ¾ 0 0 0 0 0 0 Bit 7~6 ²¾² Unimplemented.

1. · PAWU Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0 PAWU: Port A bit 7 ~ bit 0 Wake-up Control 0: Disable 1: Enable I/O Port Control Registers Each I/O port has its own control register known as PAC~PGC.00 63 November 3. With this con- trol register. Each pin of the I/O ports is directly mapped to a bit in its associated port control register. a feature that is important for battery and other low-power applications. Various methods exist to wake-up the microcontroller. 2009 . instructions can still be used to read the output register. to control the input/output configuration. the corre- sponding bit of the control register must be written as a ²1². read as ²0² Bit 1~0 PGPU: Port G bit 1 ~ bit 0 Pull-High Control 0: Disable 1: Enable Port A Wake-up The HALT instruction forces the microcontroller into the SLEEP or IDLE Mode which preserves power. This will then allow the logic state of the input pin to be di- rectly read by instructions. · PAC Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 1 1 1 1 1 1 1 1 · PBC Register ¨ HT68F40/HT68F50/HT68F60 Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 1 1 1 1 1 1 1 1 Rev. However. If the pin is currently setup as an output. the I/O pin will be setup as a CMOS output. When the corresponding bit of the control register is written as a ²0². one of which is to change the logic condition on one of the Port A pins from high to low. For the I/O pin to function as an input. Each pin on Port A can be selected individually to have this wake-up feature using the PAWU register. HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 · PGPU Register ¨ HT68F60 Bit 7 6 5 4 3 2 1 0 Name ¾ ¾ ¾ ¾ ¾ ¾ D1 D0 R/W ¾ ¾ ¾ ¾ ¾ ¾ R/W R/W POR ¾ ¾ ¾ ¾ ¾ ¾ 0 0 Bit 7~2 ²¾² Unimplemented. it should be noted that the program will in fact only read the status of the output data latch and not the actual logic status of the output pin. each CMOS output or input can be reconfigured dynamically under software control. This function is especially suitable for applications that can be woken up via external switches.

2009 .00 64 November 3. HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 · PCC Register ¨ HT68F30/HT68F40/HT68F50/HT68F60 Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 1 1 1 1 1 1 1 1 · PDC Register ¨ HT68F40/HT68F50/HT68F60 Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 1 1 1 1 1 1 1 1 · PEC Register ¨ HT68F40/HT68F50/HT68F60 Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 1 1 1 1 1 1 1 1 · PFC Register ¨ HT68F60 Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 1 1 1 1 1 1 1 1 Bit 7~0 I/O Port bit 7 ~ bit 0 Input/Output Control 0: Output 1: Input · PBC Register ¨ HT68F20/HT68F30 Bit 7 6 5 4 3 2 1 0 Name ¾ ¾ D5 D4 D3 D2 D1 D0 R/W ¾ ¾ R/W R/W R/W R/W R/W R/W POR ¾ ¾ 0 0 0 0 0 0 Bit 7~6 ²¾² Unimplemented. read as ²0² Bit 5~0 PBC: Port B bit 5 ~ bit 0 Input/Output Control 0: Output 1: Input Rev. 1.

read as ²0² Bit 3~0 PCC: Port C bit 3 ~ bit 0 Input/Output Control 0: Output 1: Input · PFC Register ¨ HT68F40/HT68F50 Bit 7 6 5 4 3 2 1 0 Name ¾ ¾ ¾ ¾ ¾ ¾ D1 D0 R/W ¾ ¾ ¾ ¾ ¾ ¾ R/W R/W POR ¾ ¾ ¾ ¾ ¾ ¾ 0 0 Bit 7~2 ²¾² Unimplemented. 2009 . read as ²0² Bit 1~0 PFC: Port F bit 1 ~ bit 0 Input/Output Control 0: Output 1: Input · PGC Register ¨ HT68F60 Bit 7 6 5 4 3 2 1 0 Name ¾ ¾ ¾ ¾ ¾ ¾ D1 D0 R/W ¾ ¾ ¾ ¾ ¾ ¾ R/W R/W POR ¾ ¾ ¾ ¾ ¾ ¾ 0 0 Bit 7~2 ²¾² Unimplemented.00 65 November 3. HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 · PCC Register ¨ HT68F20 Bit 7 6 5 4 3 2 1 0 Name ¾ ¾ ¾ ¾ D3 D2 D1 D0 R/W ¾ ¾ ¾ ¾ R/W R/W R/W R/W POR ¾ ¾ ¾ ¾ 0 0 0 0 Bit 7~4 ²¾² Unimplemented. 1. read as ²0² Bit 1~0 PGC: Port G bit 1 ~ bit 0 Input/Output Control 0: Output 1: Input Rev.

1. Some de- vices include PRM0. a wide range of different functions can be incorporated into even relatively small package sizes. HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 Pin-remapping Functions The flexibility of the microcontroller range is greatly enhanced by the use of pins that have more than one function. The way in which the pin function of each pin is selected is different for each function and a priority order is established where more than one pin function is selected simultaneously. Limited numbers of pins can force serious design constraints on designers but by supplying pins with multi-functions. many of these difficulties can be overcome. 2009 . Additionally there are a series of PRM0. PRM1 or PRM2 registers which can select the functions of certain pins. PRM1 and PRM2 registers to establish certain pin functions. · Pin-remapping Register List ¨ HT68F30 Register Bit Name 7 6 5 4 3 2 1 0 PRM0 ¾ ¾ ¾ ¾ ¾ PCPRM SIMPS0 PCKPS ¨ HT68F40 Register Bit Name 7 6 5 4 3 2 1 0 PRM0 ¾ C1XPS0 ¾ C0XPS0 PDPRM SIMPS1 SIMPS0 PCKPS PRM1 TCK2PS TCK1PS TCK0PS ¾ INT1PS1 INT1PS0 INT0PS1 INT0PS0 PRM2 ¾ ¾ TP21PS TP20PS TP1B2PS TP1APS TP01PS TP00PS ¨ HT68F50 Register Bit Name 7 6 5 4 3 2 1 0 PRM0 ¾ C1XPS0 ¾ C0XPS0 PDPRM SIMPS1 SIMPS0 PCKPS PRM1 TCK2PS TCK1PS TCK0PS ¾ INT1PS1 INT1PS0 INT0PS1 INT0PS0 PRM2 TP31PS TP30PS TP21PS TP20PS TP1B2PS TP1APS TP01PS TP00PS ¨ HT68F60 Register Bit Name 7 6 5 4 3 2 1 0 PRM0 C1XPS1 C1XPS0 C0XPS1 C0XPS0 PDPRM SIMPS1 SIMPS0 PCKPS PRM1 TCK2PS TCK1PS TCK0PS INT2PS1 INT1PS1 INT1PS0 INT0PS1 INT0PS0 PRM2 TP31PS TP30PS TP21PS TP20PS TP1B2PS TP1APS TP01PS TP00PS Rev. However by allowing the same pins to share several different functions and providing a means of function selection. Pin-remapping Registers The limited number of supplied pins in a package can impose restrictions on the amount of functions a certain device can contain.00 66 November 3.

SDI/SDA on PC0. PINT on PC4 · PRM0 Register ¨ HT68F40/HT68F50 Bit 7 6 5 4 3 2 1 0 Name ¾ C1XPS0 ¾ C0XPS0 PDPRM SIMPS1 SIMPS0 PCKPS R/W ¾ R/W ¾ R/W R/W R/W R/W R/W POR ¾ 0 ¾ 0 0 0 0 0 Bit 7 ²¾² Unimplemented. TCK1 on PD3 change to PD7 if SIMPS1. TP2_0 on PD1 change to PB7. PINT on PC3 1: PCK on PC5. 2009 . read as ²0² Bit 6 C1XPS0: C1X Pin Remapping Control 0: C1X on PA5 1: C1X on PF1 Bit 5 ²¾² Unimplemented. SCS on PD0 10: SDO on PB6. SCS on PC6 Bit 0 PCKPS: PCK and PINT Pin Remapping Control 0: PCK on PC2. SDI/SDA on PA6. SCK/SCL on PA7. read as ²0² Bit 2 PCPRM: PC1~PC0 pin-shared function Pin Remapping Control 0: No change 1: TP1B_0 on PC0 change to PA6. PINT on PC3 1: PCK on PC5. read as ²0² Bit 4 C0XPS0: C0X Pin Remapping Control 0: C0X on PA0 1: C0X on PF0 Bit 3 PDPRM: PD3~PD0 pin-shared function Pin Remapping Control 0: No change 1: TCK2 on PD0 change to PB6. SDI/SDA on PA6. SIMPS0: SIM Pin Remapping Control 00: SDO on PA5. 1. SDI/SDA on PB7.00 67 November 3. HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 · PRM0 Register ¨ HT68F30 Bit 7 6 5 4 3 2 1 0 Name ¾ ¾ ¾ ¾ ¾ PCPRM SIMPS0 PCKPS R/W ¾ ¾ ¾ ¾ ¾ R/W R/W R/W POR ¾ ¾ ¾ ¾ ¾ 0 0 0 Bit 7~3 ²¾² Unimplemented. SCK/SCL on PC7. TCK0 on PD2 change to PD6. TP1B_1 on PC1 change to PA7 if SIMPS0=1 Bit 1 SIMPS0: SIM Pin Remapping Control 0: SDO on PA5. SCK/SCL on PA7. SDI/SDA on PD2. SCK/SCL on PD6. SCS on PB5 01: SDO on PD3. SIMPS0=01 Bit 2~1 SIMPS1. PINT on PC4 Rev. SCS on PD7 11: Undefined Bit 0 PCKPS: PCK and PINT Pin Remapping Control 0: PCK on PC2. SCS on PB5 1: SDO on PC1. SCK/SCL on PD1.

SCS on PD0 Bit 0 PCKPS: PCK and PINT Pin Remapping Control 0: PCK on PC2. TCK0 on PD2 change to PD6. HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 · PRM0 Register ¨ HT68F60 Bit 7 6 5 4 3 2 1 0 Name C1XPS1 C1XPS0 C0XPS1 C0XPS0 PDPRM SIMPS1 SIMPS0 PCKPS R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~6 C1XPS1. SIMPS0=01 or 11 Bit 2~1 SIMPS1. SCS on PD0 10: SDO on PB6. SCK/SCL on PD6. SCK/SCL on PD1. C1XPS0: C1X Pin Remapping Control 00: C1X on PA5 01: C1X on PF1 10: C1X on PG1 11: Undefined Bit 5~4 C0XPS1.00 68 November 3. SDI/SDA on PD2. PINT on PC4 · PRM1 Register ¨ HT68F40/HT68F50 Bit 7 6 5 4 3 2 1 0 Name TCK2PS TCK1PS TCK0PS ¾ INT1PS1 INT1PS0 INT0PS1 INT0PS0 R/W R/W R/W R/W ¾ R/W R/W R/W R/W POR 0 0 0 ¾ 0 0 0 0 Bit 7 TCK2PS: TCK2 Pin Remapping Control 0: TCK2 on PC2 1: TCK2 on PD0 Bit 6 TCK1PS: TCK1 Pin Remapping Control 0: TCK1 on PA4 1: TCK1 on PD3 Bit 5 TCK0PS: TCK0 Pin Remapping Control 0: TCK0 on PA2 1: TCK0 on PD2 Bit 4 ²¾² Unimplemented. read as ²0² Bit 3~2 INT1PS1. SDI/SDA on PB7. PINT on PC3 1: PCK on PC5. TP2_0 on PD1 change to PB7. TCK1 on PD3 change to PD7 if SIMPS1. SDI/SDA on PA6. C0XPS0: C0X Pin Remapping Control 00: C0X on PA0 01: C0X on PF0 10: C0X on PG0 11: Undefined Bit 3 PDPRM: PD3~PD0 pin-shared function Pin Remapping Control 0: No change 1: TCK2 on PD0 change to PB6. SCS on PD7 11: SDO on PD1. SIMPS0: SIM Pin Remapping Control 00: SDO on PA5. SCK/SCL on PD3. 2009 . INT0PS0: INT0 Pin Remapping Control 00: INT0 on PA3 01: INT0 on PC4 10: Undefined 11: INT0 on PE6 Rev. SCS on PB5 01: SDO on PD3. SDI/SDA on PD2. SCK/SCL on PA7. 1. INT1PS0: INT1 Pin Remapping Control 00: INT1 on PA4 01: INT1 on PC5 10: Undefined 11: INT1 on PE7 Bit 1~0 INT0PS1.

1. read as ²0² Bit 5 TP21PS: TP2_1 Pin Remapping Control 0: TP2_1 on PC4 1: TP2_1 on PD4 Bit 4 TP20PS: TP2_0 Pin Remapping Control 0: TP2_0 on PC3 1: TP2_0 on PD1 Bit 3 TP1B2PS: TP1B_2 Pin Remapping Control 0: TP1B_2 on PC5 1: TP1B_2 on PE4 Bit 2 TP1APS: TP1A Pin Remapping Control 0: TP1A on PA1 1: TP1A on PC7 Bit 1 TP01PS: TP0_1 Pin Remapping Control 0: TP0_1 on PC5 1: TP0_1 on PD5 Bit 0 TP00PS: TP0_0 Pin Remapping Control 0: TP0_0 on PA0 1: TP0_0 on PC6 Rev. 2009 .00 69 November 3. INT0PS0: INT0 Pin Remapping Control 00: INT0 on PA3 01: INT0 on PC4 10: INT0 on PE0 11: INT0 on PE6 · PRM2 Register ¨ HT68F40 Bit 7 6 5 4 3 2 1 0 Name ¾ ¾ TP21PS TP20PS TP1B2PS TP1APS TP01PS TP00PS R/W ¾ ¾ R/W R/W R/W R/W R/W R/W POR ¾ ¾ 0 0 0 0 0 0 Bit 7~6 ²¾² Unimplemented. HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 · PRM1 Register ¨ HT68F60 Bit 7 6 5 4 3 2 1 0 Name TCK2PS TCK1PS TCK0PS INT2PS INT1PS1 INT1PS0 INT0PS1 INT0PS0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7 TCK2PS: TCK2 Pin Remapping Control 0: TCK2 on PC2 1: TCK2 on PD0 Bit 6 TCK1PS: TCK1 Pin Remapping Control 0: TCK1 on PA4 1: TCK1 on PD3 Bit 5 TCK0PS: TCK0 Pin Remapping Control 0: TCK0 on PA2 1: TCK0 on PD2 Bit 4 INT2PS: INT2 Pin Remapping Control 0: INT2 on PC4 1: INT2 on PE2 Bit 3~2 INT1PS1. INT1PS0: INT1 Pin Remapping Control 00: INT1 on PA4 01: INT1 on PC5 10: INT1 on PE1 11: INT1 on PE7 Bit 1~0 INT0PS1.

2009 . HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 · PRM2 Register ¨ HT68F50/HT68F60 Bit 7 6 5 4 3 2 1 0 Name TP31PS TP30PS TP21PS TP20PS TP1B2PS TP1APS TP01PS TP00PS R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7 TP31PS: TP3_1 Pin Remapping Control 0: TP3_1 on PD0 1: TP3_1 on PE3 Bit 6 TP30PS: TP3_0 Pin Remapping Control 0: TP3_0 on PD3 1: TP3_0 on PE5 Bit 5 TP21PS: TP2_1 Pin Remapping Control 0: TP2_1 on PC4 1: TP2_1 on PD4 Bit 4 TP20PS: TP2_0 Pin Remapping Control 0: TP2_0 on PC3 1: TP2_0 on PD1 Bit 3 TP1B2PS: TP1B_2 Pin Remapping Control 0: TP1B_2 on PC5 1: TP1B_2 on PE4 Bit 2 TP1APS: TP1A Pin Remapping Control 0: TP1A on PA1 1: TP1A on PC7 Bit 1 TP01PS: TP0_1 Pin Remapping Control 0: TP0_1 on PC5 1: TP0_1 on PD5 Bit 0 TP00PS: TP0_0 Pin Remapping Control 0: TP0_0 on PA0 1: TP0_0 on PC6 Rev.00 70 November 3. 1.

1.u p S e le c t Generic Input/Output Structure Rev. One of these is a high to low transition of any of the that all I/O pins will default to an input state.u p W r ite C o n tr o l R e g is te r C K Q C h ip R e s e t S I/O p in R e a d C o n tr o l R e g is te r D a ta B it D Q W r ite D a ta R e g is te r C K Q S M U R e a d D a ta R e g is te r X S y s te m W a k e -u p P A o n ly W a k e . modify it to the required new types to be shown.i² instructions. Note that when using drawings.i² and ²CLR [m]. one of the first things to con. PAC~PGC. are then programmed to setup some pins as outputs. bit values and then rewrite this data back to the output ports. these output pins will have an initial high output value unless the associated port data registers.H ig h V D D R e g is te r C o n tr o l B it S e le c t W e a k D a ta B u s D Q P u ll. After a reset. all of the I/O data Mode. The microcontroller must first read in wide range of pin-shared structures does not permit all the data on the entire port. The tion takes place. Programming Considerations Port A has the additional capability of providing wake-up Within the user program. When the device is in the SLEEP or IDLE sider is port initialisation. As the exact individual bits in the port control register using the ²SET logical construction of the I/O pin will differ from these [m]. a read-modify-write opera- with the functional understanding of the I/O pins. Single or multiple pins on Port A can be which depends on the other connected circuitry and setup to have this function. whether pull-high selections have been chosen. the level of Port A pins. they are supplied as a guide only to assist these bit control instructions. 2009 . PA~PG. HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 I/O Pin Structures be achieved byte-wide by loading the correct values into The accompanying diagrams illustrate the internal the appropriate port control register or by programming structures of some generic I/O pin types. This means up. If the port control registers.00 71 November 3. are first programmed. various methods are available to wake the device and port control registers will be set high. Se- lecting which pins are inputs and which are outputs can P u ll. functions.

Each indi- name TM. The addition of input and out- TMs will be described in this section.1. TM1. In- Compact Type TM. To implement time related functions each de- upon which device is selected with each TM having a vice includes several Timer Modules. Function CTM STM ETM Timer/Counter Ö Ö Ö I/P Capture ¾ Ö Ö Compare Match Output Ö Ö Ö PWM Channels 1 1 2 Single Pulse Output ¾ 1 1 PWM Alignment Edge Edge Edge & Centre PWM Adjustment Period & Duty Duty or Period Duty or Period Duty or Period TM Function Summary Each device in the series contains a specific number of either Compact Type. Compare Match Output and Single Pulse Type TM. TM0~TM3. TM2 and TM3. HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 Timer Modules . The common fea- ation of PWM signals. the detailed opera- put pins for each TM ensures that users are provided tion regarding each of the TM types will be described in with timing units with a wide and flexible range of fea- separate sections. Each of the TMs has either two or tures to all of the Compact. Although similar in nature. abbreviated to the reference name of TM0. Standard Type and Enhanced Type TM units which are shown in the table together with their individual reference name. scribed here with more detailed information provided in the individual Compact. namely serve to provide operations such as Timer/Counter. accompanying table. 2009 .00 72 November 3. The TMs are multi-purpose timing units and vidual TM can be categorised as a certain type. Standard and Enhanced TM sections.TM One of the most fundamental functions in any Introduction microcontroller device is the ability to control and mea- The devices contain from two to four TMs depending sure time. between the three types of TMs are summarised in the The common features of the different TM types are de. Standard and Enhanced three individual interrupts. Device TM0 TM1 TM2 TM3 HT68F20 10-bit CTM 10-bit STM ¾ ¾ HT68F30 10-bit CTM 10-bit ETM ¾ ¾ HT68F40 10-bit CTM 10-bit ETM 16-bit STM ¾ HT68F50 10-bit CTM 10-bit ETM 16-bit STM 10-bit CTM HT68F60 10-bit CTM 10-bit ETM 16-bit STM 10-bit CTM TM Name/Type Reference Rev. the different TM Output as well as being the functional unit for the gener- types vary in their feature complexity. Standard Type TM or Enhanced put Capture. The main features and differences tures.

the fTBC clock source or to a high or low level or to toggle when a compare match the external TCKn pin. drive the internal TM. The TM input pin. TP1B_2 TM Output Pins Rev. HT68F30 TP0_0. HT68F50 TP2_0. HT68F40 TP0_0. one for each of the internal comparator tails are provided in the accompanying table. The TCKn pin clock As the TM output pins are pin-shared with other func- source is used to allow an external signal to drive the TM tion. TP0_1 TP2_0. The clock source which drives the main counter in each The TM input pin can be chosen to have either a rising or TM can originate from various sources. which generate a TM interrupt when a compare match condition occurs. TP1B_0. The bel TPn. in effect dis. pre-programmed internal comparators. the de- ternal interrupts. HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 TM Operation type TM has three internal comparators and comparator The three different types of TM offer a diverse range of A or comparator B or comparator P compare match functions. TP3_1 TP1B_1. registers. TP0_1 TP1A. irrespective of what type. The selection of falling active edge. TP2_1 TMPC0. TMPC1 TP3_0. When the TM is in the Compare Match Output clock source can be a ratio of either the system clock Mode. The key to understanding how the TM oper. connecting the TM clock source. has one TM match situation. When the free TM External Pins ru n n in g c ount er h a s t he s a m e v al u e a s t h e pre-programmed comparator. TP1B_0. A single bit in one of the registers determines if its associated pin is to be used as an external TM output TM Interrupts pin or if it is to have another function. these pins can be controlled by the TM to switch fSYS or the internal high clock fH. When a TM interrupt is generated it can be used to clear ates is to see it in terms of a free running counter whose the counter and also to change the state of the TM out- v a lu e is t h e n c o m p a r ed w i t h t h e v a l u e o f put pin. is es- which can clear the counter and perhaps also change sentially a clock source for the TM and is selected using the condition of the TM output pin. with the label TCKn.1. the TM output function must first be setup using as an external clock source or for event counting.00 73 November 3. TP2_1 TMPC0. TP3_1 TP1B_1. This ex- counter is driven by a user selectable clock source. TP1B_2 TP0_0. TP1B_0. TP1B_2 TP0_0. Note that setting these bits to the situation occurs. from simple timing operations to PWM signal functions. TP0_1 ¾ TMPC0 TP1B_1 TP1A. put pins for each TM type and device is different. ternal TM input pin allows an external clock source to which can be an internal clock or an external pin. it consequently has three internal interrupts. TMPC1 TP3_0. The external TPn output pin is also the value 101 will select a reserved clock input. TMPC1 TP1B_1. As the Enhanced Device CTM STM ETM Registers HT68F20 TP0_0 TP1_0. A or comparator P. HT68F60 TP2_0. TP2_1 TMPC0. generation. The internal TM the TnCK2~TnCK0 bits in the TMnC0 register. TP1B_0. a TM interrupt signal will be generated input pin. known as a compare Each of the TMs. TP1_1 ¾ TMPC0 TP1A. This external TM input pin is shared with other functions but will be connected to the TM Clock Source internal TM if selected using the TnCK2~TnCK0 bits. the required clock source is implemented using the The TMs each have one or more output pins with the la- TnCK2~TnCK0 bits in the TM control registers. The number of out- The Compact and Standard type TMs each have two in. TP0_1 TP1A. 2009 . pin where the TM generates the PWM output waveform.

1. 2009 . if reset to zero the pin will retain its original other function. is implemented using one or two reg- isters. Setting the bit high will setup the corre- sponding pin as a TM input/output. HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 TM Input/Output Pin Control Registers Selecting to have a TM input/output or whether to retain its other shared function.00 74 November 3. Bit Registers Device 7 6 5 4 3 2 1 0 TMPC0 HT68F20 ¾ ¾ T1CP1 T1CP0 ¾ ¾ ¾ T0CP0 TMPC0 HT68F30 T1ACP0 ¾ T1BCP1 T1BCP0 ¾ ¾ T0CP1 T0CP0 HT68F40 TMPC0 HT68F50 T1ACP0 T1BCP2 T1BCP1 T1BCP0 ¾ ¾ T0CP1 T0CP0 HT68F60 TMPC1 HT68F40 ¾ ¾ ¾ ¾ ¾ ¾ T2CP1 T2CP0 HT68F50 TMPC1 ¾ ¾ T3CP1 T3CP0 ¾ ¾ T2CP1 T2CP0 HT68F60 TM Input/Output Pin Control Registers List P A 0 O u tp u t F u n c tio n 0 P A 0 /T P 0 _ 0 1 O u tp u t T 0 C P 0 T M 0 (C T M ) T C K In p u t P A 2 /T C K 0 P A 1 O u tp u t F u n c tio n 0 P A 1 /T P 1 _ 0 1 0 1 T 1 C P 0 P A 1 P C 0 O u tp u t F u n c tio n 0 P C 0 /T P 1 _ 1 O u tp u t 1 0 1 T 1 C P 1 P C 0 1 C a p tu re In p u t 0 T M 1 (S T M ) T 1 C P 1 1 0 T 1 C P 0 T C K In p u t P A 4 /T C K 1 HT68F20 TM Function Pin Control Block Diagram Rev. with a single bit in each register corresponding to a TM input/output pin.

HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 P A 0 O u tp u t F u n c tio n 0 P A 0 /T P 0 _ 0 1 0 1 T 0 C P 0 P A 0 P C 5 O u tp u t F u n c tio n 0 P C 5 /T P 0 _ 1 O u tp u t 1 0 1 T M 0 T 0 C P 1 (C T M ) P C 5 T C K In p u t P A 2 /T C K 0 P A 1 O u tp u t F u n c tio n 0 P A 1 /T P 1 A 1 C C R A O u tp u t T 1 A C P 0 C C R A C a p tu re In p u t 1 0 T 1 A C P 0 P C 0 O u tp u t F u n c tio n 0 P C 0 /T P 1 B _ 0 1 0 1 T 1 B C P 0 P C 0 T M 1 (E T M ) P C 1 O u tp u t F u n c tio n 0 P C 1 /T P 1 B _ 1 C C R B O u tp u t 1 0 1 T 1 B C P 1 P C 1 1 C C R B C a p tu re In p u t 0 T 1 B C P 1 1 0 T 1 B C P 0 T C K In p u t P A 4 /T C K 1 HT68F30 TM Function Pin Control Block Diagram Rev. 2009 .00 75 November 3.1.

2009 .00 76 November 3.1. HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 P A 0 O u tp u t F u n c tio n 0 P A 0 /T P 0 _ 0 1 0 1 T 0 C P 0 P A 0 P C 5 O u tp u t F u n c tio n 0 P C 5 /T P 0 _ 1 O u tp u t 1 0 1 T M 0 T 0 C P 1 (C T M ) P C 5 T C K In p u t P A 2 /T C K 0 P C 3 O u tp u t F u n c tio n 0 P C 3 /T P 2 _ 0 1 0 1 T 2 C P 0 P C 3 P C 4 O u tp u t F u n c tio n 0 P C 4 /T P 2 _ 1 O u tp u t 1 0 1 T 2 C P 1 P C 4 1 C a p tu re In p u t 0 T M 2 (S T M ) T 2 C P 1 1 0 T 2 C P 0 T C K In p u t P C 2 /T C K 2 HT68F40 TM0 & TM2 Function Pin Control Block Diagram Rev.

HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 P A 1 O u tp u t F u n c tio n 0 P A 1 /T P 1 A 1 C C R A O u tp u t T 1 A C P 0 C C R A C a p tu re In p u t 1 0 T 1 A C P 0 P C 0 O u tp u t F u n c tio n 0 P C 0 /T P 1 B _ 0 1 0 1 T 1 B C P 0 P C 0 P C 1 O u tp u t F u n c tio n 0 P C 1 /T P 1 B _ 1 1 0 1 T 1 B C P 1 T M 1 (E T M ) P C 1 P C 5 O u tp u t F u n c tio n 0 P C 5 /T P 1 B _ 2 C C R B O u tp u t 1 0 1 T 1 B C P 2 P C 5 1 C C R B C a p tu re In p u t 0 T 1 B C P 2 1 0 T 1 B C P 1 1 0 T 1 B C P 0 T C K In p u t P A 4 /T C K 1 HT68F40 TM1 Function Pin Control Block Diagram Rev.1. 2009 .00 77 November 3.

2009 . HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 P A 0 O u tp u t F u n c tio n 0 P A 0 /T P 0 _ 0 1 0 1 T 0 C P 0 P A 0 P C 5 O u tp u t F u n c tio n 0 P C 5 /T P 0 _ 1 O u tp u t 1 0 1 T M 0 T 0 C P 1 (C T M ) P C 5 T C K In p u t P A 2 /T C K 0 P C 3 O u tp u t F u n c tio n 0 P C 3 /T P 2 _ 0 1 0 1 T 2 C P 0 P C 3 P C 4 O u tp u t F u n c tio n 0 P C 4 /T P 2 _ 1 O u tp u t 1 0 1 T 2 C P 1 P C 4 1 C a p tu re In p u t 0 T M 2 (S T M ) T 2 C P 1 1 0 T 2 C P 0 T C K In p u t P C 2 /T C K 2 P D 3 O u tp u t F u n c tio n 0 P D 3 /T P 3 _ 0 1 0 1 T 3 C P 0 P D 3 P D 0 O u tp u t F u n c tio n 0 P D 0 /T P 3 _ 1 O u tp u t 1 0 1 T M 3 T 3 C P 1 (C T M ) P D 0 T C K In p u t P C 4 /T C K 3 HT68F50 and HT68F60 TM0.00 78 November 3. TM3 Function Pin Control Block Diagram Rev. TM2.1.

HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 P A 1 O u tp u t F u n c tio n 0 P A 1 /T P 1 A 1 C C R A O u tp u t T 1 A C P 0 C C R A C a p tu re In p u t 1 0 T 1 A C P 0 P C 0 O u tp u t F u n c tio n 0 P C 0 /T P 1 B _ 0 1 0 1 T 1 B C P 0 P C 0 P C 1 O u tp u t F u n c tio n 0 P C 1 /T P 1 B _ 1 1 0 1 T 1 B C P 1 T M 1 (E T M ) P C 1 P C 5 O u tp u t F u n c tio n 0 P C 5 /T P 1 B _ 2 C C R B O u tp u t 1 0 1 T 1 B C P 2 P C 5 1 C C R B C a p tu re In p u t 0 T 1 B C P 2 1 0 T 1 B C P 1 1 0 T 1 B C P 0 T C K In p u t P A 4 /T C K 1 HT68F50 and HT68F60 TM1 Function Pin Control Block Diagram Rev.00 79 November 3. 2009 .1.

read as ²0² Bit 1 T0CP1: TP0_1 pin Control 0: disable 1: enable Bit 0 T0CP0: TP0_0 pin Control 0: disable 1: enable Rev.00 80 November 3. 2009 .1. 6 Unimplemented. HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 · TMPC0 Register ¨ HT68F20 Bit 7 6 5 4 3 2 1 0 Name ¾ ¾ T1CP1 T1CP0 ¾ ¾ ¾ T0CP0 R/W ¾ ¾ R/W R/W ¾ ¾ ¾ R/W POR ¾ ¾ 0 1 ¾ ¾ ¾ 1 Bit 7. read as ²0² Bit 5 T1BCP1: TP1B_1 pin Control 0: disable 1: enable Bit 4 T1BCP0: TP1B_0 pin Control 0: disable 1: enable Bit 3~2 Unimplemented. read as ²0² Bit 0 T0CP0: TP0_0 pin Control 0: disable 1: enable ¨ HT68F30 Bit 7 6 5 4 3 2 1 0 Name T1ACP0 ¾ T1BCP1 T1BCP0 ¾ ¾ T0CP1 T0CP0 R/W R/W ¾ R/W R/W ¾ ¾ R/W R/W POR 1 ¾ 0 1 ¾ ¾ 0 1 Bit 7 T1ACP0: TP1A pin Control 0: disable 1: enable Bit 6 Unimplemented. read as ²0² Bit 5 T1CP1: TP1_1 pin Control 0: disable 1: enable Bit 4 T1CP0: TP1_0 pin Control 0: disable 1: enable Bit 3~1 Unimplemented.

1. 2009 . read as ²0² Bit 1 T0CP1: TP0_1 pin Control 0: disable 1: enable Bit 0 T0CP0: TP0_0 pin Control 0: disable 1: enable · TMPC1 Register ¨ HT68F40 Bit 7 6 5 4 3 2 1 0 Name ¾ ¾ ¾ ¾ ¾ ¾ T2CP1 T2CP0 R/W ¾ ¾ ¾ ¾ ¾ ¾ R/W R/W POR ¾ ¾ ¾ ¾ ¾ ¾ 0 1 Bit 7~2 Unimplemented. read as ²0² Bit 1 T2CP1: TP2_1 pin Control 0: disable 1: enable Bit 0 T2CP0: TP2_0 pin Control 0: disable 1: enable Rev. HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 ¨ HT68F40/HT68F50/HT68F60 Bit 7 6 5 4 3 2 1 0 Name T1ACP0 T1BCP2 T1BCP1 T1BCP0 ¾ ¾ T0CP1 T0CP0 R/W R/W R/W R/W R/W ¾ ¾ R/W R/W POR 1 0 0 1 ¾ ¾ 0 1 Bit 7 T1ACP0: TP1A pin Control 0: disable 1: enable Bit 6 T1BCP2: TP1B_2 pin Control 0: disable 1: enable Bit 5 T1BCP1: TP1B_1 pin Control 0: disable 1: enable Bit 4 T1BCP0: TP1B_0 pin Control 0: disable 1: enable Bit 3~2 Unimplemented.00 81 November 3.

T n M 0 T n P O L T n O N T n C C L R b 0 ~ b 9 T n IO 1 . read as ²0² Bit 1 T2CP1: TP2_1 pin Control 0: disable 1: enable Bit 0 T2CP0: TP2_0 pin Control 0: disable 1: enable Compact Type TM Although the simplest form of the three TM types.1. TP0_1. Timer/Event Counter and PWM Output modes. read as ²0² Bit 5 T3CP1: TP3_1 pin Control 0: disable 1: enable Bit 4 T3CP0: TP3_0 pin Control 0: disable 1: enable Bit 3~2 Unimplemented. T n IO 0 T n P A U C o m p a ra to r A M a tc h 1 0 . TM Input Pin TM Output Pin HT68F20 10-bit CTM 0 TCK0 TP0_0 HT68F30 10-bit CTM 0 TCK0 TP0_0. TP3_1 HT68F60 10-bit CTM 0. 2009 . TP0_1 HT68F50 10-bit CTM 0. TP0_1. 3 TCK0.u p C o u n te r 1 T P n _ 1 1 1 0 T C K n 1 1 1 T n M 1 . TCK3 TP0_0.b it C o u n t.00 82 November 3. TP3_0. TP3_0. TP0_1 HT68F40 10-bit CTM 0 TCK0 TP0_0.b it C o m p a r a to r P T n P F In te rru p t fS Y S /4 0 0 0 b 7 ~ b 9 fS Y S 0 0 1 T n O C fH /1 6 0 1 0 fH /6 4 0 1 1 T P n _ 0 fT B C 1 0 0 O u tp u t P o la r ity T P n P in C o u n te r C le a r 0 C o n tro l C o n tro l O u tp u t R e s e rv e d 1 0 1 1 0 .b it C o m p a r a to r A T n A F In te rru p t T n C K 2 ~ T n C K 0 C C R A Compact Type TM Block Diagram Rev. the Compact TM type still contains three operating modes. TP3_1 C C R P C o m p a ra to r P M a tc h 3 . which are Compare Match Output. TCK3 TP0_0. CTM Name TM No. HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 ¨ HT68F50/HT68F60 Bit 7 6 5 4 3 2 1 0 Name ¾ ¾ T3CP1 T3CP0 ¾ ¾ T2CP1 T2CP0 R/W ¾ ¾ R/W R/W ¾ ¾ R/W R/W POR ¾ ¾ 0 1 ¾ ¾ 0 1 Bit 7~6 Unimplemented. These two external output pins can be the same sig- nal or the inverse signal. 3 TCK0. The Compact TM can also be controlled with an external input pin and can drive one or two external output pins.

All operating Comparator A and Comparator P. These comparators setup conditions are selected using relevant internal will compare the value in the counter with CCRP and registers. The Compact Type TM can At its core is a 10-bit count-up counter which is driven by operate in a number of different operational modes. 2009 . HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 Compact TM Operation also usually be generated. The using the application program. is to clear the counter by remaining two registers are control registers which changing the TnON bit from low to high. while a read/write register The only way of changing the value of the 10-bit counter pair exists to store the internal 10-bit CCRA value. The CCRP is three bits wide whose Compact Type TM Register Description value is compared with the highest three bits in the counter while the CCRA is the ten bits and therefore Overall operation of the Compact TM is controlled using compares with all counter bits. When these conditions occur. read as ²0² Bit 1~0 TM0DH: TM0 Counter High Byte Register bit 1 ~ bit 0 TM0 10-bit Counter bit 9 ~ bit 8 Rev. be driven by different clock sources including an input There are also two internal comparators with the names. can a user selectable internal or external clock source. CCRA registers. The counter will setup the different operating and control modes as well also be cleared automatically by a counter overflow or a as the three CCRP bits.1. compare match with one of its associated comparators.00 83 November 3. a TM interrupt signal will Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 TM0C0 T0PAU T0CK2 T0CK1 T0CK0 T0ON T0RP2 T0RP1 T0RP0 TM0C1 T0M1 T0M0 T0IO1 T0IO0 T0OC T0POL T0DPX T0CCLR TM0DL D7 D6 D5 D4 D3 D2 D1 D0 TM0DH ¾ ¾ ¾ ¾ ¾ ¾ D9 D8 TM0AL D7 D6 D5 D4 D3 D2 D1 D0 TM0AH ¾ ¾ ¾ ¾ ¾ ¾ D9 D8 Compact TM Register List (if CTM is TM0) · TM0DL Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R R R R R R R R POR 0 0 0 0 0 0 0 0 Bit 7~0 TM0DL: TM0 Counter Low Byte Register bit 7 ~ bit 0 TM0 10-bit Counter bit 7 ~ bit 0 · TM0DH Register Bit 7 6 5 4 3 2 1 0 Name ¾ ¾ ¾ ¾ ¾ ¾ D9 D8 R/W ¾ ¾ ¾ ¾ ¾ ¾ R R POR ¾ ¾ ¾ ¾ ¾ ¾ 0 0 Bit 7~2 Unimplemented. six registers. pin and can also control an output pin. A read only register pair exists to store the internal counter 10-bit value.

When the bit changes state from low to high the internal counter value will be reset to zero. HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 · TM0AL Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0 TM0AL: TM0 CCRA Low Byte Register bit 7 ~ bit 0 TM0 10-bit CCRA bit 7 ~ bit 0 · TM0AH Register Bit 7 6 5 4 3 2 1 0 Name ¾ ¾ ¾ ¾ ¾ ¾ D9 D8 R/W ¾ ¾ ¾ ¾ ¾ ¾ R/W R/W POR ¾ ¾ ¾ ¾ ¾ ¾ 0 0 Bit 7~2 Unimplemented. Clearing the bit to zero restores normal counter operation. When in a Pause condition the TM will remain powered up and continue to consume power. clearing the bit disables the TM. Selecting the Reserved clock input will effectively disable the internal counter. Bit 6~4 T0CK2~T0CK0: Select TM0 Counter clock 000: fSYS/4 001: fSYS 010: fH/16 011: fH/64 100: fTBC 101: Reserved 110: TCK0 rising edge clock 111: TCK0 falling edge clock These three bits are used to select the clock source for the TM. Setting the bit high enables the counter to run.1. The counter will retain its residual value when this bit changes from low to high and resume counting from this value when the bit changes to a low value again. The external pin clock source can be chosen to be active on the rising or falling edge. however when the bit changes from high to low. as specified by the T0OC bit. read as ²0² Bit 1~0 TM0AH: TM0 CCRA High Byte Register bit 1 ~ bit 0 TM0 10-bit CCRA bit 9 ~ bit 8 · TM0C0 Register Bit 7 6 5 4 3 2 1 0 Name T0PAU T0CK2 T0CK1 T0CK0 T0ON T0RP2 T0RP1 T0RP0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7 T0PAU: TM0 Counter Pause Control 0: run 1: pause The counter can be paused by setting this bit high. when the T0ON bit changes from low to high. The clock source fSYS is the system clock. 2009 . the details of which can be found in the oscillator section. Rev. Bit 3 T0ON: TM0 Counter On/Off Control 0: Off 1: On This bit controls the overall on/off function of the TM. the internal counter will retain its residual value. Clearing this bit to zero will stop the counter from counting and turn off the TM which will reduce its power consumption.00 84 November 3. while fH and fTBC are other internal clocks. If the TM is in the Compare Match Output Mode then the TM output pin will be reset to its initial condition.

The function that these bits select depends upon in which mode the TM is running. Bit 5~4 T0IO1~T0IO0: Select TP0_0. The TM output pin can be setup to switch high. TP0_1 output function Compare Match Output Mode 00: No change 01: Output low 10: Output high 11: Toggle output PWM Mode 00: Force inactive state 01: Force active state 10: PWM output 11: Undefined Timer/counter Mode unused These two bits are used to determine how the TM output pin changes state when a certain condition is reached. Rev. In the Timer/Counter Mode. When the bits are both zero. the compare values exist in 128 clock cycle multiples. the T0IO1 and T0IO0 bits determine how the TM output pin changes state when a compare match occurs from the Comparator A. the TM output pin control must be disabled. In the Compare Match Output Mode. HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 Bit 2~0 T0RP2~T0RP0: TM0 CCRP 3-bit register. Setting the T0CCLR bit to zero ensures that a compare match with the CCRP values will reset the internal counter. Note that the output level requested by the T0IO1 and T0IO0 bits must be different from the initial value setup using the T0OC bit otherwise no change will occur on the TM output pin when a compare match occurs. which are then compared with the internal counter's highest three bits. switch low or to toggle its present state when a compare match occurs from the Comparator A. After the TM output pin changes state it can be reset to its initial level by changing the level of the T0ON bit from low to high.00 85 November 3. The result of this comparison can be selected to clear the internal counter if the T0CCLR bit is set to zero. To ensure reliable operation the TM should be switched off before any changes are made to the T0M1 and T0M0 bits. 2009 . The initial value of the TM output pin should be setup using the T0OC bit in the TM0C1 register. then no change will take place on the output. · TM0C1 Register Bit 7 6 5 4 3 2 1 0 Name T0M1 T0M0 T0IO1 T0IO0 T0OC T0POL T0DPX T0CCLR R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~6 T0M1~T0M0: Select TM0 Operating Mode 00: Compare Match Output Mode 01: Undefined Mode 10: PWM Mode 11: Timer/Counter Mode These bits setup the required operating mode for the TM. As the CCRP bits are only compared with the highest three counter bits.1. compared with the TM0 Counter bit 9~bit 7 Comparator P Match Period 000: 1024 TM0 clocks 001: 128 TM0 clocks 010: 256 TM0 clocks 011: 384 TM0 clocks 100: 512 TM0 clocks 101: 640 TM0 clocks 110: 768 TM0 clocks 111: 896 TM0 clocks These three bits are used to setup the value on the internal CCRP 3-bit register. Clearing all three bits to zero is in effect allowing the counter to overflow at its maximum value.

CCRA .duty 1: CCRP . Comparator A and Comparator P. When the bit is low. In the Compare Match Output Mode it determines the logic level of the TM output pin before a compare match occurs.duty. TP0_1 Output polarity Control 0: Non-invert 1: Invert This bit controls the polarity of the TP0_0 or TP0_1 output pin. A counter overflow clearing method can only be implemented if the CCRP bits are all cleared to zero.period This bit. With the T0CCLR bit set high. either of which can be selected to clear the internal counter. determines which of the CCRA and CCRP registers are used for period and duty control of the PWM waveform. Bit 0 T0CCLR: Select TM0 Counter clear condition 0: TM0 Comparatror P match 1: TM0 Comparatror A match This bit is used to select the method which clears the counter. In the PWM Mode it determines if the PWM signal is active high or active low. Bit 1 T0DPX: TM0 PWM period/duty Control 0: CCRP . Its operation depends upon whether TM is being used in the Compare Match Output Mode or in the PWM Mode. Bit 2 T0POL: TP0_0. CCRA . The T0CCLR bit is not used in the PWM Mode. Remember that the Compact TM contains two comparators. When the bit is set high the TM output pin will be inverted and not inverted when the bit is zero. TP0_1 Output control bit Compare Match Output Mode 0: Initial low 1: Initial high PWM Mode 0: Active low 1: Active high This is the output control bit for the TM output pin. 2009 . the counter will be cleared when a compare match occurs from the Comparator A.00 86 November 3. Rev. HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 Bit 3 T0OC: TP0_0. It has no effect if the TM is in the Timer/Counter Mode.period. It has no effect if the TM is in the Timer/Counter Mode. the counter will be cleared when a compare match occurs from the Comparator P or with a counter overflow.1.

Compare Match Output Mode. The way in which the TM output pin changes cleared. Note that if the TnIO1 and TnIO0 bits are zero counter will be cleared when a compare match occurs then no pin change will take place. One is when a compare match occurs from state are determined by the condition of the TnIO1 and Comparator P. a compare match from Comparator A and a com. bits TnM1 and TnM0 in the TMnC1 is made. value. will both be gener. compare match occurs from Comparator A. PWM Therefore when TnCCLR is high no TnPF interrupt re- Mode or Timer/Counter Mode. rupt request flag. TnIO0 = 11 Toggle Output Select Compare Match Output Mode . however here the TnAF in- terrupt request flag will not be generated. from Comparator A. after a comparison To select this mode.1. The TnPF inter- flow. Output pin reset to initial state by TnON bit rising edge Rev. With TnCCLR = 0 the Comparator P match will clear the counter 2. The TM output pin can zero which allows the counter to overflow. 2009 . In this mode output pin condition however only changes state when once the counter is enabled and running it can be an TnAF interrupt request flag is generated after a com- cleared by three methods. The TM register. TnIO0 = 10 Output Pin Active High Output Reset to initial value Select Here TnIO1. Here both be selected using the TnIO1 and TnIO0 bits to go high. TnM0 = 00 Value overflow CCRP = 0 CCRP > 0 Counter cleared by CCRP value 0x3FF CCRP > 0 CCRP Pause Resume Counter Stop Reset CCRA Time TnON bit TnPAU bit TnPOL bit CCRP Int. will have no effect on the TM low. pare match occurs from Comparator A. here only the TnAF inter- Counter Counter TnCCRL = 0. is setup using the If the TnCCLR bit in the TMnC1 register is high then the TnOC bit. condition of the TM output pin. Compare Match Output Mode As the name of the mode suggests. HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 Compact Type TM Operating Modes rupt request flag will be generated even if the value of The Compact Type TM can operate in one of three oper. the counter will overflow when its reaches its maxi- register. generated from a compare match pare match from Comparator P. If the CCRA bits are all selected using the TnM1 and TnM0 bits in the TMnC1 zero.00 87 November 3. The initial ated. ating modes. should be set to ²00² respectively. to go low or to toggle from its present condition when a tor A and Comparator P respectively. the CCRP bits is less than that of the CCRA registers. which is setup after the TnON bit changes from low to high. the other is when the CCRP bits are all TnIO0 bits in the TMnC1 register. TnAF and TnPF interrupt request flags for the Compara. TM output pin controlled only by TnAF flag 3. TnM1. there are two ways in which the counter can be output pin. 3FF Hex. the TM output pin will change state. Flag TnPF CCRA Int.TnCCLR = 0 Note: 1. When the TnCCLR bit is occurs from Comparator P. These are a counter over. Flag TnAF TM O/P Pin Output Pin set Output not affected by TnAF flag Output inverts to Initial Level Output Toggle when TnPOL is high Remains High until reset by TnON bit Low if TnOC = 0 with TnAF flag Now TnIO1. The operating mode is quest flag will be generated. However. mum 10-bit.

TM output pin controlled only by TnAF flag 3. HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 Counter TnCCLR = 1. generated on CCRA overflow Flag TnAF CCRP Int. TnIO0 = 10 Active High Output Output Pin Select Reset to initial value Here TnIO 1. 2009 . Flag TnPF Output does TnPF not not change generated TM O/P Pin Output Pin set Output not affected by TnAF flag to Initial Level Output Toggle remains High until reset by TnON bit Output inverts Low if TnOC = 0 with TnAF flag when TnPOL is high Now TnIO1.TM output pin reset to initial state by TnON rising edge 4. TnM0 = 00 Value CCRA = 0 CCRA > 0 Counter cleared by CCRA value Counter overflows 0x3FF CCRA = 0 CCRA Pause Resume Counter Stop Reset CCRP Time TnON bit TnPAU bit TnPOL bit No TnAF flag CCRA Int.00 88 November 3.1. TnIO0 = 11 Toggle Output Select Compare Match Output Mode .TnCCLR = 1 Note: 1. TnPF flags not generated when TnCCLR = 1 Rev. TnM1. With TnCCLR = 1 the Comparator A match will clear the counter 2.

To select this mode. In the PWM mode. TnCCLR bit has no influence on PWM operation Rev. HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 Timer/Counter Mode As both the period and duty cycle of the PWM waveform To select this mode. By providing a signal of fixed fre. The TnOC bit in tion within the TM is useful for applications which require the TMnC1 register is used to select the required polar- functions such as motor control. the choice of generated waveform is register should be set to 11 respectively. TnM1. bits TnM1 and TnM0 in the TMnC1 can be controlled. cycle is determined using the TnDPX bit in the TMnC1 the pin can be used as a normal I/O pin or other register. TnIO0 = 00 or 01 4. Therefore the counter and thus control the PWM waveform frequency. one for each of the CCRA and CCRP. As the TM output pin is not used in this mode. TnIO0 bits are used to enable the PWM output or to quency but of varying duty cycle on the TM output pin. TnIO0 = 10 Output Inverts Here TnIO1. Flag TnPF TnIO1. and CCRP registers are used to generate the PWM terrupt flags. TnIO0 = 00 Resume PWM Output PWM resumes operation When TnPOL = 1 PWM Period Output Forced to Inactive Output remains at same level set by CCRP level but PWM function PWM Duty Cycle keeps running internally set by CCRA PWM Mode . while the other one is used to control the duty cycle. Counter Value Counter Cleared by CCRP DPX = 0. one register is used to clear the internal Mode the TM output pin is not used. TnIO0 = 10 PWM Output TnIO1.TnDPX = 0 Note: 1.Counter cleared by CCRP 2. heating control. ity of the PWM waveform while the two TnIO1 and nation control etc. PWM Output Mode An interrupt flag. illumi. Here TnDPX = 0 . TnIO0 = 00 TnIO1. The PWM func. The square wave AC waveform can be generated with vary. The exception is that in the Timer/Counter waveform. The extremely flexible. Counter Clear sets PWM Period 3. TnIO0 = 10 Output Inactive PWM Output TM Pin TnOC = 1 TM Pin TnOC = 0 TnIIO1. the TnCCLR bit Timer/Counter Mode operates in an identical way to the has no effect on the PWM operation. a force the TM output pin to a fixed high or low level.1. TnPOL bit is used to reverse the polarity of the PWM ing equivalent DC RMS values. TnM0 = 10 CCRP Counter reset Counter Stop when TnON Pause Resume if TnON bit low returns high CCRA Time TnON bit TnPAU bit TnPOL bit Interrupts still generated CCRA Int.00 89 November 3. above description and Timing Diagrams for the Com. can therefore be controlled by the values in the CCRA and CCRP registers. Internal PWM function continues even when TnIO1. either Comparator A or Comparator P. Flag TnAF CCRP Int. 2009 . pare Match Output Mode can be used to understand its Which register is used to control either frequency or duty function. bits TnM1 and TnM0 in the TMnC1 will be generated when a compare match occurs from register should be set to 10 respectively. Both of the CCRA Compare Match Output Mode generating the same in. The PWM waveform frequency and duty cycle pin-shared function. output waveform.

Here TnDPX = 1 .Counter cleared by CCRA 2. TnIO0 = 00 or 01 4. TnIO0 = 10 Output Inverts Here TnIO1.1. TnCCLR bit has no influence on PWM operation Rev.TnDPX = 1 Note: 1. Flag TnAF TnIO1. Counter Clear sets PWM Period 3. TnIO0 = 00 TnIO1. TnM1. TnIO0 = 10 PWM Output Output Inactive TnIO1. Flag TnPF CCRA Int. TnIO0 = 00 Resume PWM Output PWM resumes operation When TnPOL = 1 PWM Period Output Forced to Inactive Output remains at same level set by CCRA level but PWM function PWM Duty Cycle keeps running internally set by CCRP PWM Mode . Internal PWM function continues even when TnIO1. TnM0 = 10 CCRA Counter reset Counter Stop when TnON Pause Resume if TnON bit low returns high CCRP Time TnON bit TnPAU bit TnPOL bit Interrupts still generated CCRP Int.00 90 November 3. HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 Counter Value Counter Cleared by CCRA DPX = 1. 2009 . TnIO0 = 10 PWM Output TM Pin TnOC = 1 TM Pin TnOC = 0 TnIO1.

These comparators will vant internal registers. T n IO 0 T n P A U 1 0 o r 1 6 . can be driven by different clock sources selectable internal or external clock source. which are Compare Match Output.1. The Standard wide and the other is 16-bits wide. TP2_1 HT68F50 16-bit STM 2 TCK2 TP2_0. A read only register pair exists to therefore compares all counter bits. while a read/write register pair exists to store the internal 10 or The only way of changing the value of the 10 or 16-bit 16-bit CCRA value. is to clear the control registers which setup the different operating and counter by changing the TnON bit from low to high. T n M 0 T n P O L T C K n 1 1 1 T n O N b 0 ~ b 9 o r b 0 ~ b 1 5 T n IO 1 . TM Input Pin TM Output Pin HT68F20 10-bit STM 1 TCK1 TP1_0. one is 10-bits rupt signal will also usually be generated.b it C o u n t. T n IO 0 T n C K 2 ~ T n C K 0 C C R A E d g e D e te c to r Standard Type TM Block Diagram Rev. store the internal counter 10 or 16-bit value. TP2_1 HT68F60 16-bit STM 2 TCK2 TP2_0. CTM Name TM No. compare the value in the counter with CCRP and CCRA Standard Type TM Register Description registers. The control modes as well as the three or eight CCRP bits. HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 Standard Type TM . The CCRP comparator is 3 or 8-bits wide whose value is compared the with highest 3 or 8 bits in Overall operation of the Standard TM is controlled using the counter while the CCRA is the ten or sixteen bits and a series of registers. Com. Single Pulse Output and PWM Output modes.00 91 November 3.b it C o m p a r a to r P T n P F In te rru p t b 7 ~ b 9 o r b 8 ~ b 1 5 T n O C fS Y S /4 0 0 0 fS Y S 0 0 1 fH /1 6 0 1 0 T P n _ 0 fH /6 4 O u tp u t P o la r ity T P n P in 0 1 1 C o u n te r C le a r 0 1 0 o r 1 6 . 2009 .u p C o u n te r C o n tro l C o n tro l In p u t/O u tp u t fT B C 1 0 0 1 T P n _ 1 R e s e rv e d 1 0 1 1 1 0 T n C C L R T n M 1 .STM The Standard Type TM contains five operating modes. When these conditions occur. a TM inter- There are two sizes of Standard TMs. The remaining two registers are counter using the application program. Timer/Event Counter. Cap- ture Input. At the core is a 10 or Type TM can operate in a number of different opera- 16-bit count-up counter which is driven by a user tional modes. counter will also be cleared automatically by a counter overflow or a compare match with one of its associated C C R P C o m p a ra to r P M a tc h 3 o r 8 . There are including an input pin and can also control an output pin. TP2_1 Standard TM Operation comparators. TP1_1 HT68F30 ¾ ¾ ¾ ¾ HT68F40 16-bit STM 2 TCK2 TP2_0.b it C o m p a ra to r A M a tc h T n A F In te rru p t C o m p a ra to r A T n IO 1 . All operating setup conditions are selected using rele- parator A and Comparator P. also two internal comparators with the names. The Standard TM can also be controlled with an external in- put pin and can drive one or two external output pins.

Rev. When in a Pause condition the TM will remain powered up and continue to consume power.10-bit STM Bit 7 6 5 4 3 2 1 0 Name T1PAU T1CK2 T1CK1 T1CK0 T1ON T1RP2 T1RP1 T1RP0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7 T1PAU: TM1 Counter Pause Control 0: run 1: pause The counter can be paused by setting this bit high. Selecting the Reserved clock input will effectively disable the internal counter. The clock source fSYS is the system clock. Bit 6~4 T1CK2~T1CK0: Select TM1 Counter clock 000: fSYS/4 001: fSYS 010: fH/16 011: fH/64 100: fTBC 101: Reserved 110: TCK1 rising edge clock 111: TCK1 falling edge clock These three bits are used to select the clock source for the TM. 2009 . the details of which can be found in the oscillator section. while fH and fTBC are other internal clocks. HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 TM1C0 T1PAU T1CK2 T1CK1 T1CK0 T1ON T1RP2 T1RP1 T1RP0 TM1C1 T1M1 T1M0 T1IO1 T1IO0 T1OC T1POL T1DPX T1CCLR TM1DL D7 D6 D5 D4 D3 D2 D1 D0 TM1DH ¾ ¾ ¾ ¾ ¾ ¾ D9 D8 TM1AL D7 D6 D5 D4 D3 D2 D1 D0 TM1AH ¾ ¾ ¾ ¾ ¾ ¾ D9 D8 10-bit Standard TM Register List (for HT68F20) Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 TM2C0 T2PAU T2CK2 T2CK1 T2CK0 T2ON ¾ ¾ ¾ TM2C1 T2M1 T2M0 T2IO1 T2IO0 T2OC T2POL T2DPX T2CCLR TM2DL D7 D6 D5 D4 D3 D2 D1 D0 TM2DH D15 D14 D13 D12 D11 D10 D9 D8 TM2AL D7 D6 D5 D4 D3 D2 D1 D0 TM2AH D15 D14 D13 D12 D11 D10 D9 D8 TM2RP D7 D6 D5 D4 D3 D2 D1 D0 16-bit Standard TM Register List (for HT68F40/HT68F50/HT68F60) · 10-bit Standard TM Register List .00 92 November 3. The counter will retain its residual value when this bit changes from low to high and resume counting from this value when the bit changes to a low value again.1.HT68F20 ¨ TM1C0 Register . Clearing the bit to zero restores normal counter operation. The external pin clock source can be chosen to be active on the rising or falling edge.

TP1_1 01: Input capture at falling edge of TP1_0. Clearing all three bits to zero is in effect allowing the counter to overflow at its maximum value.1. TP1_1 10: Input capture at falling/rising edge of TP1_0. TP1_1 output function Compare Match Output Mode 00: No change 01: Output low 10: Output high 11: Toggle output PWM Mode/Single Pulse Output Mode 00: Force inactive state 01: Force active state 10: PWM output 11: Single pulse output Capture Input Mode 00: Input capture at rising edge of TP1_0. Setting the bit high enables the counter to run. the internal counter will retain its residual value until the bit returns high again. when the T1ON bit changes from low to high. ¨ TM1C1 Register . HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 Bit 3 T1ON: TM1 Counter On/Off Control 0: Off 1: On This bit controls the overall on/off function of the TM. clearing the bit disables the TM.00 93 November 3. TP1_1 11: Input capture disabled Timer/counter Mode: Unused Rev. as specified by the T1OC bit. When the bit changes state from low to high the internal counter value will be reset to zero. compared with the TM1 Counter bit 9~bit 7 Comparator P Match Period 000: 1024 TM1 clocks 001: 128 TM1 clocks 010: 256 TM1 clocks 011: 384 TM1 clocks 100: 512 TM1 clocks 101: 640 TM1 clocks 110: 768 TM1 clocks 111: 896 TM1 clocks These three bits are used to setup the value on the internal CCRP 3-bit register. Bit 2~0 T1RP2~T1RP0: TM1 CCRP 3-bit register. As the CCRP bits are only compared with the highest three counter bits. In the Timer/Counter Mode. 2009 . the compare values exist in 128 clock cycle multiples. Clearing this bit to zero will stop the counter from counting and turn off the TM which will reduce its power consumption. The result of this comparison can be selected to clear the internal counter if the T1CCLR bit is set to zero. If the TM is in the Compare Match Output Mode then the TM output pin will be reset to its initial condition. Setting the T1CCLR bit to zero ensures that a compare match with the CCRP values will reset the internal counter. Bit 5~4 T1IO1~T1IO0: Select TP1_0. To ensure reliable operation the TM should be switched off before any changes are made to the T1M1 and T1M0 bits. the TM output pin control must be disabled. however when the bit changes from high to low.10-bit STM Bit 7 6 5 4 3 2 1 0 Name T1M1 T1M0 T1IO1 T1IO0 T1OC T1POL T1DPX T1CCLR R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~6 T1M1~T1M0: Select TM1 Operating Mode 00: Compare Match Output Mode 01: Capture Input Mode 10: PWM Mode or Single Pulse Output Mode 11: Timer/Counter Mode These bits setup the required operating mode for the TM. which are then compared with the internal counter's highest three bits.

duty. Bit 1 T1DPX: TM1 PWM period/duty Control 0: CCRP . Bit 2 T1POL: TP1_0. A counter overflow clearing method can only be implemented if the CCRP bits are all cleared to zero. Remember that the Standard TM contains two comparators. When the bits are both zero. Single Pulse or Input Capture Mode. HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 These two bits are used to determine how the TM output pin changes state when a certain condition is reached. Bit 0 T1CCLR: Select TM1 Counter clear condition 0: TM1 Comparatror P match 1: TM1 Comparatror A match This bit is used to select the method which clears the counter. the T1IO1 and T1IO0 bits determine how the TM output pin changes state when a compare match occurs from the Comparator A. It has no effect if the TM is in the Timer/Counter Mode.period. With the T1CCLR bit set high. TP1_1 Output polarity Control 0: non-invert 1: invert This bit controls the polarity of the TP1_0 or TP1_1 output pin.1. either of which can be selected to clear the internal counter. The initial value of the TM output pin should be setup using the T1OC bit in the TM1C1 register. Rev. Its operation depends upon whether TM is being used in the Compare Match Output Mode or in the PWM Mode/ Single Pulse Output Mode. In the PWM Mode it determines if the PWM signal is active high or active low. then no change will take place on the output.00 94 November 3. It has no effect if the TM is in the Timer/Counter Mode.period This bit. Comparator A and Comparator P. CCRA . The TM output pin can be setup to switch high. When the bit is low. In the Compare Match Output Mode. CCRA .duty 1: CCRP . The function that these bits select depends upon in which mode the TM is running. the counter will be cleared when a compare match occurs from the Comparator A. TP1_1 Output control bit Compare Match Output Mode 0: initial low 1: initial high PWM Mode/ Single Pulse Output Mode 0: Active low 1: Active high This is the output control bit for the TM output pin. The T1CCLR bit is not used in the PWM. After the TM output pin changes state it can be reset to its initial level by changing the level of the T1ON bit from low to high. the counter will be cleared when a compare match occurs from the Comparator P or with a counter overflow. When the bit is set high the TM output pin will be inverted and not inverted when the bit is zero. switch low or to toggle its present state when a compare match occurs from the Comparator A. Note that the output level requested by the T1IO1 and T1IO0 bits must be different from the initial value setup using the T1OC bit otherwise no change will occur on the TM output pin when a compare match occurs. Bit 3 T1OC: TP1_0. In the Compare Match Output Mode it determines the logic level of the TM output pin before a compare match occurs. 2009 . determines which of the CCRA and CCRP registers are used for period and duty control of the PWM waveform.

read as ²0² Bit 1~0 TM1DH: TM1 Counter High Byte Register bit 1~bit 0 TM1 10-bit Counter bit 9~bit 8 ¨ TM1AL Register .10-bit STM Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R R R R R R R R POR 0 0 0 0 0 0 0 0 Bit 7~0 TM1DL: TM1 Counter Low Byte Register bit 7~bit 0 TM1 10-bit Counter bit 7~bit 0 ¨ TM1DH Register . 2009 .10-bit STM Bit 7 6 5 4 3 2 1 0 Name ¾ ¾ ¾ ¾ ¾ ¾ D9 D8 R/W ¾ ¾ ¾ ¾ ¾ ¾ R R POR ¾ ¾ ¾ ¾ ¾ ¾ 0 0 Bit 7~2 Unimplemented. HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 ¨ TM1DL Register .1.10-bit STM Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0 TM1AL: TM1 CCRA Low Byte Register bit 7~bit 0 TM1 10-bit CCRA bit 7~bit 0 ¨ TM1AH Register .10-bit STM Bit 7 6 5 4 3 2 1 0 Name ¾ ¾ ¾ ¾ ¾ ¾ D9 D8 R/W ¾ ¾ ¾ ¾ ¾ ¾ R/W R/W POR ¾ ¾ ¾ ¾ ¾ ¾ 0 0 Bit 7~2 Unimplemented. read as ²0² Bit 1~0 TM1AH: TM1 CCRA High Byte Register bit 1~bit 0 TM1 10-bit CCRA bit 9~bit 8 Rev.00 95 November 3.

HT68F40/HT68F50/HT68F60 ¨ TM2C0 Register . HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 · 16-bit Standard TM Register List .16-bit STM Bit 7 6 5 4 3 2 1 0 Name T2PAU T2CK2 T2CK1 T2CK0 T2ON ¾ ¾ ¾ R/W R/W R/W R/W R/W R/W ¾ ¾ ¾ POR 0 0 0 0 0 ¾ ¾ ¾ Bit 7 T2PAU: TM2 Counter Pause Control 0: Run 1: Pause The counter can be paused by setting this bit high. Bit 2~0 Unimplemented. The clock source fSYS is the system clock. T2CK1. 2009 . When in a Pause condition the TM will remain powered up and continue to consume power. When the bit changes state from low to high the internal counter value will be reset to zero. Bit 6~4 T2CK2. Clearing the bit to zero restores normal counter operation.00 96 November 3. when the T2ON bit changes from low to high. Clearing this bit to zero will stop the counter from counting and turn off the TM which will reduce its power consumption. read as ²0² Rev. Selecting the Reserved clock input will effectively disable the internal counter. the internal counter will retain its residual value until the bit returns high again. The external pin clock source can be chosen to be active on the rising or falling edge. while fH and fTBC are other internal clocks. clearing the bit disables the TM. T2CK0: Select TM2 Counter clock 000: fSYS/4 001: fSYS 010: fH/16 011: fH/64 100: fTBC 101: Reserved 110: TCK2 rising edge clock 111: TCK2 falling edge clock These three bits are used to select the clock source for the TM. If the TM is in the Compare Match Output Mode then the TM output pin will be reset to its initial condition. the details of which can be found in the oscillator section. as specified by the T2OC bit. The counter will retain its residual value when this bit changes from low to high and resume counting from this value when the bit changes to a low value again. Setting the bit high enables the counter to run.1. however when the bit changes from high to low. Bit 3 T2ON: TM2 Counter On/Off Control 0: Off 1: On This bit controls the overall on/off function of the TM.

switch low or to toggle its present state when a compare match occurs from the Comparator A. Its operation depends upon whether TM is being used in the Compare Match Output Mode or in the PWM Mode/ Single Pulse Output Mode. The initial value of the TM output pin should be setup using the T2OC bit in the TM2C1 register. TP2_1 01: Input capture at falling edge of TP2_0. Bit 5~4 T2IO1~T2IO0: Select TP2_0. the T2IO1 and T2IO0 bits determine how the TM output pin changes state when a compare match occurs from the Comparator A. Note that the output level requested by the T2IO1 and T2IO0 bits must be different from the initial value setup using the T2OC bit otherwise no change will occur on the TM output pin when a compare match occurs. 2009 . the TM output pin control must be disabled. TP2_1 output function Compare Match Output Mode 00: No change 01: Output low 10: Output high 11: Toggle output PWM Mode/ Single Pulse Output Mode 00: Force inactive state 01: Force active state 10: PWM output 11: Single pulse output Capture Input Mode 00: Input capture at rising edge of TP2_0. Bit 3 T2OC: TP2_0. HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 ¨ TM2C1 Register . In the PWM Mode it determines if the PWM signal is active high or active low. After the TM output pin changes state it can be reset to its initial level by changing the level of the T2ON bit from low to high. In the Compare Match Output Mode. The TM output pin can be setup to switch high. TP2_1 11: Input capture disabled Timer/counter Mode: Unused These two bits are used to determine how the TM output pin changes state when a certain condition is reached. then no change will take place on the output. Rev. TP2_1 Output control bit Compare Match Output Mode 0: Initial low 1: Initial high PWM Mode/ Single Pulse Output Mode 0: Active low 1: Active high This is the output control bit for the TM output pin. In the Compare Match Output Mode it determines the logic level of the TM output pin before a compare match occurs. The function that these bits select depends upon in which mode the TM is running. To ensure reliable operation the TM should be switched off before any changes are made to the T2M1 and T2M0 bits. TP2_1 10: Input capture at falling/rising edge of TP2_0. In the Timer/Counter Mode.00 97 November 3. When the bits are both zero.1.16-bit STM Bit 7 6 5 4 3 2 1 0 Name T2M1 T2M0 T2IO1 T2IO0 T2OC T2POL T2DPX T2CCLR R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~6 T2M1~T2M0: Select TM2 Operating Mode 00: Compare Match Output Mode 01: Capture Input Mode 10: PWM Mode or Single Pulse Output Mode 11: Timer/Counter Mode These bits setup the required operating mode for the TM. It has no effect if the TM is in the Timer/Counter Mode.

period.00 98 November 3. ¨ TM2DL Register . HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 Bit 2 T2POL: TP2_0.16-bit STM Bit 7 6 5 4 3 2 1 0 Name D15 D14 D13 D12 D11 D10 D9 D8 R/W R R R R R R R R POR 0 0 0 0 0 0 0 0 Bit 7~0 TM2DH: TM2 Counter High Byte Register bit 7~bit 0 TM2 16-bit Counter bit 15~bit 8 ¨ TM2AL Register . With the T2CCLR bit set high.duty. the counter will be cleared when a compare match occurs from the Comparator P or with a counter overflow. Bit 0 T2CCLR: Select TM2 Counter clear condition 0: TM2 Comparator P match 1: TM2 Comparator A match This bit is used to select the method which clears the counter. TP2_1 Output polarity Control 0: Non-invert 1: Invert This bit controls the polarity of the TP2_0 or TP2_1 output pin. When the bit is set high the TM output pin will be inverted and not inverted when the bit is zero.1. It has no effect if the TM is in the Timer/Counter Mode.period This bit. Single Pulse or Input Capture Mode. When the bit is low. either of which can be selected to clear the internal counter. Bit 1 T2DPX: TM2 PWM period/duty Control 0: CCRP . CCRA . 2009 . The T1CCLR bit is not used in the PWM.duty 1: CCRP . A counter overflow clearing method can only be implemented if the CCRP bits are all cleared to zero.16-bit STM Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R R R R R R R R POR 0 0 0 0 0 0 0 0 Bit 7~0 TM2DL: TM2 Counter Low Byte Register bit 7~bit 0 TM2 16-bit Counter bit 7~bit 0 ¨ TM2DH Register . determines which of the CCRA and CCRP registers are used for period and duty control of the PWM waveform. CCRA . Remember that the Standard TM contains two comparators.16-bit STM Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0 TM2AL: TM2 CCRA Low Byte Register bit 7~bit 0 TM2 16-bit CCRA bit 7~bit 0 Rev. Comparator A and Comparator P. the counter will be cleared when a compare match occurs from the Comparator A.

generated from a compare match cleared by three methods. condition of the TM output pin. As the name of the mode suggests. register. after a comparison is made. One is when a compare match from Compara.1. The way in which the TM output pin changes pare match from Comparator P. The TM output pin can cleared.16-bit STM Bit 7 6 5 4 3 2 1 0 Name D15 D14 D13 D12 D11 D10 D9 D8 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0 TM2AH: TM2 CCRA High Byte Register bit 7~bit 0 TM2 16-bit CCRA bit 15~bit 8 ¨ TM2RP Register . Here both TnAF and compare match occurs from Comparator A. the TM output pin. The initial TnPF interrupt request flags for Comparator A and Com. will have no effect on the TM flow. Clearing all eight bits to zero is in effect allowing the counter to overflow at its maximum value. Standard Type TM Operating Modes from Comparator A. counter will be cleared when a compare match occurs Rev. a compare match from Comparator A and a com. The result of this comparison can be selected to clear the internal counter if the T2CCLR bit is set to zero. here only the TnAF inter- The Standard Type TM can operate in one of five oper. there are two ways in which the counter can be TnIO0 bits in the TMnC1 register. will change state. which are then compared with the internal counter's highest eight bits. should be set to 00 respectively. However. is setup using the TnOC bit. When the TnCCLR bit is state are determined by the condition of the TnIO1 and low. be selected using the TnIO1 and TnIO0 bits to go high. rupt request flag will be generated even if the value of ating modes. Note that if the TnIO1 and TnIO0 bits are zero If the TnCCLR bit in the TMnC1 register is high then the then no pin change will take place. output pin. Capture Input Therefore when TnCCLR is high no TnPF interrupt re- Mode or Timer/Counter Mode. the CCRA can not be set to ²0². The TnPF inter- once the counter is enabled and running it can be rupt request flag. The TM Compare Output Mode output pin condition however only changes state when To select this mode. TnON bit changes from low to high. the other is when the CCRP bits are all zero which to go low or to toggle from its present condition when a allows the counter to overflow. The operating mode is quest flag will be generated. bits TnM1 and TnM0 in the TMnC1 an TnAF interrupt request flag is generated after a com- register. As the CCRP bits are only compared with the highest eight counter bits. Setting the T2CCLR bit to zero ensures that a compare match with the CCRP values will reset the internal counter. These are a counter over. put Mode. tor P. Compare Match Output Mode. 2009 . will both be generated.00 99 November 3. PWM Out. In this mode pare match occurs from Comparator A. In the Compare Match Out- selected using the TnM1 and TnM0 bits in the TMnC1 put Mode. the compare values exist in 256 clock cycle multiples. the CCRP bits is less than that of the CCRA registers.16-bit STM Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0 TM2RP: TM2 CCRP Register bit 7 ~ bit 0 TM2 CCRP 8-bit register. Single Pulse Output Mode. occurs from Comparator P. compared with the TM2 Counter bit 15 ~ bit 8. HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 ¨ TM2AH Register . Comparator P Match Period 0: 65536 TM2 clocks 1~255: 256 x (1~255) TM2 clocks These eight bits are used to setup the value on the internal CCRP 8-bit register. which is setup after the parator P respectively.

Output pin reset to initial state by TnON bit rising edge Rev. TnM0 = 00 Counter Value overflow CCRP = 0 CCRP > 0 Counter cleared by CCRP value 0x3FF CCRP > 0 CCRP Pause Resume Counter Stop Reset CCRA Time TnON bit TnPAU bit TnPOL bit CCRP Int. HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 Counter TnCCRL = 0.1. TM output pin controlled only by TnAF flag 3. With TnCCLR = 0 the Comparator P match will clear the counter 2. TnM1. TnIO0 = 10 Output Pin Active High Output Reset to initial value Select Here TnIO1. Flag TnPF CCRA Int. Flag TnAF TM O/P Pin Output inverts Output Pin set Output not affected by TnAF flag Output Toggle when TnPOL is high to Initial Level Remains High until reset by TnON bit Low if TnOC = 0 with TnAF flag Now TnIO1. TnIO0 = 11 Toggle Output Select Compare Match Output Mode .TnCCLR = 0 Note: 1. 2009 .00 100 November 3.

HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 Counter TnCCLR = 1.1. TnPF flags not generated when TnCCLR = 1 Rev. With TnCCLR = 1 the Comparator A match will clear the counter 2. TnIO0 = 10 Active High Output Output Pin Select Reset to initial value Here TnIO 1.TnCCLR = 1 Note: Points to note for above diagram: 1. TnM1. generated on CCRA overflow Flag TnAF CCRP Int. TM output pin controlled only by TnAF flag 3. 2009 .TM output pin reset to initial state by TnON rising edge 4.00 101 November 3. TnIO0 = 11 Toggle Output Select Compare Match Output Mode . TnM0 = 00 Value CCRA = 0 CCRA > 0 Counter cleared by CCRA value Counter overflows 0x3FF CCRA = 0 CCRA Pause Resume Counter Stop Reset CCRP Time TnON bit TnPAU bit TnPOL bit No TnAF flag CCRA Int. Flag TnPF Output does TnPF not not change generated TM O/P Pin Output Pin set Output not affected by TnAF flag to Initial Level Output Toggle remains High until reset by TnON bit Output inverts Low if TnOC = 0 with TnAF flag when TnPOL is high Now TnIO1.

In the PWM mode. the TnCCLR bit Timer/Counter Mode operates in an identical way to the has no effect as the PWM period. TnM1. Flag TnPF TnIO1. TnIO0 = 10 PWM Output TnIO1. Flag TnAF CCRP Int. illumination control etc. Internal PWM function continues even when TnIO1. a square wave AC waveform can be gen.TnDPX = 0 Note: 1. TnM0 = 10 CCRP Counter reset Counter Stop when TnON Pause Resume if TnON bit low returns high CCRA Time TnON bit TnPAU bit TnPOL bit Interrupts still generated CCRA Int. TnCCLR bit has no influence on PWM operation Rev. Which pare Match Output Mode can be used to understand its register is used to control either frequency or duty cycle function. TnIO0 = 00 TnIO1. Here TnDPX = 0 . Both of the CCRA and Compare Match Output Mode generating the same in. The PWM waveform frequency and duty cycle can pin-shared function. Therefore the and thus control the PWM waveform frequency. the TMnC1 register is used to select the required polar- The PWM function within the TM is useful for applica. TnIO0 = 10 Output Inverts Here TnIO1. By providing a force the TM output pin to a fixed high or low level. bits TnM1 and TnM0 in the TMnC1 will be generated when a compare match occurs from register should be set to 10 respectively and also the either Comparator A or Comparator P. the other one is used to control the duty cycle. PWM Output Mode An interrupt flag. The extremely flexible. To select this mode.00 102 November 3. one register is used to clear the internal counter Mode the TM output pin is not used. As the TM output pin is not used in this mode.1. TnIO0 = 00 Resume PWM Output PWM resumes operation When TnPOL = 1 PWM Period Output Forced to Inactive Output remains at same level set by CCRP level but PWM function PWM Duty Cycle keeps running internally set by CCRA PWM Mode . TnIO0 = 00 or 01 4. output waveform. Counter Value Counter Cleared by CCRP TnDPX = 0. 2009 . The signal of fixed frequency but of varying duty cycle on the TnPOL bit is used to reverse the polarity of the PWM TM output pin. erated with varying equivalent DC RMS values. ity of the PWM waveform while the two TnIO1 and tions which require functions such as motor control. The TnOC bit in TnIO1 and TnIO0 bits should be set to 10 respectively. TnIO0 = 10 Output Inactive PWM Output TM Pin TnOC = 1 TM Pin TnOC = 0 TnIIO1. bits TnM1 and TnM0 in the TMnC1 can be controlled. one for each of the CCRA and CCRP. Counter Clear sets PWM Period 3. is determined using the TnDPX bit in the TMnC1 regis- the pin can be used as a normal I/O pin or other ter. HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 Timer/Counter Mode As both the period and duty cycle of the PWM waveform To select this mode. the choice of generated waveform is register should be set to 11 respectively. The exception is that in the Timer/Counter form. therefore be controlled by the values in the CCRA and CCRP registers. CCRP registers are used to generate the PWM wave- terrupt flags. TnIO0 bits are used to enable the PWM output or to heating control. while above description and Timing Diagrams for the Com.Counter cleared by CCRP 2.

TnIO0 = 10 PWM Output Output Inactive TnIO1. Flag TnPF CCRA Int.00 103 November 3. TnM1. TnCCLR bit has no influence on PWM operation Rev. TnM0 = 10 CCRA Counter reset Counter Stop when TnON Pause Resume if TnON bit low returns high CCRP Time TnON bit TnPAU bit TnPOL bit Interrupts still generated CCRP Int. HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 Counter Value Counter Cleared by CCRA TnDPX = 1.Counter cleared by CCRA 2.1. TnIO0 = 00 or 01 4. 2009 . TnIO0 = 00 Resume PWM Output PWM resumes operation When TnPOL = 1 PWM Period Output Forced to Inactive Output remains at same level set by CCRA level but PWM function PWM Duty Cycle keeps running internally set by CCRP PWM Mode .TnDPX = 1 Note: 1. TnIO0 = 10 Output Inverts Here TnIO1. TnIO0 = 10 PWM Output TM Pin TnOC = 1 TM Pin TnOC = 0 TnIO1. Flag TnAF TnIO1. Counter Clear sets PWM Period 3. Internal PWM function continues even when TnIO1. TnIO0 = 00 TnIO1. Here TnDPX = 1 .

s et by TCKn pin Software Cleared by Software Software Software Trigger CCRA match Trigger Clear Trigger TCKn pin TCKn pin Trigger TnPAU bit TnPOL bit No CCRP Interrupt generated CCRP Int. The generated pulse trail- ing edge will be generated when the TnON bit is cleared The trigger for the pulse output leading edge is a low to to zero. TnM0 = 10. Counter stopped by CCRA match 2. TnIO1. bits TnM1 and TnM0 in the TMnC1 TCKn pin. TnIO0 = 00 When TnPOL = 1 Pulse Width Output Forced to Inactive TnIO1. which will in turn initiate the Single Pulse out- register should be set to 10 respectively and also the put. The TnON bit should remain high when will generate a single shot pulse on the TM output pin. the TnON bit can also be made to L e a d in g E d g e T r a ilin g E d g e S /W C o m m a n d S /W C o m m a n d S E T "T n O N " C L R "T n O N " T n O N b it T n O N b it o r o r 0 ® 1 1 ® 0 T C K n P in T r a n s itio n C C R A M a tc h C o m p a re T M n O u tp u t P in P u ls e W id th = C C R A V a lu e Single Pulse Generation Counter Value TnM1. TnIO0 = 11 TM Pin TnOC = 1 TM Pin TnOC = 0 Output Inverts Here TnIO1. Flag TnAF TnIO1. However in the parator A. HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 Single Pulse Mode automatically change from low to high using the external To select this mode. which can be imple- program or when a compare match occurs from Com- mented using the application program. 2009 . Pulse triggered by TCKn pin or setting TnON bit high 4. When the TnON bit transitions to a high level.1. be generated. Single Pulse Mode.00 104 November 3. the pulse is in its active state. CCRP is not used 3. TnIO0 = 11 Single Pulse Output TnIO1. TnIO0 = 00 Output Inactive TnIO1. which can be implemented using the application high transition of the TnON bit. counter will start running and the pulse leading edge will The Single Pulse Output Mode. Flag TnPF CCRA Int. TnIO0 = 11 Counter Stopped by CCRA CCRA Counter reset Counter Stops when TnON Pause Resume by software returns high CCRP Time TnON bit Auto. as the name suggests. TCKn pin active edge will auto set TnON bit Rev. the TnIO1 and TnIO0 bits should be set to 11 respectively. TnIO0 = 11 set by CCRA level but counter keeps Resume Single Pulse Output running internally Single Pulse Mode Note: 1.

TnM0 = 01 and active edge set by TnIO1 and TnIO0 bits 2. In this way the CCRA TPn_0 or TPn_1 pin the counter will continue to free run value can be used to control the pulse width. then no capture operation will take place irre- for applications such as pulse width measurements. No output function . TM Capture input pin active edge transfers counter value to CCRA 3. whose active edge can be either a rising edge. A compare until the TnON bit changes from high to low. TnCCLR bit not used 4. If the TnIO1 and TnIO0 bits are both value of the internal counter and can therefore be used set high. TPn_0 or TPn_1 pin to be a rising edge. Counting the number of overflow interrupt signals from the CCRP can be a use- Capture Input Mode ful method in measuring long pulse widths.TnOC and TnPOL bits not used 5. in this way the CCRP value can be used to the TnON bit changes from low to high when the counter control the maximum counter value. Flag TnPF CCRA Value XX YY XX YY TnIO1. This mode en. a to run. spective of what happens on the TPn_0 or TPn_1 pin.1.Disable Capture Capture Input Mode Note: 1. falling edge or both rising and falling edges. 2009 . CCRP sets counter maximum value Rev. TnM1. When a match from Comparator A will also generate a TM inter. compare match occurs from Comparator P. HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 However a compare match from Comparator A will also be latched into the CCRA registers and a TM interrupt automatically clear the TnON bit and thus generate the generated. CCRP compare match occurs the counter will reset rupt. The counter is started ture Mode. TnIO0 Value 00 . output.Falling edge 10 . The TnIO1 To select this mode bits TnM1 and TnM0 in the TMnC1 and TnIO0 bits can select the active trigger edge on the register should be set to 01 respectively. Irrespective of what events occur on the Single Pulse output trailing edge. falling edge or ables external signals to capture and store the present both edge types. TnM0 = 01 Value Counter overflow CCRP Stop Counter Reset YY XX Pause Resume Time TnON bit TnPAU bit Active Active Active edges TM Capture Pin edge edge CCRA Int. The counter can only be reset back to zero when back to zero. Flag TnAF CCRP Int. put capture operation to be executed. then any transitions on this pin may cause an in- tiated using the application program. The TnCCLR and When the required edge transition appears on the TnDPX bits are not used in this Mode. a TM inter- The TnCCLR and TnDPX bits are not used in this Mode. In the Single Pulse Mode CCRP is not used.Rising edge 01 . When a CCRP restarts. rupt will also be generated. The external signal is supplied on the TPn_0 or TPn_1 however it must be noted that the counter will continue pin. This is because if the pin is setup as an when the TnON bit changes from low to high which is ini. TPn_0 or TPn_1 pin the present value in the counter will Counter TnM1. care must be taken if the TM is in the Input Cap- TnIO0 bits in the TMnC1 register.Both edges 11 . the active As the TPn_0 or TPn_1 pin is pin shared with other func- edge transition type is selected using the TnIO1 and tions.00 105 November 3.

TP1B_0. TP1B_1. CTM Name TM No. T n B M 0 T n B P O L C C R B T n B IO 1 .b it C o m p a ra to r B M a tc h T P n B -1 C o n tro l C o n tro l In p u t/O u tp u t C o m p a ra to r B T P n B -2 T n B F In te rru p t T n B M 1 . T n A IO 0 C C R A E d g e D e te c to r T n B O C T P n B -0 O u tp u t P o la r ity T P n B P in 1 0 . T n IO 0 Enhanced Type TM Block Diagram Rev. also usually be generated. Comparator B and Com. which are Compare Match Output. TP1B_2 HT68F50 10-bit ETM 1 TCK1 TP1A. pin and can also control output pins.1. conditions are selected using relevant internal registers. C C R P C o m p a ra to r P M a tc h 3 . The counter will clock source. TP1B_0. compare match with one of its associated comparators. These comparators will compare the value in When these conditions occur. T n B IO 0 E d g e D e te c to r T n IO 1 . T n A M 0 T n A P O L T C K n 1 1 1 T n P A U b 0 ~ b 9 T n A IO 1 . T n A IO 0 C o m p a ra to r A M a tc h T n A F T n C K 2 ~ T n C K 0 1 0 .b it U p /D o w n C o u n te r C o n tro l C o n tro l In p u t/O u tp u t fT B C 1 0 0 1 R e s e rv e d 1 0 1 1 1 0 T n O N T n C C L R T n A M 1 . CCRB and CCRP registers. The Enhanced TM can also be controlled with an external in- put pin and can drive three or four external output pins.00 106 November 3. TP1B_2 Enhanced TM Operation The only way of changing the value of the 10-bit counter At its core is a 10-bit count-up/count-down counter using the application program. TP1B_2 HT68F60 10-bit ETM 1 TCK1 TP1A. parator P. TP1B_0. Cap- ture Input.b it In te rru p t C o m p a ra to r A T n A IO 1 . TP1B_1 HT68F40 10-bit ETM 1 TCK1 TP1A. Comparator A. Single Pulse Output and PWM Output modes. All operating setup pared with all counter bits. 2009 .b it C o m p a r a to r P T n P F In te rru p t b 7 ~ b 9 T n A O C fS Y S /4 0 0 0 fS Y S 0 0 1 fH /1 6 0 1 0 C o u n te r O u tp u t P o la r ity T P n A P in fH /6 4 0 1 1 C le a r 0 T P n A 1 0 . is to clear the counter by which is driven by a user selectable internal or external changing the TnON bit from low to high. TM Input Pin TM Output Pin HT68F20 ¾ ¾ ¾ ¾ HT68F30 10-bit ETM 1 TCK1 TP1A. TP1B_1. can compared with the highest 3-bits in the counter while be driven by different clock sources including an input CCRA and CCRB are 10-bits wide and therefore com. There are three internal comparators with also be cleared automatically by a counter overflow or a the names. a TM interrupt signal will the counter with the CCRA. TP1B_1. Timer/Event Counter. HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 Enhanced Type TM . The Enhanced Type TM can The CCRP comparator is 3-bits wide whose value is operate in a number of different operational modes.ETM The Enhanced Type TM contains five operating modes. TP1B_0.

Bit 6~4 T1CK2~T1CK0: Select TM1 Counter clock 000: fSYS/4 001: fSYS 010: fH/16 011: fH/64 100: fTBC 101: Reserved 110: TCK1 rising edge clock 111: TCK1 falling edge clock These three bits are used to select the clock source for the TM. clearing the bit disables the TM. 2009 . while two read/write register pairs exist to store the internal 10-bit CCRA and CCRB value. Clearing this bit to zero will stop the counter from counting and turn off the TM which will reduce its power consumption. Selecting the Reserved clock input will effectively disable the internal counter. however when the bit changes from high to low. When in a Pause condition the TM will remain powered up and continue to consume power.1. When the bit changes state from low to high the internal counter value will be reset to zero. A read only register pair exists to store the internal counter 10-bit value.HT68F30/HT68F40/HT68F50/HT68F60 ¨ TM1C0 Register . the internal counter will retain its residual value until the bit returns high again. Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 TM1C0 T1PAU T1CK2 T1CK1 T1CK0 T1ON T1RP2 T1RP1 T1RP0 TM1C1 T1AM1 T1AM0 T1AIO1 T1AIO0 T1AOC T1APOL T1CDN T1CCLR TM1C2 T1BM1 T1BM0 T1BIO1 T1BIO0 T1BOC T1BPOL T1PWM1 T1PWM0 TM1DL D7 D6 D5 D4 D3 D2 D1 D0 TM1DH ¾ ¾ ¾ ¾ ¾ ¾ D9 D8 TM1AL D7 D6 D5 D4 D3 D2 D1 D0 TM1AH ¾ ¾ ¾ ¾ ¾ ¾ D9 D8 TM1BL D7 D6 D5 D4 D3 D2 D1 D0 TM1BH ¾ ¾ ¾ ¾ ¾ ¾ D9 D8 10-bit Enhanced TM Register List (if ETM is TM1) · 10-bit Enhanced TM Register List . The counter will retain its residual value when this bit changes from low to high and resume counting from this value when the bit changes to a low value again. The external pin clock source can be chosen to be active on the rising or falling edge. HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 Enhanced Type TM Register Description Overall operation of the Enhanced TM is controlled using a series of registers. Rev. Setting the bit high enables the counter to run. The clock source fSYS is the system clock. the details of which can be found in the oscillator section.00 107 November 3. while fH and fTBC are other internal clocks. Clearing the bit to zero restores normal counter operation.10-bit ETM Bit 7 6 5 4 3 2 1 0 Name T1PAU T1CK2 T1CK1 T1CK0 T1ON T1RP2 T1RP1 T1RP0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7 T1PAU: TM1 Counter Pause Control 0: run 1: pause The counter can be paused by setting this bit high. Bit 3 T1ON: TM1 Counter On/Off Control 0: Off 1: On This bit controls the overall on/off function of the TM. The remaining three registers are control registers which setup the different operating and control modes as well as the three CCRP bits.

HT68F20/HT68F30/HT68F40/HT68F50/HT68F60

If the TM is in the Compare Match Output Mode then the TM output pin will be reset to its initial
condition, as specified by the T1OC bit, when the T1ON bit changes from low to high.
Bit 2~0 T1RP2~T1RP0: TM1 CCRP 3-bit register, compared with the TM1 Counter bit 9~bit 7
Comparator P Match Period
000: 1024 TM1 clocks
001: 128 TM1 clocks
010: 256 TM1 clocks
011: 384 TM1 clocks
100: 512 TM1 clocks
101: 640 TM1 clocks
110: 768 TM1 clocks
111: 896 TM1 clocks
These three bits are used to setup the value on the internal CCRP 3-bit register, which are then
compared with the internal counter¢s highest three bits. The result of this comparison can be
selected to clear the internal counter if the T1CCLR bit is set to zero. Setting the T1CCLR bit to
zero ensures that a compare match with the CCRP values will reset the internal counter. As the
CCRP bits are only compared with the highest three counter bits, the compare values exist in 128
clock cycle multiples. Clearing all three bits to zero is in effect allowing the counter to overflow at
its maximum value.

¨ TM1C1 Register - 10-bit ETM

Bit 7 6 5 4 3 2 1 0
Name T1AM1 T1AM0 T1AIO1 T1AIO0 T1AOC T1APOL T1CDN T1CCLR
R/W R/W R/W R/W R/W R/W R/W R R/W
POR 0 0 0 0 0 0 0 0

Bit 7~6 T1AM1~T1AM0: Select TM1 CCRA Operating Mode
00: Compare Match Output Mode
01: Capture Input Mode
10: PWM Mode or Single Pulse Output Mode
11: Timer/Counter Mode
These bits setup the required operating mode for the TM. To ensure reliable operation the TM
should be switched off before any changes are made to the T1AM1 and T1AM0 bits. In the
Timer/Counter Mode, the TM output pin control must be disabled.
Bit 5~4 T1AIO1~T1AIO0: Select TP1A output function
Compare Match Output Mode
00: No change
01: Output low
10: Output high
11: Toggle output
PWM Mode/ Single Pulse Output Mode
00: Force inactive state
01: Force active state
10: PWM output
11: Single pulse output
Capture Input Mode
00: Input capture at rising edge of TP1A
01: Input capture at falling edge of TP1A
10: Input capture at falling/rising edge of TP1A
11: Input capture disabled
Timer/counter Mode
Unused
These two bits are used to determine how the TM output pin changes state when a certain
condition is reached. The function that these bits select depends upon in which mode the TM is
running.

Rev.1.00 108 November 3, 2009

HT68F20/HT68F30/HT68F40/HT68F50/HT68F60

In the Compare Match Output Mode, the T1AIO1 and T1AIO0 bits determine how the TM
output pin changes state when a compare match occurs from the Comparator A. The TM output
pin can be setup to switch high, switch low or to toggle its present state when a compare match
occurs from the Comparator A. When the bits are both zero, then no change will take place on
the output. The initial value of the TM output pin should be setup using the T1AOC bit in the
TM1C1 register. Note that the output level requested by the T1AIO1 and T1AIO0 bits must be
different from the initial value setup using the T1AOC bit otherwise no change will occur on the
TM output pin when a compare match occurs. After the TM output pin changes state it can be
reset to its initial level by changing the level of the T1ON bit from low to high.
Bit 3 T1AOC: TP1A Output control bit
Compare Match Output Mode
0: Initial low
1: Initial high
PWM Mode/ Single Pulse Output Mode
0: Active low
1: Active high
This is the output control bit for the TM output pin. Its operation depends upon whether TM is
being used in the Compare Match Output Mode or in the PWM Mode/ Single Pulse Output Mode.
It has no effect if the TM is in the Timer/Counter Mode. In the Compare Match Output Mode it
determines the logic level of the TM output pin before a compare match occurs. In the PWM
Mode it determines if the PWM signal is active high or active low.
Bit 2 T1APOL: TP1A Output polarity Control
0: Non-invert
1: Invert
This bit controls the polarity of the TP1A output pin. When the bit is set high the TM output pin
will be inverted and not inverted when the bit is zero. It has no effect if the TM is in the
Timer/Counter Mode.
Bit 1 T1CDN: TM1 Counter count up or down flag
0: Count up
1: Count down
Bit 0 T1CCLR: Select TM1 Counter clear condition
0: TM1 Comparator P match
1: TM1 Comparator A match
This bit is used to select the method which clears the counter. Remember that the Enhanced
TM contains two comparators, Comparator A and Comparator P, either of which can be selected
to clear the internal counter. With the T1CCLR bit set high, the counter will be cleared when a
compare match occurs from the Comparator A. When the bit is low, the counter will be cleared
when a compare match occurs from the Comparator P or with a counter overflow. A counter
overflow clearing method can only be implemented if the CCRP bits are all cleared to zero. The
T1CCLR bit is not used in the PWM, Single Pulse or Input Capture Mode.

Rev.1.00 109 November 3, 2009

HT68F20/HT68F30/HT68F40/HT68F50/HT68F60

¨ TM1C2 Register - 10-bit ETM

Bit 7 6 5 4 3 2 1 0
Name T1BM1 T1BM0 T1BIO1 T1BIO0 T1BOC T1BPOL T1PWM1 T1PWM0
R/W R/W R/W R/W R/W R/W R/W R R/W
POR 0 0 0 0 0 0 0 0

Bit 7~6 T1BM1~T1BM0: Select TM1 CCRB Operating Mode
00: Compare Match Output Mode
01: Capture Input Mode
10: PWM Mode or Single Pulse Output Mode
11: Timer/Counter mode
These bits setup the required operating mode for the TM. To ensure reliable operation the TM
should be switched off before any changes are made to the T1BM1 and T1BM0 bits. In the
Timer/Counter Mode, the TM output pin control must be disabled.
Bit 5~4 T1BIO1~T1BIO0: Select TP1B_0, TP1B_1, TP1B_2 output function
Compare Match Output Mode
00: No change
01: Output low
10: Output high
11: Toggle output
PWM Mode/Single Pulse Output Mode
00: Force inactive state
01: Force active state
10: PWM output
11: Single pulse output
Capture Input Mode
00: Input capture at rising edge of TP1B_0, TP1B_1, TP1B_2
01: Input capture at falling edge of TP1B_0, TP1B_1, TP1B_2
10: Input capture at falling/rising edge of TP1B_0, TP1B_1, TP1B_2
11: Input capture disabled
Timer/counter Mode
Unused
These two bits are used to determine how the TM output pin changes state when a certain
condition is reached. The function that these bits select depends upon in which mode the
TM is running.
In the Compare Match Output Mode, the T1BIO1 and T1BIO0 bits determine how the TM
output pin changes state when a compare match occurs from the Comparator A. The TM output
pin can be setup to switch high, switch low or to toggle its present state when a compare match
occurs from the Comparator A. When the bits are both zero, then no change will take place on
the output. The initial value of the TM output pin should be setup using the T1BOC bit in the
TM1C2 register. Note that the output level requested by the T1BIO1 and T1BIO0 bits must be
different from the initial value setup using the T1BOC bit otherwise no change will occur on the
TM output pin when a compare match occurs. After the TM output pin changes state it can be
reset to its initial level by changing the level of the T1ON bit from low to high.
Bit 3 T1BOC: TP1B_0, TP1B_1, TP1B_2 Output control bit
Compare Match Output Mode
0: Initial low
1: Initial high
PWM Mode/ Single Pulse Output Mode
0: Active low
1: Active high
This is the output control bit for the TM output pin. Its operation depends upon whether TM is
being used in the Compare Match Output Mode or in the PWM Mode/ Single Pulse Output Mode.
It has no effect if the TM is in the Timer/Counter Mode. In the Compare Match Output Mode it
determines the logic level of the TM output pin before a compare match occurs. In the PWM
Mode it determines if the PWM signal is active high or active low.

Rev.1.00 110 November 3, 2009

HT68F20/HT68F30/HT68F40/HT68F50/HT68F60

Bit 2 T1BPOL: TP1B_0, TP1B_1, TB1B_2 Output polarity Control
0: Non-invert
1: Invert
This bit controls the polarity of the TP1B_0, TP1B_1, TP1B_2 output pin. When the bit is set
high the TM output pin will be inverted and not inverted when the bit is zero. It has no effect if the
TM is in the Timer/Counter Mode.
Bit 1~0 T1PWM1~T1PWM0: Select PWM Mode
00: Edge aligned
01: Centre aligned, compare match on count up
10: Centre aligned, compare match on count down
11: Centre aligned, compare match on count up or down

¨ TM1DL Register - 10-bit ETM

Bit 7 6 5 4 3 2 1 0
Name D7 D6 D5 D4 D3 D2 D1 D0
R/W R R R R R R R R
POR 0 0 0 0 0 0 0 0

Bit 7~0 TM1DL: TM1 Counter Low Byte Register bit 7~bit 0
TM1 10-bit Counter bit 7~bit 0

¨ TM1DH Register - 10-bit ETM

Bit 7 6 5 4 3 2 1 0
Name ¾ ¾ ¾ ¾ ¾ ¾ D9 D8
R/W ¾ ¾ ¾ ¾ ¾ ¾ R R
POR ¾ ¾ ¾ ¾ ¾ ¾ 0 0

Bit 7~2 Unimplemented, read as ²0²
Bit 1~0 TM1DH: TM1 Counter High Byte Register bit 1~bit 0
TM1 10-bit Counter bit 9~bit 8

¨ TM1AL Register - 10-bit ETM

Bit 7 6 5 4 3 2 1 0
Name D7 D6 D5 D4 D3 D2 D1 D0
R/W R/W R/W R/W R/W R/W R/W R/W R/W
POR 0 0 0 0 0 0 0 0

Bit 7~0 TM1AL: TM1 CCRA Low Byte Register bit 7~bit 0
TM1 10-bit CCRA bit 7~bit 0

¨ TM1AH Register - 10-bit ETM

Bit 7 6 5 4 3 2 1 0
Name ¾ ¾ ¾ ¾ ¾ ¾ D9 D8
R/W ¾ ¾ ¾ ¾ ¾ ¾ R/W R/W
POR ¾ ¾ ¾ ¾ ¾ ¾ 0 0

Bit 7~2 Unimplemented, read as ²0²
Bit 1~0 TM1AH: TM1 CCRA High Byte Register bit 1~bit 0
TM1 10-bit CCRA bit 9~bit 8

Rev.1.00 111 November 3, 2009

Pulse Output Capture Output Mode Output Mode ter Mode Mode Mode CCRB Compare Match Output Mode Ö Ö Ö ¾ ¾ CCRB Timer/Counter Mode Ö Ö Ö ¾ ¾ CCRB PWM Output Mode Ö Ö Ö ¾ ¾ CCRB Single Pulse Output Mode ¾ ¾ ¾ Ö ¾ CCRB Input Capture Mode Ö Ö Ö ¾ Ö Compare Output Mode If the TnCCLR bit in the TMnC1 register is high then the To select this mode. One is when a com- pare match occurs from Comparator P. the CCRP bits is less than that of the CCRA registers. TnAM0 and TnBM1. PWM Output Mode. will both be generated. Single Pulse Output Mode. a compare match from Therefore when TnCCLR is high no TnPF interrupt re- Comparator A and a compare match from Comparator quest flag will be generated.10-bit ETM Bit 7 6 5 4 3 2 1 0 Name ¾ ¾ ¾ ¾ ¾ ¾ D9 D8 R/W ¾ ¾ ¾ ¾ ¾ ¾ R/W R/W POR ¾ ¾ ¾ ¾ ¾ ¾ 0 0 Bit 7~2 Unimplemented. Compare Match Output Mode.00 112 November 3. In this mode once the counter is en.1. Capture Input Mode or Timer/Counter Mode. rupt request flag will be generated even if the value of abled and running it can be cleared by three methods. However. counter will be cleared when a compare match occurs TnBM0 in the TMnC1/TMnC2 registers should be all from Comparator A. bits TnAM1. and the TnBM1 and TnBM0 bits in the TMnC2 register. The operating mode is selected using the TnAM1 and TnAM0 bits in the TMnC1. 2009 . When the TnCCLR bit is low. P. read as ²0² Bit 1~0 TM1BH: TM1 CCRB High Byte Register bit 1~bit 0 TM1 10-bit CCRB bit 9 ~ bit 8 Enhanced Type TM Operating Modes The Enhanced Type TM can operate in one of five operating modes. These are a counter overflow. Rev. CCRA Com. HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 ¨ TM1BL Register . here only the TnAF inter- cleared to zero.10-bit ETM Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7 ~ 0 TM1BL: TM1 CCRB Low Byte Register bit 7~bit 0 TM1 10-bit CCRB bit 7~bit 0 ¨ TM1BH Register . the other is when the CCRP bits are all zero which allows the counter to overflow. there are two ways in which the counter can be cleared. CCRA CCRA Single CCRA Input CCRA PWM ETM Operating Mode pare Match Timer/Coun. Here both the TnAF and TnPF interrupt re- quest flags for Comparator A and Comparator P respec- tively.

and the TnBIO1 and TnBIO0 bits in the zero then no pin change will take place.00 113 November 3. generated from Comparator B. TnAM1. TMnC2 register for ETM CCRB. Note of the TnAIO1 and TnAIO0 bits in the TMnC1 register for that if the TnAIO1. gle from its present condition when a compare match ter a compare match occurs from Comparator A or Com. will have no put pin. occurs from Comparator A or a compare match occurs parator B. is setup using the TnAOC or TnBOC bit for output pin changes state is determined by the condition TPnA or TPnB_0. TPnA output pin controlled only by TnAF flag 3. which is setup after the TnON bit changes from effect on the TM output pin.1. The TM TPnA pin) and TnBIO1. With TnCCLR = 0 the Comparator P match will clear the counter 2. TnAM0 = 00 overflow CCRP = 0 CCRP > 0 Counter cleared by CCRP value 0x3FF CCRP > 0 CCRP Pause Resume Counter Stop Reset CCRA Time TnON bit TnPAU bit TnAPOL bit CCRP Int. HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 As the name of the mode suggests. TnBIO0 bits (for the TPnB_0. after a comparison be selected using the TnAIO1. TnAIO0 = 10 Output Pin Active High Output Select Reset to initial value Here TnAIO1. TnBIO0 bits are ETM CCRA. the TM output pin. output pin condition however only changes state when TPnB_1 or TPnB_2 pins) to go high. TPnB_1.TnCCLR = 0 Note: 1. The TM output pin can Counter Value Counter TnCCLR = 0. The TnPF interrupt request flag. Flag TnPF CCRA Int. Output pin reset to initial state by TnON bit rising edge Rev.TnAIO0 and TnBIO1. TnAIO0 bits (for the is made. 2009 . TnAIO0 = 11 Toggle Output Select ETM CCRA Compare Match Output Mode . to go low or to tog- an TnAF or TnBF interrupt request flag is generated af. The way in which the TM low to high. TPnB_2 output pins. Flag TnAF TPnA O/P Pin Output Pin set Output not affected by TnAF flag Output inverts to Initial Level Output Toggle Remains High until reset by TnON bit when TnAPOL is high Low if TnAOC = 0 with TnAF flag Now TnAIO1. will change state. The initial condition of the TM out- from a compare match from Comparator P.

2009 .TnCCLR = 0 Note: 1. Output pin reset to initial state by TnON bit rising edge Rev.1. With TnCCLR = 0 the Comparator P match will clear the counter 2. TnBIO0 = 10 Output Pin Active High Output Select Reset to initial value Here TnBIO1. TnBM1. TnBIO0 = 11 Toggle Output Select ETM CCRB Compare Match Output Mode . Flag TnPF CCRB Int.00 114 November 3. HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 Counter Value Counter TnCCLR = 0. Flag TnBAF TPnB O/P Pin Output inv erts Output Pin set Output not affected by TnBF flag Output Toggle when TnBPOL is high to Initial Level Remains High until reset by TnON bit Low if TnBOC = 0 with TnBF flag Now TnBIO1. TPnB output pin controlled only by TnBF flag 3. TnBM0 = 00 overflow CCRP = 0 CCRP > 0 Counter cleared by CCRP value 0x3FF CCRP > 0 CCRP Pause Resume Counter Stop Reset CCRB Time TnON bit TnPAU bit TnBPOL bit CCRP Int.

TPnA output pin reset to initial state by TnON rising edge 4. TnAM0 = 00 Value CCRA = 0 CCRA > 0 Counter cleared by CCRA value Counter overflows 0x3FF CCRA = 0 CCRA Pause Resume Counter Stop Reset CCRP Time TnON bit TnPAU bit TnAPOL bit No TnAF flag CCRA Int. generated on CCRA overflow Flag TnAF CCRP Int.00 115 November 3. 2009 . HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 Counter TnCCLR = 1. Flag TnPF Output does TnPF not not change generated TPnA O/P Pin Output Pin set Output not affected by TnAF flag to Initial Level Output Toggle remains High until reset by TnON bit Output inverts Low if TnAOC = 0 with TnAF flag when TnAPOL is high Now TnAIO1.1.TnCCLR = 1 Note: 1. TnAM1. TnAIO0 = 10 Active High Output Select Output Pin Reset to initial value Here TnAIO1. With TnCCLR = 1 the Comparator A match will clear the counter 2. TPnA output pin controlled only by TnAF flag 3. TnPF flags not generated when TnCCLR = 1 Rev. TnAIO0 = 11 Toggle Output Select ETM CCRA Compare Match Output Mode .

TPnB output pin controlled only by TnBF flag 3. TnBIO0 = 11 Toggle Output Select ETM CCRB Compare Match Output Mode . TPnB output pin reset to initial state by TnON rising edge 4. TnPF flags not generated when TnCCLR = 1 Rev. generated on CCRA overflow Flag TnAF CCRB Int. TnBIO0 = 10 Active High Output Select Output Pin Reset to initial value Here TnBIO1.00 116 November 3.1. With TnCCLR = 1 the Comparator A match will clear the counter 2. TnBM1.TnCCLR = 1 Note: 1. 2009 . HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 Counter TnCCLR = 1. TnBM0 = 00 Value CCRA = 0 CCRA > 0 Counter cleared by CCRA value Counter overflows 0x3FF CCRA = 0 CCRA Pause Resume Counter Stop Reset CCRB Time TnON bit TnPAU bit TnBPOL bit No TnAF flag CCRA Int. Flag TnBF TPnB O/P Pin Output Pin set Output not affected by TnBF flag to Initial Level Output Toggle remains High until reset by TnON bit Output inverts Low if TnBOC = 0 with TnBF flag when TnBPOL is high Now TnBIO1.

TnCCLR=1 CCRA 1 2 3 511 512 1021 1022 1023 Period 1 2 3 511 512 1021 1022 1023 B Duty CCRB · ETM. quire functions such as motor control. TnAM0 and TnBM1. · ETM. Center-aligned Mode. As the TM output pin is not used in PWM outputs on their relative TPnA and TPnB pins. which can be either edge or centre type. used to setup different duty cycle values to provide dual derstand its function. thus reduc- function within the TM is useful for applications which re. With all power currents switching on at the TnAM0 and TnBM1. the PWM period the polarity of the PWM output waveform. and TPnA output pin is not used. the leading edge of the PWM signals PWM Output Mode will all be generated concurrently when the counter is re- To select this mode. TnCCLR=0 CCRP 001b 010b 011b 100b 101b 110b 111b 000b Period 128 256 384 512 640 768 896 1024 A Duty CCRA B Duty CCRB · ETM. level. power applications. In the PWM mode. TnAIO0 and can be controlled. Edge-aligned Mode. Center-aligned Mode. The TnAOC and TnBOC bits in the TMnC1 and varying equivalent DC RMS values. PWM Mode. In edge alignment. Now both CCRA and CCRB registers can be for the Compare Match Output Mode can be used to un. The PWM PWM active signals will occur sequentially. bits TnAM1. the PWM period is set using Timer/Counter Mode the TM output pin is not used. the TnCCLR bit is output or to force the TM output pin to a fixed high or low used to determine in which way the PWM period is con. from either the Comparator A. this mode. TnAIO0 and TnBIO1. PWM Mode. TnBIO0 bits pairs are used to enable the PWM extremely flexible.00 117 November 3. In centre alignment the centre of the TnBIO0 bits should be set to 10 respectively. HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 Timer/Counter Mode can be finely controlled using the CCRA registers. TMnC2 register are used to select the required polarity of As both the period and duty cycle of the PWM waveform the PWM waveform while the two TnAIO1. The CCRP bits are not used set high. The exception is that in the TnCCLR bit cleared to zero. one of the eight values of the three CCRP bits. PWM Mode. one for each of the CCRA. TnAM1. TnCCLR=0 CCRP 001b 010b 011b 100b 101b 110b 111b 000b Period 256 512 768 1024 1280 1536 1792 2046 A Duty (CCRA´2)-1 B Duty (CCRB´2)-1 · ETM.1. In this To select this mode. il. TnCCLR=1 CCRA 1 2 3 511 512 1021 1022 1023 Period 2 4 6 1022 1024 2042 2044 2046 B Duty (CCRB´2)-1 Rev. The TnAPOL and TnBPOL bit are used to reverse trolled. in multi- Therefore the above description and Timing Diagrams ples of 128. the required bit pairs. alignment type. will be generated when a compare match occurs frequency but of varying duty cycle on the TM output pin. case the CCRB registers are used to set the PWM duty TnBM0 in the TMnC1 and TMnC2 register should all be value (for TPnB output pins). heating control. Interrupt flags. The Timer/Counter Mode operates in an identi. set to zero. TnBM0 should be set to 10 respec. the choice of generated waveform is TnBIO1. CCRB and lumination control etc. same time. ing the level of simultaneous power switching currents. Comparator B or Com- a square wave AC waveform can be generated with parator P. the pin can be used as a normal I/O pin or The TnPWM1 and TnPWM0 bits determine the PWM other pin-shared function. PWM Mode. The PWM output can cal way to the Compare Match Output Mode generating only be generated on the TPnB output pins. With the TnCCLR bit set high. With the the same interrupt flags. By providing a signal of fixed CCRP. 2009 . this may give rise to problems in higher tively and also the TnAIO1. Edge-aligned Mode.

Flag TnAF CCRB Int. TnBIO0) = 00 or 01 3.1. Internal PWM function continues even when TnAIO1. 2009 . TnAIO0 ( or TnBIO1. TnA(B)M0 = 10 TnPWM1/TnPWM0 = 00 CCRP Counter reset Counter Stops when TnON Paus e Resume if TnON bit low returns high CCRA CCRB Time TnON bit TnPAU bit TnAPOL bit Interrupt still generated CCRA Int. HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 TnCCLR = 0. Counter Value Counter Cleared by CCRP Mode Bits TnA(B)M1.outputs remain TnAIO1. TnAIO0 = 00 TnAIO1. CCRA controls TPnA PWM duty and CCRB controls TPnB PWM duty Rev.Edge Aligned Note: 1. TnAIO0 = 10 Output Inactive TPnA Pin TnAOC = 1 PWM resumes operation . Here TnCCLR = 0 therefore CCRP clears counter and determines PWM period 2. Flag TnBF CCRP Int. Duty Cycle TnAIO0 = 00 set by CCRB Output is Inactive PWM Period set by CCRP PWM runs internally PWM Mode . Flag TnPF TnAIO1. TnAIO0 = 10 Output Inverts Duty Cycle at same level set by CCRA Resume PWM Output When TnAPOL = 1 TPnB Pin TnBOC = 1 TPnB Pin TnBOC = 0 Here TnAIO1.00 118 November 3. TnAIO0 = 10 PWM Output TnAIO1.

1. 2009 . CCRA controls TPnB PWM period and CCRB controls TPnB PWM duty Rev.Edge Aligned Note: 1. Flag TnAF CCRB Int. Here TnCCLR = 1 therefore CCRA clears counter and determines PWM period 2. Internal PWM function continues even when TnBIO1. HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 TnCCLR = 1. TnBIO0 = 00 or 01 3.00 119 November 3.outputs remain at same level TPnB Pin TnBOC = 1 TPnB Pin TnBOC = 0 Duty Cycle Output Inverts s et by CCRB When TnBPOL = 1 PWM Period set by CCRA PWM Mode . TnA(B)M0 = 10 TnPW M1/TnPWM0 = 00 Counter Counter Cleared by CCRA Value CCRA Counter reset Counter Stops when TnON Paus e Resume if TnON bit low returns high CCRB Time TnON bit TnPAU bit TnBPOL bit CCRA Int. Mode Bits TnA(B)M1. Flag TnBF PWM resumes operation .

2009 . TnAIO0 = 10 PWM Output PWM Output TPnA Pin TnAOC = 1 Duty Cycle set by CCRA Output Inverts When TnAPOL = 1 TPnB Pin TnBOC = 1 TPnB Pin TnBOC = 0 Duty Cycle set by CCRB PW M Period set by CCRP PWM Mode . Mode Bits TnA(B)M1. TnBIO0) = 00 or 01 4. Flag TnAF CCRB Int.Centre Aligned Note: 1. TnA(B)M0 = 10 TnPWM1/TnPWM0 = 11 Counter Value Counter Stops CCRP if TnON bit low Counter reset when TnON returns high Pause Resume CCRA CCRB Time TnON bit TnPAU bit TnAPOL bit CCRA Int. Flag TnPF TnAIO1. TnAIO0 = 10 TnAIO1.00 120 November 3. CCRA controls TPnA PWM duty and CCRB controls TPnB PWM duty Rev. Here TnCCLR = 0 therefore CCRP clears counter and determines PWM period 2. TnAIO0 ( or TnBIO1. HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 TnCCLR = 0. Flag TnBF CCRP Int. Internal PWM function continues even when TnAIO1.1. TnAIO0 = 00 Output Inactive TnAIO1. TnPWM1/TnPWM0 = 11 therefore PWM is centre aligned 3.

Mode Bits TnA(B)M1. HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 TnCCLR = 1. Internal PWM function continues even when TnBIO1.1. 2009 . Flag TnAF TPnB Pin TnBOC = 1 TPnB Pin TnBOC = 0 Duty Cycle set by CCRB Output Inverts PWM Period When TnBPOL = 1 set by CCRA PWM Mode .00 121 November 3. TnPWM1/TnPWM0 = 11 therefore PWM is centre aligned 3. Here TnCCLR = 1 therefore CCRA clears counter and determines PWM period 2. Flag TnBF CCRA Int. TnA(B)M0 = 10 TnPWM1/TnPWM0 = 11 Counter Value Counter Stops CCRA Counter reset when if TnON bit low TnON returns high Pause Resume CCRB Time TnON bit TnPAU bit TnBPOL bit CCRB Int. CCRA controls the TPnB PWM period and CCRB controls the TPnB PWM duty Rev.Centre Aligned Note: 1. TnBIO0 = 00 or 01 4.

1. L e a d in g E d g e T r a ilin g E d g e S /W C o m m a n d S /W C o m m a n d S E T "T n O N " C L R "T n O N " T n O N b it T n O N b it o r o r 0 ® 1 1 ® 0 T C K n P in T r a n s itio n C C R A M a tc h C o m p a re T P n A O u tp u t P in P u ls e W id th = C C R A V a lu e T P n B O u tp u t P in P u ls e W id th = C C R A . the required bit pairs. The generated TnAM0 and TnBM1. When the TnON bit transitions to a high level. The TnON bit should remain To select this mode.C C R B V a lu e Single Pulse Generation Rev. Single Pulse output trailing edge of TPnA and TPnB. high when the pulse is in its active state. 2009 . However in the Single match from Comparator A and Comparator B will also Pulse Mode. pulse trailing edge of TPnA and TPnB will be generated tively and also the corresponding TnAIO1. as the name suggests. which can be implemented used to control the pulse width of TPnB. TnBM0 should be set to 10 respec. HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 Single Pulse Output Mode TPnA will be generated. TnBIO0 bits should be set to 11 respectively. The CCRA-CCRB value can be match from Comparator B. plemented using the application program or when a The Single Pulse Output Mode. the TnON bit can also be made to automat.00 122 November 3. which can be im- TnBIO1. TnAM1. which can be im. generate TM interrupts. TnAIO0 and when the TnON bit is cleared to zero. In plemented using the application program. However a compare match from Comparator A will also The trigger for the pulse TPnA output leading edge is a automatically clear the TnON bit and thus generate the low to high transition of the TnON bit. In the Single Pulse TPnA. compare match occurs from Comparator A. the Mode CCRP is not used. The counter can only be reset ically change from low to high using the external TCKn back to zero when the TnON bit changes from low to pin. will generate a single shot pulse on the TM output pin. The TnCCLR bit is also not counter will start running and the pulse leading edge of used. The trigger this way the CCRA value can be used to control the for the pulse TPnB output leading edge is a compare pulse width of TPnA. which will in turn initiate the Single Pulse output of high when the counter restarts. A compare using the application program.

TnAIO0 and TnBIO1. TnAIO0 and TnBIO1. TnAIO0 and TnBIO1. TnAM0 and TnBM1. TnBIO0 = 11 by CCRA CCRA Counter reset Counter Stops when TnON Pause Resume by software returns high CCRB Time TnON bit Auto. TnAIO0 and Output Inverts Pulse Width TnAIO1.CCRB TPnB Pin TnBOC = 0 Output Inverts When TnBPOL = 1 ETM . TnAIO0 and TnBIO1. TnBM0 = 10. Flag TnBF CCRA Int. Flag TnAF TnAIO1. 2009 .Single Pulse Mode Rev. Counter Value Counter Stopped TnAIO1. TnBPOL bit CCRB Int. TnBIO0 = 11 TPnA Pin TnAOC = 1 TPnA Pin TnAOC = 0 Here TnAIO1.00 123 November 3.1. TnBIO0 = 00 Output Inactive = 11 Single Pulse Output TnAIO1. HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 TnAM1. TnBIO0 = 00 Resume Single Pulse Output set by CCRA Output Forced to Inactive TPnB Pin level but counter keeps running internally TnBOC = 1 Pulse Width set by CCRA . s et by TCKn pin Software Cleared by Software Software Software Trigger CCRA match Trigger Clear Trigger TCKn pin TCKn pin Trigger TnPAU bit TnAPOL. TnBIO0 TnAIO1. TnBIO0 = 11 When TnAPOL = 1 TnBIO1. TnAIO0 and TnBIO1.

in this way the CCRP value can be used to control To select this mode bits TnAM1. also be generated. then any transitions on this pin registers and a TM interrupt generated. 2009 . TnAPOL and TnBPOL TPnB_2 pins the counter will continue to free run until bits are not used in this mode. falling edge or both edge types. the maximum counter value. TnBIO0 bits in the TMnC1 and tive of what happens on the TPnA and TPnB_0. then no capture operation will take place irrespec- TnAIO0 and TnBIO1. the TnON bit changes from high to low. a TM interrupt will set to 01 respectively. TnAM0 and TnBM1. application program. TPnB_1. Counting the number of overflow in- nals to capture and store the present value of the inter. The counter is started when the TnON TPnB_1. When a CCRP compare TnBM0 in the TMnC1 and TMnC2 registers should be match occurs from Comparator P. TnAIO0 and TnBIO1. however it must be noted that bit changes from low to high which is initiated using the the counter will continue to run. TnBOC. TnAIO0 and such as pulse width measurements. TPnB_2 on the TPnA and TPnB_0. TM Capture input pin active edge transfers counter value to CCRA 3. This is because if the in the counter will be latched into the CCRA and CCRB pin is setup as an output. Irrespective of may cause an input capture operation to be executed. TnAM0 = 01 Counter Counter Value overflow CCRP Stop Counter Reset YY XX Pause Resume Time TnON bit TnPAU bit Active Active Active edges TM Capture Pin edge edge CCRA Int. The TnCCLR.1. No output function . TMnC2 registers. CCRP sets counter maximum value Rev. TnBIO0 bits are both set edge transition type is selected using the TnAIO1. high. TnAM0 = 01 and active edge set by TnAIO1 and TnAIO0 bits 2. The external signal TnBIO1. Flag TnAF CCRP Int. TPnB_1. TPnB_2 pins.Disable Capture ETM CCRA Capture Input Mode Note: 1. a a rising edge. what events occur on the TPnA and TPnB_0. terrupt signals from the CCRP can be a useful method in nal counter and can therefore be used for applications measuring long pulse widths. care must be taken if the and TPnB_0.Rising edge 01 . TnCCLR bit not used 4. The TnAIO1. TnBIO0 bits can select the active trigger edge is supplied on the TPnA and TPnB_0.Both edges 11 . TPnB_1. When a CCRP compare match occurs the counter will reset back to TnAM1. As the TPnA and TPnB_0. TPnB_2 pins the present value TM is in the Capture Input Mode. TnAOC. HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 Capture Input Mode zero.Falling edge 10 . Flag TnPF CCRA Value XX YY XX YY TnAIO1. If the falling edge or both rising and falling edges. TPnB_2 pins are When the required edge transition appears on the TPnA pin shared with other functions. TPnB_1. TnAM1. This mode enables external sig. the active TnAIO1. TnAIO0 Value 00 .00 124 November 3. TPnB_1.TnAOC and TnAPOL bits not used 5. whose active edge can be either a rising edge. TPnB_2 pins to be pins.

TnBM1. HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 TnBM1. CCRP sets counter maximum value Rev. TnBM0 = 01 Counter Counter Value overflow CCRP Stop Counter Reset YY XX Pause Resume Time TnON bit TnPAU bit Active Active Active edges TM Capture Pin edge edge CCRB Int. Flag TnPF CCRB Value XX YY XX YY TnBIO1. TM Capture input pin active edge transfers counter value to CCRB 3. TnBM0 = 01 and active edge set by TnBIO1 and TnBIO0 bits 2.1.Disable Capture ETM CCRB Capture Input Mode Note: 1.TnBOC and TnBPOL bits not used 5. TnBIO0 Value 00 .00 125 November 3. No output function . Flag TnBF CCRP Int.Rising edge 01 .Both edges 11 .Falling edge 10 . 2009 . TnCCLR bit not used 4.

The comparator output is recorded via a bit in register table applies to both registers. then the interrupt flag should be first set high before entering the SLEEP or IDLE Mode. C0OUT or C1OUT bit and not the output pin which gen.00 126 November 3. output polarity. however. The device contains two comparator functions which Comparator Registers are used to compare two analog voltages and provide an output based on their difference. the resulting generated interrupt flag will enabled. its relevant interrupt flag the microcontroller enters the SLEEP or IDLE Mode. Additional comparator functions include. some spurious out- normal I/O pins the comparators do not waste precious put signals may be generated on the comparator output I/O pins if there functions are otherwise unused. will be set. As the comparator in- polarity select. CP0C and CP1C. When If the comparator is enabled. when the comparator is enabled. 1. one for each comparator. The hysteresis function. As corresponding bits in isters. if enabled. their respective control register. Register Bit Name 7 6 5 4 3 2 1 0 CP0C C0SEL C0EN C0POL C0OUT C0OS ¾ ¾ C0HYEN CP1C C1SEL C1EN C1POL C1OUT C1OS ¾ ¾ C1HYEN Comparator Registers List Comparator Interrupt Programming Considerations Each also possesses its own interrupt function. but can also be trans- ferred out onto a shared I/O pin. Rev. the two registers have identical functions. Ideally the comparator should switch C n X C n . one assigned to each com. As comparator pins are shared with normal I/O pins the erates an interrupt. If it is required to disable a wake-up from occurring. hysteresis etc. and if the corresponding interrupt enable bit however as it will consume a certain amount of power. 2009 . HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 Comparators Two independent analog comparators are contained Any pull-high resistors connected to the shared com- within these devices. These functions offer flexibility via parator input pins will be automatically disconnected their register controlled features such as power-down. due to the slow rising or falling nature of the input sig- nals. tion. it will remain active when any one of the changes state. then if the trol register is ²1²) or read as port data register value external input lines cause the Comparator output to (port control register is ²0²) if the comparator function is change state. also generate a wake-up. also increases the Comparator Operation switching offset value. In sharing their pins with puts approach their switching level. is set. at the point where the positive and negative inputs sig- C n S E L nals are at the same voltage level. Note that it is the changing state of the SLEEP or IDLE Mode is entered. This can be minimised by selecting the hysteresis C n P O L C n O U T function will apply a small amount of positive feedback C n + to the comparator. they following parator. unavoid- Comparator able input offsets introduce some uncertainties here. Full control over the There are two registers for overall comparator opera- two internal comparators is provided via two control reg. If the microcontroller is in the SLEEP I/O registers for these pins will be read as zero (port con- or IDLE Mode and the Comparator is enabled. hysteresis functions and power down control. then a jump to its relevant interrupt vector will be the user may wish to consider disabling it before the executed.

Bit 2~1 unimplemented. As a result. If the bit is high the comparator C0OUT bit will be inverted. If the bit is zero then the C0OUT bit will reflect the non-inverted output condition of the comparator. The polarity of the bit is determined by the voltages on the comparator inputs and by the condition of the C0POL bit. Rev. If the bit is zero the comparator will be switched off and no power consumed even if analog voltages are applied to its inputs. as specified in the Comparator Electrical Characteristics table. 1. If the bit is set to ²1² or the C0SEL bit is ²0² the comparator output signal is only used internally by the device allowing the shared comparator output pin to retain its normal I/O operation. If the bit is high the comparator will be selected and the two comparator input pins will be enabled. HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 · CP0C Register Bit 7 6 5 4 3 2 1 0 Name C0SEL C0EN C0POL C0OUT C0OS ¾ ¾ C0HYEN R/W R/W R/W R/W R R/W ¾ ¾ R/W POR 1 0 0 0 0 ¾ ¾ 1 Bit 7 C0SEL: Select Comparator pins or I/O pins 0: I/O pin select 1: Comparator pin select This is the Comparator pin or I/O pin select bit. read as ²0² Bit 0 C0HYEN: Hysteresis Control 0: Off 1: On This is the hysteresis control bit and if set high will apply a limited amount of hysteresis to the comparator. Any pull-high configuration options associated with the comparator shared pins will also be automatically disconnected. For power sensitive applications this bit should be cleared to zero if the comparator is not used or before the device enters the SLEEP or IDLE mode.00 127 November 3. 2009 . Bit 4 C0OUT: Comparator output bit C0POL=0 0: C0+ < C0- 1: C0+ > C0- C0POL=1 0: C0+ > C0- 1: C0+ < C0- This bit stores the comparator output bit. If the bit is set to ²0² and the C0SEL bit is ²1² the comparator output is connected to an external C0X pin. Bit 5 C0POL: Comparator output polarity 0: output not inverted 1: output inverted This is the comparator polarity bit. The positive feedback induced by hysteresis reduces the effect of spurious switching near the comparator threshold. Bit 3 C0OS: Output path select 0: C0X pin 1: Internal use This is the comparator output path select control bit. Bit 6 C0EN: Comparator On/Off control 0: Off 1: On This is the Comparator on/off control bit. these two pins will lose their I/O pin functions.

00 128 November 3. Rev. If the bit is high the comparator C1OUT bit will be inverted. The polarity of the bit is determined by the voltages on the comparator inputs and by the condition of the C1POL bit. Bit 4 C1OUT: Comparator output bit C1POL=0 0: C1+ < C1- 1: C1+ > C1- C1POL=1 0: C1+ > C1- 1: C1+ < C1- This bit stores the comparator output bit. Bit 2~1 unimplemented. Bit 3 C1OS: Output path select 0: C1X pin 1: Internal use This is the comparator output path select control bit. For power sensitive applications this bit should be cleared to zero if the comparator is not used or before the device enters the SLEEP or IDLE mode. Any pull-high configuration options associated with the comparator shared pins will also be automatically disconnected. as specified in the Comparator Electrical Characteristics table. 2009 . The positive feedback induced by hysteresis reduces the effect of spurious switching near the comparator threshold. HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 · CP1C Register Bit 7 6 5 4 3 2 1 0 Name C1SEL C1EN C1POL C1OUT C1OS ¾ ¾ C1HYEN R/W R/W R/W R/W R R/W ¾ ¾ R/W POR 1 0 0 0 0 ¾ ¾ 1 Bit 7 C1SEL: Select Comparator pins or I/O pins 0: I/O pin select 1: Comparator pin select This is the Comparator pin or I/O pin select bit. Bit 6 C1EN: Comparator On/Off control 0: Off 1: On This is the Comparator on/off control bit. If the bit is high the comparator will be selected and the two comparator input pins will be enabled. If the bit is zero then the C1OUT bit will reflect the non-inverted output condition of the comparator. If the bit is zero the comparator will be switched off and no power consumed even if analog voltages are applied to its inputs. If the bit is set to ²1² or the C1SEL bit is ²0² the comparator output signal is only used internally by the device allowing the shared comparator output pin to retain its normal I/O operation. Bit 5 C1POL: Comparator output polarity 0: output not inverted 1: output inverted This is the comparator polarity bit. these two pins will lose their I/O pin functions. If the bit is set to ²0² and the C1SEL bit is ²1² the comparator output is connected to an external C1X pin. As a result. 1. read as ²0² Bit 0 C1HYEN: Hysteresis Control 0: Off 1: On This is the hysteresis control bit and if set high will apply a limited amount of hysteresis to the comparator.

where the device can be either mas. SDO. Originally developed by ²1² to enable SCS pin function. The SIM interface pins Data Input and Serial Data Output lines.SIM These devices contain a Serial Interface Module. connected to the SPI interface is carried out in a slave/master mode with all data transfer initiations be- SPI Interface ing implemented by the master. serial data interface that has a relatively simple commu. tionally disabled or enabled using the SIMEN bit in the lected using pull-high control registers. devices. S C S S C S ter or slave. S D O S D I The communication is full duplex and operates as a S D I S D O slave/master type. As the SPI interface pins are pin-shared with normal I/O terface function must first be selected using a configura- pins and with the I2C function pins. As both interface types share the same pins must first be enabled by selecting the SIM enable con- and registers. named SIM2~SIM0. · SPI Interface Operation tively simple communication protocols. in the SIMC0 register. If the master D a ta B u s S IM D S D I P in T x /R x S h ift R e g is te r S D O P in C K E N b it C lo c k E n a b le /D is a b le E d g e /P o la r ity C K P O L B b it C o n tro l B u s y C o n fig u r a tio n S ta tu s W C O L F la g O p tio n S C K P in fS Y S T R F F la g fT B C C lo c k S o u r c e S e le c t T M 0 C C R P m a tc h fre q u e n c y /2 S C S P in C S E N b it C o n fig u r a tio n O p tio n E n a b le /D is a b le SPI Block Diagram Rev. set CSEN bit to EEPROM memory devices etc. single SCS pin only one slave device can be utilized. ternal peripheral devices such as sensors. and also if the SIMC0 register. 2 external SPI or I C based hardware such as sensors. S P I M a s te r S P I S la v e nication protocol simplifying the programming require- S C K S C K ments when communicating with external hardware devices. These tion option has been configured it can also be addi- pull-high resistors of the SIM pin-shared I/O are se. HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 Serial Interface Module . Although the SPI interface specification can control multiple slave devices from a single master.00 129 November 3. After the SPI configura- bits. the SPI interface tion option. SCK and SCS. The Master also con- trols the clock signal. but SPI Master/Slave Connection this device provided only one SCS pin. nication with external peripheral hardware. to allow an easy method of commu. these serial The SPI interface is a full duplex synchronous serial interface types allow the microcontroller to interface to data link. Flash or The SCS pin is controlled by software. the master can use I/O pin to select the slave I2C interface types. 2009 . the four line SPI interface is a synchronous SCS pin will be floating state. Serial Clock line and SCS is the Slave Select line. etc. Pins SDI and SDO are the Serial Flash or EEPROM memory. 1. Communication between devices SIM function is enabled. As the device only contains a The SPI interface is often used to communicate with ex. It is a four line interface with pin names SDI. which needs to control multiple slave devices from a single includes both the four line SPI interface or the two line master. the choice of whether the SPI or I2C type figuration option and setting the correct bits in the is used is made using the SIM operating mode control SIMC0 and SIMC2 registers. Having rela. SCK is the are pin-shared with other I/O pins therefore the SIM in. set CSEN bit to ²0² the Motorola.

The same register is used by both the SPI and I2C functions.00 130 November 3. Note 2 that the SIMC1 register is only used by the I C interface. ¨ WCOL and CSEN bit enabled or disable select SPI Registers The status of the SPI interface pins is determined by a number of factors such as whether the device is in the There are three internal registers which control the over- master or slave mode and upon the condition of certain all operation of the SPI interface. Before the device writes data to the SPI bus. 2009 . These are the SIMD control bits such as CSEN and SIMEN. Another two SPI configura- ¨ Transmission complete flag tion options determine if the CSEN and WCOL bits are ¨ Rising or falling active clock edge to be used. HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 The SPI function in this device offers the following There are several configuration options associated with features: the SPI interface. the device can read it from the SIMD register. 1. Note that if the configuration option does not ¨ LSB first or MSB first data transmission modes select the SIM function then the SIMEN bit in the SIMC0 register will have no effect. One of these is to enable the SIM ¨ Full duplex synchronous data transfer function which selects the SIM pins rather than normal ¨ Both Master and Slave modes I/O pins. Any transmis- sion or reception of data from the SPI bus must be made via the SIMD register. After the data is received from the SPI bus. Register Bit Name 7 6 5 4 3 2 1 0 SIMC0 SIM2 SIM1 SIM0 PCKEN PCKP1 PCKP0 SIMEN ¾ SIMD D7 D6 D5 D4 D3 D2 D1 D0 SIMC2 D7 D6 CKPOLB CKEG MLS CSEN WCOL TRF SIM Registers List The SIMD register is used to store the data being transmitted and received. · SIMD Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR x x x x x x x x ²x² unknown Rev. data register and two registers SIMC0 and SIMC2. the actual data to be transmitted must be placed in the SIMD register.

SPI clock is fTBC 100: SPI master mode. SPI clock is fSYS/4 001: SPI master mode. · SIMC0 Register Bit 7 6 5 4 3 2 1 0 Name SIM2 SIM1 SIM0 PCKEN PCKP1 PCKP0 SIMEN ¾ R/W R/W R/W R/W R/W R/W R/W R/W ¾ POR 1 1 1 0 0 0 0 ¾ Bit 7~5 SIM2. SIMC0 and SIMC2. HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 There are also two control registers for the SPI interface. or SDA and SCL lines will be in a floating condition and the SIM operating current will be reduced to a minimum value. Register SIMC2 is used for other control functions such as LSB/MSB selection. the contents of the I2C control bits such as HTX and TXAK will remain at the previous settings and should therefore be first initialised by the application program while the relevant I2C flags such as HCF. If the SIM is configured to operate as an SPI interface via the SIM2~SIM0 bits. the SIMC0 register is also used to control the Peripheral Clock Prescaler. Bit 4 PCKEN: PCK Output Pin Control 0: Disable 1: Enable Bit 3~2 PCKP1. SPI clock is fSYS/16 010: SPI master mode. Register SIMC0 is used to control the enable/disable function and to set the data transmission clock fre- quency. The SIMC1 register is not used by the SPI function. SPI clock is fSYS/64 011: SPI master mode. only by the I2C function. they are used to control the SPI Master/Slave selection and the SPI Master clock frequency. 2009 . The SIM configuration option must have first enabled the SIM interface for this bit to be effective. When the bit is high the SIM interface is enabled. the contents of the SPI control registers will remain at the previous settings when the SIMEN bit changes from low to high and should therefore be first initialised by the application program. 1. SRW and RXAK will be set to their default states. As well as selecting if the I2C or SPI function. read as ²0² Rev. Note that the SIMC2 register also has the name SIMA which is used by the I2C function. SPI clock is TM0 CCRP match frequency/2 101: SPI slave mode 110: I2C slave mode 111: Unused mode These bits setup the overall operating mode of the SIM function. The SPI clock is a function of the system clock but can also be chosen to be sourced from the TM0. HBB. SIM1. write collision flag etc. Bit 0 unimplemented. If the SPI Slave Mode is selected then the clock will be supplied by an external Master device. the SDI. SDO. If the SIM is configured to operate as an I2C interface via the SIM2~SIM0 bits and the SIMEN bit changes from low to high. PCKP0: Select PCK output pin frequency 00: fSYS 01: fSYS/4 10: fSYS/8 11: TM0 CCRP match frequency/2 Bit 1 SIMEN: SIM Control 0: Disable 1: Enable The bit is the overall on/off control for the SIM interface. HAAS. SIM0: SIM Operating Mode Control 000: SPI master mode. When the SIMEN bit is cleared to zero to disable the SIM interface. SCK and SCS. Although not connected with the SPI function.00 131 November 3.

The bit can be cleared by the application program. 2009 . These two bits must be configured before data transfer is executed otherwise an erroneous clock edge may be generated. Bit 0 TRF: SPI Transmit/Receive Complete flag 0: Data is being transferred 1: SPI data transmission is completed The TRF bit is the Transmit/Receive Complete flag and is set ²1² automatically when an SPI data transmission is completed. Note that using the WCOL bit can be disabled or enabled via configuration option. HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 · SIMC2 Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 CKPOLB CKEG MLS CSEN WCOL TRF R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~6 Undefined bit This bit can be read or written by user software program. then the SCK line will be high when the clock is inactive. Note that using the CSEN bit can be disabled or enabled via configuration option. It can be used to generate an interrupt. Bit 2 CSEN: SPI SCS pin Control 0: Disable 1: Enable The CSEN bit is used as an enable/disable for the SCS pin. Setting the bit high will select MSB first and low for LSB first. Bit 3 MLS: SPI Data shift order 0: LSB 1: MSB This is the data shift select bit and is used to select how the data is transferred. The CKPOLB bit determines the base condition of the clock line. then the SCS pin will be disabled and placed into a floating condition. Bit 4 CKEG: Determines SPI SCK active clock edge type CKPOLB=0 0: SCK is high base level and data capture at SCK rising edge 1: SCK is high base level and data capture at SCK falling edge CKPOLB=1 0: SCK is low base level and data capture at SCK falling edge 1: SCK is low base level and data capture at SCK rising edge The CKEG and CKPOLB bits are used to setup the way that the clock signal outputs and inputs data on the SPI bus. When the CKPOLB bit is low. then the SCK line will be low when the clock is inactive. then the SCK line will be high when the clock is inactive. If this bit is low. then the SCK line will be low when the clock is inactive. If the bit is high the SCS pin will be enabled and used as a select pin.00 132 November 3. If this bit is high it means that data has been attempted to be written to the SIMD register during a data transfer operation. Rev. Bit 5 CKPOLB: Determines the base condition of the clock line 0: the SCK line will be high when the clock is inactive 1: the SCK line will be low when the clock is inactive The CKPOLB bit determines the base condition of the clock line. if the bit is high. if the bit is high. When the CKPOLB bit is low. either MSB or LSB first. 1. The CKEG bit determines active clock edge type which depends upon the condition of CKPOLB bit. This writing operation will be ignored if data is being transferred. but must set to ²0² by the application program. Bit 1 WCOL: SPI Write Collision flag 0: No collision 1: Collision The WCOL flag is used to detect if a data collision has occurred.

C K E G = 1 ) S C K (C K P O L B = 0 .H ig h ) S C S S IM E N . C K E G = 1 ) S D O (C K E G = 0 ) D 7 /D 0 D 6 /D 1 D 5 /D 2 D 4 /D 3 D 3 /D 4 D 2 /D 5 D 1 /D 6 D 0 /D 7 S D O (C K E G = 1 ) D 7 /D 0 D 6 /D 1 D 5 /D 2 D 4 /D 3 D 3 /D 4 D 2 /D 5 D 1 /D 6 D 0 /D 7 S D I D a ta C a p tu re W r ite to S IM D SPI Master Mode Timing S C S S C K (C K P O L B = 1 ) S C K (C K P O L B = 0 ) S D O D 7 /D 0 D 6 /D 1 D 5 /D 2 D 4 /D 3 D 3 /D 4 D 2 /D 5 D 1 /D 6 D 0 /D 7 S D I D a ta C a p tu re W r ite to S IM D ( S D O d o e s n o t c h a n g e u n til fir s t S C K e d g e ) SPI Slave Mode Timing . C K E G = 0 ) S C K (C K P O L B = 1 . The accompanying timing diagram shows the rela- using the application program. 1. transmission/reception will begin si. any ous configurations of the CKPOLB and CKEG bits. data on the SDI pin will be shifted into the SIMD register. then in the Master Mode.CKEG=0 Rev. C S E N = 1 S C K (C K P O L B = 1 . when data is written to data to be transferred should be well prepared at the ap- the SIMD register. the upon the configurations of the CKPOLB bit and CKEG TRF flag will be set automatically. 2009 . S IM E N = 1 .00 133 November 3. but must be cleared bit. C K E G = 0 ) S C K (C K P O L B = 0 . when tionship between the slave data and SCS signal for vari- the clock signal from the master has been received. In the Slave Mode. The slave bit high. data in the SIMD register will be transmitted and any The SPI will continue to function even in the IDLE Mode. propriate moment relative to the SCS signal depending multaneously. C S E N = 0 ( E x te r n a l P u ll. HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 SPI Communication The master should output an SCS signal to enable the After the SPI interface is enabled by setting the SIMEN slave device before a clock signal is provided. When the data transfer is complete.

0 1 0 .00 134 November 3. 1. 2009 . SPI Slave Mode Timing . HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 S C S S C K (C K P O L B = 1 ) S C K (C K P O L B = 0 ) S D O D 7 /D 0 D 6 /D 1 D 5 /D 2 D 4 /D 3 D 3 /D 4 D 2 /D 5 D 1 /D 6 D 0 /D 7 S D I D a ta C a p tu re W r ite to S IM D ( S D O c h a n g e s a s s o o n a s w r itin g o c c u r s . if S IM E N = 1 a n d C S E N = 0 . S IM [2 :0 ]= 1 0 1 N 0 0 1 . (T R F = 1 ? ) C K E G . C S E N a n d M L S Y R e a d D a ta S IM E N = 1 fro m S IM D A C le a r T R F T ra n s fe r N F in is h e d ? Y E N D SPI Transfer Control Flowchart Rev.CKEG=1 A S P I tra n s fe r W r ite D a ta C le a r W C O L in to S IM D M a s te r m a s te r o r S la v e s la v e ? Y W C O L = 1 ? S IM [2 :0 ]= 0 0 0 . S D O is flo a tin g if S C S = 1 ) N o te : F o r S P I s la v e m o d e .0 1 1 o r 1 0 0 N T r a n s m is s io n c o m p le te d ? C o n fig u r e C K P O L B . S P I is a lw a y s e n a b le d a n d ig n o r e s th e S C S le v e l.

00 135 November 3. A configuration op- 2 tion exists to allow a clock other than the system clock The I C interface is used to communicate with external 2 to drive the I C interface. Before the slave can transmit and receive data. Both master and transmitted and received on the I2C bus. EEPROM memory determines the debounce time of the I2C interface. HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 I2C Interface SIMC0 register will have no effect. one is known as the master above SPI section. which is shown in the the bidirectional I2C bus. if selected. There are three control registers associated with the ceived on the I2C bus. and serial clock line. SDA. SIMC1 and SIMA and one data regis- When two devices communicate with each other on ter. SIMC0. it is a two line low This uses the internal clock to in effect add a speed serial interface for synchronous serial data trans. sibility of glitches on the clock line causing erroneous relatively simple communication protocol and the ability operation. can be to accommodate multiple devices on the same bus has chosen to be either 1 or 2 system clocks. is used to store the data being device and one as the slave device. The advantage of only two lines for communication. which only operates in slave mode. as each device on the I2C bus is identified · I2C Registers by a unique address which will be transmitted and re. As many devices may be connected together on the same bus. Another configuration option peripheral devices such as sensors. it is the microcontroller writes data to the I2C bus. I2C bus. The debounce time. made it an extremely popular interface type for many S T A R T s ig n a l applications. register. S T O P s ig n a l son it is necessary that external pull-high resistors are fro m M a s te r connected to these outputs. etc. their outputs are both open drain types. fro m M a s te r V D D S e n d s la v e a d d r e s s a n d R /W b it fr o m M a s te r S D A S C L A c k n o w le d g e D e v ic e D e v ic e D e v ic e fr o m s la v e S la v e M a s te r S la v e I2C Master Slave Bus Connection S e n d d a ta b y te fro m M a s te r · I2C Interface Operation The I2C serial interface is a two line interface. the slave transmit mode and the slave receive Any transmission or reception of data from the I2C bus mode. For this rea. Bit SIMEN and bits function which selects the SIM pins rather than normal SIM2~SIM0 in register SIMC0 are used by the I2C in- I/O pins. Originally developed by Philips. One of these is to enable the which is used by the SPI function. Note that if the configuration option does not terface. select the SIM function then the SIMEN bit in the Register Bit Name 7 6 5 4 3 2 1 0 SIMC0 SIM2 SIM1 SIM0 PCKEN PCKP1 PCKP0 SIMEN ¾ SIMC1 HCF HANS HBB HTX TXAK SRW IAMWU RXAK SIMD D7 D6 D5 D4 D3 D2 D1 D0 SIMA IICA6 IICA5 IICA4 IICA3 IICA2 IICA1 IICA0 D0 I2C Registers List Rev. the actual master device that has overall control of the bus. After the data is received from the I2C bus. a serial A c k n o w le d g e fr o m s la v e data line. must be made via the SIMD register. SCL. 1. For data to be transmitted must be placed in the SIMD these devices. there are two methods of transferring data on the I2C the microcontroller can read it from the SIMD register. however. There are several configuration options associated Note that the SIMA register also has the name SIMC2 with the I2C interface. Note that no chip select line exists. bus. 2009 . The SIMD register. debounce time to the external clock to reduce the pos- fer. SIMD.

SPI clock is TM0 CCRP match frequency/2 101: SPI slave mode 110: I2C slave mode 111: Unused mode These bits setup the overall operating mode of the SIM function. Bit 4 PCKEN: PCK Output Pin Control 0: Disable 1: Enable Bit 3~2 PCKP1. HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 · SIMC0 Register Bit 7 6 5 4 3 2 1 0 Name SIM2 SIM1 SIM0 PCKEN PCKP1 PCKP0 SIMEN ¾ R/W R/W R/W R/W R/W R/W R/W R/W ¾ POR 1 1 1 0 0 0 0 ¾ Bit 7~5 SIM2. SPI clock is fSYS/64 011: SPI master mode. 2009 . If the SPI Slave Mode is selected then the clock will be supplied by an external Master device. Bit 0 unimplemented. the contents of the I2C control bits such as HTX and TXAK will remain at the previous settings and should therefore be first initialised by the application program while the relevant I2C flags such as HCF. HBB. SDO.00 136 November 3. SPI clock is fSYS/4 001: SPI master mode. The SIM configuration option must have first enabled the SIM interface for this bit to be effective. SCK and SCS. PCKP0: Select PCK output pin frequency 00: fSYS 01: fSYS/4 10: fSYS/8 11: TM0 CCRP match frequency/2 Bit 1 SIMEN: SIM Control 0: Disable 1: Enable The bit is the overall on/off control for the SIM interface. HAAS. SRW and RXAK will be set to their default states. The SPI clock is a function of the system clock but can also be chosen to be sourced from the TM0. When the bit is high the SIM interface is enabled. the SDI. the contents of the SPI control registers will remain at the previous settings when the SIMEN bit changes from low to high and should therefore be first initialised by the application program. As well as selecting if the I2C or SPI function. they are used to control the SPI Master/Slave selection and the SPI Master clock frequency. If the SIM is configured to operate as an SPI interface via SIM2~SIM0 bits. or SDA and SCL lines will be in a floating condition and the SIM operating current will be reduced to a minimum value. SIM0: SIM Operating Mode Control 000: SPI master mode. 1. SPI clock is fTBC 100: SPI master mode. When the SIMEN bit is cleared to zero to disable the SIM interface. If the SIM is configured to operate as an I2C interface via the SIM2~SIM0 bits and the SIMEN bit changes from low to high. SIM1. SPI clock is fSYS/16 010: SPI master mode. read as ²0² Rev.

it means that a acknowledge signal has been received at the 9th clock. When the RXAK flag is ²0². the slave transmitter will release the SDA line to allow the master to send a STOP signal to release the I2C Bus. When this occurs. The flag will be set to ²0² when the bus is free which will occur when a STOP signal is detected. When the SRW flag is zero. HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 · SIMC1 Register Bit 7 6 5 4 3 2 1 0 Name HCF HAAS HBB HTX TXAK SRW IAMWU RXAK R/W R R R R/W R/W R R/W R POR 1 0 0 0 0 0 0 1 2 Bit 7 HCF: I C Bus data transfer completion flag 0: Data is being transferred 1: Completion of an 8-bit data transfer The HCF flag is the data transfer flag. the master will write data to the bus. Bit 4 HTX: Select I2C slave device is transmitter or receiver 0: Slave device is the receiver 1: Slave device is the transmitter Bit 3 TXAK: I2C Bus transmit acknowledge flag 0: Slave send acknowledge flag 1: Slave do not send acknowledge flag The TXAK bit is the transmit acknowledge flag. Bit 2 SRW: I2C Slave Read/Write flag 0: Slave device should be in receive mode 1: Slave device should be in transmit mode The SRW flag is the I2C Slave Read/Write flag. When the transmitted address and slave address is match. therefore the slave device should be in receive mode to read this data. This flag will be ²1² when the I2C bus is busy which will occur when a START signal is detected. Bit 1 IAMWU: I2C Address Match Wake-up Control 0: Disable 1: Enable This bit should be set to ²1² to enable I2C address match wake up from SLEEP or IDLE Mode. 2009 . Bit 5 HBB: I2C Bus busy flag 0: I2C Bus is not busy 1: I2C Bus is busy The HBB flag is the I2C busy flag. This flag is used to determine if the slave device address is the same as the master transmit address. 1. the slave device checks the RXAK flag to determine if the master receiver wishes to receive the next byte. Rev.00 137 November 3. This flag determines whether the master device wishes to transmit or receive data from the I2C bus. the slave device will check the SRW flag to determine whether it should be in transmit mode or receive mode. if there is no match then the flag will be low. this bit will be transmitted to the bus on the 9th clock from the slave device. the master is requesting to read data from the bus. This flag will be zero when data is being transferred. If the addresses match then this bit will be high. after 8 bits of data have been transmitted. After the slave device receipt of 8-bits of data. that is when the HAAS flag is set high. The slave transmitter will therefore continue sending out data until the RXAK flag is ²1². The slave device must always set TXAK bit to ²0² before further data is received. Bit 6 HAAS: I2C Bus address match flag 0: Not address match 1: Address match The HASS flag is the address match flag. If the SRW flag is high. When the slave device in the transmit mode. Bit 0 RXAK: I2C Bus Receive acknowledge flag 0: Slave receive acknowledge flag 1: Slave do not receive acknowledge flag The RXAK flag is the receiver acknowledge flag. Upon completion of an 8-bit data transfer the flag will go high and an interrupt will be generated. so the slave device should be in transmit mode.

HT68F20/HT68F30/HT68F40/HT68F50/HT68F60

The SIMD register is used to store the data being transmitted and received. The same register is used by both the SPI
and I2C functions. Before the device writes data to the SPI bus, the actual data to be transmitted must be placed in the
SIMD register. After the data is received from the SPI bus, the device can read it from the SIMD register. Any transmis-
sion or reception of data from the SPI bus must be made via the SIMD register.
· SIMD Register

Bit 7 6 5 4 3 2 1 0
Name D7 D6 D5 D4 D3 D2 D1 D0
R/W R/W R/W R/W R/W R/W R/W R/W R/W
POR x x x x x x x x
²x² unknown

· SIMA Register

Bit 7 6 5 4 3 2 1 0
Name IICA6 IICA5 IICA4 IICA3 IICA2 IICA1 IICA0 ¾
R/W R/W R/W R/W R/W R/W R/W R/W ¾
POR x x x x x x x ¾
²x² unknown
2
Bit 7~1 IICA6~ IICA0: I C slave address
IICA6~ IICA0 is the I2C slave address bit 6~ bit 0.
The SIMA register is also used by the SPI interface but has the name SIMC2. The SIMA
register is the location where the 7-bit slave address of the slave device is stored. Bits 7~ 1 of the
SIMA register define the device slave address. Bit 0 is not defined.
When a master device, which is connected to the I2C bus, sends out an address, which
matches the slave address in the SIMA register, the slave device will be selected. Note that the
SIMA register is the same register address as SIMC2 which is used by the SPI interface.
Bit 0 Undefined bit
This bit can be read or written by user software program.

D a ta B u s

I2C D a ta R e g is te r S la v e A d d r e s s R e g is te r
(S IM D ) (S IM A )

A d d re s s A d d re s s M a tc h
H T X B it C o m p a ra to r H A A S B it I2C In te rru p t
D ir e c tio n C o n tr o l

S C L P in
D a ta in L S B
S D A P in S h ift R e g is te r
D a ta O u t M S B R e a d /w r ite S la v e
M S R W B it
U
X E n a b le /D is a b le A c k n o w le d g e
8 - b it D a ta C o m p le te H C F B it
T r a n s m it/R e c e iv e
C o n tr o l U n it D e te c t S ta rt o r S to p
H B B B it

2
I C Block Diagram

Rev. 1.00 138 November 3, 2009

HT68F20/HT68F30/HT68F40/HT68F50/HT68F60

I2C Bus Communication I2C Bus Start Signal
Communication on the I2C bus requires four separate The START signal can only be generated by the master
steps, a START signal, a slave device address transmis- device connected to the I2C bus and not by the slave de-
sion, a data transmission and finally a STOP signal. vice. This START signal will be detected by all devices
When a START signal is placed on the I2C bus, all de- connected to the I2C bus. When detected, this indicates
vices on the bus will receive this signal and be notified of that the I2C bus is busy and therefore the HBB bit will be
the imminent arrival of data on the bus. The first seven set. A START condition occurs when a high to low transi-
bits of the data will be the slave address with the first bit tion on the SDA line takes place when the SCL line re-
being the MSB. If the address of the slave device mains high.
matches that of the transmitted address, the HAAS bit in
2
the SIMC1 register will be set and an I C interrupt will be Slave Address
generated. After entering the interrupt service routine, The transmission of a START signal by the master will
the slave device must first check the condition of the 2
be detected by all devices on the I C bus. To determine
HAAS bit to determine whether the interrupt source orig- which slave device the master wishes to communicate
inates from an address match or from the completion of with, the address of the slave device will be sent out im-
an 8-bit data transfer. During a data transfer, note that mediately following the START signal. All slave devices,
after the 7-bit slave address has been transmitted, the after receiving this 7-bit address data, will compare it
following bit, which is the 8th bit, is the read/write bit with their own 7-bit slave address. If the address sent
whose value will be placed in the SRW bit. This bit will out by the master matches the internal address of the
be checked by the slave device to determine whether to microcontroller slave device, then an internal I2C bus in-
go into transmit or receive mode. Before any transfer of terrupt signal will be generated. The next bit following
data to or from the I2C bus, the microcontroller must in- the address, which is the 8th bit, defines the read/write
itialise the bus, the following are steps to achieve this: status and will be saved to the SRW bit of the SIMC1
Step 1 register. The slave device will then transmit an acknowl-
edge bit, which is a low level, as the 9th bit. The slave
Set the SIM2~SIM0 and SIMEN bits in the SIMC0 regis-
device will also set the status flag HAAS when the ad-
ter to ²1² to enable the I2C bus.
dresses match.
Step 2
As an I2C bus interrupt can come from two sources,
2
Write the slave address of the device to the I C bus ad- when the program enters the interrupt subroutine, the
dress register SIMA. HAAS bit should be examined to see whether the inter-
Step 3 rupt source has come from a matching slave address or
from the completion of a data byte transfer. When a
Set the SIME and SIM Muti-Function interrupt enable bit slave address is matched, the device must be placed in
of the interrupt control register to enable the SIM inter- either the transmit mode and then write data to the SIMD
rupt and Multi-function interrupt. register, or in the receive mode where it must implement
a dummy read from the SIMD register to release the
S ta rt
SCL line.

I2C Bus Read/Write Signal
S E T S IM [2 :0 ]= 1 1 0
S E T S IM E N
The SRW bit in the SIMC1 register defines whether the
slave device wishes to read data from the I2C bus or
W r ite S la v e write data to the I2C bus. The slave device should exam-
A d d re s s to S IM A
ine this bit to determine if it is to be a transmitter or a re-
ceiver. If the SRW flag is ²1² then this indicates that the
2
N o I2C B u s Y e s master device wishes to read data from the I C bus,
In te rru p t= ?
therefore the slave device must be setup to send data to
C L R S IM E S E T S IM E a n d M F n E the I2C bus as a transmitter. If the SRW flag is ²0² then
P o ll S IM F to d e c id e
w h e n to g o to I2C B u s IS R W a it fo r In te r r u p t
this indicates that the master wishes to send data to the
I2C bus, therefore the slave device must be setup to
G o to M a in P r o g r a m G o to M a in P r o g r a m read data from the I2C bus as a receiver.

I2C Bus Slave Address Acknowledge Signal
I2C Bus Initialisation Flow Chart
After the master has transmitted a calling address, any
slave device on the I2C bus, whose own internal address
matches the calling address, must generate an ac-
knowledge signal. The acknowledge signal will inform

Rev. 1.00 139 November 3, 2009

HT68F20/HT68F30/HT68F40/HT68F50/HT68F60

the master that a slave device has accepted its calling ²0², before it can receive the next data byte. If the slave
address. If no acknowledge signal is received by the transmitter does not receive an acknowledge bit signal
master then a STOP signal must be transmitted by the from the master receiver, then the slave transmitter will
master to end the communication. When the HAAS flag release the SDA line to allow the master to send a STOP
is high, the addresses have matched and the slave de- signal to release the I2C Bus. The corresponding data
vice must check the SRW flag to determine if it is to be a will be stored in the SIMD register. If setup as a transmit-
transmitter or a receiver. If the SRW flag is high, the ter, the slave device must first write the data to be trans-
slave device should be setup to be a transmitter so the mitted into the SIMD register. If setup as a receiver, the
HTX bit in the SIMC1 register should be set to ²1². If the slave device must read the transmitted data from the
SRW flag is low, then the microcontroller slave device SIMD register.
should be setup as a receiver and the HTX bit in the
When the slave receiver receives the data byte, it must
SIMC1 register should be set to ²0². generate an acknowledge bit, known as TXAK, on the
9th clock. The slave device, which is setup as a trans-
I2C Bus Data and Acknowledge Signal
mitter will check the RXAK bit in the SIMC1 register to
The transmitted data is 8-bits wide and is transmitted af- determine if it is to send another data byte, if not then it
ter the slave device has acknowledged receipt of its will release the SDA line and await the receipt of a STOP
slave address. The order of serial bit transmission is the signal from the master.
MSB first and the LSB last. After receipt of 8-bits of data,
the receiver must transmit an acknowledge signal, level

S ta rt S la v e A d d r e s s S R W A C K
S C L

1 0 1 1 0 1 0 1 0
S D A

D a ta A C K S to p
S C L

1 0 0 1 0 1 0 0

S D A
S = S ta rt (1 b it)
S A = S la v e A d d r e s s ( 7 b its )
S R = S R W b it ( 1 b it)
M = S la v e d e v ic e s e n d a c k n o w le d g e b it ( 1 b it)
D = D a ta (8 b its )
A = A C K (R X A K b it fo r tr a n s m itte r , T X A K b it fo r r e c e iv e r 1 b it)
P = S to p (1 b it)

S S A S R M D A D A S S A S R M D A D A P

Note: * When a slave address is matched, the device must be placed in either the transmit mode and then write data
to the SIMD register, or in the receive mode where it must implement a dummy read from the SIMD register to
release the SCL line.
I2C Communication Timing Diagram

Rev. 1.00 140 November 3, 2009

HT68F20/HT68F30/HT68F40/HT68F50/HT68F60

S ta rt

N o H A A S = 1 Y e s
?

N o H T X = 1 Y e s Y e s S R W = 1 N o
? ?

R e a d fro m
S IM D to r e le a s e C L R H T X
S E T H T X
S C L lin e C L R T X A K

D u m m y re a d fro m
R E T I W r ite d a ta to S IM D
S IM D to r e le a s e
to r e le a s e S C L L in e
S C L L in e
Y e s R X A K = 1
?
N o R E T I R E T I

C L R H T X W r ite d a ta to S IM D
C L R T X A K r e le a s e S C L L in e

D u m m y re a d fro m
S IM D to r e le a s e R E T I
S C L L in e

R E T I

I2C Bus ISR Flow Chart

Rev. 1.00 141 November 3, 2009

HT68F20/HT68F30/HT68F40/HT68F50/HT68F60

Peripheral Clock Output
The Peripheral Clock Output allows the device to supply for the Peripheral Clock Output can originate from either
external hardware with a clock signal synchronised to the TM0 CCRP match frequency/2 or a divided ratio of
the microcontroller clock. the internal fSYS clock. The PCKEN bit in the SIMC0 reg-
ister is the overall on/off control, setting PCKEN bit to
Peripheral Clock Operation ²1² enables the Peripheral Clock, setting PCKEN bit to
As the peripheral clock output pin, PCK, is shared with ²0² disables it. The required division ratio of the system
I/O line, the required pin function is chosen via PCKEN clock is selected using the PCKP1 and PCKP0 bits in
in the SIMC0 register. The Peripheral Clock function is the same register. If the device enters the SLEEP Mode
controlled using the SIMC0 register. The clock source this will disable the Peripheral Clock output.

· SIMC0 Register

Bit 7 6 5 4 3 2 1 0
Name SIM2 SIM1 SIM0 PCKEN PCKP1 PCKP0 SIMEN ¾
R/W R/W R/W R/W R/W R/W R/W R/W ¾
POR 1 1 1 0 0 0 0 ¾

Bit 7~5 SIM2, SIM1, SIM0: SIM operating mode control
000: SPI master mode; SPI clock is fSYS/4
001: SPI master mode; SPI clock is fSYS/16
010: SPI master mode; SPI clock is fSYS/64
011: SPI master mode; SPI clock is fTBC
100: SPI master mode; SPI clock is TM0 CCRP match frequency/2
101: SPI slave mode
110: I2C slave mode
111: Unused mode
These bits setup the overall operating mode of the SIM function. As well as selecting if the I2C
or SPI function, they are used to control the SPI Master/Slave selection and the SPI Master clock
frequency. The SPI clock is a function of the system clock but can also be chosen to be sourced
from the TM0. If the SPI Slave Mode is selected then the clock will be supplied by an external
Master device.
Bit 4 PCKEN: PCK output pin control
0: Disable
1: Enable
Bit 3~2 PCKP1, PCKP0: select PCK output pin frequency
00: fSYS
01: fSYS/4
10: fSYS/8
11: TM0 CCRP match frequency/2
Bit 1 SIMEN: SIM control
0: Disable
1: Enable
The bit is the overall on/off control for the SIM interface. When the SIMEN bit is cleared to zero
to disable the SIM interface, the SDI, SDO, SCK and SCS, or SDA and SCL lines will be in a
floating condition and the SIM operating current will be reduced to a minimum value. When the bit
is high the SIM interface is enabled. The SIM configuration option must have first enabled the
SIM interface for this bit to be effective. Note that when the SIMEN bit changes from low to high
the contents of the SPI control registers will be in an unknown condition and should therefore be
first initialised by the application program.
Bit 0 unimplemented, read as ²0²

Rev. 1.00 142 November 3, 2009

HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 Interrupts Interrupts are an important part of any microcontroller ing convention of these follows a specific pattern. The external interrupts Global EMI ¾ ¾ are generated by the action of the external INT0~INT3 Comparator CPnE CPnF n = 0 or 1 and PINT pins. The first is the INTC0~INTC3 registers TM TnAE TnAF n = 0~3 which setup the primary interrupts. which basically means the set. 1. while the internal interrupts are gener- ated by various internal functions such as the TMs. The number of regis- ters depends upon the device chosen but fall into three TnPE TnPF categories. EEPROM and SIM.00 143 November 3. First is system. LVD. rary suspension of the main program allowing the microcontroller to direct attention to their respective Enable Request Function Notes Bit Flag needs. 2009 . INTn Pin INTnE INTnF n = 0~3 Comparators. then the (optional) such as a Timer Module requires microcontroller atten. When an external event or an internal function listed an abbreviated interrupt type. LVD LVE LVF ¾ tions occur and the setting of interrupt enable bits by the application program. The nam- · Interrupt Register Contents ¨ HT68F20 Bit Name 7 6 5 4 3 2 1 0 INTEG ¾ ¾ ¾ ¾ INT1S1 INT1S0 INT0S1 INT0S0 INTC0 ¾ CP0F INT1F INT0F CP0E INT1E INT0E EMI INTC1 ¾ MF1F MF0F CP1F ¾ MF1E MF0E CP1E INTC2 MF3F TB1F TB0F MF2F MF3E TB1E TB0E MF2E MFI0 ¾ ¾ T0AF T0PF ¾ ¾ T0AE T0PE MFI1 ¾ ¾ T1AF T1PF ¾ ¾ T1AE T1PE MFI2 DEF LVF XPF SIMF DEE LVE XPE SIME Rev. their corresponding interrupt will enforce a tempo. able/disable bit or ²F² for request flag. Multi-function MFnE MFnF n = 0~5 Interrupt Registers Time Base TBnE TBnF n = 0 or 1 Overall interrupt control. EEPROM DEE DEF ¾ ters. Time Base. located in the Special Purpose Data Memory. SIM SIME SIMF ¾ ting of request flags when certain microcontroller condi. Finally there is an INTEG register to setup the Interrupt Register Bit Naming Conventions external interrupt trigger edge type. number of that interrupt followed by either an ²E² for en- tion. Each register contains a number of enable bits to enable or disable individual registers as well as interrupt flags to indicate the presence of an interrupt request. the second is the TnBE TnBF MFI0~MFI3 registers which setup the Multi-function in- terrupts. as PINT Pin XPE XPF ¾ shown in the accompanying table. is controlled by a series of regis. The device contains several external interrupt and internal interrupts functions.

00 144 November 3. 2009 . 1. HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 ¨ HT68F30 Bit Name 7 6 5 4 3 2 1 0 INTEG ¾ ¾ ¾ ¾ INT1S1 INT1S0 INT0S1 INT0S0 INTC0 ¾ CP0F INT1F INT0F CP0E INT1E INT0E EMI INTC1 ¾ MF1F MF0F CP1F ¾ MF1E MF0E CP1E INTC2 MF3F TB1F TB0F MF2F MF3E TB1E TB0E MF2E MFI0 ¾ ¾ T0AF T0PF ¾ ¾ T0AE T0PE MFI1 ¾ T1BF T1AF T1PF ¾ T1BE T1AE T1PE MFI2 DEF LVF XPF SIMF DEE LVE XPE SIME ¨ HT68F40 Bit Name 7 6 5 4 3 2 1 0 INTEG ¾ ¾ ¾ ¾ INT1S1 INT1S0 INT0S1 INT0S0 INTC0 ¾ CP0F INT1F INT0F CP0E INT1E INT0E EMI INTC1 ¾ MF1F MF0F CP1F ¾ MF1E MF0E CP1E INTC2 MF3F TB1F TB0F MF2F MF3E TB1E TB0E MF2E MFI0 T2AF T2PF T0AF T0PF T2AE T2PE T0AE T0PE MFI1 ¾ T1BF T1AF T1PF ¾ T1BE T1AE T1PE MFI2 DEF LVF XPF SIMF DEE LVE XPE SIME ¨ HT68F50 Bit Name 7 6 5 4 3 2 1 0 INTEG ¾ ¾ ¾ ¾ INT1S1 INT1S0 INT0S1 INT0S0 INTC0 ¾ CP0F INT1F INT0F CP0E INT1E INT0E EMI INTC1 ¾ MF1F MF0F CP1F ¾ MF1E MF0E CP1E INTC2 MF3F TB1F TB0F MF2F MF3E TB1E TB0E MF2E MFI0 T2AF T2PF T0AF T0PF T2AE T2PE T0AE T0PE MFI1 ¾ T1BF T1AF T1PF ¾ T1BE T1AE T1PE MFI2 DEF LVF XPF SIMF DEE LVE XPE SIME MFI3 ¾ ¾ T3AF T3PF ¾ ¾ T3AE T3PE Rev.

00 145 November 3. read as ²0² Bit 3~2 INT1S1. 2009 . INT0S0: interrupt edge control for INT0 pin 00: disable 01: rising edge 10: falling edge 11: rising and falling edges Rev. INT1S0: interrupt edge control for INT1 pin 00: disable 01: rising edge 10: falling edge 11: rising and falling edges Bit 1~0 INT0S1. HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 ¨ HT68F60 Bit Name 7 6 5 4 3 2 1 0 INTEG INT3S1 INT3S0 INT2S1 INT2S0 INT1S1 INT1S0 INT0S1 INT0S0 INTC0 ¾ INT2F INT1F INT0F INT2E INT1E INT0E EMI INTC1 MF0F CP1F CP0F INT3F MF0E CP1E CP0E INT3E INTC2 ¾ MF3F MF2F MF1F ¾ MF3E MF2E MF1E INTC3 MF5F TB1F TB0F MF4F MF5E TB1E TB0E MF4E MFI0 T2AF T2PF T0AF T0PF T2AE T2PE T0AE T0PE MFI1 ¾ T1BF T1AF T1PF ¾ T1BE T1AE T1PE MFI2 DEF LVF XPF SIMF DEE LVE XPE SIME MFI3 ¾ ¾ T3AF T3PF ¾ ¾ T3AE T3PE · INTEG Register ¨ HT68F20/HT68F30/HT68F40/HT68F50 Bit 7 6 5 4 3 2 1 0 Name ¾ ¾ ¾ ¾ INT1S1 INT1S0 INT0S1 INT0S0 R/W ¾ ¾ ¾ ¾ R/W R/W R/W R/W POR ¾ ¾ ¾ ¾ 0 0 0 0 Bit 7~4 unimplemented. 1.

read as ²0² Bit 6 CP0F: Comparator 0 interrupt request flag 0: no request 1: interrupt request Bit 5 INT1F: INT1 interrupt request flag 0: no request 1: interrupt request Bit 4 INT0F: INT0 interrupt request flag 0: no request 1: interrupt request Bit 3 CP0E: Comparator 0 interrupt control 0: disable 1: enable Bit 2 INT1E: INT1 interrupt control 0: disable 1: enable Bit 1 INT0E: INT0 interrupt control 0: disable 1: enable Bit 0 EMI: Global interrupt control 0: disable 1: enable Rev. INT3S0: Interrupt edge control for INT3 pin 00: disable 01: rising edge 10: falling edge Bit 5~4 INT2S1. HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 ¨ HT68F60 Bit 7 6 5 4 3 2 1 0 Name INT3S1 INT3S0 INT2S1 INT2S0 INT1S1 INT1S0 INT0S1 INT0S0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~6 INT3S1. INT2S0: interrupt edge control for INT2 pin 00: disable 01: rising edge 10: falling edge 11: rising and falling edges Bit 3~2 INT1S1.00 146 November 3. INT0S0: interrupt edge control for INT0 pin 00: disable 01: rising edge 10: falling edge 11: rising and falling edges · INTC0 Register ¨ HT68F20/HT68F30/HT68F40/HT68F50 Bit 7 6 5 4 3 2 1 0 Name ¾ CP0F INT1F INT0F CP0E INT1E INT0E EMI R/W ¾ R/W R/W R/W R/W R/W R/W R/W POR ¾ 0 0 0 0 0 0 0 Bit 7 unimplemented. 2009 . 1. INT1S0: interrupt edge control for INT1 pin 00: disable 01: rising edge 10: falling edge 11: rising and falling edges Bit 1~0 INT0S1.

read as ²0² Bit 6 INT2F: INT2 interrupt request flag 0: no request 1: interrupt request Bit 5 INT1F: INT1 interrupt request flag 0: no request 1: interrupt request Bit 4 INT0F: INT0 interrupt request flag 0: no request 1: interrupt request Bit 3 INT2E: INT2 interrupt control 0: disable 1: enable Bit 2 INT1E: INT1 interrupt control 0: disable 1: enable Bit 1 INT0E: INT0 interrupt control 0: disable 1: enable Bit 0 EMI: Global interrupt control 0: disable 1: enable Rev.00 147 November 3. 1. HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 ¨ HT68F60 Bit 7 6 5 4 3 2 1 0 Name ¾ INT2F INT1F INT0F INT2E INT1E INT0E EMI R/W ¾ R/W R/W R/W R/W R/W R/W R/W POR ¾ 0 0 0 0 0 0 0 Bit 7 unimplemented. 2009 .

read as ²0² Bit 6 MF1F: Multi-function Interrupt 1 Request Flag 0: no request 1: interrupt request Bit 5 MF0F: Multi-function Interrupt 0 Request Flag 0: no request 1: interrupt request Bit 4 CP1F: Comparator 1 Interrupt Request Flag 0: no request 1: interrupt request Bit 3 unimplemented. read as ²0² Bit 2 MF1E: Multi-function Interrupt 1 Control 0: disable 1: enable Bit 1 MF0E: Multi-function Interrupt 0 Control 0: disable 1: enable Bit 0 CP1E: Comparator 1 Interrupt Control 0: disable 1: enable Rev. 1.00 148 November 3. 2009 . HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 · INTC1 Register ¨ HT68F20/HT68F30/HT68F40/HT68F50 Bit 7 6 5 4 3 2 1 0 Name ¾ MF1F MF0F CP1F ¾ MF1E MF0E CP1E R/W ¾ R/W R/W R/W ¾ R/W R/W R/W POR ¾ 0 0 0 ¾ 0 0 0 Bit 7 unimplemented.

2009 .00 149 November 3. HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 ¨ HT68F60 Bit 7 6 5 4 3 2 1 0 Name MF0F CP1F CP0F INT3F MF0E CP1E CP0E INT3E R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7 MF0F: Multi-function Interrupt 0 Request Flag 0: no request 1: interrupt request Bit 6 CP1F: Comparator 1 Interrupt Request Flag 0: no request 1: interrupt request Bit 5 CP0F: Comparator 0 Interrupt Request Flag 0: no request 1: interrupt request Bit 4 INT3F: INT3 Interrupt Request Flag 0: no request 1: interrupt request Bit 3 MF0E: Multi-function Interrupt 0 Control 0: disable 1: enable Bit 2 CP1E: Comparator 1 Interrupt Control 0: disable 1: enable Bit 1 CP0E: Comparator 0 Interrupt Control 0: disable 1: enable Bit 0 INT3E: INT3 Interrupt Control 0: disable 1: enable Rev. 1.

1.00 150 November 3. HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 · INTC2 Register ¨ HT68F20/HT68F30/HT68F40/HT68F50 Bit 7 6 5 4 3 2 1 0 Name MF3F TB1F TB0F MF2F MF3E TB1E TB0E MF2E R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7 MF3F: Multi-function Interrupt 3 Request Flag 0: no request 1: interrupt request Bit 6 TB1F: Time Base 1 Interrupt Request Flag 0: no request 1: interrupt request Bit 5 TB0F: Time Base 0 IInterrupt Request Flag 0: no request 1: interrupt request Bit 4 MF2F: Multi-function Interrupt 2 Request Flag 0: no request 1: interrupt request Bit 3 MF3E: Multi-function Interrupt 3 Control 0: disable 1: enable Bit 2 TB1E: Time Base 1 Interrupt Control 0: disable 1: enable Bit 1 TB0E: Time Base 0 Interrupt Control 0: disable 1: enable Bit 0 MF2E: Multi-function Interrupt 2 Control 0: disable 1: enable Rev. 2009 .

read as ²0² Bit 6 MF3F: Multi-function Interrupt 3 Request Flag 0: no request 1: interrupt request Bit 5 MF2F: Multi-function Interrupt 2 Request Flag 0: no request 1: interrupt request Bit 4 MF1F: Multi-function Interrupt 1 Request Flag 0: no request 1: interrupt request Bit 3 unimplemented.00 151 November 3. 1. HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 ¨ HT68F60 Bit 7 6 5 4 3 2 1 0 Name ¾ MF3F MF2F MF1F ¾ MF3E MF2E MF1E R/W ¾ R/W R/W R/W ¾ R/W R/W R/W POR ¾ 0 0 0 ¾ 0 0 0 Bit 7 unimplemented. read as ²0² Bit 2 MF3E: Multi-function Interrupt 3 Control 0: disable 1: enable Bit 1 MF2E: Multi-function Interrupt 2 Control 0: disable 1: enable Bit 0 MF1E: Multi-function Interrupt 1 Control 0: disable 1: enable Rev. 2009 .

read as ²0² Bit 1 T0AE: TM0 Comparator A match interrupt control 0: disable 1: enable Bit 0 T0PE: TM0 Comparator P match interrupt control 0: disable 1: enable Rev. HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 · INTC3 Register ¨ HT68F60 Bit 7 6 5 4 3 2 1 0 Name MF5F TB1F TB0F MF4F MF5E TB1E TB0E MF4E R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7 MF5F: Multi-function interrupt 5 request flag 0: no request 1: interrupt request Bit 6 TB1F: Time Base 1 interrupt request flag 0: no request 1: interrupt request Bit 5 TB0F: Time Base 0 interrupt request flag 0: no request 1: interrupt request Bit 4 MF4F: Multi-function interrupt 4 request flag 0: no request 1: interrupt request Bit 3 MF5E: Multi-function interrupt 5 control 0: disable 1: enable Bit 2 TB1E: Time Base 1 interrupt control 0: disable 1: enable Bit 1 TB0E: Time Base 0 interrupt control 0: disable 1: enable Bit 0 MF4E: Multi-function interrupt 4 control 0: disable 1: enable · MFI0 Register ¨ HT68F20/HT68F30 Bit 7 6 5 4 3 2 1 0 Name ¾ ¾ T0AF T0PF ¾ ¾ T0AE T0PE R/W ¾ ¾ R/W R/W ¾ ¾ R/W R/W POR ¾ ¾ 0 0 ¾ ¾ 0 0 Bit 7~6 unimplemented. 1.00 152 November 3. 2009 . read as ²0² Bit 5 T0AF: TM0 Comparator A match interrupt request flag 0: no request 1: interrupt request Bit 4 T0PF: TM0 Comparator P match interrupt request flag 0: no request 1: interrupt request Bit 3~2 unimplemented.

1. HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 ¨ HT68F40/HT68F50/HT68F60 Bit 7 6 5 4 3 2 1 0 Name T2AF T2PF T0AF T0PF T2AE T2PE T0AE T0PE R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7 T2AF: TM2 Comparator A match interrupt request flag 0: no request 1: interrupt request Bit 6 T2PF: TM2 Comparator P match interrupt request flag 0: no request 1: interrupt request Bit 5 T0AF: TM0 Comparator A match interrupt request flag 0: no request 1: interrupt request Bit 4 T0PF: TM0 Comparator P match interrupt request flag 0: no request 1: interrupt request Bit 3 T2AE: TM2 Comparator A match interrupt control 0: disable 1: enable Bit 2 T2PE: TM2 Comparator P match interrupt control 0: disable 1: enable Bit 1 T0AE: TM0 Comparator A match interrupt control 0: disable 1: enable Bit 0 T0PE: TM0 Comparator P match interrupt control 0: disable 1: enable · MFI1 Register ¨ HT68F20 Bit 7 6 5 4 3 2 1 0 Name ¾ ¾ T1AF T1PF ¾ ¾ T1AE T1PE R/W ¾ ¾ R/W R/W ¾ ¾ R/W R/W POR ¾ ¾ 0 0 ¾ ¾ 0 0 Bit 7~6 unimplemented. read as ²0² Bit 5 T1AF: TM1 Comparator A match interrupt request flag 0: no request 1: interrupt request Bit 4 T1PF: TM1 Comparator P match interrupt request flag 0: no request 1: interrupt request Bit 3~2 unimplemented. read as ²0² Bit 1 T1AE: TM1 Comparator A match interrupt control 0: disable 1: enable Bit 0 T1PE: TM1 Comparator P match interrupt control 0: disable 1: enable Rev.00 153 November 3. 2009 .

1. read as ²0² Bit 2 T1BE: TM1 Comparator P match interrupt control 0: disable 1: enable Bit 1 T1AE: TM1 Comparator A match interrupt control 0: disable 1: enable Bit 0 T1PE: TM1 Comparator P match interrupt control 0: disable 1: enable · MFI2 Register Bit 7 6 5 4 3 2 1 0 Name DEF LVF XPF SIMF DEE LVE XPE SIME R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7 DEF: Data EEPROM interrupt request flag 0: No request 1: Interrupt request Bit 6 LVF: LVD interrupt request flag 0: No request 1: Interrupt request Bit 5 XPF: External peripheral interrupt request flag 0: No request 1: Interrupt request Bit 4 SIMF: SIM interrupt request flag 0: No request 1: Interrupt request Bit 3 DEE: Data EEPROM Interrupt Control 0: Disable 1: Enable Bit 2 LVE: LVD Interrupt Control 0: Disable 1: Enable Bit 1 XPE: External Peripheral Interrupt Control 0: Disable 1: Enable Bit 0 SIME: SIM Interrupt Control 0: Disable 1: Enable Rev. 2009 . HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 ¨ HT68F30/HT68F40/HT68F50/HT68F60 Bit 7 6 5 4 3 2 1 0 Name ¾ T1BF T1AF T1PF ¾ T1BE T1AE T1PE R/W ¾ R/W R/W R/W ¾ R/W R/W R/W POR ¾ 0 0 0 ¾ 0 0 0 Bit 7 unimplemented. read as ²0² Bit 6 T1BF: TM1 Comparator B match interrupt request flag 0: no request 1: interrupt request Bit 5 T1AF: TM1 Comparator A match interrupt request flag 0: no request 1: interrupt request Bit 4 T1PF: TM1 Comparator B match interrupt request flag 0: no request 1: interrupt request Bit 3 unimplemented.00 154 November 3.

the relevant interrupt request flag will be set. the stack must from this interrupt vector. such sociated request flags. will be transferred onto the stack. even if the related will be the value of the corresponding interrupt vector. read as ²0² Bit 5 T3AF: TM3 Comparator A match interrupt request flag 0: no request 1: interrupt request Bit 4 T3PF: TM3 Comparator P match interrupt request flag 0: no request 1: interrupt request Bit 3~2 unimplemented. which stores the address of the next instruction to be ex. Program Counter address from the stack and allows the microcontroller to continue with normal execution at the point where the interrupt occurred. If the stack is full. If immediate service is desired. 2009 . until the Stack Pointer is decre- The microcontroller will then fetch its next instruction mented. when set will wake-up the device if it is in SLEEP or ate interrupt. 1. however to prevent a wake-up from occur- ring the corresponding flag should be set before the de- minated with a ²RETI². The global interrupt enable bit. This will prevent any fur- if the enable bit is zero then although the interrupt re. will be cleared automatically. read as ²0² Bit 1 T3AE: TM3 Comparator A match interrupt control 0: disable 1: enable Bit 0 T3PE: TM3 Comparator P match interrupt control 0: disable 1: enable Interrupt Operation The various interrupt enable bits. the re- vector. to al- ecuted. interrupt is enabled. neous requests. the Program Counter. All of the interrupt request flags routine. If an interrupt requires immediate servicing while the When an interrupt is generated. Here is located the code to control the appropri. The interrupt service routine must be ter. the interrupt re- Counter will then be loaded with a new address which quest will not be acknowledged. Rev. the EMI bit should be set after entering the routine. The instruction at this vector be prevented from becoming full. all the other interrupts condition of the interrupt enable bit. Comparator A or Comparator B diagrams with their order of priority. IDLE Mode. In case of simulta- will usually be a ²JMP² which will jump to another sec. together with their as- When the conditions for an interrupt event occur. Some interrupt match etc. HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 · MFI3 Register ¨ HT68F50/HT68F60 Bit 7 6 5 4 3 2 1 0 Name ¾ ¾ T3AF T3PF ¾ ¾ T3AE T3PE R/W ¾ ¾ R/W R/W ¾ ¾ R/W R/W POR ¾ ¾ 0 0 ¾ ¾ 0 0 Bit 7~6 unimplemented. if other quest flag is set an actual interrupt will not be generated interrupt requests occur during this interval. quest flag will still be recorded. if cleared to zero.00 155 November 3. However. will disable all interrupts. EMI bit set high then the program will jump to its relevant vector. The Program low interrupt nesting. which retrieves the original vice is in SLEEP or IDLE Mode. are shown in the accompanying as a TM Comparator P. as the global interrupt enable bit. program is already in another interrupt service routine. sources have their own individual vector while others Whether the request flag actually generates a program share the same multi-function interrupt vector. although and the program will not jump to the relevant interrupt the interrupt will not be immediately serviced. ther interrupt nesting from occurring. Once an jump to the relevant interrupt vector is determined by the interrupt subroutine is serviced. the accompanying diagram shows the tion of program which is known as the interrupt service priority that is applied. If the enable bit is will be blocked.

HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 EMI auto disabled in ISR Legend Interrupt Request Enable Master Vector xxF Request Flag – no auto reset in ISR Priority Name Flags Bits Enable High xxF Request Flag – auto reset in ISR INT0 Pin INT0F INT0E EMI 04H xxE Enable Bit INT1 Pin INT1F INT1E EMI 08H Interrupt Request Enable Comp. 1 CP1F CP1E EMI 10H TM0 P T0PF T0PE TM0 A T0AF T0AE M. Funct. 1 MF1F MF1E EMI 18H TM1 A T1AF T1AE TM1 B T1BF T1BE SIM SIMF SIME M. 1. 3 MF3F MF3E EMI 2CH Low Interrupts contained within Multi-Function Interrupts HT68F30 only Interrupt Structure . 0 CP0F CP0E EMI 0CH Name Flags Bits Comp.HT68F20/HT68F30 Rev.00 156 November 3. 0 MF0F MF0E EMI 14H TM1 P T1PF T1PE M. 2009 . Funct. 2 MF2F MF2E EMI 20H PINT Pin XPF XPE Time Base 0 TB0F TB0E EMI 24H Time Base 1 TB1F TB1E EMI 28H LVD LVF LVE EEPROM DEF DEE M. Funct. Funct.

1 CP1F CP1E EMI 10H TM0 P TP0AF T0PE TM0 A TP0AF T0AE M. 0 CP0F CP0E EMI 0CH Name Flags Bits Comp. 1 MF1F MF1E EMI 18H TM1 B T1BF T1BE TM3 P T3PF T3PE TM3 A T3AF T3AE SIM SIMF SIME M. Funct. Funct. 2009 .00 157 November 3. Funct.HT68F40/HT68F50 Rev. 0 MF0F MF0E EMI 14H TM2 P T2PF T2PE TM2 A T2AF T2AE TM1 P T1PF T1PE TM1 A T1AF T1AE M. 2 MF2F MF2E EMI 20H PINT Pin XPF XPE Time Base 0 TB0F TB0E EMI 24H Time Base 1 TB1F TB1E EMI 28H LVD LVF LVE EEPROM DEF DEE M. 3 MF3F MF3E EMI 2CH Low Interrupts contained within Multi-Function Interrupts HT68F50 only Interrupt Structure . Funct. HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 EMI auto disabled in ISR Legend Interrupt Request Enable Master Vector xxF Request Flag – no auto reset in ISR Priority Name Flags Bits Enable High xxF Request Flag – auto reset in ISR INT0 Pin INT0F INT0E EMI 04H xxE Enable Bit INT1 Pin INT1F INT1E EMI 08H Interrupt Request Enable Comp. 1.

Funct. Funct.00 158 November 3. 2009 .HT68F60 Rev. 1. 4 MF4F MF4E EMI 30H PINT Pin XPF XPE Time Base 0 TB0F TB0E EMI 34H Time Base 1 TB1F TB1E EMI 38H LVD LVF LVE EEPROM DEF DEE M. Funct. 5 MF5F MF5E EMI 3CH Low Interrupts contained within Multi-Function Interrupts Interrupt Structure . 1 CP1F CP1E EMI 18H TM0 P T0PF T0PE TM0 A T0AF T0AE M. Funct. Funct. 2 MF2F MF2E EMI 24H TM2 A T2AF T2AE TM3 P T3PF T3PE M. 1 MF1F MF1E EMI 20H TM1 B T1BF T1BE TM2 P T2PF T2PE M. Funct. 0 CP0F CP0E EMI 14H Name Flags Bits Comp. 0 MF0F MF0E EMI 1CH TM1 P T1PF T1PE TM1 A T1AF T1AE M. 3 MF3F MF3E EMI 28H TM3 A T3AF T3AE SIM SIMF SIME M. HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 EMI auto disabled in ISR Interrupt Request Enable Master Vector Priority Name Flags Bits Enable High Legend INT0 Pin INT0F INT0E EMI 04H xxF Request Flag – no auto reset in ISR INT1 Pin INT1F INT1E EMI 08H xxF Request Flag – auto reset in ISR INT2 Pin INT2F INT2E EMI 0CH xxE Enable Bit INT3 Pin INT3F INT3E EMI 10H Interrupt Request Enable Comp.

Note that the INTEG reg- The function of the Time Base Interrupts is to provide reg- ister can also be used to disable the external interrupt ular time signal in the form of an internal interrupt. whose type is chosen by the edge select bits. a other interrupts. a situation that will occur when When the interrupt is enabled. a subroutine call to the comparator interrupt vector. INT0F~INT3F. LVD interrupt and EEPROM Interrupt. When the interrupt is ser- dress. an interrupt request flag. EMI. To allow the pro. they can only be configured as full. are set. EMI. are set. which will occur when a are formed from other existing interrupt sources. the external inter- Multi-function Interrupt flags will be automatically reset rupt request flags. gram to branch to its respective interrupt vector ad. respective external interrupt enable bit. and viced. the related corresponding bit in the port control register. CP0F or CP1F. Additionally the correct interrupt edge will be set when any of their included functions generate type must be selected using the INTEG register to en. must first be set. Note that any pull-high resistor se- the TM Interrupts. not full and the comparator inputs generate a compara- tor output transition. the stack is cleared to disable other interrupts. To allow the pro- Time Base overflows. the global interrupt enable bit. An external interrupt re. when the trigger edge type. To allow the program to branch able the external interrupt function and to choose the to its respective interrupt vector address. The Multi-function interrupt flags must first be set. the stack is not full and the the comparator output changes state. will be automatically when the interrupt is serviced. A comparator interrupt request will vector addresses. namely able other interrupts. will take place. Within these devices there are up to six Multi-function tions on the pins INT0~INT3. interrupts. To The comparator interrupt is controlled by the two inter- allow the program to branch to their respective interrupt nal comparators. must TB1F. the stack is not full and the correct and the EMI bit will be automatically cleared to disable transition type appears on the external interrupt pin. CP0E and CP1E. EMI and take place when the comparator interrupt request flags. the TM Interrupts. and either one of the interrupts contained within external interrupt pins if their external interrupt enable each of Multi-function interrupt occurs. the request flags from the reset and the EMI bit will be automatically cleared to dis- original source of the Multi-function interrupts. LVD interrupt and EEPROM Interrupt will not be even if the pin is used as an external interrupt input. a subroutine call to their respective gram to branch to its respective interrupt vector ad- vector locations will take place. and any of the Multi-function interrupt request flags. quest will take place when the external interrupt request these interrupts have no independent source. 1. namely transition. Rev. TB0F or TB1F will be set. When the interrupt is serviced. Time Base enable bits. A choice of either rising or falling or both edge types can be chosen Time Base Interrupts to trigger an external interrupt.00 159 November 3. As the external interrupt pins are Multi-function interrupt is enabled and the stack is not pin-shared with I/O pins. When these happens their respec- tive interrupt request flags. When the interrupt is serviced. terrupt. will be automatically reset and the EMI bit will be first be set. automatically reset and must be manually reset by the The INTEG register is used to select the type of active application program. will be automatically reset interrupt is enabled. it must be noted that. although the place. TB0F or comparator interrupt enable bits. the global interrupt enable bit. subroutine call to the external interrupt vector. 2009 . will take However. the respective interrupt request flag. When the Multi-Function request flag. A Multi-function interrupt request will take place when dress. are controlled by the overflow signals from their respec- Comparator Interrupt tive timer functions. Unlike the other independent interrupts. but rather flags. will be au- tomatically reset and the EMI bit will be automatically cleared to disable other interrupts. External Peripheral In- lections on the external interrupt pins will remain valid terrupt. HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 External Interrupt Multi-function Interrupt The external interrupts are controlled by signal transi. When the interrupt is serviced. to one of the Multi-function interrupt vectors will take The pin must also be setup as an input by setting the place. They function. MF0F~MF5F are set. When the interrupt is enabled. SIM Interrupt. the global interrupt enable bit. External Peripheral In- appears on the external interrupt pins. SIM Interrupt. the external interrupt request flags. INT0E~INT3E. INT0F~INT3F. TB0E or TB1E. edge that will trigger the external interrupt. a subroutine call bit in the corresponding interrupt register has been set.

the division ratio of which is se- lected by programming the appropriate bits in the TBC register to obtain longer interrupt periods whose value ranges. 1. The clock source that generates fTB. Their clock sources origi- nate from the internal clock source fTB. HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 The purpose of the Time Base Interrupt is to provide an interrupt signal at fixed time periods. This fTB input clock passes through a divider. 2009 .00 160 November 3. can originate from several different sources. which in turn controls the Time Base interrupt period. as shown in the System Operating Mode section. · TBC Register Bit 7 6 5 4 3 2 1 0 Name TBON TBCK TB11 TB10 LXTLP TB02 TB01 TB00 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 1 1 0 1 1 1 Bit 7 TBON: TB0 and TB1 Control 0: Disable 1: Enable Bit 6 TBCK: Select fTB Clock 0: fTBC 1: fSYS/4 Bit 5~4 TB11~TB10: Select Time Base 1 Time-out Period 00: 4096/fTB 01: 8192/fTB 10: 16384/fTB 11: 32768/fTB Bit 3 LXTLP: LXT Low Power Control 0: Disable 1: Enable Bit 2~0 TB02~TB00: Select Time Base 0 Time-out Period 000: 256/fTB 001: 512/fTB 010: 1024/fTB 011: 2048/fTB 100: 4096/fTB 101: 8192/fTB 110: 16384/fTB 111: 32768/fTB T B 0 2 ~ T B 0 0 fS Y S /4 L X T M M ¸ 2 8 ~ 2 1 5 T im e B a s e 0 In te r r u p t U fT B fT B C U X L IR C X ¸ 2 1 2 ~ 2 1 5 T im e B a s e 1 In te r r u p t C o n fig u r a tio n T B C K B it O p tio n T B 1 1 ~ T B 1 0 Time Base Interrupt Rev.

the global interrupt enable bit. the EMI bit will be automatically Multi-function Interrupt. while the Enhanced Type TM has three in- When the interrupt is enabled. a situa- tion which occurs when a TM comparator P. and associated The Compact and Standard Type TMs have two inter- Multi-function interrupt enable bit. MFnE. must first be set. When the interrupt is enabled. tion detects a low power supply voltage. bit. All of the TM interrupts are contained within the negative transition appears on the External Peripheral Multi-function Interrupts. a subroutine call to the re. When the Low Voltage way to the external interrupt and is contained within the Interrupt is serviced. which occurs terrupt is serviced. When the interrupt is enabled. the EMI set. external pe- ripheral interrupt enable bit. Multi-function interrupt request flag will be also automat- quest flag. and the Serial Interface Interrupt enable cleared. the stack is not full and a byte of data has been transmitted or re. A SIM Interrupt request will take place when the Interrupt vector. As the TM interrupt re- its respective interrupt vector address. nal Peripheral Interrupt is serviced. SIME. EMI. the The Serial Interface Module Interrupt. a subroutine call to the respective Standard Type TMs there are two interrupt request flags Multi-function Interrupt. the EMI bit will be For the Enhanced Type TM there are three interrupt re- automatically cleared to disable other interrupts. and relevant ripheral Interrupt pin. 1. LVF. interrupt enable bit. TnAE and TnBE. must LVD Interrupt first be set. LVE. EMI. the stack is not full and a low voltage condi- External Peripheral Interrupt tion occurs. EMI. An LVD Interrupt request will spective Multi-function Interrupt vector. a subroutine call to the Multi-function Inter- The External Peripheral Interrupt operates in a similar rupt vector. A or B As the XPF flag will not be automatically cleared. To allow the program to branch to its Multi-function interrupt request flag will be also automat- respective interrupt vector address. they have rupt enable bit. The external peripheral interrupt pin is pin-shared with several other To allow the program to branch to its respective interrupt pins with different functions. spective TM Interrupt enable bit. When the TM interrupt is will take place when the EEPROM Interrupt request serviced. For each of the Compact and Interrupt pin. TnPF and TnAF and two enable bits TnPE and TnAE. The Low Voltage Detector Interrupt is contained within ceived by the SIM interface. Multi-function Interrupt enable bit. and associated Multi-function the application program. XPF. the EMI bit will be automatically when a byte of data has been received or transmitted by cleared to disable other interrupts. rupts each. is set. XPE. EEPROM Interrupt enable bit. the stack is not full EEPROM Interrupt and a TM comparator match situation occurs. is When the Serial Interface Interrupt is serviced. a subroutine call to the respective Multi-function terrupt. When the interrupt is enabled. is contained within the tine call to the relevant Multi-function Interrupt vector lo- Multi-function Interrupt. An EEPROM Interrupt request cations. vector address. will take place. is set. program to branch to its respective interrupt vector ad- TM Interrupts dress. the global inter. Low Voltage will not be automatically cleared. which occurs when the Low Voltage Detector func- bit will be automatically cleared to disable other inter. it has to be cleared by the application program. it has to be cleared by Interrupt enable bit. which occurs when an EEPROM Write able other interrupts. 2009 . a subrou- The EEPROM Interrupt. will take place. and associated Multi-function interrupt enable bit. place when any of the TM request flags are set. will take place. which occurs when a negative ically cleared. also known as the stack is not full and an EEPROM Write or Read cycle SIM interrupt. the stack is not full and a terrupts. the Multi-function Interrupt. take place when the LVD Interrupt request flag. As the DEF flag will not be automatically enable bit.00 161 November 3. it has match situation happens. Rev. the EMI bit will be automatically cleared to dis- flag. to be cleared by the application program. TnAF and TnBF and three enable bits ever only the Multi-function interrupt request flag will be TnPE. the global interrupt ically cleared. DEF. it has to be cleared by the application program. re- erly configured to enable it to operate as an External Pe. When the EEPROM In- SIM Interrupt request flag. quest flags TnPF. will take place. As the LVF flag will not be automatically edge transition appears on the PINT pin. quest flags will not be automatically cleared. however only the Multi-function interrupt request program to branch to its respective interrupt vector ad- flag will be also automatically cleared. the global interrupt enable bit. A Peripheral Interrupt request cleared to disable other interrupts. To allow the cleared. As the SIMF flag dress. To allow the program to branch to flag will be automatically cleared. HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 Serial Interface Module Interrupt must first be set. however only the the SIM interface. A TM interrupt request will take also automatically cleared. is contained within the Multi-function In. to be cleared by the application program. will take place. It must therefore be prop. When the Exter. is set. must first be set. ends. DEE. must first be set. To allow the rupts. however only the will take place when the External Peripheral Interrupt re. When the interrupt is enabled. how. SIMF. EMI. and Muti-function interrupt enable bits. the global interrupt enable bit. however only the related MFnF or Read cycle ends. EMI.

routine is executed. Rev. a microcontroller when it is in SLEEP or IDLE Mode. Inter- ing up the microcontroller when in the SLEEP or IDLE rupts often occur in an unpredictable manner or need to Mode. RETI instruction may be executed. A wake-up is generated when an interrupt re. before enter SLEEP or IDLE Mode. as only the Multi-function interrupt request flags. and its system oscillator stopped. it will re. HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 Interrupt Wake-up Function It is recommended that programs do not use the ²CALL² Each of the interrupt functions has the capability of wak. the low power supply voltage or comparator input change wake up being generated when the interrupt request may cause their respective interrupt flag to be set high flag changes from low to high. a re- quested interrupt can be prevented from being serviced. interrupts. The RET instruction however only executes a return to the main program leaving the EMI bit in its Where a certain interrupt is contained within a present zero state and therefore disabling the execution Multi-function interrupt. will be automatically cleared. should be set high before the device enters the SLEEP then when the interrupt is serviced. 2009 . To return from an interrupt subroutine. be serviced immediately. If only one stack is left and the quest flag changes from low to high and is independent interrupt is not well controlled. The RETI instruction main in this condition in the interrupt register until the in addition to executing a return to the main program corresponding interrupt is serviced or until the request also automatically sets the EMI bit high to allow further flag is cleared by the application program. situations such as ex. If an interrupt wake-up function is to be dis. either a RET or however. their contents Programming Considerations should be saved to the memory at the beginning of the interrupt service routine. tered by the interrupt service program. status register or other registers are al- on the interrupt wake-up function. once an interrupt request flag is set. quence will be damaged once a CALL subroutine is exe- even though the device is in the SLEEP or IDLE Mode cuted in the interrupt subroutine. If it is required to prevent and consequently generate an interrupt. instruction within the interrupt service subroutine. if the contents of the or IDLE Mode. abled then the corresponding interrupt request flag As only the Program Counter is pushed onto the stack. By disabling the relevant interrupt enable bits. the individual request flag for the function needs to be cleared by the application program. the original control se- of whether the interrupt is enabled or not. Therefore. Care must a certain interrupt from waking up the microcontroller therefore be taken if spurious wake-up situations are to then its respective request flag should be first set high be avoided. Every interrupt has the capability of waking up the ternal edge transitions on the external interrupt pins. then when the interrupt service of further interrupts. 1. The interrupt enable bits have no effect accumulator. MF0F~MF5F.00 162 November 3.

which are setup as out. Timer instructions and is set when executing the ²HALT² Standby Current Considerations instruction. the interrupt which woke-up the device connected. The TO flag is set if a WDT time-out occurs. · A WDT overflow · The Data Memory contents and registers will maintain If the system is woken up by an external reset. as there may stack is full. cution at the instruction following the ²HALT² instruction. TO. wake-up methods will initiate a reset operation. in which case the regular interrupt response inputs. the ²HALT² instruction. This also applies to de. PDF. puts or if setup as inputs must have pull-high resistors In this situation. 2009 . such as other CMOS not full. If an interrupt request flag is set high before be required if the configuration options have enabled entering the SLEEP or IDLE Mode. The first is where the related increased current consumption. the system. These should be placed in a condition in which when a stack level becomes free. Rev. 1. if the · The WDT will be cleared and resume counting if the device is woken up by a WDT overflow. tion of the related interrupt will be disabled. will be system power-up or executing the clear Watchdog set and the Watchdog time-out flag. the de- their present condition. then two possi- input pins could create internal oscillations and result in ble situations may occur. but will rather be ser- which are connected to I/O pins. be woken up from one of various sources listed as follows: tion in the application program. Also note that additional standby current will also takes place. viced later when the related interrupt is finally enabled or puts. The other situation is minimum current is drawn or connected only to external where the related interrupt is enabled and the stack is circuits that do not draw current. perhaps only in the order of several micro-amps. the other flags remain in Mode is to keep the current consumption of the device their original status. vice will experience a full system reset. and causes a wake-up that only resets the Program As the main reason for entering the SLEEP or IDLE Counter and Stack Pointer. The WDT will stop if its clock source originates from the system clock. nected to either a fixed high or low level as any floating If the system is woken up by an interrupt. The PDF flag is cleared by a · In the status register. to as low a value as possible. it can or IDLE Mode and that is to execute the ²HALT² instruc. When a Port A pin wake-up occurs. however. All high-impedance input pins must be con. in which case the program will resume exe- be unbonbed pins. the Power Down flag.00 163 November 3. ining the TO and PDF flags. there are other considerations Each pin on Port A can be setup using the PAWU regis- which must also be taken into account by the circuit de. a Watchdog WDT clock source is selected to come from the fSUB Timer reset will be initiated. the pro- Special attention must be made to the I/O pins on the gram will resume execution at the instruction following device. the ac- tual source of the wake-up can be determined by exam- · The I/O ports will maintain their present condition. These must either be setup as out. Care must also be taken with the loads. interrupt is disabled or the interrupt is enabled but the vices which have different package types. When this instruction is · An external reset executed. will not be immediately serviced. the wake-up func- the LIRC oscillator. the following will occur: · An external falling edge on Port A · The system clock will be stopped and the application · A system interrupt program will stop at the ²HALT² instruction. ter to permit a negative transition on the pin to wake-up signer if the power consumption is to be minimised. Although both of these clock source and the WDT is enabled. will be cleared. HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 Power Down Mode and Wake-up Entering the IDLE or SLEEP Mode Wake-up There is only one way for the device to enter the SLEEP After the system enters the SLEEP or IDLE Mode.

0V 101: 3.4V Rev. VLVD2~VLVD0.6V 111: 4. This enabled the device to monitor the be detemined. 1. it may be desirable to switch off LVD Register the circuit when not in use. circuits.00 164 November 3. This function may be that the VDD voltage is above the preset low voltage especially useful in battery applications where the sup.7V 100: 3. HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 Low Voltage Detector . VDD. value.2V 010: 2. are used to select one of eight · LVDC Register Bit 7 6 5 4 3 2 1 0 Name ¾ ¾ LVDO LVDEN ¾ VLVD2 VLVD1 VLVD0 R/W ¾ ¾ R R/W ¾ R/W R/W R/W POR ¾ ¾ 0 0 ¾ 0 0 0 Bit 7~6 unimplemented.3V 110: 3. A low voltage condition is indicated when power supply voltage.0V 001: 2. also fixed voltages below which a low voltage condition will known as LVD. read as ²0² Bit 2~0 VLVD2 ~ VLVD0: Select LVD Voltage 000: 2.4V 011: 2. Three bits in this register. The Low Voltage Detector also has the capability to zero will switch off the internal low voltage detector of generating an interrupt signal. an important consideration in The Low Voltage Detector function is controlled using a power sensitive battery powered applications. If the LVDO bit is low. 2009 .LVD Each device has a Low Voltage Detector function. read as ²0² Bit 5 LVDO: LVD Output Flag 0: No Low Voltage Detect 1: Low Voltage Detect Bit LVDEN: Low Voltage Detector Control 0: Disable 1: Enable Bit 3 unimplemented. The LVDEN bit is used to control the overall ply voltage will gradually reduce as the battery ages. Clearing the bit ated. single register with the name LVDC. high will enable the low voltage detector. as on/off function of the low voltage detector. Setting the bit it allows an early warning battery low signal to be gener. and provide a warning signal the LVDO bit is set. this indicates should it fall below a certain level. As the low voltage detector will consume a cer- tain amount of power.

age setup function. SCOM Function for LCD The devices have the capability of driving external LCD panels. VDD. causing an in- Output Control terrupt to be generated if VDD falls below the preset LVD voltage. Note also which Port C pins are used for LCD driving.4V.0V and 4. The bias resistor choice is imple- SLEEP or IDLE Mode. This enables the LCD COM driver to tion is supplied by a reference voltage which will be generate the necessary VDD/2 voltage levels for LCD 1/2 automatically enabled. however this bit is tector. mented using the ISEL1 and ISEL0 bits in the SCOMC register. used in conjunction with the COMnEN bits to select cuitry to stabilise before reading the LVDO bit. When the device is powered bias operation. SCOM0~ SCOM3. down the low voltage detector will remain active if the The SCOMEN bit in the SCOMC register is the overall LVDEN bit is high. V D D V D D S C O M o p e r a tin g c u r r e n t V L V D V D D /2 S C O M 0 ~ L V D E N S C O M 3 L V D O C O M n E N S C O M E N tL V D S LVD Operation The Low Voltage Detector also has its own interrupt which is contained within one of the Multi-function inter. in addition to polling the LVDO bit. at Port Control register does not need to first setup the pins the voltage nears that of VLVD. VDD. 1. The Low Voltage Detector func. LCD COM Bias rupts. An external LCD panel can be driven using this device ing the power supply voltage. 1 1 SCOMn VDD/2 the LVF interrupt request flag will be set. falls below this pre-determined value. PC6 ~ PC7 port. a time delay tLVDS should be allowed for the cir. PC6 ~ PC7 voltage level stored in the LVDC register. as segment pins. however if the Low Voltage De. Note that the that as the VDD voltage may rise and fall rather slowly. The LCD COM driver enables a range of selections to tector wake up function is not required then the LVF flag be provided to suit the requirement of the LCD panel should be first set high before the device enters the which is being used. HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 LVD Operation LCD Operation The Low Voltage Detector function operates by compar. using the SCOMC register which in addition to control- the LVDO bit will be set high indicating a low power sup. When 1 0 I/O 0 or 1 the device is powered down the Low Voltage Detector will remain active if the LVDEN bit is high. In this case. Rev.00 165 November 3. master control for the LCD driver. This has a pins as common pins and using other output ports lines range of between 2. with a pre-specified by configuring the PC0~PC3 or PC0 ~ PC1. After enabling the Low Voltage De. The LCD driver function is controlled ply voltage. When the power sup. This will cause the device to wake-up from the LCD Bias Control SLEEP or IDLE Mode. providing an alternative means of low voltage de- tection. The LCD signals (COM and SEG) are generated using the application program. are pin shared with certain pin on the PC0~ PC3 or PC0 ~ PC1. The common pins for LCD driving. ling the overall on/off function also controls the bias volt- ply voltage condition. LVDO transitions. 2009 . there may be multiple bit as outputs to enable the LCD driver operation. The interrupt SCOMEN COMnEN Pin Function O/P Level will only be generated after a delay of tLVD after the LVDO 0 X I/O 0 or 1 bit has been set high by a low voltage condition.

00 166 November 3. ISEL0: ISEL1 ~ ISEL0: Select SCOM typical bias current (VDD=5V) 00: 25mA 01: 50mA 10: 100mA 11: 200mA Bit 4 SCOMEN: SCOM module Control 0: Disable 1: Enable Bit 3 COM3EN: PC3 or SCOM3 selection 0: GPIO 1: SCOM3 Bit 2 COM2EN: PC2 or SCOM2 selection 0: GPIO 1: SCOM2 Bit 1 COM1EN: PC1 or SCOM1 selection 0: GPIO 1: SCOM1 Bit 0 COM0EN: PC0 or SCOM0 selection 0: GPIO 1: SCOM0 Rev. HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 · SCOMC Register ¨ HT68F20 Bit 7 6 5 4 3 2 1 0 Name D7 ISEL1 ISEL0 SCOMEN COM3EN COM2EN COM1EN COM0EN R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7 Reserved Bit 0: Correct level . 1.bit must not be set high Bit 6~5 ISEL1.bit must be reset to zero for correct operation 1: Unpredictable operation . 2009 .

2009 . HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 ¨ HT68F30/HT68F40/HT68F50/HT68F60 Bit 7 6 5 4 3 2 1 0 Name D7 ISEL1 ISEL0 SCOMEN COM3EN COM2EN COM1EN COM0EN R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7 Reserved Bit 0: Correct level .00 167 November 3.bit must be reset to zero for correct operation 1: Unpredictable operation .bit must not be set high Bit 6~5 ISEL1. ISEL0: Select SCOM typical bias current (VDD=5V) 00: 25mA 01: 50mA 10: 100mA 11: 200mA Bit 4 SCOMEN: SCOM module control 0: disable 1: enable Bit 3 COM3EN: PC7 or SCOM3 selection 0: GPIO 1: SCOM3 Bit 2 COM2EN: PC6 or SCOM2 selection 0: GPIO 1: SCOM2 Bit 1 COM1EN: PC1 or SCOM1 selection 0: GPIO 1: SCOM1 Bit 0 COM0EN: PC0 or SCOM0 selection 0: GPIO 1: SCOM0 Rev. 1.

2 instructions LVR Options LVR Function: 8 1. 2009 . 8MHz 3.fL: 2 1. As these options are programmed into the device using the hardware programming tools. 2. 1 instructions 2. 4MHz 4 2. Enable 2.00 168 November 3. HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 Configuration Options Configuration options refer to certain options within the MCU that are programmed into the device during the program- ming process. 3. 12MHz Note: The fSUB and the fTBC clock source are LXT or LIRC selection by the fL configuration option. fSYS/4 HIRC Frequency Selection: 1.15V 4. HIRC Low Speed System Oscillator Selection . 2. 1. 4. All options must be defined for proper system function. Disable LVR Voltage Selection: 1. the details of which are shown in the table. Reset Pin Options PB0/RES Pin Options: 5 1.fH: 1.20V Rev. ERC 3. LIRC WDT Clock Selection .55V 3. fSUB 2. LXT 2.10V 9 2. Options Oscillator Options High Speed System Oscillator Selection . I/O pin Watchdog Options Watchdog Timer Function: 6 1. HXT 1 2. RES pin 2. Enable 2. During the development process. No. Disable CLRWDT Instructions Selection: 7 1.fS: 3 1. once they are selected they cannot be changed later using the application program. these options are selected using the HT-IDE software development tools.

Enable 2. Disable SPI . 1. Enable 2. ²**² It is recommended that this component is added in environments where power line noise is significant. Disable SPI . 2009 .CSEN bit: 12 1.1 ~ 1 m F P B 5 ~ P B 7 V S S P C 0 ~ P C 7 P D 0 ~ P D 7 O S C O S C 1 C ir c u it P E 0 ~ P E 5 O S C 2 S e e O s c illa to r P F 0 ~ P F 7 S e c tio n P G 0 ~ P G 1 O S C X T 1 C ir c u it X T 2 S e e O s c illa to r S e c tio n Note: ²*² It is recommended that this component is added for added ESD protection. No debounce 13 2.WCOL bit: 11 1. Disable I2C Debounce Time Selection: 1.00 169 November 3. 2 system clock debounce Application Circuits V D D 0 . Options SIM Options SIM Function: 10 1. Rev. 1 system clock debounce 3. HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 No.0 1 m F * * V D D 1 0 k W ~ R e s e t 1 0 0 k W C ir c u it 1 N 4 1 4 8 * 0 . Enable 2.1 m F R E S P A 0 ~ P A 7 3 0 0 W * 0 .

HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 Instruction Set Introduction sure correct handling of carry and borrow data when re- C e n t ra l t o t he s uc c es s f ul oper a t i on o f a n y sults exceed 255 for addition and less than 0 for sub- traction. There is The transfer of data within the microcontroller program no requirement to jump back to the original jumping off is one of the most frequently used operations. the Instruction Timing zero flag may be set if the result of the operation is zero. it must be noted that if the re. they have been subdivided into several func- instructions involving data manipulation. the program important data transfer applications is to receive data will continue with the next instruction or skip over it and from the input ports and transfer data to the output ports. They differ in the tions would be ²CLR PCL² or ²MOV PCL. Another form of logical data manipulation comes from tion cycle. The standard logical operations such as AND. One of the most vidual bits. data manipulation is a necessary feature of most microcontroller appl i c a t i ons . In the case of Holtek in the destination specified. One instruction cycle is equal to 4 system left. One special use of three kinds of MOV instructions. the program case of skip instructions. it is important to realize that any other instructions division calculations. In the case of a JMP instruction. routine using the CALL instruction. jump to the following instruction. 2009 . INCA. which is a set of pro- INC. the rotate instructions such as RR. Rotate instructions are useful for oscillator. RET. microcontroller. through the Accumulator which may involve additional programming steps. or ta. if no skip is involved return instruction RET in the subroutine which will cause then only one cycle is required.5ms and branch or call instructions would be im. Different rotate instructions exist depending on pro- clock cycles. most instructions would be implemented serial port programming applications where data can be within 0. OR. the program to jump back to the address right after the CALL instruction. garding the condition of a certain data memory or indi- diate data directly into the Accumulator. W i t hi n t he H o l t e k microcontroller instruction set are a range of add and subtract instruction mnemonics to enable the necessary arithmetic to be carried out. These instructions are the key to decision making and branching within the pro- Arithmetic Operations gram perhaps determined by the condition of certain in- The ability to perform certain arithmetic operations and put switches or by the condition of internal data bits. Although instructions which re. As instructions which change the contents of the Program branching takes the form of either jumps to PCL will imply a direct jump to that new address. Examples of such instruc. data must pass tional groupings. For the sense that in the case of a subroutine call. Making point as in the case of the CALL instruction. The exceptions to this are branch. which involve manipulation of the Program Counter Low register or PCL will also take one more cycle to imple. call. must return to the instruction immediately when the sub- sult of the comparison involves a skip operation then routine has been carried out. Here a decision is first made re- vice-versa as well as being able to move specific imme. Depending upon the conditions. RRC and RLC ble read instructions where two instruction cycles are which provide a simple means of rotating one bit right or required. a comprehensive and flexible set of over 60 instructions is provided to enable programmers Logical and Rotate Operations to implement their application with the minimum of pro- gramming overheads. In all logical data operations. As with the case of most codes. Another application where rotate data to the JMP. XOR and CPL all have their own instruction within the Holtek For easier understanding of the various instruction microcontroller instruction set. CALL. RETI and table read instruc.00 170 November 3. operations are used is to implement multiplication and tions. Most instructions are implemented within one instruc. A². one specified locations using the JMP instruction or to a sub- more cycle will be required. therefore in the case of an 8MHz system gram requirements. This is done by placing a this will also take one more cycle. The increment and decrement instructions microcontroller is its instruction set. Branches and Control Transfer ment. the Moving and Transferring Data program simply jumps to the desired location. DEC and DECA provide a simple means of gram instruction codes that directs the microcontroller to increasing or decreasing by a value of one of the values perform certain operations. data can be and extremely useful set of branch instructions are the transferred from registers to the Accumulator and conditional branches. RL. 1. where it can be examined and the necessary serial bit quire one more cycle to implement are generally limited set high or low. Care must be taken to en- Rev. rotated from an internal register into the Carry bit from plemented within 1ms.

AC. set categorised according to function and can be con- ation instructions are used.[m] Logical XOR ACC to Data Memory 1Note Z AND A. OV ADCM A. C.[m] Logical XOR Data Memory to ACC 1 Z ANDM A. magnetic environments. OV DAA [m] Decimal adjust ACC for Addition with result in Data Memory 1Note C Logic Operation AND A. OV SBCM A.[m] Add Data Memory to ACC with Carry 1 Z. Mnemonic Description Cycles Flag Affected Arithmetic ADD A.[m] Add Data Memory to ACC 1 Z. AC. manipulate the input data to ensure that other bits are not changed and then output the port Instruction Set Summary with the correct new data. OV ADC A. C.i² or ²CLR [m]. For their relevant operations. In addition to the above functional instructions. m: Data Memory address nient to store the fixed data in the Data Memory. when working with large amounts of x: Bits immediate data fixed data.[m] Subtract Data Memory from ACC with Carry 1 Z. the volume involved often makes it inconve. OV SUBM A. OV SUB A. AC.[m] Subtract Data Memory from ACC 1 Z. C. 8-bit output port. OV ADD A. A: Accumulator come this problem. OV SUB A. Table Read Operations Table conventions: Data storage is normally implemented by using regis- ters.[m] Logical OR ACC to Data Memory 1Note Z XORM A.x Logical AND immediate Data to ACC 1 Z OR A. C. AC.[m] Subtract Data Memory from ACC with Carry.i² instructions respectively. AC. AC. C. C.[m] Subtract Data Memory from ACC with result in Data Memory 1Note Z.x Subtract immediate data from the ACC 1 Z. This read-modify-write pro.[m] Add ACC to Data Memory 1Note Z. C. C. ture removes the need for programmers to first read the refer to the functional related sections. a range ory is an extremely flexible feature of all Holtek of other instructions also exist such as the ²HALT² in- microcontrollers. C. The fea. However.[m] Logical AND ACC to Data Memory 1Note Z ORM A. The following table depicts a summary of the instruction cess is taken care of automatically when these bit oper.x Logical XOR immediate Data to ACC 1 Z CPL [m] Complement Data Memory 1Note Z CPLA [m] Complement Data Memory with result in ACC 1 Z Increment & Decrement INCA [m] Increment Data Memory with result in ACC 1 Z INC [m] Increment Data Memory 1Note Z DECA [m] Decrement Data Memory with result in ACC 1 Z DEC [m] Decrement Data Memory 1Note Z Rev.[m] Logical OR Data Memory to ACC 1 Z XOR A.[m] Add ACC to Data memory with Carry 1Note Z. AC. A set of easy to use instruc- tions provides the means by which this fixed data can be referenced and retrieved from the Program Memory. OV ADDM A. Holtek microcontrollers allow an i: 0~7 number of bits area of Program Memory to be setup as a table where addr: Program memory address data can be directly stored.00 171 November 3.x Logical OR immediate Data to ACC 1 Z XOR A. This feature is especially useful for struction for Power-down operations and instructions to output port bit programming where individual bits or port control the operation of the Watchdog Timer for reliable pins can be directly set high or low using either the ²SET program operations under extreme electric or electro- [m]. To over. AC.x Add immediate data to ACC 1 Z. sulted as a basic instruction reference using the follow- ing listed conventions.[m] Logical AND Data Memory to ACC 1 Z OR A. OV SBC A. C. result in Data Memory 1Note Z. 2009 . AC. AC. 1. HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 Bit Operations Other Operations The ability to provide single bit operations on Data Mem.

Any instruction which changes the contents of the PCL will also require 2 cycles for execution. Rev.x Return from subroutine and load immediate data to ACC 2 None RETI Return from interrupt 2 None Table Read TABRD [m] Read table to TBLH and Data Memory 2note None TABRDL [m] Read table (last page) to TBLH and Data Memory 2Note None Miscellaneous NOP No operation 1 None CLR [m] Clear Data Memory 1Note None SET [m] Set Data Memory 1Note None CLR WDT Clear Watchdog Timer 1 TO. if no skip takes place only one cycle is required.A Move ACC to Data Memory 1Note None MOV A. 2009 . 3.00 172 November 3. PDF SWAP [m] Swap nibbles of Data Memory 1Note None SWAPA [m] Swap nibbles of Data Memory with result in ACC 1 None HALT Enter power down mode 1 TO. PDF CLR WDT2 Pre-clear Watchdog Timer 1 TO. HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 Mnemonic Description Cycles Flag Affected Rotate RRA [m] Rotate Data Memory right with result in ACC 1 None RR [m] Rotate Data Memory right 1Note None RRCA [m] Rotate Data Memory right through Carry with result in ACC 1 C RRC [m] Rotate Data Memory right through Carry 1Note C RLA [m] Rotate Data Memory left with result in ACC 1 None RL [m] Rotate Data Memory left 1Note None RLCA [m] Rotate Data Memory left through Carry with result in ACC 1 C RLC [m] Rotate Data Memory left through Carry 1Note C Data Move MOV A. For skip instructions.i Skip if bit i of Data Memory is zero 1Note None SNZ [m].i Set bit of Data Memory 1Note None Branch JMP addr Jump unconditionally 2 None SZ [m] Skip if Data Memory is zero 1Note None SZA [m] Skip if Data Memory is zero with data movement to ACC 1note None SZ [m]. 1. The TO and PDF flags are cleared after both ²CLR WDT1² and ²CLR WDT2² instructions are consecutively executed. Otherwise the TO and PDF flags remain unchanged. For the ²CLR WDT1² and ²CLR WDT2² instructions the TO and PDF flags may be affected by the execution status.i Skip if bit i of Data Memory is not zero 1Note None SIZ [m] Skip if increment Data Memory is zero 1Note None SDZ [m] Skip if decrement Data Memory is zero 1Note None SIZA [m] Skip if increment Data Memory is zero with result in ACC 1Note None SDZA [m] Skip if decrement Data Memory is zero with result in ACC 1Note None CALL addr Subroutine call 2 None RET Return from subroutine 2 None RET A. PDF Note: 1.[m] Move Data Memory to ACC 1 None MOV [m].i Clear bit of Data Memory 1Note None SET [m].x Move immediate data to ACC 1 None Bit Operation CLR [m]. if the result of the comparison involves a skip then two cycles are required. 2. PDF CLR WDT1 Pre-clear Watchdog Timer 1 TO.

HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 Instruction Definition ADC A. Z. AC. The result is stored in the specified Data Memory. AC. C ADCM A. C ADD A. Z. Operation [m] ¬ ACC + [m] + C Affected flag(s) OV. The result is stored in the Data Memory. AC. The result is stored in the Accumulator. Operation ACC ¬ ACC + [m] Affected flag(s) OV. The result is stored in the Accumulator. C ADD A. Operation ACC ¬ ACC ²AND² x Affected flag(s) Z ANDM A.[m] Logical AND ACC to Data Memory Description Data in the specified Data Memory and the Accumulator perform a bitwise logical AND op- eration.[m] Add Data Memory to ACC with Carry Description The contents of the specified Data Memory. AC.x Logical AND immediate data to ACC Description Data in the Accumulator and the specified immediate data perform a bitwise logical AND operation.[m] Add ACC to Data Memory with Carry Description The contents of the specified Data Memory. 1. Operation ACC ¬ ACC ²AND² [m] Affected flag(s) Z AND A. C ADDM A.00 173 November 3. Operation [m] ¬ ACC + [m] Affected flag(s) OV.[m] Add Data Memory to ACC Description The contents of the specified Data Memory and the Accumulator are added. Accumulator and the carry flag are added.[m] Logical AND Data Memory to ACC Description Data in the Accumulator and the specified Data Memory perform a bitwise logical AND op- eration.x Add immediate data to ACC Description The contents of the Accumulator and the specified immediate data are added. The result is stored in the Accumulator. AC. Z. C AND A. Operation ACC ¬ ACC + x Affected flag(s) OV. 2009 .[m] Add ACC to Data Memory Description The contents of the specified Data Memory and the Accumulator are added. The result is stored in the specified Data Memory. Z. Accumulator and the carry flag are added. The result is stored in the Accumulator. Operation ACC ¬ ACC + [m] + C Affected flag(s) OV. Operation [m] ¬ ACC ²AND² [m] Affected flag(s) Z Rev. Z. The result is stored in the Accumulator.

00 174 November 3. Re- petitively executing this instruction without alternately executing CLR WDT2 will have no effect. The specified address is then loaded and the program continues execution from this new address.i ¬ 0 Affected flag(s) None CLR WDT Clear Watchdog Timer Description The TO. PDF flags and the WDT are all cleared. Operation [m] ¬ 00H Affected flag(s) None CLR [m]. PDF flags and the WDT are all cleared. Re- petitively executing this instruction without alternately executing CLR WDT1 will have no effect. PDF flags and the WDT are all cleared. Operation [m]. Operation Stack ¬ Program Counter + 1 Program Counter ¬ addr Affected flag(s) None CLR [m] Clear Data Memory Description Each bit of the specified Data Memory is cleared to 0. Note that this instruction works in conjunc- tion with CLR WDT1 and must be executed alternately with CLR WDT1 to have effect. HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 CALL addr Subroutine call Description Unconditionally calls a subroutine at the specified address. The Program Counter then in- crements by 1 to obtain the address of the next instruction which is then pushed onto the stack. As this instruction requires an additional operation. Note that this instruction works in conjunc- tion with CLR WDT2 and must be executed alternately with CLR WDT2 to have effect. Operation WDT cleared TO ¬ 0 PDF ¬ 0 Affected flag(s) TO. Operation WDT cleared TO ¬ 0 PDF ¬ 0 Affected flag(s) TO. Operation WDT cleared TO ¬ 0 PDF ¬ 0 Affected flag(s) TO. 1. PDF CLR WDT2 Pre-clear Watchdog Timer Description The TO. it is a two cycle instruc- tion. PDF CLR WDT1 Pre-clear Watchdog Timer Description The TO. PDF Rev.i Clear bit of Data Memory Description Bit i of the specified Data Memory is cleared to 0. 2009 .

2009 .1 Affected flag(s) Z DECA [m] Decrement Data Memory with result in ACC Description Data in the specified Data Memory is decremented by 1. If the high nibble is greater than 9 or if the C flag is set. Bits which previously contained a 1 are changed to 0 and vice versa. HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 CPL [m] Complement Data Memory Description Each bit of the specified Data Memory is logically complemented (1¢s complement). Operation [m] ¬ [m] . then a value of 6 will be added to the high nibble. The result is stored in the Accu- mulator. PDF Rev. 06H. Operation [m] ¬ ACC + 00H or [m] ¬ ACC + 06H or [m] ¬ ACC + 60H or [m] ¬ ACC + 66H Affected flag(s) C DEC [m] Decrement Data Memory Description Data in the specified Data Memory is decremented by 1. The contents of the Data Memory and registers are retained.00 175 November 3.1 Affected flag(s) Z HALT Enter power down mode Description This instruction stops the program execution and turns off the system clock. The contents of the Data Memory remain unchanged. Only the C flag may be affected by this instruction which indicates that if the original BCD sum is greater than 100. The WDT and prescaler are cleared. If the low nibble is greater than 9 or if AC flag is set. 60H or 66H depending on the Accumulator and flag conditions. Operation ACC ¬ [m] . Operation TO ¬ 0 PDF ¬ 1 Affected flag(s) TO. it allows multiple precision decimal addition. 1. Essentially. Operation [m] ¬ [m] Affected flag(s) Z CPLA [m] Complement Data Memory with result in ACC Description Each bit of the specified Data Memory is logically complemented (1¢s complement). The complemented result is stored in the Accumulator and the contents of the Data Memory remain unchanged. the decimal conversion is performed by add- ing 00H. The power down flag PDF is set and the WDT time-out flag TO is cleared. Otherwise the low nibble remains unchanged. Operation ACC ¬ [m] Affected flag(s) Z DAA [m] Decimal-Adjust ACC for addition with result in Data Memory Description Convert the contents of the Accumulator value to a BCD ( Binary Coded Decimal) value re- sulting from the previous addition of two BCD variables. Bits which previously contained a 1 are changed to 0 and vice versa. then a value of 6 will be added to the low nibble.

The result is stored in the Accumu- lator. The contents of the Data Memory remain unchanged. As this requires the insertion of a dummy instruction while the new address is loaded. Operation ACC ¬ [m] Affected flag(s) None MOV A.A Move ACC to Data Memory Description The contents of the Accumulator are copied to the specified Data Memory. Operation No operation Affected flag(s) None OR A. Operation ACC ¬ x Affected flag(s) None MOV [m]. Operation [m] ¬ ACC Affected flag(s) None NOP No operation Description No operation is performed. The result is stored in the Accumulator. Execution continues with the next instruction. it is a two cycle instruction.[m] Logical OR Data Memory to ACC Description Data in the Accumulator and the specified Data Memory perform a bitwise logical OR oper- ation. HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 INC [m] Increment Data Memory Description Data in the specified Data Memory is incremented by 1.00 176 November 3. 1. Program execution then continues from this new address.x Move immediate data to ACC Description The immediate data specified is loaded into the Accumulator. 2009 . Operation Program Counter ¬ addr Affected flag(s) None MOV A.[m] Move Data Memory to ACC Description The contents of the specified Data Memory are copied to the Accumulator. Operation ACC ¬ [m] + 1 Affected flag(s) Z JMP addr Jump unconditionally Description The contents of the Program Counter are replaced with the specified address. Operation [m] ¬ [m] + 1 Affected flag(s) Z INCA [m] Increment Data Memory with result in ACC Description Data in the specified Data Memory is incremented by 1. Operation ACC ¬ ACC ²OR² [m] Affected flag(s) Z Rev.

Program execution continues at the restored address. 1. Program execution continues at the re- stored address. The result is stored in the Accumulator.0 ¬ [m].(i+1) ¬ [m]. (i = 0~6) ACC. Operation [m]. EMI is the master interrupt global enable bit.x Return from subroutine and load immediate data to ACC Description The Program Counter is restored from the stack and the Accumulator loaded with the specified immediate data.i. Operation [m] ¬ ACC ²OR² [m] Affected flag(s) Z RET Return from subroutine Description The Program Counter is restored from the stack. the pending Interrupt routine will be processed be- fore returning to the main program.[m] Logical OR ACC to Data Memory Description Data in the specified Data Memory and the Accumulator perform a bitwise logical OR oper- ation.(i+1) ¬ [m].x Logical OR immediate data to ACC Description Data in the Accumulator and the specified immediate data perform a bitwise logical OR op- eration.7 Affected flag(s) None Rev. The rotated result is stored in the Accumulator and the contents of the Data Memory re- main unchanged. (i = 0~6) [m]. HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 OR A. Operation Program Counter ¬ Stack EMI ¬ 1 Affected flag(s) None RL [m] Rotate Data Memory left Description The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0. 2009 . If an interrupt was pending when the RETI instruction is executed.0 ¬ [m]. Operation Program Counter ¬ Stack Affected flag(s) None RET A. The result is stored in the Data Memory.00 177 November 3. Operation ACC ¬ ACC ²OR² x Affected flag(s) Z ORM A.i. Operation Program Counter ¬ Stack ACC ¬ x Affected flag(s) None RETI Return from interrupt Description The Program Counter is restored from the stack and the interrupts are re-enabled by set- ting the EMI bit. Operation ACC.7 Affected flag(s) None RLA [m] Rotate Data Memory left with result in ACC Description The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0.

i ¬ [m]. Operation ACC.i ¬ [m].0 Affected flag(s) None RRC [m] Rotate Data Memory right through Carry Description The contents of the specified Data Memory and the carry flag are rotated right by 1 bit.7 ¬ C C ¬ [m]. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged.7 ¬ [m]. (i = 0~6) ACC. 1.(i+1) ¬ [m].7 ¬ C C ¬ [m].(i+1). (i = 0~6) [m]. (i = 0~6) [m].0 ¬ C C ¬ [m]. (i = 0~6) ACC. Bit 7 replaces the Carry bit and the original carry flag is rotated into bit 0. Operation [m].0 Affected flag(s) C Rev.0 Affected flag(s) None RRA [m] Rotate Data Memory right with result in ACC Description Data in the specified Data Memory and the carry flag are rotated right by 1 bit with bit 0 ro- tated into bit 7.(i+1) ¬ [m].00 178 November 3.0 ¬ C C ¬ [m]. (i = 0~6) [m].i ¬ [m]. Bit 0 re- places the Carry bit and the original carry flag is rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. (i = 0~6) ACC. HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 RLC [m] Rotate Data Memory left through Carry Description The contents of the specified Data Memory and the carry flag are rotated left by 1 bit.i.(i+1). Bit 7 replaces the Carry bit and the original carry flag is rotated into the bit 0. 2009 .7 Affected flag(s) C RR [m] Rotate Data Memory right Description The contents of the specified Data Memory are rotated right by 1 bit with bit 0 rotated into bit 7. Operation [m].i.0 Affected flag(s) C RRCA [m] Rotate Data Memory right through Carry with result in ACC Description Data in the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7.i ¬ [m]. Operation ACC.(i+1). Operation [m]. Operation ACC.7 ¬ [m].(i+1). The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged.7 Affected flag(s) C RLCA [m] Rotate Data Memory left through Carry with result in ACC Description Data in the specified Data Memory and the carry flag are rotated left by 1 bit.

Operation ACC ¬ [m] . Operation [m] ¬ FFH Affected flag(s) None SET [m]. the following instruction is skipped. the program proceeds with the following instruction. If the result is 0 the following instruction is skipped. The result is stored in the Accumulator. it is a two cycle instruction. AC.1 Skip if [m] = 0 Affected flag(s) None SDZA [m] Skip if decrement Data Memory is zero with result in ACC Description The contents of the specified Data Memory are first decremented by 1. The result is stored in the Data Memory. If the result is not 0 the program proceeds with the following instruction.i ¬ 1 Affected flag(s) None Rev. 2009 .[m] .C Affected flag(s) OV. As this requires the insertion of a dummy instruction while the next instruction is fetched. Operation [m]. HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 SBC A. the C flag will be cleared to 0. As this requires the insertion of a dummy in- struction while the next instruction is fetched.1 Skip if ACC = 0 Affected flag(s) None SET [m] Set Data Memory Description Each bit of the specified Data Memory is set to 1.[m] . If the result is not 0. C SDZ [m] Skip if decrement Data Memory is 0 Description The contents of the specified Data Memory are first decremented by 1. AC. it is a two cycle instruction. the C flag will be set to 1. Z.i Set bit of Data Memory Description Bit i of the specified Data Memory is set to 1. If the result is 0. Note that if the result of subtraction is negative. 1.[m] Subtract Data Memory from ACC with Carry and result in Data Memory Description The contents of the specified Data Memory and the complement of the carry flag are sub- tracted from the Accumulator. the C flag will be set to 1. C SBCM A. otherwise if the result is positive or zero.[m] Subtract Data Memory from ACC with Carry Description The contents of the specified Data Memory and the complement of the carry flag are sub- tracted from the Accumulator. Operation [m] ¬ [m] . Z. otherwise if the result is positive or zero. Operation [m] ¬ ACC . the C flag will be cleared to 0. Operation ACC ¬ ACC . The result is stored in the Accumulator but the specified Data Memory contents remain unchanged.C Affected flag(s) OV. Note that if the re- sult of subtraction is negative.00 179 November 3.

As this requires the insertion of a dummy instruction while the next instruction is fetched. Operation ACC ¬ [m] + 1 Skip if ACC = 0 Affected flag(s) None SNZ [m]. If the result is 0. As this requires the insertion of a dummy in- struction while the next instruction is fetched. the C flag will be set to 1. 1. As this re- quires the insertion of a dummy instruction while the next instruction is fetched. the following instruction is skipped. If the result is 0.00 180 November 3. The result is stored in the Accumulator. C Rev. HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 SIZ [m] Skip if increment Data Memory is 0 Description The contents of the specified Data Memory are first incremented by 1.i Skip if bit i of Data Memory is not 0 Description If bit i of the specified Data Memory is not 0. AC. the C flag will be cleared to 0. otherwise if the result is positive or zero. If the result is not 0 the program proceeds with the following instruction. the C flag will be set to 1.i ¹ 0 Affected flag(s) None SUB A. If the result is not 0 the program proceeds with the following instruction. Operation Skip if [m]. otherwise if the result is positive or zero.[m] Affected flag(s) OV. the C flag will be set to 1. Z. 2009 . Note that if the result of subtraction is negative. Note that if the result of subtraction is negative.[m] Affected flag(s) OV. C SUBM A.[m] Subtract Data Memory from ACC Description The specified Data Memory is subtracted from the contents of the Accumulator. the following instruction is skipped. it is a two cycle instruction. The result is stored in the Data Memory.x Subtract immediate data from ACC Description The immediate data specified by the code is subtracted from the contents of the Accumu- lator. If the result is 0 the program proceeds with the following instruction. Operation ACC ¬ ACC . AC. Z. AC. The result is stored in the Accumulator. Operation [m] ¬ [m] + 1 Skip if [m] = 0 Affected flag(s) None SIZA [m] Skip if increment Data Memory is zero with result in ACC Description The contents of the specified Data Memory are first incremented by 1. Operation [m] ¬ ACC . it is a two cycle instruction. The result is stored in the Accumulator but the specified Data Memory contents remain unchanged.[m] Subtract Data Memory from ACC with result in Data Memory Description The specified Data Memory is subtracted from the contents of the Accumulator. the following instruction is skipped. Note that if the result of subtraction is nega- tive. the C flag will be cleared to 0. Operation ACC ¬ ACC . the C flag will be cleared to 0. C SUB A.x Affected flag(s) OV. otherwise if the result is positive or zero. it is a two cycle instruction. Z.

As this re- quires the insertion of a dummy instruction while the next instruction is fetched. it is a two cycle instruction. 2009 . Operation ACC. Operation [m] ¬ program code (low byte) TBLH ¬ program code (high byte) Affected flag(s) None TABRDL [m] Read table (last page) to TBLH and Data Memory Description The low byte of the program code (last page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH.00 181 November 3.i Skip if bit i of Data Memory is 0 Description If bit i of the specified Data Memory is 0. The result is stored in the Accumulator. If the result is not 0 the program proceeds with the following instruction. If the value is zero. HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 SWAP [m] Swap nibbles of Data Memory Description The low-order and high-order nibbles of the specified Data Memory are interchanged. it is a two cycle instruction.4 Affected flag(s) None SWAPA [m] Swap nibbles of Data Memory with result in ACC Description The low-order and high-order nibbles of the specified Data Memory are interchanged.3~[m]. the following instruction is skipped.0 « [m]. the following instruction is skipped. 1. Operation Skip if [m] = 0 Affected flag(s) None SZA [m] Skip if Data Memory is 0 with data movement to ACC Description The contents of the specified Data Memory are copied to the Accumulator. As this requires the insertion of a dummy instruc- tion while the next instruction is fetched.7 ~ [m].0 Affected flag(s) None SZ [m] Skip if Data Memory is 0 Description If the contents of the specified Data Memory is 0.0 ¬ [m]. Operation [m]. If the result is not 0 the program proceeds with the following instruc- tion. Operation ACC ¬ [m] Skip if [m] = 0 Affected flag(s) None SZ [m]. the program proceeds with the following instruction.i = 0 Affected flag(s) None TABRD [m] Read table to TBLH and Data Memory Description The program code addressed by the table pointer (TBHP and TBLP) is moved to the speci- fied Data Memory and the high byte m