Dieu Khien He Thong Co Dien Tu Dung VDK PDF

B LAO NG THNG BINH V X HI
TRNG C NGH K THUT CNG NGH

TP. H CH MINH
GIO TRNH
IU KHIN H THNG C IN T
S DNG VI IU KHIN
(Dng cho trnh Cao ng)
TPHCM, thng 08 nm 2014

1
LI GII THIU
Gio trnh c nhm bin son t u da theo chng trnh khung v mn
hc iu khin h thng c in t s dng Vi iu khin ca khoa in
in t. Vi iu khin c s dng trong ti liu ny l h ATMEGA32 ca
hng ATMEL. y l mt trong nhng vi iu khin mnh v c s dng
rng ri hin nay.
Tp. H Ch Minh, ngy thng . nm 20

Tham gia bin son
1. Ch bin: Nguyn Vit Bc
2. nh Na
2
MC LC
MC TRANG
Li gii thiu........................................................................................ 1
Mc lc ................................................................................................. 2
Bi m u: Khi qut chung........................................................................ 3
1. S tng qut h thng c in t
2. Cu trc phn cng
Bi 1: Ngn ng C cho AVR ......................................................................... 21
1. Gii thiu phn mm CodeVisionAVR
2. Ngn ng C cho Vi iu Khin AVR
Bi 2: Lp trnh v m phng mt s chng trnh ng dng ................. 41
1. Lp trnh giao tip vi 8 LED n.
2. Lp trnh giao tip vi 2 LED 7 on.
3. Lp trnh giao tip vi ma trn phm bm
4. Lp trnh giao tip vi LCD
5. Lp trnh giao tip vi ng c bc
6. Lp trnh giao tip iu khin van t, xi lanh..
7. Hng dn s dng phn mn m phng Proteus
8. Hng dn cch np chng trnh cho vi iu khin.
Bi 3: Th nghim v vn hnh h thng c in t ................................. 84
1. Lp rp mch iu khin
2. Lp cm bin, nt n v phn t chp hnh vi Port I/O
3. Chy th v sa li
Ti liu tham kho ........................................................................................ 113
3
Bi m u
KHI QUT CHUNG
Mc tiu:
- Trnh by ng s khi chc nng ca h thng c in t;
- Phn tch c cu trc bn trong ca vi iu khin.
- c ng tn tng chn ca vi mch.
1. S tng qut h thng c in t

1.1. H thng c in t dng vi iu khin
Trn thc t, h thng c in t khng c mt nh ngha r rng. N c tch
bit hon ton cc phn ring bit nhng c kt hp trong qu trnh thc
hin. S kt hp ny c trnh by hnh sau, bao gm cc phn ring bit
in-in t, C kh v My tnh lin kt chng li trong cc lnh vc gio dc
v o to, cng vic thc t v cc ngnh cng nghip sn xut th trng.
Nh vy, h thng c in t l mt lnh vc a ngnh ca khoa hc k thut

hnh thnh t cc ngnh kinh in nh: C kh, in-in t v khoa hc tnh
ton tin hc. Trong tng hp h thng cc mn hc nh Truyn ng in,
Truyn ng c, Thy-kh, o lng cm bin, k thut vi x l hay vi iu
khin, lp trnh PLC
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1.2. V tr, chc nng ca vi iu khin trong h thng c in t
ng vai tr l mt b phn u no iu khin ton b h thng cn li, vi iu

khin cng nh vi x l v PLC l thnh phn khng th thiu c ca mt h
thng c in t. N l iu kin tin quyt cho s hot ng nhp nhng v
chnh xc ca ton b h thng.
2. Cu trc phn cng
2.1.Gii thiu h vi iu khin AVR
Vi iu khin AVR l b x l RISC vi kin trc Harvard vi c im l n
v x l trung tm (CPU) c b nh chng trnh v b nh d liu tch bit.
H vi iu khin AVR c nhng c im sau:
B nh flash c tch hp ngay trn chip v c kh nng lp trnh ngay
trn h thng c s dng lm b nh chng trnh.
Cc thanh ghi lm vic a nng 32-X-8 kt ni trc tip vi khi x l s
hc (ALU), cho php truy cp nhanh hn khi s dng cc chng lm bin
nh.
B nh d liu ngay trn chp loi EEPROM v RAM c hu ht trong
cc thnh vin AVR.
Hot ng vi xung nhp t 0 n 16 MHZ. Hu ht cc lnh thc hin
trong 1 chu k my
C b hot ng nh thi ngay trn chp v lp trnh c vi b chia tn
s tch bit. B nh thi s dng trong cc ng dng cn s phn nh
thi gian m s kin
Cc ngun ngt bn trong v bn ngoi.
C b nh thi watchdog (dng khi phc hot ng ca h thng khi
xy ra li treo phn mm) ngay trn chp v lp trnh c vi b dao
ng c lp.
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Nhiu chp c mch dao ng RC ngay trn chp.

2.2. S chn v chc nng tng chn
Hnh 1. S chn ATMEGA32

- Chn 1-8 l 8 bt vo ra ca cng B, xc nh t PB0-PB7
+ PB0(XCK/T0) - Xung vo/ra bn ngoi/u vo
time/counter 0
+ PB1(T1) - u vo time/counter 1
+ PB2(INT2/AIN0) - Ngt 2 bn ngoi/u vo khng
nh b so snh
+ PB3(OC0/AIN1) - u ra time/counter 0/u vo ph
nh b so snh
+ PB4(SS) - Chn u vo t
+ PB5(MOSI) - u vo Bus vo/ra ch/t
+ PB6(MISO) - u ra Bus vo/ra ch/t
+ PB7(SCK) - Bus ni tip clock
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- Chn 9 l u vo RESET: Khi tn hiu c a ln mc cao (trong t

nht 2 chu k my), cc thanh ghi trong b vi iu khin c ti nhng gi tr
thch hp khi ng h thng.
- Chn 10 l chn cp ngun.
- Chn 11 l chn ni GND.
- Chn 12 l XTAL2: u ra b khuch i o
- Chn 13 l XTAL1: u vo b khuch i o v u vo mch to
xung bn trong.
- Chn 14-21 l 8 bt vo ra ca cng D, xc nh t PD0-PD7
+ PD0(RXD) - Cng ni tip u vo
+ PD1(TXD) - Cng ni tip u ra
+ PD2(INT0) - Ngt 0 bn ngoi
+ PD3(INT1) - Ngt 1 bn ngoi
+ PD4(OC1B) - u ra so so snh timer/counter1 B
+ PD5(OC1A) - u ra so so snh timer/counter1 A
+ PD6(ICP) - u vo timer/counter1
+ PD7(CO2) - u ra timer/counter1
- Chn 22-29 l 8 bt vo ra ca cng C, xc nh t PC0-PC7
+ PC0(SCL) - Bus clock ni tip
+ PC1(SDA) - Bus vo/ra d liu ni tip
+ PC2(TCK) - Kim tra xung
+ PC3(TMS) - Chn ch kim tra
+ PC4(TDO) - D liu ra kim tra
+ PC5(TDI) - D liu vo kim tra
+ PC6(TOSC1) - Dao ng Timer1
+ PC7(TOSC2) - Dao ng Timer2
- Chn 30 l AVCC: Ngun cugn cp cho cng A v b chuyn i A/D
- Chn 31 lGND: Chn ni Mass ca chip.
- Chn 32 l AREF: u vo tng t lin quan n b chuyn i A/D
- Chn 33-40 l 8 bt vo ca cng A, xc nh t PA7-PA0: l cc u
vo (ADC7-ADC0) ca b chuyn i A/D.
2.3. Kin trc h AVR
Cc b x l AVR c kin trc Harvard, ngha l c b nh d liu v b nh
chng trnh tch bit nhau. Bus d liu dng cho b nh d liu l mt bus 8
7
bit, cho php ni hu ht cc ngoi vi vi tp thanh ghi. Bus d liu dng cho b
nh chng trnh c rng 16 bit v ch ni vi tp thanh ghi lnh.
B nh chng trnh l loi b nh flash. Dung lng chnh xc ca b nh
ny c s thay i khc nhau gia cc b vi x l cng h. B nh chng trnh
gm 1 phn l Application Flash Section (dng cho chng trnh ng dng) v
phn Boot Flash Section (phn khi ng). Boot section s c kho st
trong cc phn sau, trong bi ny khi ni v b nh chng trnh, chng ta t
hiu l Application section.
Hnh 2. Kin trc ca h AVR

Thc cht, Application Section bao gm 2 phn:
Phn cha cc m lnh (Instructions)
Phn cha cc vector ngt (Interrupt Vectors).
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Cc vector ngt nm phn u ca Application section (t a ch 0x0000)

v di n bao nhiu ty thuc vo loi chip. Phn cha instruction nm lin
sau , chng trnh vit cho chip phi c load vo phn ny.
B nh d liu (Data Memory): y l phn cha cc thanh ghi quan trng
nht ca chip, vic lp trnh cho chip phn ln l truy cp b nh ny. B nh
d liu trn cc chip AVR c ln khc nhau ty theo mi chip, tuy nhin
v c bn phn b nh ny c chia thnh 5 phn:
Phn 1: bao gm 32 thanh ghi R0 R31, mi thanh ghi c rng l 8
bit. Tt c cc b iu khin ca h AVR u c tp thanh ghi ny
Hnh 3. Bn b nh ca AVR
Phn 2: phn ny nm ngay sau Register File, bao gm 64 thanh ghi
c gi l 64 thanh ghi nhp/xut (64 I/O register) hay cn gi l
vng nh I/O (I/O Memory). Vng nh I/O l ca ng giao tip gia CPU
v thit b ngoi vi. Tt c cc thanh ghi iu khin, trng thica thit
b ngoi vi u nm y. Vic iu khin cc PORT ca AVR s lin
quan n 3 thanh ghi DDRx, PORTx v PINx, tt c 3 thanh ghi ny u
nm trong vng nh I/O. Xa hn, nu mun truy xut cc thit b ngoi vi
khc nh Timer, chuyn i Analog/Digital, giao tip USARTu thc
hin thng qua vic iu khin cc thanh ghi trong vng nh ny.
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Phn 3: B nh SRAM bn trong (Internal SRAM). B nh ny c hu

ht trn cc b vi x l AVR dung lng b nh ny c dung lng thay
i t 128 byte n 4 kbyte. B nh SRAM s dng cho cc bin cng
nh cho ngn xp
Phn 4: B nh SRAM ngoi (External SRAM) ch c b vi x l c
ln nh AT90S8515, ATMEGA128
Phn 5: B nh EEPROM (Electrically Ereasable Programmable ROM)
c hu ht trn cc b vi iu khin AVR c truy nhp theo bn nh
tch bit. a ch bt u ca b nh EEPROM lun l 0x000 Cc b vi
x l khc nhau c t 64 byte n 4 kbyte b nh EEPROM
Hnh 4. Cc thanh ghi R

2.4.Cc cng vo/ra
Vi iu khin ATMEGA32 c 32 ng vo ra chia lm bn nhm 8 bit mt.
Cc ng vo ra ny c rt nhiu tnh nng v c th lp trnh c. y
chng ta s xt chng l cc cng vo ra s. Nu xt trn mt ny th cc cng
vo ra ny l cng vo ra hai chiu (bi directional) c th nh hng theo
tng bit. V cha c in tr ko ln pull-up c th lp trnh c. Mc d mi
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Port c cc c im ring nhng khi xt chng l cc cng vo ra s th vic

iu khin vo ra d liu hon ton nh nhau.
Mi cng c cc thanh ghi sau: thanh ghi d liu cng (PORTA, PORTB,
PORTC, PORTD), thanh ghi d liu iu khin cng (DDRA, DDRB, DDRC,
DDRD) v a ch chn vo ca cng (PINA, PINB, PINC, PIND).
+ Thanh ghi DDRx:
y l thanh ghi 8 bit (c th c v ghi), c tc dng iu khin hng cng
Px (tc l cng ra hay cng vo). Nu nh mt bit trong thanh ghi ny c set
th bit tng ng trn Px c nh ngha nh mt cng ra. Ngc li nu
nh bit khng c set th bit tng ng trn Px l cng vo.
V d: Cho port A l ng ra:
DDRA = 0xff;
Cho 4 bit thp ca port B l ng vo, 4 bit cao l ng ra:
DDRB=0xf0;
+ Thanh ghi PORTx:
Thanh ghi 8 bit c th c/ghi ny l thanh ghi d liu ca cng Px.
Trong trng hp nu cng c nh ngha l cng ra th khi ta ghi mt bit ln
thanh ghi ny th chn tng ng trn Port cng c cng mc logic.
Trong trng hp m cng c nh ngha l cng vo th thanh ghi ny li
mang d liu iu khin cng. C th nu bit no ca thanh ghi ny c set
(a ln mc 1) th in tr treo (pull-up) ca chn tng ng ca port s
c kch hot. Ngc li n s trng thi tng tr cao. Thanh ghi ny sau khi
khi ng VK s c gi tr l 0x00.
V d: Kch hot 8 in tr treo ca portB
DDRB = 0x00;
PORTB = 0xff;
+ a ch chn vo PINx:
y l a ch cho php truy nhp trc tip ra cc chn vt l ca vi iu khin.
Tt nhin v th m vi a ch ny bn ch c th c m thi (Khng th ghi
c!!!)
V d: c d liu t PortB v ct vo bin data
data = PINB;
2.5.B nh thi
Timer/Counter l cc module c lp vi CPU. Chc nng chnh ca chng, l
nh thi (to ra mt khong thi gian, m thi gian) v m s kin. Trn
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cc chip AVR, cc b Timer/Counter cn c thm chc nng to ra cc xung

iu ch rng PWM (Pulse Width Modulation). mt s dng AVR, mt s
Timer/Counter cn c dng nh cc b canh chnh thi gian (calibration)
trong cc ng dng thi gian thc.
Cc b Timer/Counter c chia theo rng thanh ghi cha gi tr nh thi
hay gi tr m ca chng, c th trn chip Atmega8 c 2 b Timer 8 bit
(Timer/Counter0 v Timer/Counter2) v 1 b 16 bit (Timer/Counter1). Ch
hot ng v phng php iu khin ca tng Timer/Counter cng khng hon
ton ging nhau
c tnh:
- Bao gm cc b Timer 8 bit 16 bit, thng c t 3 4 b Timer
- C cc knh PWM (t 4 n 8 knh tu loi )
- Bao gm nhiu ch ngt v PWM
- C th l mt knh m ring bit
- T ng xo Timer trong ch so snh (t ng np li)
- C ch PWM
- To ra tn s
- m cc d kin ngt ngoi
- To ra cc ngt trn v ngt so snh
Cc ch hot ng ca timer:
+ Ch thng thng
y l ch hot ng n gin nht ca Timer. B m s lin tc m tng
ln cho n khi vt qu gi tr ln nht TOP v sau s c khi ng li
ti gi tr BOTTOM. Trong cc hot ng thng thng th c trn s c
thit lp khi gi tr trong Timer t gi tr khng v khng b xo i. Tuy nhin
nu m ngt trn c chp nhn th c ngt s t ng b xo khi ngt c
thc hin. Gi tr trong Timer c th c vit vo bt c lc no
+ Ch so snh (CTC)
y l ch m gi tr trong Timer lun c so snh vi gi tr trong thanh
ghi ORC. Khi gi tr trong Timer bng gi tr trong thanh ghi ORC th gi tr
trong Timer s b xo i. Gi tr trong ORC ng vai tr l gi tr TOP cho b
m. Ch ny cng cho php to ra tn s so snh u ra. Tuy nhin trong
ch ny nu gi tr mi ghi vo thanh ghi ORC m nh hn gi tr tc thi
ca b m th th 1 so snh s b l, khi b m s m n gi tr ln nht
sau ri xung gi tr 0 trc khi so snh tip theo xut hin.
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S thi gian ca ch CTC

+ Ch fast PWM
Cho php to ra sng vi tn s cao. S khc bit c bn gia Fast PWM vi
cc loi PWM khc l n ch s dng 1 sn dc. B m s m t Bottom
n Max sau khi ng li t Bottom. Trong ch khng o u ra ca
chn so snh OCx s bi xo khi c php ton so snh gia TCNTx v thanh ghi
ORC l bng nhau. V s c set ln 1 khi gi tr t Bottom. Trong ch
o, u ra o s c set ln 1 khi s so snh gia thanh ghi ORC v gi tr
trong Timer bng nhau v s b xo khi gi tr t Bottom. Trong c hai trng
hp ny tn s ca ch Fast PWM u gp i so vi ch phase correct
PWM s dng hai sn dc Vi tn s cao ny ch Fast PWM rt tt
cho cc ng dng nh ADC hay chnh lu. Ngoi ra vi tn s cao gip lm
gim kch thc ca thit b ngoi nh cun dy t t gip lm gim ton b
chi ph cho h thng.
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+ Ch Phase correct PWM
Ch ny hot ng da trn hai sn ln xung. B m s m lin tc t

gi tr BOTTOM n gi tr MAX v sau t gi tr MAX n gi tr
BOTTOM. Trong ch so snh khng o chn so snh (OCx) s b xa khi
gi tr TCNTx bng gi tr OCRx trong qu trnh m ln v s c set bng 1
khi gi tr so snh xut hin trong qu trnh m xung. Ch so snh o th
cc gi tr l ngc li. Vi hot ng hai sn xung ny th ch ny khng
to ra c tn s nh nh ch mt sn xung. Nhng do tnh cn i ca hai
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sn xung th n tt hn cho iu khin ng c. Ch phase correct PWM

hot ng c nh l 8 bt. Trong ch ny b m s tng cho n khi t gi
tr MAX, khi n s i chiu m.
T biu thi gian ta nhn thy vic thay i tn s trong hot ng ca
phase correct PWM c th thay th bng hai gi tr l MAX v BOTTOM. N
linh hot hn so vi ch Fast PWM.
Tn s c th tnh theo cng thc nh sau:
F = fc/N*510
Trong N to ra bi b chia n c cc gi tr l:1, 8, 64, 256 hoc 1024
Cc thanh ghi trong b Timer/ Counter
Thanh ghi iu khin - TCCRx:
Bt 3,6 WG00-WG01: y l cc bit chn ch trong Timer. Cc gi tr

c m t trong bng sau.
Bng chn ch Timer:
Bt 5-4 : COM00-COM01: Quy nh gi tr u ra trong cc php so snh

Bt 2: 0 CS2:0: y l cc bt quy nh xung cp cho hot ng ca Timer.
Bng di y m t ton b cc gi tr Chn ch cho xung Clock
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Thanh ghi c ngt-TIFR:
Bt 1-OCFx : Khi hai gi tr bng nhau bt ny c set ln bng 1.

Bt 1-TVOx : Khi b m vt qu gi tr Top th bt ny c set bng 1.
Thanh ghi mt n ngt-TIMSK:
Bt 1 OCIEx: Khi bt ny c set ln bng 1 th cho php ngt so snh.

Bt 0 TOIEX : Khi bt ny c set ln bng 1 th cho php ngt trn.
2.6.Cc b so snh (Analog Comparator)
B so snh tng t ca AVR c u vo l hai chn PB2 v PB3 (nh hnh
v), vi chn PB2 c ni vo cc dng ca b so snh v PB3 c ni
vo cc m ca b so snh. N to ra hai mc logic nu V+>V- th tn hiu ra
l 1 v ngc li l 0.
iu khin v quan st trng thi ca b so snh thng qua thanh ghi ACSR.
Thanh ghi ACSR l mt thanh ghi 8 bit c a ch trong cc thanh ghi I/O l
0x08 v c a ch trong khng gian b nh SRAM l 0x28. Trong 8 bit th c
7 bit c nh ngha v bit 6 khng c nh ngha. N ch c th c v
lun c gi tr logic l 0.
Bit 7-ACD (Analog Comparator Disable)) y l bit iu khin.Bit ny
trc tip iu khin hot ng ca AC (b so snh tng t). Nu bit ny
c set ln 1 th ngun cung cp cho AC hot ng b tt. Ch : ta c
th thay i gi tr logic ca bit ny lc no cng c ngng hot
ng ca chng hoc cho chng hot ng tr li nhng khi thay i gi
tr logic ca n th ngt (ngt ca AC) cn b cm nu khng n s sinh ra
mt ngt (C th l bit ACIE cn b xa).
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S khi b so snh tng t

Bit 5-ACO (Analog Comparator Output) bit trng thi. Bit ny c ni
trc tip vi u ra ca b so snh tng t.
Bit 4-ACI (Analog Comparator Interrupt Flag) C bo ngt ca b so
snh. Nu c ny c set v cc ngt c php th mt chng trnh
phc v ngt c gi v chng c xa bng phn cng khi chng
trnh bo ngt c phc v. Cc trng hp lm thay i trng thi c
ny ngoi vic thay i bit ACD s c ni ti trong cc bt 0 v 1.
Bit 3 ACIE (AC Interrupt Enable) bit iu khin. Nu bit ny c set
th ngt ny c php v ngc li.
Bit 2 ACIC (Analog Comparator Input Capture Enable) bit iu khin.
Khi bit ny c set ln 1 th u ra ca AC c ni trc tip vo u
vo ca chc nng bt s kin ca Timer/counter 1.( c thm
timer/counter1).
Bit ACIS1 v ACIS0 (AC Interrupt Mode Select) y l hai bit iu
khin.
ACIS1 ACIS0 Ch ngt
0 0 Theo mc
0 1 Dnh ring (cha dng n)
1 0 Sn xung
1 1 Sn ln
Ch : Cc bit ny cng c th c thay i bt c khi no. Nhng khi thay i
th ngt ca n phi b cm.
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Ta c th s dng lnh SBI hoc CBIU thay i trng thi cc bit trn thanh
ghi ny tr bit ACI. Bt ny sau khi c c cng s b xa (nu n c set).
Thit lp port u vo cho b so snh tng t: Hai chn PB2 v PB3 ny cn
c thit lp l u vo vo b in tr treo.
lp trnh cho AC ta bt u cc bc sau:
Bc 1: Thit lp cc chn u vo ADC.
Bc 2: Chn cc ch cho AC v nh dng ngt .
Bc 3: Khi ng AC bng cch xa bit ADC.
2.7.Giao din ngoi vi ni tip SPI
SPI l mt giao din thc hin vic trao i d liu gia cc thit b tng thch
vi khung gi liu 8bit v c truyn ng b. SPI cho php truyn d liu ni
tip ng b gia thit b ngoi vi v vi iu khin AVR hoc gia cc vi iu
khin AVR. SPI ca ATMEGA32 c cc c im:
- Ch song cng, truyn d liu ng b 3 dy.
- C th gi vai tr Master hoc Slave.
- Bit MSB hoc LSB c th c truyn trc ty vo ngi lp trnh.
- Bn tc truyn c th lp trnh thng qua hai bit.
- C ngt bo kt thc truyn.
- Vn hnh t trng thi ng (c nh thc t trng thi ng).
iu khin khi giao tip SPI th chng ta c 3 thanh ghi. l 1 thanh ghi
iu khin: SPCR(SPI control Register), mt thanh ghi trang thi SPSR (SPI
Status Register) v thanh ghi d liu SPDR (SPI Data Register).
Thanh ghi SPCR
y l thanh ghi 8 bit c a ch trong cc thanh I/O l 0x0D v trong SRAM l
0x2D. Cc bit trong thanh ghi ny u c th c hoc ghi
- Bit 7-SPIE: SPI interrupt enable. Bit ny cho php ngt ca b truyn tin
SPI (nu ngt ton cc v ngt ny c cho php th nu c SPIF c
bt th ngt s c phc v) .
- Bit 6-SPE: SPI Enable. Nu bit ny c set th khi SPI s c hot
ng v n phi c set trong sut qu trnh SPI hot ng.
- Bit 5-DORD: Data order. Khi m DORD c set th LSB ca byte d
liu s c truyn trc v ngc li.
- Bit 4-MSTR: Master/Slave select. y l bit dng la chn ch
master hay slave. Nu bit ny c set th b SPI ny c vai tr l Master
v ngc li. Nu nh SS c cu hnh l li vo v c t xung
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mc thp th MSTR b xa v 0v SPIF v SPSR b t ln 1 khi bn

s phi t li MSTR v 1.
- Bit 3-CPOL: Clock polarity. Khi bit ny c set th SCK mc cao
trong trng thi ng v ngc li.
- Bit 2-CPHA: Clock Phase. Quy nh pha kch hot ca xung nhp.
- Bit 1,0-SPR1,SPR0: Clock rate select: y l hai bit iu khin tc
xung nhp truyn ca kt ni v c thit lp trn Master. N khng c
tc dng g nu nh ta thit lp trn slave.
V gi tr ca chng ng theo t hp cc bit nh sau:

SPR1 SPR0 Tn s SCK
0 0 Fcl/4
0 1 Fcl/16
1 0 Fcl/64
1 1 Fcl/128
Nh vy y l thanh ghi iu khin ton b khi SPI t vai tr (Master/slave
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n tc truyn, cho php ngt, cho php hot ng, mc logic trong trang thi
ng v pha kch hot xung nhp.
V d 1:
Thit lp giao din SPI vi vai tr Master tc truyn l Fcl/128 pha kch hot
xung nhp thp khng cho php ngt v cha cho php hot ng.
l c iu trc ht cc bn cn phi thit lp cc chn cho SPI. C th
SCK l chn PB7 l output ng ngha vi DDB7 c set.MISO(PB6) l chn
vo v vy DDB6 xa v kch hot in tr ko th PORTB6 phi c set
ln 1. MOSI(PB5) l chn ra do DDB5 cn phi set ln 1. SS(PB4) y l
chn la chon thit b Slave v vy c nh ngha l chn ra v mc tch cc
thp (xa DDB4 v PORTB4).
on chng trnh nh sau:
sbi 0x17,7 ;set bit DDBR7 - t SCK l chn ra.
cbi 0x17,6 ;xa bit DDBR6-t PB6 l cng vo.
sbi 0x18,6 ;set bit PORTB6-Kch hot in tr ko.
sbi 0x17,5 ;t PB5 l chn ra.sbi 0x17,4cbi 0x18,4
OUT 0x0d,0b00010111
thit lp cho n l Slave th hon ton tng t.
Thanh ghi SPSR
y l thanh ghi 8 bit (c a ch 0x0e/0x2e) lu gi trng thi ca b truyn
nhn SPI. Nhng n ch c hai bt c nh ngha c kh nng c v ghi. Cc
bit cn li khng c nh ngha v khi c chng th c gi tr zero.
- Bit 7 - SPIF (SPI Interrupt Flag) Khi truyn xong mt byte d liu th bit
ny c set v mt ngt c to ra. Nu bit cho php ngt SPIE trong
thanh ghi SPCR c set v ngt ton cc c cho php th ngt c
thi hnh. Nu khng n s b b qua. Khi m chn ss ca Master c
nh ngha l cng vo li c thit lp mc thp th c ny cng c
set. N c xa bi phn cng hi ngt c phc v.
- Bit 6 - WCOL (Write Collision Flag) C bo xung t khi ghi. C ny
c set ln 1 nu nh d liu c ghi ln thanh ghi d liu SPI khi
ang din ra mt cuc truyn. V n c xa cng vi c SPIF khi c
thanh ghi trng thi v truy nhp vo thanh ghi d liu. bt u mt
cuc truyn th cc bn cn cho php b truyn nhn hot ng. Khi
truyn bn ch cn ghi byte d liu cn truyn ln thanh ghi d liu v i
cho ti khi c c SPIF bt ln ri tip tc truyn byte mi. bt u
nhn d liu cng vy. SPI c khi ng, ch khi no c SPIF bt
ln. y l s ghp ni gia hai b SPI song cng (nh ca 2 vi iu
20
khin AVR). i vi VK AVR th cc chn SCK (Serial clock) l chn

PB7, y l chn xung nhp ra trong trng hp n l Master v l chn
xung nhp vo nu n l Slave.
Khi ghi d liu ln thanh ghi d liu SPDR ca khi Master s khi ng b to
xung v d liu c dch v a ra chn MOSI (PB5) v vo chn MOSI ca
slave (PB5 i vi AVR). Sau khi dch ht mt byte b to xung ngng hot
ng, v c SPIF c pht bo kt thc truyn. Nu nh ngt ny c php
th chng trnh phc vu ngt s c phc v v khi c s b xa. u vo
la chn slave (SS v l chn PB4) c set mc tch cc thp la chn thit
b SPI slave v c dng cho vic ghp ni nhiu VK. Hai thanh ghi dch ca
hai b truyn v nhn (Master v slave) c xem nh l mt thanh ghi dch
vng 16 bit. V trong mt ln trao i d liu th d liu thanh ghi ca Master
v slave trao i cho nhau. Mt bSIP lm ng thi c hai nhim v
truyn v nhn nhng chng li ch c mt b m khi truyn v c hai b m
khi nhn.
Nh vy c ngha l d liu truyn i s khng c ghi ln thanh ghi d liu
truyn nu nh byte trc cha c truyn xong (hay c SPIF cha c
bt). V khi nhn d liu cng vy d liu cn phi c c trc khi d liu
mi c nhn xong.
21
Bi 1
NGN NG C CHO AVR
Mc tiu:
- Phn tch, gii thch c cc chng trnh vit bng C cho AVR
- ng dng cc tp lnh vo gii quyt cc bi ton thc t t ra
- C thc t gic, tch cc trong hc tp.
1. Gii thiu phn mm CodeVisionAVR

1.1. Gii thiu trnh dch CODEVISIONAVR C COMPILER
Trnh dch CodevisionAVR l trnh dch C cho h AVR. Trnh dch ny h tr
nhiu hm nh: c ADC, LCD, truyn thng, ISP, ng h thi gian thc
Trnh dch ny cn tch hp nhiu chng trnh nh kim tra truyn thng, np
trc tip ngay trn h thng nh mch np STK 200 hoc STK 500.
1.2. Cch to mt Project trong CodevisionAVR khng t sinh code
Khi ng chng trnh bng cch kch p chut vo biu tng trn mn hnh
CodecovisionAVR C Compile:
Sau chng trnh s khi ng v hin th nh sau:
22
To mt Project bng cch vo File / New:
Sau mn hnh s ra nh sau:

23
Chn Project sau n OK , sau mn hnh s hin ra nh sau:
Chn No (khng s dng Wizard ca chng trnh), mn hnh s hin ra nh

sau:
t tn Project sau ch ng dn n th mc cn lu ri n Save.

24
Ta c hnh sau:
25
Chn Tab C Compile mn hnh s ra nh hnh di : Sau chn chp, chn

tn s thch anh.V d chn chp ATMEGA 32, Clock l 16 MHz:
Chn tab After Build v check vo Program the Chip

26
Bc tip theo chng ta to 1 file.c bng cch vo File / New v chn Source.
Mn hnh s ra nh sau:
Sau cc bn son chng trnh, v d chng trnh to xung chn s 40 ca

chp. Cng PORTA.0 y l on m chng trnh:
#include <mega32.h>// thu vien chua dia chi cac thanh ghi chip
ATMEGA32
#include <delay.h>// thu vien chua cac delay
#define Xung PORTA.0 // dinh nghia dia chi dau tao xung
27
// chuong trinh chinh

void main(void)
{
DDRA=0xFF; //tat ca PORTA deu la dau ra
while (1)// vong lap vo tan
{
Xung=~Xung; // dao muc xung
delay_us(500);// tao tre 500 us
}
}
Sau lu file di dng .C. By gii ta thm file .C va to vo projet bng
cch vo Project / Configure:
Sau cc bn chn nut Add v chn file cn thm vo Project

28
Sau n Open:
Chn OK, sau n Shiflt+F9 bin dch chng trnh mn hnh s hin ra:
29
1.3. Cch to mt Project trong CodevisionAVR t sinh code

Sau khi khi ng chng trnh CodevisionAVR ta chn biu tng hnh bnh
rng trn thanh cng c (Run codeWiZardAVR Automatic Program Generator ).
Kch p chut vo vng nh du :
Sau chng trnh t sinh code xut hin:
Chng trnh s c cc tab Chip, Pports, Timers Tu theo tng ng dng khc
nhau m s c nhng la chn ch tng tab khc nhau, v d ta chn chp l
ATMGA32, Clock 32MHz, Portb tt c l g ra chng ta s lm nh sau: tab
chip chn chp ATMEGA32, Clock l 32MHz. Tab Ports chn Port B tt c l
u ra:
30
Sau lu project :
Lu file .C:
31
Lu file project dng prj:
Lu file.cwp:
32
Sau khi hon thnh cc bc trn chng trnh s to ra mt form chng trnh
t ch hot ng cho cc ngoi vi c trn chip. Cng vic cn li l vit
chng trnh tu theo thut ton v yu cu cng ngh.
Sau khi lp trnh song chng ta n F9 bin dch th hoc n Shift +F9 bin
dch chng trnh.
2. Ngn ng C cho Vi iu Khin AVR
2.1. Gii thiu
Ngn ng lp trnh thng chia lm 2 loi: Ngn ng bc thp (Assembler) v
Ngn ng bc cao (Pascal, Basic, C,). Ngn ng bc cao l cc ngn ng gn
vi ngn ng con ngi, do vic lp trnh bng cc ngn ng ny tr nn d
dng v n gin hn.
Khi s dng ngn ng C ngi lp trnh khng cn hiu su sc v cu trc ca
b vi iu khin. C ngha l vi mt ngi cha quen vi mt vi iu khin
cho trc s xy dng c chng trnh mt cch nhanh chng hn, do khng
phi mt thi gian tm hiu kin trc ca vi iu khin . V vic s dng li
cc chng trnh xy dng trc cng d dng hn, c th s dng ton
b hoc sa cha mt phn.
2.2. Cc kiu d liu c bn
Kiu d liu cho bit phm vi m 1 bin s dng trong chng trnh c th c.
Bin l ni dng cha s liu khi lp trnh.
Kiu S bit Khong gi tr
Char 8 -128 +127
Unsigned char 8 0 255
Int 16 -32768 - +32767
Unsigned int 16 0 - 65535
Long 32 -2147483648 - +2147483647
Unsigned long 32 0 4294697295
Bit 1 0-1
* Khai bo bin:
- C php: Kiu_d_liu Tn_bin;
V d:
Unsigned char x;
- Khi khai bo bin c th gn lun cho bin gi tr ban u.
33
V d:
Thay v: unsigned char x;
x = 0;
Ta ch cn: unsigned char x = 0;
- C th khai bo nhiu bin cng mt kiu mt lc.
V d: unsigned int x,y,z,t;
2.3. Mng
Mng l mt tp hp nhiu phn t cng mt kiu gi tr v chung mt tn.
Cc phn t ca mng phn bit vi nhau bi ch s hay s th t ca phn t
trong dy phn t. Mi phn t c vai tr nh mt bin v lu tr c mt gi
tr c lp vi cc phn t khc ca mng.
Mng c th l mng mt chiu hoc mng nhiu chiu
Khai bo: Tn_kiu Vng_nh Tn_mng[s_phn_t_mng];
Khi b trng s phn t mng ta s c mng c s phn t bt k.
V d:
Unsigned int data a[5],b[2] [3];
Vi khai bo trn ta s c: mng a l mng mt chiu 5 phn t. Mng b l mng
hai chiu, tng s phn t l 6.
Ch s ca mng bt u t s 0. Mng c bao nhiu chiu phi cung cp y
by nhiu ch s
V du: phn t mng b[0] [1] l ng
Khi vit b[0] l sai
2.4. Cc php ton trong ngn ng C
a. Php gn
Php gn k hiu: =.
C php: Bin_1 = Bin_2;
Trong Bin_2 c th l gi tr xc nh cng c th l bin.
V d: x = 3;
x = x + 1;
b. Php ton s hc
Php ton ngha V d

+ Php cng x = a+b
- Php tr x = a-b
34
* Php nhn x = a*b
/ Php chia ly phn nguyn x = a/b

(a = 9, b = 2 x = 4)
% Php chia ly phn d x = a%b
(a = 9, b = 2 x = 1)
c. Php ton Logic
Php ton ngha V d

&& Php V Logic (AND)
|| Php Hoc Logic (OR)
! Php Ph nh (NOT)
d. Cc php ton so snh
Php ton ngha V d

> So snh ln hn
>= So snh ln hn hoc bng

< So snh nh hn
<= So snh nh hn hoc bng

== So snh bng nhau
!= So snh khc nhau
e. Php ton thao tc Bit
Php ton ngha V d

& Php v (AND) Bit_1 & Bit_2
| Php hoc (OR) Bit_1 | Bit_2

! Php o (NOT) !Bit_1
^ Php hoc loi tr (XOR) Bit_1 ^ Bit_2

35
<< Dch tri a<<3
>> Dch phi a>>4

~ Ly b theo bit ~a
e. Php ton kt hp
Php ton ngha V d

+= Ton t cng v gn a+=5 <=> a=a+5
-= Ton t tr v gn a-=5 <=> a=a-5

*= Ton t nhn v gn a*=5 <=> a=a*5
/= Ton t chia v gn a/=5 <=> a=a/5
%= Ton t chia ly s d v a%=5 <=> a=a%5
gn
f. Php tng gim
Php ton ngha V d

++ Tng 1 n v
-- Gim 1 n v
2.5. Cc lnh c bn trong C

Cu lnh r nhnh if:
- Cu trc: if(dieu_kien)
{
// on chng trnh
}
Gii thch: nu dieu_kien ng th x l cc cu lnh bn trong cn sai th nhy

qua.
36
- Cu trc: if(dieu_kien)
{
// on chng trnh 1
}
else
{
// on chng trnh 2
}
Gii thch: nu dieu_kien ng th x l on chng trnh 1 bn trong cn
sai th x l on chng trnh 2
Cu lnh la chn:
Cu trc: switch (bien)
{
case gia_tri_1: {//cc cu lnh break;}
...
case gia_tri_n: {//cc cu lnh break;}
}
Gii thch: nu "bien" c gia_tri_1 th thc hin cc cu lnh tng ng ri sau
thot khi cu trc nh cu lnh break.
Bin c gia_tri_2 th thc hin cu lnh tng ng ri thot.
.
Bin c gia_tri_n th thc hin cc cu lnh tng ng ri thot.
Vng lp xc nh:
Cu trc: for(n=m;n<l;n++)
{
// cc cu lnh x l
}
Gii thch:
m, l l gi tr (m < l) , cn n l bin.
thc hin lp cc cu lnh (l-m) ln.
37
V d 1: Vit chng trnh tm ra s ln nht trong mng 100 phn t

Unsigned char mang[100], i, max;
{
max=mang[0];
for (i=1; i<100; i++)
{
If (max<mang[i]) max=mang[i];
}
}
V d 2: Sp xp tng dn 1 mng gm 100 phn t s char
Unsigned char mang[100], x, y, tam;
{
for (x=0; x<=98; x++)
for(y=x+1; y<=99; y++)
{
If (mang[x]>mang[y])
{
tam=mang[x];
mang[x]=mang[y];
mang[y]=tam;
}
}
}
Vng lp khng xc nh while:

Cu trc: while(dieu_kien)
{
// cc cu lnh
}
Gii thch: thc hin lp cc cu lnh trong khi iu kin cn ng. Nu iu
kin sai th thot khi vng lp.
V d: i s 1 byte sang s nh phn
Unsigned char so, np[8], i;
38
{
i=0;
While(so!=0)
{
np[i]=so%2; // s d ct vo mng np
so=so/2; //ly thng s
i++;
}
}
Vng lp khng xc nh do while:
Cu trc: do
{
// cc cu lnh
} while(dieu_kien);
Gii thch: thc hin lp cc cu lnh sau kim tra iu kin nu ng, nu
sai th thot khi vng lp.
2.6. Chng trnh con
Chng trnh con hay gi l hm (function) l on chng trnh c chc nng
nht nh c tch ra ring. Khi mun s dng hm, ngi s dng ch cn gi
tn hm. Nu hm yu cu cc tham s th ta phi cung cp y . Ch gi tr
tr v ca hm.
Vic s dng chng trnh con trong lp trnh s lm cho chng trnh chnh tr
nn sng sa v d hiu.
2.7. Cu trc chng trnh C
1. Cu trc chng trnh
* Cu trc
1. Khai bo ch th tin x l
2. Khai bo cc bin ton cc
3. Khai bo nguyn mu cc hm
4. Xy dng cc hm v chng trnh chnh
* V d:
#include<regx51.h>
Khai bo ch th tin x l
#include<string.h>
#define Led1 P1_0
39
Unsigned char code Led_arr[3];

Khai bo bin ton cc
Unsigned char data dem;
Unsigned int xdata X;
Void delay(unsigned int n);

Khai bo nguyn mu hm
bit kiemtra(unsigned int a);
void delay(unsigned int n)

{
Khai bo bin cc b;
M chng trnh tr; Xy dng cc hm
} v chng trnh
chnh
bit kiemtra (unsigned int a)
{
Khai bo bin cc b;
M chng trnh kim tra bin a;
}
void main()
{
Khai bo bin cc b;
M chng trnh chnh;
}
Ch : Hm khng khai bo nguyn mu phi c xy dng trc hm c li
gi hm . v d trn do hm bit kiemtra(unsigned int a) c khai bo
nguyn mu hm trn nn c th xy dng hm bt k v tr no trong
chng trnh.
2. Ch th tin x l
Cc ch th tin x l khng phi l cc lnh ca ngn ng C m l cc lnh gip
cho vic son tho chng trnh ngun C trc khi bin dch. Khi dch mt
chng trnh C th khng phi chnh bn chng trnh ngun m ta son tho
c dch. Trc khi dch, cc lnh tin x l s chnh l bn gc, sau bn
chnh l ny s c dch. C ba cch chnh l c dng l:
o Php thay th #define
40
o Php chn tp #include

o Php la chn bin dch #ifdef
* Ch th #define
o Ch th #define cho php to cc macro thay th n gin
o C php: #define Tn_thay_th dy_k_t
o V d: #define N 100
* Ch th #include
o Ch th #include bo cho trnh bin dch nhn ni dung ca tp khc v
chn vo tp chng trnh ngun m ta son tho.
o C php:
Cch 1: #include<tn_tp>
Cch 2: #includetn_tp
o V d:
Cch 1: #include<regx51.h>
cch ny tp regx51.h s c tm trong th mc INC chn
vo chng trnh ngun.
Cch 2: #includeregx51.h
cch ny tp regx51.h s c tm trong th mc cha chng
trnh ngun nu khng c mi tm trong th mc INC
3. Ch thch trong chng trnh
Vit ch thch trong trnh nhm mc ch gii thch ngha ca cu lnh, on
chng trnh hoc hot ng ca hm. Vit ch thch s gip cho ngi c c
th hiu c chng trnh d dng v nhanh chng.
Ch thch khng nh hng n chng trnh m ta son tho.
Li gii thch c t sau du // nu ch thch ch vit trn mt dng hoc
trong cp du \* v *\.
41
Bi 2
LP TRNH V M PHNG MT S CHNG TRNH NG DNG
Mc tiu:
- Phn tch c yu cu ca thut ton t ra.
- Vit ng chng trnh theo yu cu thut ton
- M phng c mch in t bng phn mm Proteus v sa li chng trnh.
- Sng to trong hc tp
1. Lp trnh giao tip vi 8 LED n

Trong module ny ta hc cch iu khin 8 Led n (2 mu). Xem li hnh v s
mch ta thy, 8 Led ny c ni n Port A v B ca vi mch 8255-1
Cc thng s ca Led n thng s dng l in p lm vic ca Led khong
2V, dng qua Led khong t 10 n 20 mA.
1.1. Bi thc hnh 1
/*****************************************************
Chip : ATmega32
Tn s thch anh : 16 MHz
Chc nng : Led chp tt 2 mu
*****************************************************/
#include <mega32.h>
#include <delay.h>
#include <8255.h>
#include <matrix.h>
void insys(void); //khai bo nguyn mu hm

//---------------------------------------------------
void main(void)
{
insys();
DDRA.2=1;
PORTA.2=1; //tt n nn mn hnh LCD
output_A(0xff); //tt ma trn LED
output_K(0xffff);
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write8255(0X80,'W',PPI_1);
while(1)
{
//led xanh
write8255(0Xff,'A',PPI_1); //cho led xanh sng
write8255(0X00,'B',PPI_1); //led do tat
delay_ms(500);
write8255(0X00,'A',PPI_1); //tat led xanh
delay_ms(500);
// led
write8255(0Xff,'B',PPI_1);
write8255(0X00,'A',PPI_1);
delay_ms(500);
write8255(0X00,'B',PPI_1);
delay_ms(500);
}
}
//-----khoi tao cac port

void insys(void)
{
PORTA=0x00;
DDRA=0xFF;
PORTB=0x00;
DDRB=0xFF;
PORTC=0x00;
DDRC=0xF0;
PORTD=0x00;
DDRD=0x00;
}
Cu hi bi tp
a. Thay i chng trnh Led sng 3 mu?
43
................................................................................................................................
................................................................................................................................
b. Thay i chng trnh Led thay i mu m khng c khong thi gian
tt?
................................................................................................................................
................................................................................................................................
................................................................................................................................
c. Cho bit Led xanh ni n Port no ca IC 8225 th my?
................................................................................................................................
d. Cho bit Led ni n Port no ca IC 8225 th my?
................................................................................................................................
1.2. Bi thc hnh 2
#include <mega32.h>
#include <delay.h>
#include <8255.h>
#include <matrix.h>
unsigned char a;
void insys(void);
//---------------------------------------------------
void main(void)
{
insys();
DDRA.2=1;
PORTA.2=1; //tat den nen man hinh LCD
output_A(0xff); //tat ma tran

output_K(0xffff);
write8255(0X80,'W',PPI_1);
while(1)
{
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//led G
a=0x01;
while(a!=0)
{
write8255(a,'A',PPI_1);
delay_ms(500);
a=a<<1;
}
a=0x80;
write8255(0X00,'A',PPI_1); //led xanh tat
while(a!=0)
{
write8255(a,'B',PPI_1);
delay_ms(500);
a=a>>1;
}
}
}
//-----khoi tao cac port
void insys(void)
{
PORTA=0x00;
DDRA=0xFF;
PORTB=0x00;
DDRB=0xFF;
PORTC=0x00;
DDRC=0xF0;
PORTD=0x00;
DDRD=0x00;
}
Cu hi Bi tp
45
a. Vit li chng trnh trn s dng vng lp for?

..........................................................................................................................................
..........................................................................................................................................
..........................................................................................................................................
..........................................................................................................................................
..........................................................................................................................................
..........................................................................................................................................
b. Vit li chng trnh Led sng dch 2 mu?
..........................................................................................................................................
..........................................................................................................................................
..........................................................................................................................................
..........................................................................................................................................
..........................................................................................................................................
..........................................................................................................................................
c. Thay on chng trnh Led xanh sng dch bng on chng trnh sau.
Quan st v rt nhn xt
a=0xfe;
while(a!=0)
{
write8255(~a,'A',PPI_1);
delay_ms(500);
a=a<<1;
}
..........................................................................................................................................
..........................................................................................................................................
..........................................................................................................................................
..........................................................................................................................................
d. Vit chng trnh cho Led sng dn t 2 pha, 1 pha l mu xanh, 1 pha l
mu
..........................................................................................................................................
..........................................................................................................................................
..........................................................................................................................................
..........................................................................................................................................
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..........................................................................................................................................
2. Lp trnh giao tip vi 2 LED 7 on
Module ny gii thiu cch iu khin Led 7 on, c th l:
+ Gii thiu cch to m 7 on cho Led
+ Gii thiu phng php qut Led
Do y khng s dng IC gii m LED 7 on, nn khi ta mun Led sng 1
con s no th ta phi xut 1 gi tr tng ng iu khin cc on Led sng.
Ta gi gi tr l m 7 on ca s .
Phng php qut: Ti mi mt thi im ta ch cho 1 transistor dn v 3

transistor cn li tt, d liu gi ra s sng trn led tng ng vi transistor dn.
Sau cho 1 transistor khc dn v gi d liu hin th cho led , qu trnh
47
iu khin ny din ra ln lt cho n khi ht 4 led. Vi tc gi d liu

nhanh v do mt ta c lu nh nn ta nhn thy 4 led sng cng 1 lc.
u im ca phng php ny l vi s chn giao tip nh, ta vn iu khin
c s lng Led ln. Ngoi ra mch ngun cung cp cho Led cng nh. Tuy
nhin phi tr gi bng vic chng trnh iu khin phc tp v sng ca
Led gim
Xem li hnh v mch nguyn l ta thy:
Cc chn ngun ca Led 7 on ni n 4 bit thp ca Port A ca
8255-2
Cc on Led ni n Port B ca 8255-2
2.1. Bi thc hnh 1
/*****************************************************
Chip : ATmega32
Chc nng : hin th 4 s khc nhau ln 4 LED theo pp qut
*****************************************************/
#include <mega32.h>
#include <delay.h>
#include <8255.h>
#include <matrix.h>
//khai bo m 7 on ca Led
unsigned char ma7doan[10]={0xc0,0xf9,0xa4,0xb0,0x99,0x92,0x82,0xf8,0x80,0x90};
void initport();
void hienthi();
void main()
{
unsigned int i,t;
initport();
output_A(0xff); //tt ma trn tit kim in
output_K(0xffff);
while(1)
{
48
hienthi();
}
}
void hienthi()
{
write8255(0x80,'W',2);
//xut ln lt tng s ra tng led trong 1 khong thi gian
write8255(0x0e,'A',2); write8255(ma7doan[0],'B',2); delay_us(1000);
write8255(0x0d,'A',2); write8255(ma7doan[1],'B',2); delay_us(1000);
write8255(0x0b,'A',2); write8255(ma7doan[2],'B',2); delay_us(1000);
write8255(0x07,'A',2); write8255(ma7doan[3],'B',2); delay_us(1000);
}
void initport()
{
PORTA=0x00;
DDRA=0xFF;
PORTB=0x00;
DDRB=0xFF;
PORTC=0x00;
DDRC=0xF0;
PORTD=0x00;
DDRD=0x00;
}
Cu hi Bi tp
a. Lu khong thi gian delay 1000us gia cc Led trong chng trnh hin th
l cn thit v khng c php thay i. Hy th cc gi tr 100ms, 50ms,
10ms, 1ms thy r phng php qut. Ghi ch
................................................................................................................................
..........................................................................................................................................
..........................................................................................................................................
..........................................................................................................................................
..........................................................................................................................................
b. Ti sao li xut cc gi tr 0x0e, 0x0d, 0x0b, 0x07 ra portA trong chng trnh
con hienthi()? Hy i cc gi tr ny sang s nh phn tm hiu!
49
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..........................................................................................................................................
..........................................................................................................................................
..........................................................................................................................................
..........................................................................................................................................
c. Hy thay i chng trnh Led hin th cc s nm trong 1 mng cc s
cho trc!
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2.2. Bi thc hnh 2
/*****************************************************
Chip : ATmega32
Chc nng : m hin th t 0000 - 9999
*****************************************************/
#include <mega32.h>
#include <delay.h>
#include <8255.h>
#include <matrix.h>
unsigned char led[4];

//khai bo m 7 on ca Led
unsigned char ma7doan[10]={0xc0,0xf9,0xa4,0xb0,0x99,0x92,0x82,0xf8,0x80,0x90};
void initport();
void giaima(unsigned int dat);
void hienthi();
void main()
{
unsigned int i,t;
50
initport();
output_A(0xff); //tt ma trn tit kim in

output_K(0xffff);
i=0000;
while(1)
{
giaima(i);
for(t=0;t<100;t++) hienthi(); //chng trnh con hienthi() c
// gi 100 ln qut v delay
if(i<9999) i++;
else i= 0;
}
}
void hienthi()
{
write8255(0x80,'W',2);
//xut ln lt tng s ra tng led trong 1 khong thi gian
write8255(0x0e,'A',2); write8255(led[3],'B',2); delay_us(1000);
write8255(0x0d,'A',2); write8255(led[2],'B',2); delay_us(1000);
write8255(0x0b,'A',2); write8255(led[1],'B',2); delay_us(1000);
write8255(0x07,'A',2); write8255(led[0],'B',2); delay_us(1000);
}
void giaima(unsigned int dat)
{
if(dat>9999) {led[0] = led[1] = led[2] = led[3] = '-';}
else
{
led[0] = ma7doan[dat/1000]; //nghn
led[1] = ma7doan[(dat%1000)/100]; //trm
led[2] = ma7doan[((dat%1000)%100)/10]; //chc
51
led[3] = ma7doan[((dat%1000)%100)%10]; //n v

}
}
void initport()
{
PORTA=0x00;
DDRA=0xFF;
PORTB=0x00;
DDRB=0xFF;
PORTC=0x00;
DDRC=0xF0;
PORTD=0x00;
DDRD=0x00;
}
Cu hi Bi tp
a. Thay i chng trnh tc m tng ln?
..........................................................................................................................................
..........................................................................................................................................
b. Th vit li chng trnh con gii m theo cch khc? Gii thch
..........................................................................................................................................
..........................................................................................................................................
..........................................................................................................................................
..........................................................................................................................................
c. Vit chng trnh m gi - pht: 2 led u hin th gi, 2 led sau hin th
pht
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52
..........................................................................................................................................
3. Lp trnh giao tip vi ma trn phm bm
3.1. Bi thc hnh 1
begin
St =1?
S St =2?
S St =3?
S St =4?
S
*

Gn St =2 Gn St =3 Gn St =4 Gn St =1
Chn ct 1 Chn ct 2 Chn ct 3 Chn ct 4
c port C (temp) c port C (temp) c port C (temp) c port C (temp)
S Hng 1 = 0? Hng 1 = 0?
S Hng 1 = 0?
S Hng 1 = 0?

M phm = 0 * M phm = 4 * M phm = 8 * M phm = 12 *
Hng 2 = 0? S Hng 2 = 0? S Hng 2 = 0? S Hng 2 = 0? S

* M phm = 1 * M phm = 5 * M phm = 9 * M phm = 13
S Hng 3 = 0? S Hng 3 = 0? S Hng 3 = 0? S Hng 3 = 0?
M phm = 2 * M phm = 6 * M phm = 10 * M phm = 14 *
Hng 4 = 0? S Hng 4 = 0? S Hng 4 = 0? S Hng 4 = 0? S

* M phm = 3 * M phm = 7 * M phm = 11 * M phm = 15
end * * * *
53
- Bin ST c vai tr chn ct qut. Mi khi chn c 1 ct qut th n

s tng ln chn ct k tip
- Hng v ct ca bn phm cng nm trong 1 portC nn khi thc hin chn
ct v c portC (c gi tr hng) th ta c cm tng gi tr c vo s
bng gi tr ta chn ct, nhng thc t th c th khc nhau nu lc ta
ang nhn phm
write8255(0b11101111,'C',PPI_1); //ghi m chn ct ra portC
temp = read8255('C',PPI_1); //c gi tr hng
- Vic thc hin kim tra xem phm no c nhn thng qua vic kim tra
gi tr hng vi 1 mt n bit thch hp
Khi chn ct (cho ct bng 0) v ti thi im nu c phm c nhn th gi

tr hng cng bng 0
/*****************************************************
Chip : ATmega32
Chc nng : c bn phm ma trn v hin th ln 2 LED 7 on
*****************************************************/
#include <mega32.h>
#include <delay.h>
#include <8255.h>
#include <matrix.h>
// Declare your global variables here

unsigned char fkey,st;
54
unsigned char
ledcode[10]={0xc0,0xf9,0xa4,0xb0,0x99,0x92,0x82,0xf8,0x80,0x90};
void insys(void);
void keypress(void)
{
unsigned char temp;
write8255(0X81,'W',PPI_1);
if(st==1) //
{
st=2;
write8255(0b11101111,'C',PPI_1); //ghi m chn ct ra portC
temp = read8255('C',PPI_1); //c li portC
if((temp&0x01)==0) //tm xem phm no c n
{ fkey=1; //nu n phm th hng =0
}
else if((temp&0x02)==0)
{ fkey=2;
}
{ fkey=3;
}
{ fkey=4;
}
}
else if(st==2)
{
st=3;
write8255(0b11011111,'C',PPI_1);
temp = read8255('C',PPI_1);
if((temp&0x01)==0)
{ fkey=5;
55
}
{ fkey=6;
}
{ fkey=7;
}
{ fkey=8;
}
}
else if(st==3)
{
st=4;
write8255(0b10111111,'C',PPI_1);
if((temp&0x01)==0)
{ fkey=9;
}
{ fkey=10;
}
{ fkey=11;
}
{ fkey=12;
}
}
else if(st==4)
{
st=1;
write8255(0b01111111,'C',PPI_1);
56
if((temp&0x01)==0)
{ fkey=13;
}
{ fkey=14;
}
{ fkey=15;
}
{ fkey=16;
}
}
}
//---------------------------------------------------
void main(void)
{
unsigned char c,dv;
insys();
output_A(0xff);
output_K(0xffff);
PORTA.2=1;
while(1)
{
keypress(); //gi chng trnh qut phm
c=fkey/10;
dv=fkey%10;
write8255(0X80,'W',PPI_2); // PA=PB=PC=output
write8255(ledcode[dv],'B',PPI_2); //m led
write8255(0b11111110,'A',PPI_2); //chn led
delay_us(2000);
57
write8255(ledcode[c],'B',PPI_2);
write8255(0b11111101,'A',PPI_2);
delay_us(2000);
}
}
//------------------------------------------------------
void insys(void)
{
fkey=0; //ban u hin th s 0
st=1; //bin thng bo ang qut ct no
PORTA=0x00;
DDRA=0xFF;
PORTB=0x00;
DDRB=0xFF;
PORTC=0x00;
DDRC=0xF0;
PORTD=0x00;
DDRD=0x00;
}
Cu hi Bi tp
a. Ghi cc m chn ct ra y.
...........................................................................................................................................
...........................................................................................................................................
...........................................................................................................................................
...........................................................................................................................................
b. Ghi ch thch v chng trnh y
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58
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3.2. Bi thc hnh 2
/*****************************************************
Chip : ATmega32
Chc nng : c bn phm ma trn v hin th ln 2 LED 7 on
*****************************************************/
#include <mega32.h>
#include <delay.h>
#include <8255.h>
#include <matrix.h>
// Declare your global variables here

unsigned char fkey;
unsigned char
ledcode[10]={0xc0,0xf9,0xa4,0xb0,0x99,0x92,0x82,0xf8,0x80,0x90};
void insys(void);
unsigned char keypress()

{
unsigned char i,quet=0x10,mh=0,mp=0xff, temp;
write8255(0X81,'W',PPI_1);
for(i=0;i<4;i++)
{
write8255(~quet,'C',PPI_1);
if((temp&0x0f)!=0x0f)
{
delay_ms(20);
if((temp&0x0f)!=0x0f)
{
if((temp&0x0f)==0x0e) mp=0+mh;
if((temp&0x0f)==0x0d) mp=1+mh;
if((temp&0x0f)==0x0b) mp=2+mh;
if((temp&0x0f)==0x07) mp=3+mh;
i=4;
59
do
{
}
while(temp&0x0f!=0x0f);
}
}
quet=quet<<1; mh=mh+4;
}
return mp;
}
//---------------------------------------------------
void main(void)
{
unsigned char c,dv;
insys();
output_A(0xff);
output_K(0xffff);
PORTA.2=1;
while(1)
{
fkey=keypress(); //gi chng trnh qut phm
if (fkey!=0xff)
{
c=fkey/10;
dv=fkey%10;
}
write8255(0X80,'W',PPI_2); // PA=PB=PC=output
write8255(ledcode[dv],'B',PPI_2); //m led
write8255(0b11111110,'A',PPI_2); //chn led
delay_us(2000);
write8255(ledcode[c],'B',PPI_2);
write8255(0b11111101,'A',PPI_2);
delay_us(2000);
60
}
}
//------------------------------------------------------
void insys(void)
{
PORTA=0x00;
DDRA=0xFF;
PORTB=0x00;
DDRB=0xFF;
PORTC=0x00;
DDRC=0xF0;
PORTD=0x00;
DDRD=0x00;
}
Cu hi Bi tp
a. Ghi ch thch v chng trnh y
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b. Khi c phm nhn th bin fkey bng bao nhiu?
.................................................................................................................................
.................................................................................................................................
c. Nu u im ca chng trnh qut phm ny so vi chng trnh trc ?
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61
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d. To th vin mykey.h s dng ln sau.
.................................................................................................................................
3.3. Bi thc hnh 3
/*****************************************************
Chip : ATmega32
Chc nng : m 00-99 c nt Start v Stop
*****************************************************/
#include <mega32.h>
#include <delay.h>
#include <8255.h>
#include <matrix.h>
#include <mykey.h> //s dng thm th vin mi to
unsigned char led[4];

unsigned char
ma7doan[10]={0xc0,0xf9,0xa4,0xb0,0x99,0x92,0x82,0xf8,0x80,0x90};
void initport();
void giaima(unsigned int dat);
void hienthi();
void main()
{
unsigned int i,t,tt;
initport();
output_A(0xff); //tat ma tran

output_K(0xffff);
PORTA.2=1; //tat man hinh LCD
i=0000;
62
tt=0;
while(1)
{
giaima(i);
while (tt==0)
{
if (keypress()==00) tt=1; //nu c phm nhn th mi tip tc
hienthi();
}
for(t=0;t<100;t++)
{
if (keypress()==01) tt=0; //nu nhn phm th stop
hienthi();
}
if(i<9999) i++;
else i= 0;
}
}
void hienthi()
{
write8255(0x80,'W',2);
write8255(0x0e,'A',2); write8255(led[3],'B',2); delay_us(1000);

write8255(0x0d,'A',2);write8255(led[2],'B',2); delay_us(1000);
write8255(0x0b,'A',2); write8255(led[1],'B',2); delay_us(1000);
write8255(0x07,'A',2);write8255(led[0],'B',2); delay_us(1000);
}
void giaima(unsigned int dat)
{
if(dat>9999) {led[0] = led[1] = led[2] = led[3] = '-';}
else
{
led[0] = ma7doan[dat/1000];
63
led[1] = ma7doan[(dat%1000)/100];
led[2] = ma7doan[((dat%1000)%100)/10];
led[3] = ma7doan[((dat%1000)%100)%10];
}
}
void initport()
{
PORTA=0x00;
DDRA=0xFF;
PORTB=0x00;
DDRB=0xFF;
PORTC=0x00;
DDRC=0xF0;
PORTD=0x00;
DDRD=0x00;
}
Cu hi Bi tp
a. Cho bit phm no l Start v phm no l Stop? Hy thay i cc phm ny
theo thch ca bn!
...........................................................................................................................................
...........................................................................................................................................
...........................................................................................................................................
b. Khi nhn nt Stop ti s ang hin th, chng trnh c dng ngay s ang
hin th hay khng? Hy khc phc.
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...........................................................................................................................................
...........................................................................................................................................
c. Bin tt c chc nng g?
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...........................................................................................................................................
d. Khi bin tt c gi tr 0 th chng trnh lm nhng vic g?
64
...........................................................................................................................................
...........................................................................................................................................
e. Vit chng trnh theo yu cu nh sau:
+ Ban u Led hin th s 00
+ Nhn phm UP ri th: Led tng 1 n v. Gi tr tng ti a l 99
+ Nhn phm DOWN ri th: Led gim 1 n v. Gi tr gim ti thiu l 00
+ Nhn phm AUTO ri th: Led t ng gim t s ang hin th v 00
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4. Lp trnh giao tip vi LCD
Trong module ny trnh by cch iu khin mn hnh LCD v s dng th vin
vit trong phn trc mylcd.h
4.1. Bi thc hnh 1
/*****************************************************
Chip : ATmega32
Chc nng : iu khin LCD hin th 2 dng ch v nhp nhy n nn
*****************************************************/
#include <mega32.h>
#include <delay.h>
#include <8255.h>
#include <mylcd.h>
#include <matrix.h>
65
//----------------------------------------------
unsigned char hang1[]={"TRUONG CD NGHE KTCN"};
unsigned char hang2[]={" KHOA DIEN-DIEN TU "};
//---------------------------------------------------
void main(void)
{ unsigned int t;
PORTA=0x00;
DDRA=0xFF;
PORTB=0x00;
DDRB=0xFF;
PORTC=0x00;
DDRC=0xF0;
PORTD=0x00;
DDRD=0x00;
output_A(0xff);
output_K(0xffff);
In_LCD(); //khi to LCD trc

led_LCD=0;
Write_command_LCD(0x80); //con tr v dng 1 ct 1

for(t=0;hang1[t]!=0;t++)
Write_data_LCD(hang1[t]); //vit ra mn hnh
Write_command_LCD(0xC0); //con tr v dng 2, ct 1

Write_data_LCD(hang2[t]);
while (1) //cho n nn LCD chp tt

{
led_LCD=0; delay_ms(1000);
66
led_LCD=1; delay_ms(1000);
};
}
Cu hi Bi tp
a. Sa li chng trnh bi tp mu v cho dng ch th 2 nhp nhy (n nn
mn hnh LCD vn sng). Cho bit tng vit chng trnh
..........................................................................................................................................
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..........................................................................................................................................
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b. Sa li chng trnh hin th tn v m s sinh vin ca bn
..........................................................................................................................................
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4.2. Bi thc hnh 2
/*****************************************************
Chip : ATmega32
Chc nng : m 00 - 99 hin th LCD
*****************************************************/
#include <mega32.h>
#include <delay.h>
#include <8255.h>
#include <mylcd.h>
#include <matrix.h>
//----------------------------------------------
unsigned char hang1[]={" CHUONG TRINH DEM "};
//---------------------------------------------------
void main(void)
{ unsigned int t;
PORTA=0x00;
DDRA=0xFF;
PORTB=0x00;
67
DDRB=0xFF;
PORTC=0x00;
DDRC=0xF0;
PORTD=0x00;
DDRD=0x00;
output_A(0xff);
output_K(0xffff);

led_LCD=1; //khng tt n nn
Write_data_LCD(hang1[t]); //vit ra mn hnh
t=0; //s dng li bin t

while (1)
{
Write_command_LCD(0xC7);
Write_data_LCD((t/10)+0x30);
Write_data_LCD((t%10)+0x30);
delay_ms(500);
t++;
if (t==100) t=0;
};
}
Cu hi Bi tp
a. Vit chng trnh m 0000 9999 hin th mn hnh LCD
..........................................................................................................................................
..........................................................................................................................................
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68
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..........................................................................................................................................
b. Vit chng trnh m gi - pht giy hin th mn hnh LCD
..........................................................................................................................................
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..........................................................................................................................................
..........................................................................................................................................
c. Ti sao dng lnh Write_command_LCD(0xC7); lun c lp trong vng
lp v tn?
..........................................................................................................................................
..........................................................................................................................................
..........................................................................................................................................
..........................................................................................................................................
d. Tm hiu ngha ca gi tr 0x30 trong lnh hin th trong vng lp?
..........................................................................................................................................
..........................................................................................................................................
..........................................................................................................................................
e. Thay gi tr 0x30 bng 0. Nhn xt
..........................................................................................................................................
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f. B sung th vin mylcd.h bng 1 hm c chc nng nh sau: di chuyn con
tr ca mn hnh LCD i n dng x, ct y
- Tn hm: gotoxy
- Tham s truyn: gi tr dng x v gi tr ct y
- Gi tr tr v: k c
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69
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..........................................................................................................................................
..........................................................................................................................................
g. B sung th vin mylcd.h bng 1 hm c chc nng nh sau: ghi 1 chui ra
mn hnh LCD
- Tn hm: put_string
- Tham s truyn: a ch chui cn ghi
- Gi tr tr v: k c
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..........................................................................................................................................
..........................................................................................................................................
4.3. Bi thc hnh 3
/*****************************************************
Chip : ATmega32
Chc nng : Chy ch trn mn hnh
*****************************************************/
#include <mega32.h>
#include <delay.h>
#include <8255.h>
#include <mylcd.h>
#include <matrix.h>
//--20 khong trng trc v sau DONG CHU CHAY---
unsigned char hang1[]={ DONG CHU CHAY };
unsigned char hang2[]={HAY CHU Y!!!}
//---------------------------------------------------
void main(void)
{ unsigned int x,y;
70
PORTA=0x00;
DDRA=0xFF;
PORTB=0x00;
DDRB=0xFF;
PORTC=0x00;
DDRC=0xF0;
PORTD=0x00;
DDRD=0x00;
output_A(0xff);
output_K(0xffff);

led_LCD=1; //khng tt n nn

for(x=0;hang2[x]!=0;x++)
Write_data_LCD(hang2[x]); //vit ra mn hnh ch Ch
delay_ms(5000);
while (1)
{
for(x=0; x<34; x++)
{
Write_command_LCD(0xC0);
for(y=0;y<20;y++)
Write_data_LCD(hang1[x+y]);
delay_ms(50);
}
};
}
Cu hi Bi tp
a. Ghi ch v chng trnh y
..........................................................................................................................................
71
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..........................................................................................................................................
..........................................................................................................................................
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b. Hy th vit chng trnh chy ch m khng cn thm d liu khong trng
nh bi mu.
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5. Lp trnh giao tip vi ng c bc (Step motor)
ng c bc c chc nng iu khin cc thit b di chuyn vi khong cch
ngn v d nh iu khin di chuyn u c a. Tu thuc vo cng sut ca
ng c m s dng cc mch giao tip cho ph hp. Thng th cc ng c
bc lun i km vi mch iu khin v ch nhn lnh t vi x l hay vi iu
khin.
Hnh ng c bc
S cun dy trong ng c bc
72
ng c bc n cc c 5 ng ra: trong c 4 u dy coil1coil4 dng

iu khin, cn u dy common dng ni ngun cung cp
Cc kiu iu khin ng c bc c 4 cun dy
Kiu 1: kch 1 cun dy, ng c quay 1 bc
Bc Cun dy c kch Chiu quay ng c
A B A\ B\ Thun Nghch
1 1 0 0 0
2 0 1 0 0
3 0 0 1 0
4 0 0 0 1
5 1 0 0 0
Kiu 2: kch 2 cun dy, ng c quay 1 bc
1 1 1 0 0
2 0 1 1 0
3 0 0 1 1
4 1 0 0 1
5 1 1 0 0
Kiu 3: pha trn gia 2 kiu kch trn, ng c quay 1/2 bc
73
1 1 0 0 0
2 1 1 0 0
3 0 1 0 0
4 0 1 1 0
5 0 0 1 0
6 0 0 1 1
7 0 0 0 1
8 1 0 0 1
9 1 0 0 0
10 1 1 0 0
Mt thng s quan trng ca ng c bc l s bc cn quay 1
vng. Thng thng th gi tr l 200 bc, ngha l mi bc gc quay ca
ng c l 1,8 (1,8 x 200 bc = 360 = 1 vng)
Lu : thi gian delay cho mi bc nm trong khong 5ms 50ms. Nhanh hn
th ng c khng p ng c v chm qu th ng c quay git cc
5.1. Bi thc hnh 1

/*****************************************************
Chip : ATmega32
Chc nng : iu khin ng c bc quay phi 1 vng v quay tri 1
vng
*****************************************************/
#include <mega32.h>
#include <delay.h>
#include <matrix.h>
//----------------------------------------------
#define Step1 PORTD.2 //4 cun dy
#define Step2 PORTD.3
#define Step4 PORTA.0
74
#define Io_step1 DDRD.2

#define Io_step4 DDRA.0
#define CW1 0
#define CW2 1
void Stepmotor(unsigned char step,unsigned int T,unsigned char CW);

void main(void)
{
output_A(0xff);
output_K(0xffff);
Io_step1=Io_step2=Io_step3=Io_step4=1;
while (1)
{
Stepmotor(200,10,CW1);
delay_ms(1000);
delay_ms(1000);
};
}
//iu khin ng c bc quay
//step = s bc
// T = thi gian delay
// CW = chiu quay
void Stepmotor(unsigned char step, unsigned int T, unsigned char CW)
{
unsigned char i, st;
st=step/4;
if(CW==CW1)
{
75
for(i=0;i<st;i++)
{
Step1=0;Step2=1;Step3=1;Step4=1;delay_ms(T);
Step1=1;Step2=1;Step3=0; Step4=1;delay_ms(T);
}
}
else if(CW==CW2)
{
for(i=0;i<st;i++)
{
}
}
}
Cu hi Bi tp
a. Thay i chng trnh tng tc ng c? Gim tc ng c? Lu
vai tr ca gi tr delay_ms(T).
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b. Thay i chng trnh ng c quay thun vng ri quay nghch vng
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c. Vit chng trnh iu khin ng c theo kiu kch 2 cun dy?
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76
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d. Gii thch vic lm st=step/4?
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5.2. Bi thc hnh 2
/*****************************************************
Chip : ATmega32
Chc nng : iu khin ng c bc bng bn phm
*****************************************************/
#include <mega32.h>
#include <delay.h>
#include <matrix.h>
#include <8255.h>
#include <mykey.h>
//----------------------------------------------
#define Step1 PORTD.2 //4 cu?n dy
#define Step4 PORTA.0

#define Io_step4 DDRA.0
#define CW1 0
#define CW2 1
void Stepmotor(unsigned char step,unsigned int T,unsigned char CW);
void main(void)
{ unsigned char fkey;
77
output_A(0xff);
output_K(0xffff);
//Io_step1=Io_step2=Io_step3=Io_step4=1;
while (1)
{
fkey=keypress(); //c bn phm
if (fkey!=0xff) //nu c phm nhn th tip tc
{
if (fkey==00)
{
write8255(0x80,'W',2);
write8255(0x0e,'A',2); write8255(0xbf,'B',2);
}
else if (fkey==01)
{
write8255(0x80,'W',2);
write8255(0x07,'A',2); write8255(0xbf,'B',2);
}
}
};
}
void Stepmotor(unsigned char step, unsigned int T, unsigned char CW)
{
unsigned char i, st;
st=step/4;
if(CW==CW1)
{
for(i=0;i<st;i++)
{
78
}
}
else if(CW==CW2)
{
for(i=0;i<st;i++)
{
}
}
}
Cu hi Bi tp
a. Thay i chng trnh khi ng c ang quay m nhn 1 phm xc nh th
ng c dng quay
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6. Lp trnh giao tip iu khin van t, xi lanh
Van t v xi lanh l cc thit b chp hnh trong mt h thng c in t. Tuy
nhin, khi m phng hoc thc hnh trn KIT ta c th s dng cc Led ch th
thay th. Trong phn ny, ngi hc hy vn dng cc bi tp lm gii
quyt cc yu cu c a ra. Hy vit cc chng trnh sau:
Bi 1: Hy vit chng trnh iu khin 4 xi-lanh bng 2 nt nhn Start/Stop
(bn phm ma trn). Bt u, cc xi lanh trng thi ng. Khi nhn nt Start,
tun t xi-lanh 1 m, cho n xi-lanh 4 m. Thi gian ch gia cc xi-lanh l 1
giy. Nu nhn nt Stop th tun t t xi-lanh 1 ng trc cho n xi-lanh 4
ng (thi gian ch l 1 giy).
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79
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Bi 2: Hy vit chng trnh iu khin m sn phm hin th Led 7 on: 2
Led tri dng ch s sn phm, 2 Led phi dng ch s thng. Khi s sn
phm t 20 th s thng tng ln 1. Khi s thng t 50 th h thng reset v gi
tr ban u. Mi khi s sn phm t 20, h thng ng gi hot ng:
Van t 1 ng trong vng 2 giy a thng i ra khi bng chuyn, h
thng tm ngng m
Van t 2 ng trong vng 1 giy, ri n van t 3 ng trong vng 2 giy
ng gi thng.
Van t 4 ng trong vng 1 giy a thng sn phm khc n. H
thng tip tc m sn phm.
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80
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7. Hng dn s dng phn mm m phng Proteus
Phn ny gii thiu s lc v phn mm m phng Proteus (phin bn ln
ti version 7.10). y l 1 phn mm mnh, tch hp nh gn cho php ta v,
thit k mch nguyn l, thit k mch in. Nhng c l chc nng c s dng
ti nhiu nht l chc nng m phng. N c kh nng m phng cc dng
mch s, mch tng t hoc vi iu khin vi tnh nng tng tc trc quan rt
cao. B th vin ca phn mm ny cho php ta kho st c rt nhiu linh
kin dng o m nh thc trc khi bt tay vo lm mch.
Khi ng phn mm bng cch click chut vo biu tng ISIS Professional
trn mn hnh. Ta c giao din chng trnh nh sau:
81
Thanh tc v: cha 1 s lnh thng dng ca thanh trnh n dng shortcuts

Thanh cng c: tp hp cc chc nng hay linh kin ph tr c s dng
trong v mch v m phng mch
Cc nt m phng
Thao tc ly linh kin: ta chn nt Components v nhn nt P (Pick Devices)

ly linh kin
Th vin m ra nh sau:
nh tn linh kin cn tm vo Keywords. Chn th vin linh kin trong

vng Category. Vng PCB Preview s hin th dng chn ca linh kin.
Sau khi tp hp linh kin ra ngoi vng lm vic xong th ta tin hnh kt ni
mch theo s c.
8. Hng dn cch np chng trnh cho vi iu khin
Sau khi bin dch sang file.hex chng ta np xung chp ca kit chy chng
82
trnh. Kt ni cp: 1 u ni cng song song ca my tnh (cng 25 chn ca

my tnh hay cn gi l cng ny in), 1 u vi gic np ISP ca ATMEG32
TRAINNING KIT, bt ngun ca kit.
Vo Settings/Programmer, chn thng s nh hnh sau:
Nhn vo hnh con chip trn thanh cng c hoc Tool/Chip Programmer hoc
Shift+F4.
Chng trnh np s khi ng. Ch chip lm vic l ATmega32.

83
Load chng trnh cn np vo b m:
Sau chn chng trnh cn np v nhn nt Program All

Sau khi np song n Cancel:
84
Bi 3
TH NGHIM V VN HNH H THNG C IN T
Mc tiu:
- Lp rp ng mch iu khin.
- Lp t ng v m bo thng s k thut cc cm bin, nt n ca h thng
c in t v kt ni vi cng vo/ra ca b vi iu khin;
- X l c li pht sinh trong h thng.
- Ch ng, sng to v an ton trong qu trnh hc tp.
1. Lp rp mch iu khin
M hnh h thng thang my 4 tng:
Thang my c thit k di chuyn vi mt tc nht nh. Tuy nhin vi

mi loi thang my c tc khc nhau th khi tin hnh thit k phn mm
iu khin thang u phi tnh ton cho hot ng ca thang my c ti u
nht da trn hai ch tiu: Thi gian ch i ca khch hng l ngn nht, v
qung ng di chuyn ca thang my l ngn nht.
Trong thc t, h thng iu khin thang my rt phc tp, nht l i vi k
thut tng t. Tuy nhin, vi s ra i ca k thut s gip h thng iu
khin thang my c n gin hn. Mt trong nhng ng dng iu khin
thang my l s dng Vi iu khin ni chung v Vi iu khin h 8051 ni
ring.
85
H thng thang my thc t gm:

1. H thng ca
2. H thng yu cu
3. H thng ch th
4. Bo hiu qu ti
5. B iu khin trung tm
6. H thng cung cp thng tin v nng lng,
H thng thang my hot ng theo nguyn l chung nh sau:
1. Khi cabin ang trong ch khng ti th cabin lun ch ch th (yu
cu) ngi s dng. Khi c lnh (yu cu) ca ngi s dng, h thng
x l s kim tra v quyt nh hot ng cho cabin, h thng ca, h
thng thng bo, h thng bo ng,
2. Khi cabin ang hot ng, nu ngi s dng ra ch th, b iu khin
trung tm s nhn tn hiu v kim tra hot ng hin thi v hot ng
yu cu ra quyt nh tip tc hay ngng hot ng ca cabin.
3. Cabin c th ln, xung theo yu cu nhng khng chp nhn ngt hot
ng hin hnh. H thng ch nhn lnh khi c thng bo cabin khng
lm vic v b qua tt c yu cu khi cabin ang hot ng. Thng tin
v tng, bung ang hin hnh v thng tin tng, bung yu cu c
lu li v so snh.
S khi h thng iu khin thang my
86
Lp rp mch nguyn l theo s sau:
2. Lp cm bin, nt n v phn t chp hnh vi Port I/O

Lp rp cc h thng cn li ca thang my theo yu cu:
Cm bin ca
87
Cm bin tng
Nt nhn ln xung mi tng
Led hin th bo tng mi tng v trong thang my
3. Chy th v sa li
Vit chng trnh iu khin thang my hot ng theo cc nguyn l
chung a ra trong phn 1.
Sa cha mch giao tip v chng trnh nu c li
V lu hot ng ca chng trnh iu khin
88
Ph lc
Cc s mch in
a. Mch tng qut
89
b. Cc ng tn hiu t CPU
90
c. Ma trn LED
91
d. Vi mch 8255
92
e. Led 7 on phng php qut

93
f. ng c bc
94
g. ng c DC
95
h. Card PT100
96
i. Card ADDA
97
j. Relay
98
Cc th vin cn lu
99
a. Th vin iu khin vi mch 8255

Th vin ny (8255.h) cha 1 s khai bo chn ca vi mch 8255 v 2 chng trnh
con cho php c v ghi vi mch.
Gii thiu IC 8255A
IC 8255A l mt trong nhng IC giao tip c s dng ph bin nht, thng c
gi l mch giao tip ngoi vi lp trnh c (Programmable Peripheral Interface
PPI)
Do cc port ca 8255A c chia thnh nhm A v nhm B tch ri nn t iu khin

ca 8255A cng c chia lm hai nhm.
Cc bit D D D dng nh cu hnh cho nhm B:
2 1 0
Bit D dng thit lp 4 bit thp ca port C:

0
D = 0 port C thp l port xut d liu (output)

0
D = 1 port C thp l port nhp d liu (input).

0
Bit D dng thit lp port B:

1
D = 0 port B l port xut d liu (output)

1
100
D = 1 port B l port nhp d liu (input).

1
Bit D dng thit lp Mode iu khin ca nhm B:

2
D = 0: nhm B hot ng Mode 0.

2
D =1: nhm B hot ng Mode 1.

2
Cc bit D ,D ,D ,D dng nh cu hnh cho nhm A:

6 5 4 3
Bit D dng thit lp 4 bit cao ca port C:

3
D = 0 port C l port xut d liu (output)

3
D = 1 port C l port nhp d liu (input).

3
Bit D dng thit lp port A:

4
D4 = 0 port A l port xut d liu(output)

D4 = 1 port A l port nhp d liu (input).
Bit D D dng thit lp Mode iu khin ca nhm A:
6 5
D D = 00: nhm a hot ng Mode 0.

6 5
D D = 01: nhm A hot ng Mode 1.

6 5
D D = 1: nhm A hot ng Mode 2.

6 5
101
Ni dung th vin
//cc bt iu khin
#define RD_8255 PORTC.4
#define RW_8255 PORTC.5
#define A0 PORTA.3
#define A1 PORTA.4
#define CS_8255_1 PORTC.7
#define CS_8255_2 PORTC.6
//cc chn iu khin vo hoc ra

//1 la ra, 0 la vao
#define IO_RD_8255 DDRC.4
#define IO_RW_8255 DDRC.5
#define IO_A0 DDRA.3
#define IO_A1 DDRA.4
#define IO_CS_8255_1 DDRC.7
#define IO_CS_8255_2 DDRC.6
#define PPI_1 1
#define PPI_2 2
/*---chng trnh con ghi d liu ra 8255

data la d liu cn ghi
ch la kenh.... 'A' la portA, 'B' la portB
'C' la port C, 'W' la thanh ghi dieu khien
cs1 la chon chip...PPI_1 hoac PPI_2 */
void write8255(unsigned char data, unsigned char ch, unsigned char csl)
{
// Port B OUPUT
DDRB=0xFF;
// cc chn tn hiu l ng ra
IO_A0 = 1;
IO_A1 = 1;
IO_CS_8255_1 = 1;
IO_CS_8255_2 = 1;
IO_RW_8255 = 1;
102
IO_RD_8255 = 1;
//la chn vi mch 8255
if(csl==PPI_1)
{
CS_8255_1 = 0;
CS_8255_2 = 1;
}
else
{
CS_8255_1 = 1;
CS_8255_2 = 0;
}
RD_8255 = 1;
//la chn Port
switch(ch)
{
case 'A': //PortA
A0 = 0;
A1 = 0;
break;
case 'B': //PortB
A0 = 1;
A1 = 0;
break;
case 'C': //PortC
A0 = 0;
A1 = 1;
break;
case 'W': //control word = thanh ghi dieu khien
A0 = 1;
A1 = 1;
}
PORTB = data; //xuat du lieu
//tao xung ghi
RW_8255 = 0; //delay_us(10);
RW_8255= 1;
CS_8255_1 = 1; //khoa cac chip

CS_8255_2 = 1;
}
103
//-------------chng trnh con c d liu t 8255----

unsigned char read8255(unsigned char ch, unsigned char csl)
{
unsigned char data;
// PORTB INPUT
DDRB=0x00;
// nh ngha cc chn tn hiu l ng ra
IO_A0 = 1;
IO_A1 = 1;
IO_CS_8255_1 = 1;
IO_CS_8255_2 = 1;
IO_RW_8255 = 1;
IO_RD_8255 = 1;
if(csl==PPI_1)
{
CS_8255_1 = 0;
CS_8255_2 = 1;
}
else
{
CS_8255_1 = 1;
CS_8255_2 = 0;
}
RW_8255 = 1;
switch(ch)
{
case 'A': //PortA
A0 = 0;
A1 = 0;
break;
case 'B': //PortB
A0 = 1;
A1 = 0;
break;
case 'C': //PortC
A0 = 0;
A1 = 1;
break;
case 'W': //thanh ghi dieu khien
104
A0 = 1;
A1 = 1;
}
//to xung c
RD_8255=0; //delay_us(10);
RD_8255=1;
data = PINB; //c d liu t 8255
CS_8255_1 = 1;
CS_8255_2 = 1;
return data; //gi tr tr v
}
b. Th vin iu khin ma trn
Th vin ny (matrix.h) dng iu khin IC cht 74HC595 kt ni n ct v hng
ca ma trn Led. Lu l ma trn 2 mu nn s dng ti 3 vi mch 74HC595 (tham
kho thm phn s mch)
Gii thiu IC 74HC595
Vi mch 74HC595 l vi mch thanh ghi dch 8 bit vi ng ra cht (8 Bit Shift Register
with Output Latch) c chc nng bin d liu ni tip thnh song song.
105
Chc nng cc chn nh sau:

- OE (output enable): cho php xut ng ra
- RCLK: xung cht
- SRCLK: xung dch
- SRCLR: xung xa
- SER: ng vo ni tip
- QA QH : cc ng ra song song
106
- QH : ng ra ni tip (dng ni tng IC)

Ta thy cu to ca IC ny gm 2 tng Flip Flop. Ng vo SER c a n FF
u tin ca tng th nht. Xung dch SRCLK s dch tng bit ng vo SER n
cc FF ca tng th nht ny. Sau 8 xung dch, ta tc ng xung cht RCLK
chuyn d liu t tng FF th nht sang tng FF th 2. Do , d liu ny s k b
nh hng cho d d liu tng 1 thay i.
Begin
a 1 bit n SER
To xung dch
Sai
Dch 8
bit?
ng
To xung cht
End
Ni dung th vin
//-------cc bit tn hiu--------
#define DATA PORTD.7 //ng vo
#define CLK PORTD.6 //xung dch
#define STK PORTC.3 //xung cht IC m dng
#define STA PORTC.2 //xung cht IC m ct
#define IO_DATA DDRD.7

#define IO_CLK DDRD.6
#define IO_STK DDRC.3
#define IO_STA DDRC.2
//---chng trnh con dch d liu ra 8 ct ca ma trn---
void ouput_A(unsigned char x)
107
{
unsigned char buffer,j;
IO_DATA =1;
IO_CLK =1;
IO_STA =1;
IO_STK =1;
buffer = 0x01; //mt n bit

for(j = 0; j < 8; j++)
{
CLK = 0; //chun b xung dch
if(x&buffer) //kim tra tng bit d liu
DATA = 1;
else
DATA = 0;
CLK = 1; //to xung dch
buffer <<= 1;
}
STA=0; //to xung cht
delay_us(50); // rng xung
STA=1;
}
//---chng trnh con dch d liu ra 8 hng ca ma trn----
//---ma trn c 2 mu nn d liu dch 16 bit---
void output_K(unsigned int x)
{
unsigned char i;
signed int buffer;
IO_DATA =1;
IO_CLK =1;
IO_STK =1;
IO_STA =1;
buffer=0x0001; //mt n bit
for(i=0;i<16;i++)
{
CLK=0;
if(x&buffer) DATA=1;
else DATA=0;
CLK=1;
108
buffer<<=1;
}
STK=0; //xung cht
delay_us(10);
STK=1;
}
c. Th vin mn hnh LCD
LCD1 LM044L
Th vin ny (mylcd.h) cha cc khai bo chn iu khin mn hnh LCD v 3
chng trnh con iu khin LCD
Gii thiu mn hnh LCD
VDD
VSS
VEE
RW
RS
D0
D1
D2
D3
D4
D5
D6
D7
E
1
2
3
4
5
6
7
8
9
10
11
12
13
14
LCD c rt nhiu dng phn bit theo kch thc t vi k t n hng chc k t, t 1
hng n vi chc hng. V d LCD 162 c ngha l c 2 hng, mi hng c 16 k t.
LCD 204 c ngha l c 4 hng, mi hng c 20 k t.
LCD c nhiu loi v s chn ca chng cng khc nhau nhng c 2 loi ph bin l
loi 14 chn v loi 16 chn, s khc nhau l cc chn ngun cung cp, cn cc chn
iu khin th khng thay i, khi s dng loi LCD no th phi tra datasheet ca
chng bit r cc chn. S chn ca LCD nh bng sau:
Chn Tn Vo/Ra Chc nng

1 Vss Power Ngun
2 Vdd Power Mass
3 Vo Analog iu chnh tng phn

4 RS Input Chn thanh ghi
= 0: iu khin
= 1: d liu
109
5 RW Input = 0: Ghi
= 1: c
6 E Input Cho php
7 D0 I/O D liu (LSB)

8 D1 I/O D liu
9 D2 I/O D liu
10 D3 I/O D liu
11 D4 I/O D liu
12 D5 I/O D liu
13 D6 I/O D liu
14 D7 I/O D liu (MSB)
Cc lnh thng dng

1. Lnh xo mn hnh Clear Display: khi thc hin lnh ny th LCD s b xo
v b m a ch c xo v 0.
M lnh: 0 0 0 0 0 0 0 1
2. Lnh di chuyn con tr v u mn hnh Cursor Home: khi thc hin lnh
ny th b m a ch c xo v 0, phn hin th tr v v tr gc b dch
trc . Ni dung b nh RAM hin th DDRAM khng b thay i.
M lnh: 0 0 0 0 0 0 1 0
3. Lnh thit lp li vo Entry mode set: lnh ny dng thit lp li vo cho
cc k t hin th, bit ID = 1 th con tr t ng tng ln 1 mi khi c 1 byte d
liu ghi vo b hin th, khi ID = 0 th con tr s khng tng: d liu mi s ghi
ln d liu c. Bit S = 1 th cho php dch chuyn d liu mi khi nhn 1
byte hin th.
M lnh: 0 0 0 0 0 1 ID S
4. Lnh iu khin con tr hin th Display Control: lnh ny dng iu
khin con tr (chohin th th bit D = 1, tt hin th th bit D = 0), tt m con tr
(m con tr th bit C = 1, tt con tr th bit C = 0), v nhp nhy con tr (cho
nhp nhy th bit B = 1, tt th bit B = 0).
M lnh: 0 0 0 0 1 D C B
5. Lnh di chuyn con tr hin th
110
M lnh: 80H con tr v dng 1 ct 1

.
M lnh: C0H con tr v dng 2 ct 1
M lnh: C1H con tr v dng 2 ct 2
.
.
M lnh: D4H con tr v dng 4 ct 1
M lnh: D5H con tr v dng 4 ct 2
.
Ni dung th vin
#define RS_LCD PORTC.4 //chn chn thanh ghi lnh hay d liu
#define RW_LCD PORTC.5 //chn c hay ghi LCD
#define E_LCD PORTA.1 //xung cho php
#define led_LCD PORTA.2 //n nn LCD
#define DATAOUT PORTB //port d liu ca LCD

#define DATAINPUT PINB
#define IO_RS_LCD DDRC.4

#define IO_RW_LCD DDRC.5
#define IO_E_LCD DDRA.1
#define IO_led_LCD DDRA.2
#define IO_DATAOUT DDRB

//-----ghi lnh ra mn hnh LCD
//tham s command chnh l m lnh
void Write_command_LCD(unsigned char command)
{
//busy_lcd();
IO_DATAOUT=0XFF;
IO_CS_8255_1=1;
IO_CS_8255_2=1;
CS_8255_1=1;
111
CS_8255_2=1;
IO_RS_LCD=1;
IO_RW_LCD=1;
IO_E_LCD =1;
DATAOUT = command; //xut m lnh

RS_LCD =0; //chn thanh ghi lnh
RW_LCD =0; //ghi
E_LCD=1; //tao xung
delay_us(100);
E_LCD=0;
delay_ms(1);
}
//----ghi k t ra mn hnh LCD---
//----data l m k t dng ascii
void Write_data_LCD(unsigned char data)
{
// busy_lcd();
IO_DATAOUT=0XFF;
IO_CS_8255_1=1;
IO_CS_8255_2=1;
CS_8255_1=1;
CS_8255_2=1;
IO_RS_LCD=1;
IO_RW_LCD=1;
IO_E_LCD =1;
DATAOUT = data;
RS_LCD =1; //chon thanh ghi data
RW_LCD =0;
E_LCD=1;
delay_us(100);
E_LCD=0;
delay_ms(1);
}
//---khi to mn hnh LCD---

void In_LCD(void)
112
{
delay_ms(500);
Write_command_LCD(0x38);
delay_ms(10);
Write_command_LCD(0x0c);
delay_ms(100);
}
113
TI LIU THAM KHO
1. Nguyn nh Ph. Gio trnh vi iu khin

2. TS. Trng Hu Tr, TS. V Th Ry, C in t v cc thnh phn c bn.
114
DANH SCH BAN BIN SON GIO TRNH DY NGH

TRNH TRUNG CP, CAO NG
Tn gio trnh: TING ANH CHUYN NGH C IN T
Tn ngh: C IN T
1. ng (b) Ch nhim
2. ng (b) Ph ch nhim
3. ng (b) Th k
4. ng (b) Thnh vin
5. ng (b) Thnh vin
6. ng (b) Thnh vin
7. ng (b) Thnh vin
8. ng (b) Thnh vin
9. ng (b) Thnh vin
115
DANH SCH HI NG NGHIM THU

GIO TRNH DY NGH TRNH TRUNG CP, CAO NG
1. ng (b) Ch tch
2. ng (b) Ph ch tch
3. ng (b) Th k
4. ng (b) Thnh vin
5. ng (b) Thnh vin
6. ng (b) Thnh vin
7. ng (b) Thnh vin
8. ng (b) Thnh vin
9. ng (b) Thnh vin

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Dieu Khien He Thong Co Dien Tu Dung VDK PDF

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B LAO NG THNG BINH V X HI

TRNG C NGH K THUT CNG NGH

TPHCM, thng 08 nm 2014

Tp. H Ch Minh, ngy thng . nm 20

1. S tng qut h thng c in t

Nh vy, h thng c in t l mt lnh vc a ngnh ca khoa hc k thut

1.2. V tr, chc nng ca vi iu khin trong h thng c in t

ng vai tr l mt b phn u no iu khin ton b h thng cn li, vi iu

Nhiu chp c mch dao ng RC ngay trn chp.

Hnh 1. S chn ATMEGA32

- Chn 9 l u vo RESET: Khi tn hiu c a ln mc cao (trong t

Hnh 2. Kin trc ca h AVR

Cc vector ngt nm phn u ca Application section (t a ch 0x0000)

Phn 3: B nh SRAM bn trong (Internal SRAM). B nh ny c hu

Hnh 4. Cc thanh ghi R

Port c cc c im ring nhng khi xt chng l cc cng vo ra s th vic

cc chip AVR, cc b Timer/Counter cn c thm chc nng to ra cc xung

S thi gian ca ch CTC

+ Ch Phase correct PWM

Ch ny hot ng da trn hai sn ln xung. B m s m lin tc t

sn xung th n tt hn cho iu khin ng c. Ch phase correct PWM

Bt 3,6 WG00-WG01: y l cc bit chn ch trong Timer. Cc gi tr

Bt 5-4 : COM00-COM01: Quy nh gi tr u ra trong cc php so snh

Thanh ghi c ngt-TIFR:

Bt 1-OCFx : Khi hai gi tr bng nhau bt ny c set ln bng 1.

Bt 1 OCIEx: Khi bt ny c set ln bng 1 th cho php ngt so snh.

S khi b so snh tng t

mc thp th MSTR b xa v 0v SPIF v SPSR b t ln 1 khi bn

V gi tr ca chng ng theo t hp cc bit nh sau:

khin AVR). i vi VK AVR th cc chn SCK (Serial clock) l chn

1. Gii thiu phn mm CodeVisionAVR

To mt Project bng cch vo File / New:

Sau mn hnh s ra nh sau:

Chn Project sau n OK , sau mn hnh s hin ra nh sau:

Chn No (khng s dng Wizard ca chng trnh), mn hnh s hin ra nh

t tn Project sau ch ng dn n th mc cn lu ri n Save.

Chn Tab C Compile mn hnh s ra nh hnh di : Sau chn chp, chn

Chn tab After Build v check vo Program the Chip

Sau cc bn son chng trnh, v d chng trnh to xung chn s 40 ca

// chuong trinh chinh

Sau cc bn chn nut Add v chn file cn thm vo Project

1.3. Cch to mt Project trong CodevisionAVR t sinh code

Sau chng trnh t sinh code xut hin:

Lu file project dng prj:

Php ton ngha V d

* Php nhn x = a*b

/ Php chia ly phn nguyn x = a/b

Php ton ngha V d

d. Cc php ton so snh

Php ton ngha V d

>= So snh ln hn hoc bng

<= So snh nh hn hoc bng

!= So snh khc nhau

e. Php ton thao tc Bit

Php ton ngha V d

| Php hoc (OR) Bit_1 | Bit_2

^ Php hoc loi tr (XOR) Bit_1 ^ Bit_2

<< Dch tri a<<3

>> Dch phi a>>4

Php ton ngha V d

-= Ton t tr v gn a-=5 <=> a=a-5

f. Php tng gim

Php ton ngha V d