CSE 6421 Computer Architecture HW5

10 points each, for a total of 40 points

1. For a data cache with a 96% hit rate and a 1-cycle hit latency, calculate the average
memory access latency. Assume that the cache miss penalty is 124 cycles.

2. Calculate the performance of a processor taking into account stalls due to data cache
and instruction cache misses. The data cache (for loads and stores) is the same as
described in question 1 and 30% of instructions are loads and stores. The instruction
cache has a hit rate of 90%, hit latency of 1 cycle and a miss penalty of 60 cycles.
Assume the base CPI using a perfect memory system (all memory accesses hit in the
cache) is 1.0. Calculate the new CPI of the pipeline. Assume the pipeline stalls for both
load and stores when they miss the cache. Finally, assume that instruction cache
misses and data cache misses never occur at the same time. Show your work.

a. Calculate the additional CPI due to the iCache stalls.

b. Calculate the additional CPI due to the DCache stalls.
c. Calculate the overall CPI for the machine.

From your textbook, Fifth edition:

5.1, 5.2

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