Steppermotor

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity stepper is
port(clk:instd_logic;
reset:instd_logic;
dir:instd_logic;
s0:inoutstd_logic_vector(3 downto 0));
end stepper;
architecturestepper_arch of stepper is
signal s1:std_logic_vector(25 downto 0);
signal s2:std_logic;
begin
process(reset,clk)
begin
if(reset='1')then
s1<=(others=>'0');
elsif(clk'event and clk='1')then
s1<=s1+1;
end if;
end process;
s2<=s1(16);
process(reset,s2)
begin
if(reset='1')then
s0<="0001";
elsif(s2'event and s2='1')then
if(dir='1')then
s0(2 downto 0)<=s0(3 downto 1);
s0(3)<=s0(0);
elsif(dir='0')then
s0(3 downto 1)<=s0(2 downto 0);
s0(0)<=s0(3);
end if;
end if;
end process;
endstepper_arch;
DC Motor
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following lines to use the declarations that are

-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
entitydc_motor is
Port ( psw : in std_logic_vector(2 downto 0);
pdcm : out std_logic;
clk : in std_logic);
enddc_motor;

architecture behavioral of dc_motor is

signalsclkdiv : std_logic_vector(12 downto 0):= "0000000000000";
signal p100k :std_logic;

begin

-- count upto 3000

process(p100k)
begin
if(rising_edge(clk)) then
sclkdiv<= sclkdiv+1;
end if;
if(sclkdiv = "1011101110000") then
sclkdiv<= "0000000000000";
end if;
end process;

process(psw,sclkdiv)
variablevdcm : bit;
begin
if(sclkdiv = "0000000000000") then
vdcm := '1';
end if;

-- 1f4,320,44c,578,6a4,7d0,8fc,9c4, to vary the speeed of a dc motor

if(psw = "000" and sclkdiv = "000111110100") then vdcm := '0';
elsif(psw = "001" and sclkdiv = "0011001000000") then vdcm := '0';
elsif(psw = "010" and sclkdiv = "0100010011000") then vdcm := '0';
elsif(psw = "011" and sclkdiv = "0101011110000") then vdcm := '0';
elsif(psw = "100" and sclkdiv = "0110101001000") then vdcm := '0';
elsif(psw = "101" and sclkdiv = "0111110100000") then vdcm := '0';
elsif(psw = "110" and sclkdiv = "1000111111000") then vdcm := '0';
elsif(psw = "111" and sclkdiv = "1001110001000") then vdcm := '0';
end if;

if(vdcm = '1') then pdcm<= '1';

elsepdcm<= '0';
end if;
end process;
end behavioral;
Triangular wave
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entitytrianglewave is
Port ( clk : in std_logic;
reset : in std_logic;
dac_out : out std_logic_vector(0 to 7));
endtrianglewave;
architecture Behavioral of trianglewave is
signaltemp:std_logic_vector(3 downto 0);
signalcounter:std_logic_vector(0 to 7);
signalen:std_logic;
begin
process(clk)
begin
ifrising_edge(clk) then
temp<=temp+1;
end if;
end process;
process(temp(3))
begin
if(reset='1')then
counter<="00000000";
elsifrising_edge(temp(3))then
if (counter<240 and en='0')then
counter<=counter+1;
en<='0';
elsif(counter=0)then
en<='0';
else
en<='1';
counter<=counter-1;
end if;
end if;
end process;
dac_out<=counter;
end Behavioral;
Square wave
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entitysquare_wave is
Port ( reset : in std_logic;
clk : in std_logic;
sq :inoutstd_logic_vector(11 downto 0));
endsquare_wave;
architecture Behavioral of square_wave is
signalclk_div:std_logic_vector(50 downto 0);
signalclkdiv:std_logic;
begin
process(reset,clk)
begin
if reset='1' then
clk_div<=(others=>'0');
elsif(clk'event and clk='1')then
clk_div<=clk_div+1;
end if;
end process;
clkdiv<=clk_div(12);
process(reset,clkdiv)
begin
if(reset='1')then
sq<=(others=>'0');
elsif(clkdiv'event and clkdiv='1')then
sq<=not sq;
end if;
end process;
end Behavioral;
Rampwave (positive)

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entityposramp_wave is
port(reset:instd_logic;
clk:instd_logic;
d0:inoutstd_logic_vector(11 downto 0));
endposramp_wave;
architecture behavioral of posramp_wave is
signalclk_div:std_logic_vector(5 downto 0);
signalclkdiv:std_logic;
begin
process(reset,clk)
begin
if(reset='1') then
clk_div<=(others=>'0');
elsif(clk'event and clk='1')then
clk_div<=clk_div+1;
end if;
end process;
clkdiv<=clk_div(1);
process(reset,clkdiv)
begin
clkdiv<=clk_div(1);
if(reset='1')then
d0<=(others=>'0');
elsif(clkdiv'event and clkdiv='1')then
d0<=d0+1;
end if;
end process;
end behavioral;
Rampwave (Negetive)

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entitynegramp_wave is
port(reset:instd_logic;
clk:instd_logic;
d0:inoutstd_logic_vector(11 downto 0));
endnegramp_wave;
architecture behavioral of negramp_wave is
signalclk_div:std_logic_vector(5 downto 0);
signalclkdiv:std_logic;
begin
process(reset,clk)
begin
if(reset='1') then
clk_div<=(others=>'0');
elsif(clk'event and clk='1')then
clk_div<=clk_div+1;
end if;
end process;
clkdiv<=clk_div(1);
process(reset,clkdiv)
begin
clkdiv<=clk_div(1);
if(reset='1')then
d0<=(others=>'0');
elsif(clkdiv'event and clkdiv='1')then
d0<=d0-1;
end if;
end process;
end behavioral;
LCD DISPLAY
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY LCD_CODE IS
PORT
(
Header6 : OUT std_logic_vector(2 DOWNTO 0);
Header5 : OUT std_logic_vector(7 DOWNTO 0);
clk100k : IN std_logic
);
END LCD_CODE;--End of Entity

ARCHITECTURE Behavioral OF LCD_CODE IS

--Signal declaration

SIGNAL clkdiv : STD_LOGIC_VECTOR(20 DOWNTO 0);

SIGNAL clkstate : STD_LOGIC_VECTOR(6 DOWNTO 0);
SIGNAL lcd_disp : STD_LOGIC_VECTOR(5 DOWNTO 0);
SIGNAL clkkey : STD_LOGIC;
SIGNAL shiftreg : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL lcd_ctr_data : STD_LOGIC_VECTOR(10 DOWNTO 0);

ALIAS lcd_control : STD_LOGIC_VECTOR(2 DOWNTO 0) IS header6(2 DOWNTO 0);

ALIAS lcd_data : STD_LOGIC_VECTOR(7 DOWNTO 0) IS header5(7 DOWNTO 0);

BEGIN
clk_div: PROCESS (clk100k)
BEGIN
IF( RISING_EDGE(clk100k)) THEN
clkdiv<= clkdiv + 1;
END IF;
clkkey<= clkdiv(14);

END PROCESS clk_div;

clkdiv1: PROCESS (clkkey)

BEGIN
IF( RISING_EDGE(clkkey)) THEN
clkstate<= clkstate + 1;
END IF;
lcd_disp<= clkstate(5 DOWNTO 0);

END PROCESS clkdiv1;

lcddisp: PROCESS (lcd_disp)

BEGIN
CASE lcd_disp IS
WHEN "000000" =>lcd_ctr_data<= "10000110100";--434 Font 5*10
WHEN "000001" =>lcd_ctr_data<= "00000110100";--"00000111000";
WHEN "000010" =>lcd_ctr_data<= "10000001110";--40e Display on and cursor blink off
WHEN "000011" =>lcd_ctr_data<= "00000001110";
WHEN "000110" =>lcd_ctr_data<= "10000000001";--401 Clear display
WHEN "000111" =>lcd_ctr_data<= "00000000001";
WHEN "001010" =>lcd_ctr_data<= "10101011001";--559 y
WHEN "001011" =>lcd_ctr_data<= "00101000001";
WHEN "001100" =>lcd_ctr_data<= "10101000101";--545 E
WHEN "001101" =>lcd_ctr_data<= "00101000100";
WHEN "001110" =>lcd_ctr_data<= "10101001110";--54e N
WHEN "001111" =>lcd_ctr_data<= "00101010011";
WHEN "010000" =>lcd_ctr_data<= "10101000101";--545 E
WHEN "010001" =>lcd_ctr_data<= "00110000000";
WHEN "010010" =>lcd_ctr_data<= "10101010000";--550 p
WHEN "010011" =>lcd_ctr_data<= "00101000010";
WHEN "010100" =>lcd_ctr_data<= "10101001111";--54f O
WHEN "010101" =>lcd_ctr_data<= "00101000001";
WHEN "010110" =>lcd_ctr_data<= "10101011001";--559 y
WHEN "010111" =>lcd_ctr_data<= "00101001110";
WHEN "011000" =>lcd_ctr_data<= "10101000001";--541 A
WHEN "011001" =>lcd_ctr_data<= "00101000111";
WHEN OTHERS =>lcd_ctr_data<= "11111111111";--7ff
END CASE ;
lcd_data <= lcd_ctr_data(7 DOWNTO 0);
lcd_control<= lcd_ctr_data(10 DOWNTO 8);
END PROCESS lcddisp;
END Behavioral;--End of arch
Dcmotor (new)
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entitydcmotor is
Port ( clk : in STD_LOGIC;
reset, dir : in STD_LOGIC;
pwm : out STD_LOGIC_VECTOR (1 downto 0);
rly : out STD_LOGIC);
enddcmotor;
architecture Behavioral of dcmotor is
signalcounter:STD_LOGIC_VECTOR (7 downto 0):="11111110";
signaldiv_reg:STD_LOGIC_VECTOR (16 downto 0);
signaldclk,ddclk,datain,tick:STD_LOGIC;
signaldcycle:integer range 0 to 255 ; begin
process(clk,div_reg) begin
if(clk'event and clk='1')then div_reg<= div_reg+1;
end if;
end process;
process(ddclk,reset) begin
if reset='0'then counter<="00000000"; pwm<="01";
elsif(ddclk'event and ddclk='1')then counter<=counter+1;
if(counter >=dcycle)then pwm(1)<='0';
elsepwm(1)<='1';
end if;
end if;
end process;
rly<=dir;
end Behavioral;