Professional Documents
Culture Documents
New Posts
What's New?Unansw ered Posts FAQ Forum Actions Com m unity Quick Links Advanced Search
Forum Digital Design and Programming PLD, SPLD, GAL, CPLD, FPGA Design
problem in instanciating multi-dimensional array in VHDL
Results 1 to 9 of 9
+ Post New Thread
problem in instanciating multi-dimensional array in VHDL
10-03-09, 11:35 #1
poopie09
vhdl memory array
Newbie level 4
Hi all,
Join Date: Mar 2009 I'm trying to initialise my rom like this
Posts: 5
Code:
Helped: 0/0
Points: 688
subtype pixel is std_logic_vector(2 downto 0);
type word is array ( 0 to 9, 0 to 9) of pixel;
Level: 5 type memory is array (0 to 13) of word;
constant rom : memory :=(
0 => "000000000000000000000000000000000000000000000001
000000000000000000000000001000001000000000000000000001
000000000001000000000000000001000000000001000000000000
000001000000000001000000000000000001000000000001000000
000000000001000000000001000000000000000000001000001000
000000000000000000000001000000000000",
1 => "000000000000000000000000000000000000000000000001
000000000000000000000000001001000000000000000000000000
000001000000000000000000000000000001000000000000000000
000000000001000000000000000000000000000001000000000000
but 000000
when
000000i0000000000
0compile,
000000000
0100
this
0000
00000
error
10010
00
is
01
00000000000
generated 00000
000000000"Type
,
000
of 0100
rom 0000
is
incompatible with type of aggregate. at he line "constant
2 => "0000000000000000000000000000000000000000000010 rom
01 :
memory :=("
001000000000000000000001000000000001000000000000000001
000000000001000000000000000000000000000001000000000000
000000000000001000000000000000000000000001000000000000
000000000000001000000000000000000000000001000000000000
Thanks
000000000000000001001001001001000000"
10-03-09, 11:35
#2
www.edaboard.com/thread144480.html 1/5
9/17/13 problem in instanciating multi-dimensional array in VHDL
10-03-09, 12:12 #2
FvM
vhdl two dimensional array
Advanced Member level 5
If you define the array multi-dimensional, the respective constants
have to be multidimensional too!
Achievements:
Use paranthesis according to the actual type definition.
Awards:
10-03-09, 12:22 #3
poopie09
array vhdl
Newbie level 4
I don't understand how, can you give me a simple example please.
Thanks
Join Date: Mar 2009
Posts: 5
Helped: 0/0
Points: 688
Level: 5
10-03-09, 12:22
10-03-09, 12:43 #4
FvM
vhdl array
Advanced Member level 5
There are, B.T.W., VHDL text books, standards, tutorials and tools
manuals, that tell about VHDL syntax.
Achievements:
www.edaboard.com/thread144480.html 2/5
9/17/13 problem in instanciating multi-dimensional array in VHDL
scheme for a structurized initialization.
You also may want to consult IEEE 1076 Chapter 9.7 Generate
statements for syntax details, that are omitted in most VHDL
manuals.
10-03-09, 12:43
10-03-09, 15:02 #5
poopie09
vhdl multidimensional array synthesis
Newbie level 4
I've done all like you told me, everything is OK, thank you very
much.
Join Date: Mar 2009 Now, if i want to read something in memory i have to call it by
Posts: 5 rom(0)(0)(0) for the first pixel for example, is it correct?
Helped: 0/0
Points: 688
Level: 5
10-03-09, 19:23 #6
FvM
vhdl multidimensional array constants
Advanced Member level 5
Yes. Depending on the intended usage of the constant data in the
design, one may try to make the synthesis tool implementing it
Achievements:
in RAM blocks, mainly to reduce resource consumption. But it's not
easy due to the multidimensional index.
Awards:
11-03-09, 17:12 #7
poopie09
vhdl+array
Newbie level 4
Hello,
I tried to index my rom like this : rom(0)(0)(0), but the compile
Join Date: Mar 2009 generates me the following error : wrong type of index.
Posts: 5 I changed my code like this
www.edaboard.com/thread144480.html 3/5
9/17/13 problem in instanciating multi-dimensional array in VHDL
Helped: 0/0 Code:
Points: 688
type line is array ( 9 downto 0 ) of std_logic_vector(
Level: 5 2 downto 0);
type word is array (0 to 9) of line;
type memory is array (0 to 13) of word;
12-03-09, 01:19 #8
FvM
vhdl generate multidimensional
Advanced Member level 5
I wasn't aware of this VHDL syntax detail, it must be
Achievements: Code:
rom(0)(0,0)<= "001";
Awards:
13-03-10, 13:55 #9
vipinlal
problem in instanciating multi-dimensional array in VHDL
Full Member level 6
hope these two links help you..
http://vhdlguru.blogspot.com/2010/02...s-in-vhdl.html
http://vhdlguru.blogspot.com/2010/03...sing-vhdl.html
HELP ME in Write Lcd From Keyboard in FPGA With Vhdl | Verilog Test Bench Generator
Similar Threads
Multi-dimensional array in VHDL (13)
Multi Dimensional Array (0)
www.edaboard.com/thread144480.html 4/5
9/17/13 problem in instanciating multi-dimensional array in VHDL
Design_C0mp!ler + multi dimensional arrays (2)
Four Dimensional Array in Verilog (2)
How to display values of multi-dimensional array in VCS? (11)
-- Edaboard Classic Contact Us Forum for Electronics Privacy Statement Terms of Service
Top
Powered by vBulletin
Copyright 2010 vBulletin Solutions, Inc. All rights reserved.
SEO by vBSEO 2011, Crawlability, Inc.
www.edaboard.com/thread144480.html 5/5