BIRLA INSTITUTE OF TECHNOLOGY & SCIENCE, PILANI - K. K.

BIRLA GOA CAMPUS

VERILOG PRACTICE PROBLEMS

Q 1: Write a verilog code for 3-to-8-line decoder having active low outputs and one active high enable
input. Use gate level modeling/dataflow modeling/behavioral modeling. Write test bench for it applying all
input combinations at the interval of 100 time units.

Q 2: Write a verilog code for quadruple 2-to-1-line multiplexer having active high enable input using
gate level modeling. When disabled, all outputs should be at logic 0. When select line is logic 0, input A
(4-bit) should be at output lines. When select line is logic 1, input B (4-bit) should be available at output
lines. Write test bench with A=0101 and B=1010. Initially, disable the circuit and after 100 time units,
enable it. Then change select input at interval of 100 time units and show the outputs.

Q 3: Write a verilog code for 2-to-4 line decoder with active high outputs and one active high enable
input using gate level/dataflow/behavioral modeling. Using this decoder and tri-state gates, construct 4-to-
1 line multiplexer. Write test bench applying 1010 at inputs and then use select lines to direct one of the
inputs to output line. What is output when decoder is disabled?