reeno:[ TTT TT TEI TIE M.E. DEGREE EXAMINATION, NOVEMBER/DECEMBER 2016. Second Semester Applied Electronics VL 7201 — CAD FOR VLSI CIRCUITS (Common to M.E. VLSI Design) (Regulations 2013) ‘Time : Three hours Maximum : 100 garks Se aes err s uw 12. Answer ALL questions. PART A— (10x 2 = 20 marks) f Draw the three design domain Gajskis y-chart. e Define tractable and intractable problems. What are the types of minimum distance rules? Differentiate constructive placement and iterative placement? List out any four local routing problems? ‘How routing is performed in standard-cell layout? What are the different delay models? What are the goals of high level synthesis? «= We Cennqueshonpaper.com What are the aspects of assignment problem? What is the role of clique partitioning in high-level synthesis? PART B— (6x 13 = 65 marks) (©) Esplin the prim’ algorithm for apansing tree with secemarypeeudo . Or (© Explain the concepts of linear programming with suitable expressions. (@) Explain the bellman ford algorithm for constraint graph Compaction. Or (®) Explain in detail the steps involved in kernighan-lin algorithm.13. 4 15, 16. b) @) @) (@) Oy (a) ) Describe the shape functions, floor plan Or i in floor planning. Explain the left edge algorithm for area routing with a pseudo code. Explain the event driven simulation and its applications. Or Explain the principle and implementation of ROBDD in detail. What is data flow graph? Explain the types of DFG used in high level synthesis. Or Explain the force directed scheduling algorithm and explain the role of it in high level synthesis. PART C— (1x 15 = 15 marks) Determine a minimum weight steiner tree as shown in figure 16 (a) corresponding to the net {a, b, ¢, 4, o} Assume that all horizontal edges have weights equal to 2 and all Vertical edges have weights equal to 1 Fig 16 (a) Steiner tree corresponding to the net M{a, b,c, d, ¢). Or Consider a gate array of size 3 rows and 3 columns, A circuit with 9 colls and 3 signal nets is to be placed on the gate-array using Force- Directed Relaxation. The initial placement is shown in figure 16 (b) below. The modules are numbered cl.....c9 & the nets Ni, N2, N3. Show the final placement and calculate the improvement in total wire length achieved by the algorithm. 2 18165