Introduction to

CMOS VLSI
Design

Slides adapted from:

N. Weste, D. Harris, CMOS VLSI Design,

© Addison-Wesley, 3/e, 2004

Outline

z A Brief History
z MOS transistors
z CMOS Logic
z CMOS Fabrication and Layout
z Design Flow
z System Design
z Logic Design
z Physical Design
z Design Verification
z Fabrication, Packaging and Testing

1
CMOS Fabrication
z CMOS transistors are fabricated on a thin silicon
wafer that serve as both a mechanical support
and electrical common point called substrate
z Lithography process similar to printing press
z On each step, different materials are deposited or
etched
z Easiest to understand by viewing both top and
cross-section of wafer in a simplified
manufacturing process
3

Inverter Cross-section
z Typically use p-type substrate for nMOS
transistors
z Requires n-well for body of pMOS transistors

2
 Well and Substrate Taps
z Substrate must be tied to GND and n-well to VDD
z Metal to lightly-doped semiconductor forms poor
connection called Shottky Diode
z Use heavily doped well and substrate contacts /
taps

Inverter Mask Set

z Transistors and wires are defined by masks
z Cross-section taken along dashed line

GND VDD

nMOS transistor pMOS transistor

substrate tap well tap
6

3
 Detailed Mask Views
n well

z Six masks
z n-well
z Polysilicon
Polysilicon

z n+ diffusion
n+ Diffusion

z p+ diffusion
z Contact
p+ Diffusion

z Metal
Contact

Metal
7

Fabrication Steps
z Start with blank wafer
z Build inverter from the bottom up
z First step will be to form the n-well
z Cover wafer with protective layer of SiO2 (oxide)
z Remove layer where n-well should be built
z Implant or diffuse n dopants into exposed wafer
z Strip off SiO2

p substrate

4
Photoresist

z Spin on photoresist
z Photoresist is a light-sensitive organic polymer
z Softens where exposed to light

Photoresist
SiO2

p substrate

Lithography

z Expose photoresist through n-well mask

z Strip off exposed photoresist

Photoresist
SiO2

p substrate

10

5
Etch

z Etch oxide with hydrofluoric acid (HF)

z Seeps through skin and eats bone; nasty stuff!!!
z Only attacks oxide where resist has been exposed

Photoresist
SiO2

p substrate

11

n-well
z n-well is formed with diffusion or ion implantation
z Diffusion
z Place wafer in furnace with arsenic gas
z Heat until As atoms diffuse into exposed Si
z Ion Implanatation
z Blast wafer with beam of As ions
z Ions blocked by SiO2, only enter exposed Si

SiO2

n well

12

6
Strip Oxide

z Strip off the remaining oxide using HF

z Back to bare wafer with n-well
z Subsequent steps involve similar series of
steps

n well
p substrate

13

Polysilicon
z Deposit very thin layer of gate oxide
z < 20 Å (6-7 atomic layers)
z Chemical Vapor Deposition (CVD) of silicon layer
z Place wafer in furnace with Silane gas (SiH4)
z Forms many small crystals called polysilicon
z Heavily doped to be good conductor

Polysilicon
Thin gate oxide

n well
p substrate

14

7
Polysilicon Patterning
z Use same lithography process to pattern polysilicon

Polysilicon

Polysilicon
Thin gate oxide

n well
p substrate

15

Self-Aligned Process

z Use oxide and masking to expose where n+

dopants should be diffused or implanted
z N-diffusion forms nMOS source, drain, and n-
well contact

n well
p substrate

16

8
N-diffusion
z Pattern oxide and form n+ regions
z Self-aligned process where gate blocks diffusion
z Polysilicon is better than metal for self-aligned gates
because it doesn’t melt during later processing

n+ Diffusion

n well
p substrate
17

N-diffusion cont.

z Historically dopants were diffused

z Usually ion implantation today
z But regions are still called diffusion

n+ n+ n+

n well
p substrate

18

9
 N-diffusion cont.

z Strip off oxide to complete patterning step

n+ n+ n+

n well
p substrate

19

P-Diffusion

z Similar set of steps form p+ diffusion regions

for pMOS source and drain and substrate
contact

p+ Diffusion

p+ n+ n+ p+ p+ n+

n well
p substrate
20

10
 Contacts
z Now we need to wire together the devices
z Cover chip with thick field oxide
z Etch oxide where contact cuts are needed

Contact

Thick field oxide

p+ n+ n+ p+ p+ n+
n well
p substrate

21

Metalization
z Sputter on aluminum over whole wafer, filling the contacts
as well
z Pattern to remove excess metal, leaving wires

M etal

Metal
Thick field oxide
p+ n+ n+ p+ p+ n+

n well
p substrate 22

11
Layout
z Chips are specified with set of masks
z Minimum dimensions of masks determine
transistor size (and hence speed, cost, and
power)
z Feature size f = distance between source and
drain
z Set by minimum width of polysilicon
z Feature size improves 30% every 3 years or so
z Normalize for feature size when describing
design rules
z Express rules in terms of λ = f/2
z E.g. λ = 0.3 µm in 0.6 µm process 23

Layout Design Rules

24

12
Design Rules Summary

z Metal and diffusion have minimum width and spacing of 4λ

z Contacts are 2λ x 2λ and must be surrounded by 1λ on the layers
above and below
z Polysilicon uses a width of 2λ
z Polysilicon overlaps diffusions by 2λ where a transistor is desired
and has spacing or 1λ away where no transistor is desired
z Polysilicon and contacts have a spacing of 3λ from other
polysilicon or contacts
z N-well surrounds pMOS transistors by 6λ and avoid nMOS
transistors by 6λ

25

Gate Layout
ƒ Layout can be very time consuming
ƒ Design gates to fit together nicely
ƒ Build a library of standard cells
ƒ Standard cell design methodology
ƒ VDD and GND should abut (standard height)
ƒ Adjacent gates should satisfy design rules
ƒ nMOS at bottom and pMOS at top
ƒ All gates include well and substrate contacts
26

13
Inverter Layout
ƒ Transistor dimensions specified as W / L ratio
- Minimum size is 4λ / 2λ, sometimes called 1 unit
- In f = 0.6 µm process, this is 1.2 µm wide,
0.6 µm long

27

Example: Inverter Standard Cell Layout

28

14
Example: 3-input NAND Standard Cell Layout

ƒ Horizontal n-diffusion and

p-diffusion strips
ƒ Vertical polysilicon gates
ƒ Metal1 VDD rail at top
ƒ Metal1 GND rail at bottom
ƒ 32 λ by 40 λ

29

Stick Diagrams
z Stick diagrams help plan layout quickly
z Need not be to scale
z Draw with color pencils or dry-erase markers

30

15
Wiring Tracks
z A wiring track is the space required for a wire
z 4 λ width, 4 λ spacing from neighbor = 8 λ pitch
z Transistors also consume one wiring track

31

Well spacing
z Wells must surround transistors by 6 λ
z Implies 12 λ between opposite transistor flavors
z Leaves room for one wire track

32

16
Area Estimation
z Estimate area by counting wiring tracks
z Multiply by 8 to express in λ

33

Design Challenges

ƒ The greatest challenge in modern VLSI is not in

designing the individual transistors but in managing
system complexity
ƒ Modern System-on-Chip designs use:
ƒ Many millions (soon billions!) of transistors
ƒ Tens to hundreds of engineers
ƒ How to cope with Complexity ?
ƒ Abstraction Level
ƒ Structured Design
ƒ Design Flow
34

17
 Design Abstraction Levels

35

Structured Design Tenets

ƒ Hierarchy
ƒ Divide and Conquer
ƒ Regularity
ƒ Reuse modules wherever possible
ƒ Ex: standard cell library
ƒ Modularity
ƒ Well-formed interface allows modules to be treated as
black boxes
ƒ Locality
ƒ Physical and Temporal
36

18
 Design Flow
ƒ Architecture: User’s perspective, what does it do?
ƒ Instruction set, MIPS, x86, Alpha, PIC, ARM, …
ƒ Microarchitecture
ƒ Single cycle, multi cycle, pipelined, superscalar?
ƒ Logic: how are functional blocks constructed ?
ƒ Ripple carry, carry look ahead, carry select adders
ƒ Circuit: how are transistors used ?
ƒ Static CMOS, pass transistors, domino logic, …
ƒ Physical: chip layout
ƒ Datapaths, memories, random logic

37

Design Flow: Gajski’s Y-Diagram

The design process can be viewed

as making transformations from
one domain to another while
maintaining the equivalency of the
domains

38

19
 Architecture: MIPS example
ƒ Instruction Set
ƒ Instruction encoding formats

39

Architecture: MIPS example cont.

40

20
Microarchitecture: MIPS example

41

Logic Design: MIPS example

ƒ Start at the top level
ƒ Define the top-level interface
ƒ Top level block diagram
ƒ Hierarchically decompose top level into units
ƒ Design the units (e.g. HDL)

42

21
Logic Design: MIPS top level block diagram

43

Logic Design: MIPS Hierarchy

44

22
Logic Design using HDLs

ƒ Hardware Description Languages

ƒ Widely used in logic design
ƒ Verilog and VHDL
ƒ Describe hardware using code
ƒ Document logic functions
ƒ Simulate logic before building
ƒ Synthesize code into gates and layout
ƒ Requires a library of standard cells

45

Circuit Design
ƒ How should logic be implemented?
ƒ NANDs and NORs vs. ANDs and ORs?
ƒ Fan-in and fan-out?
ƒ How wide should transistors be?
ƒ These choices affect speed, area, power
ƒ Logic synthesis makes these choices for you
ƒ Good enough for many applications
ƒ But when a system has critical requirement
Hand-crafted circuits are still better 46

23
Example: Full Adder

Transistors? Gate Delays?

47

Example: Carry circuit

ƒ VERILOG:
assign cout = (a&b) | (a&c) | (b&c);

48

24
 Gate-level Netlist

module carry(input a, b, c,
output cout) g1
a x
wire x, y, z; b
g2 g4
a y
cout
and g1(x, a, b); c
g3
and g2(y, a, c); b z
and g3(z, b, c); c
or g4(cout, x, y, z);

endmodule

49

Transistor-Level Netlist
module carry(input a, b, c, output cout)

wire i1, i2, i3, i4, cn;

tranif1 n1(i1, 0, a);

tranif1 n2(i1, 0, b);
tranif1 n3(cn, i1, c); a p1 b p2 b p4
i4
tranif1 n4(i2, 0, b); c p3 i3 a p5 p6
cn
tranif1 n5(cn, i2, a); cout
tranif0 p1(i3, 1, a); c n3 i1 a n5 n6
i2
tranif0 p2(i3, 1, b); a n1 b n2 b n4
tranif0 p3(cn, i3, c);
tranif0 p4(i4, 1, b);
tranif0 p5(cn, i4, a);
tranif1 n6(cout, 0, cn);
tranif0 p6(cout, 1, cn);

endmodule
50

25
SPICE Netlist
.SUBCKT CARRY A B C COUT VDD GND
MN1 I1 A GND GND NMOS W=1U L=0.18U AD=0.3P AS=0.5P
MN2 I1 B GND GND NMOS W=1U L=0.18U AD=0.3P AS=0.5P
MN3 CN C I1 GND NMOS W=1U L=0.18U AD=0.5P AS=0.5P
MN4 I2 B GND GND NMOS W=1U L=0.18U AD=0.15P AS=0.5P
MN5 CN A I2 GND NMOS W=1U L=0.18U AD=0.5P AS=0.15P
MP1 I3 A VDD VDD PMOS W=2U L=0.18U AD=0.6P AS=1 P
MP2 I3 B VDD VDD PMOS W=2U L=0.18U AD=0.6P AS=1P
MP3 CN C I3 VDD PMOS W=2U L=0.18U AD=1P AS=1P
MP4 I4 B VDD VDD PMOS W=2U L=0.18U AD=0.3P AS=1P
MP5 CN A I4 VDD PMOS W=2U L=0.18U AD=1P AS=0.3P
MN6 COUT CN GND GND NMOS W=2U L=0.18U AD=1P AS=1P
MP6 COUT CN VDD VDD PMOS W=4U L=0.18U AD=2P AS=2P
CI1 I1 GND 2FF
CI3 I3 GND 3FF
CA A GND 4FF
CB B GND 4FF
CC C GND 2FF
CCN CN GND 4FF
CCOUT COUT GND 2FF
.ENDS
51

Physical Design

ƒ Floorplan
ƒ Standard cells
ƒ Place & route
ƒ Datapaths
ƒ Slice planning
ƒ Area estimation

52

26
 MIPS floorplan

Does the design fit the chip

area budgeted ?
Estimates area of major units
and defines their relative
placement
Estimate wire lengths
Estimates wiring congestion

53

MIPS layout

54

27
Taxonomy of On-Chip structures

z Random logic
z Data paths
z Arrays
z Analog
z Input/output (I/O)

55

Synthesized MIPS Controller

56

28
Hand-Crafted MIPS Datapath

57

Standard Cells

58

29
 Synthesized MIPS

59

Area Estimation
z Need area estimates to make floorplan
z Compare to another block you already designed
z Or estimate from transistor counts
z Budget room for large wiring tracks

Some cell library vendor specify cell layout densities in Kgates/mm2

60

30
 Design Verification
ƒ Fabrication is slow & expensive
ƒ MOSIS 0.6µm masks: $1000, 3 months
ƒ State of art masks (130nm): $1M, 1 month
ƒ Debugging chips is very hard
ƒ Limited visibility into operation
ƒ Prove design is right before building!
ƒ System simulation (C/C++)
ƒ Logic simulation (HDL testbench)
ƒ Circuit simulation / formal verification
ƒ Layout vs. schematic comparison
ƒ Design & electrical rule checks
ƒ Verification is > 50% of effort on most chips !
61

Fabrication
ƒ Tapeout final layout
ƒ Formats for mask descriptions:
CIF (academia) and GDS II (industry)
ƒ Fabrication
ƒ 6, 8, 12” wafers (bare wafer costs $1000-$5000)
ƒ Optimized for throughput, not latency (turnaround times up to 10
weeks !)
ƒ Cut into individual dice
ƒ Fabs cost billions of dollars and become obsolete in a few years
ƒ Fabless semiconductor companies
ƒ Manufacturing Companies: TSMS, UMC, IBM
62

31
Packaging

ƒ Bond gold wires from die I/O pads to package

63

Testing

ƒ Test that chip operates

ƒ Design errors
ƒ Manufacturing errors
ƒ A single dust particle or wafer defect kills a die
ƒ Yields from 90% to < 10%
ƒ Depends on die size, maturity of process
ƒ Test each part before shipping to customer

64

32
 Summary

z Many chip designers spend much of their time

specifying circuits with HDL and seldom look at
the actual transistor
z However:
z Chip Design is not software engineering
z It requires a fundamental understanding of
circuit and physical design
z The best way to learn VLSI design is by doing it
65

Summary cont.

Now you know everything to start designing a

simple chip !

66

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