library ieee;

use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity adder_tb is
end adder_tb;
architecture adder_tb_arch of adder_tb is
component adder is
port(
a,b:in std_logic;
s,c:out std_logic
);
end component;
signal a,b,s,c:std_logic;
begin
uut:adder port map(a,b,s,c);
process
begin
a<='0';
b<='0';
wait for 10 ns;
a<='0';
b<='1';
wait for 10 ns;
a<='1';
b<='0';
wait for 10 ns;
a<='1';
b<='1';
wait for 10 ns;
end process;
end;