module vedic_2_x_2(a,b,c );

// two inputs a & b both of 2 bits

input [1:0]a;
input [1:0]b;

//output of 4 bits
output [3:0]c;
wire [3:0]c;

//wire to propagate the carry

wire [3:0]temp;

//stage 1
// four multiplication operation of bits according to Vedic logic done using and gates
assign c[0]=a[0]&b[0];
assign temp[0]=a[1]&b[0];
assign temp[1]=a[0]&b[1];
assign temp[2]=a[1]&b[1];

//stage two
// using two half adders
ha z1(temp[0],temp[1],c[1],temp[3]);
ha z2(temp[2],temp[3],c[2],c[3]);
endmodule
// code for half adder
module ha(a, b, sum, carry);
input a;
input b;
output sum;
output carry;
assign carry=a&b;
assign sum=a^b;
endmodule