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    Us 20160087633 a 1

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    Patent

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    © All Rights Reserved
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    8 views12 pages

    Us 20160087633 A 1

    Uploaded by

    Nidhi Sharma
    Patent

    Copyright:

    © All Rights Reserved
    Download as PDF or read online from Scribd
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    of 12
    us United States «2 Patent Application Publication co) Pub. No.: US 2016/0087633 Al oy oy ~ (6) ZHANG et al. DIFFERENTIAL DRIVER WITH PULL UP. AND PULL DOWN BOOSTERS TEXAS INSTRUMENTS, INCORPORATED, Dallas, TX (US) Applicant Inventors: Weicheng ZILANG, Cheng (CN): Huanchang HUANG, Plano, TX (US) Yani FAN, Allea, TX (US); Roland SPERLICH, Rockwall, [X (US) Appl. No 14/847,264 Filed: Sep. 8, 208 Related US. Application Data Provisional application No. 621084,196, fled on Sep. 23,2014, ‘US 20160087633 T6331 (43) Pub. Date: Mar. 24, 2016 Publication Classification GI) Ince. 03K 190934 (200601) (2) US.Cl ce MORK 19/0948 (201301) on ABSTRACT A diver includes first and second resistors coupled 10 8 sup- ply vollage and coupled to pairs of min transistors at positive ‘and negative ouiput nodes, The first and second pais of maia ‘eansisors provide emphasis and deemphasis oa the positive fd negative output nodes The driver also includes adel inverter, pal up booster and a pull down booster. The delay inverter delays and inverts each ofa par of differential iaput signals w provide delayed and inverted differential signals The pull up booster provides bypass current path tht bypasses the fist and second resistors but includes at least somo the fits and second pats of main transistors. The pull down hooster provides an additonal extent path fom the supply voltage through the frst oe second resistor to ground. cone 100 tof mamas i 3 1 t wo peeow 71d". ! IaLpReaRY dimes | am Sere t ' oe: ! aha ‘ we pe: : fae Pou bode da | oupo4 we eaeoav >| vac Hy INP_PREDRV t+—————;—— INN DE | | | —+ iN PREDRY |» WPDE | 1 1 1 u G HW Go W 1 1 r! J I ! “346, 348 rl “356, 358 1 L vo t vo Lt 1 UPON A TRANSITION OF A POSITIVE 402~| _ DIFFERENTIAL INPUT SIGNAL, ENABLING A BYPASS CURRENT PATH TO BYPASS CURRENT AROUND A FIRST OUTPUT RESISTOR t SOURCING CURRENT FROM AN ACTIVE CURRENT SOURCE THROUGH ‘A SECOND OUTPUT RESISTOR t UPON A TRANSITION OF A MINUS DIFFERENTIAL INPUT SIGNAL, ENABLING 406~“] AN ADDITIONAL CURRENT PATH TO GROUND THROUGH THE SECOND OUTPUT RESISTOR FIG. 7 404~ US 2016/0087633 Al DIFFERENTIAL DRIVER WITH PULL UP ‘AND PULL DOWN BOOSTERS (CROSS-REFERENCE TO RELATED "APPLICATIONS, {0001} ‘The present application claims priority to US. Pro- Visional Patent Application No. 62/0S4,196, filed Sep. 23 2014, tiled “An Output Swing Boosting Circuit Of Low Voltage Differential Drivers." which is hereby incorporated herein by eference in is entirety. BACKGROUND 10002] Driver circuits are used to transmit electrical sig- nals For high frequency transmissions, divers may inelude pre-emphasis and de-emphasis to compensate for high-fre- ‘quency’ channel Josses. Pre-emphasisde-emphasis means that the output signal amplitude ofthe transmission bit is ‘exaggerated tobe larger than that ofthe non-ransmission bit ‘Thats, the absolute Value of the voltage amplitude i higher during the input signal transitions than in the steady state region between inpit signal transitions. Voltage mode divers areavailableasare current made drivers. Both types of drivers have theiradvantages and disavantages and each is best used {or certain applications, BRIBE DESCRIPTION OF THE DRAWINGS. 10003] For a detailed description of various examples, re ‘erence will now be made tothe accompanying drawings in which {0004} FIG. 1 shows differential driver including a pull up booster and a pull dain booster for superior emphasis and de-cmphasis in accordance with various examples 0005} FIG. 2 shows a timing diagram in accordance with various examples; 10006] FIG, 3 shows another timing diagram showing ‘enhanced pre-emphasis and de-emphasis cae to the poll up ‘and pull down boosters; 10007] FIG. 4 shows the differential driver of FIG. 1 with ‘ditional detail for the pull and pull dawn boosters in accor ‘dance with various examples: 10008} FIG. 5 shows a timing diagram in aecordance with ‘various examples: [0009] FIG. 6 shows an implementation of an analog verter for use inthe pall down booster; and [0010] FIG. 7 shows @ method flow chart in aevordance ‘with vrions examples SUMMARY, {0011} In one embodiment, a driver includes fist and see- ‘ond resistors coupled toa supply voltage and coupled t pairs ‘of main transistors at positive and negative outpt nodes. The frst and second pairs of main transistors provide emphasis and de-emphasis on the positive and negative output nodes. The driver also includes delay inverter a pull up boosterand «pull down booster. The delay inverter delays and inverts ‘each ofa pair of differential input signals to provide delayed tnd inverted differential signals. The pal up booster provides ‘a bypass current path that bypasses the ist and seeondl esis torsbt includes atleast some of the frst and second prs of main transistors. The pull dovn booster provides an add tional cuerent pat from the supply voltage throngh the frst oF second resistor ground. Mar. 24, 2016 0012] In another embodiment, a differential driver includes a first resistor coupled to a supply voltage and to a fit pair of main tansistors at a postive output node. A sovond resistor ist be coupled tothe supply vollageand to @ second ar of main transistors ata negative omtput nade, The Tint and second pairs of main transistors are configured to provide emphasis and de-emphasis onthe positive and nega- five output nodes. A pull up bostr couples tothe fist and second resistors and is configured to provide, only during transitions of differential input signals, a bypass current path that bypasses the fist and second resistors but includes at least some ofthe fist and second pairs of main transistors. [0013] In yet another embodiment, a differential driver comprises a frst resistor to be coupled to supply voltage and toa first pair of main transistors at a positive output node. A second sista ist be eoupled to the supply voltage and toa evond pair of main transistors at a negative output node The fist and second pairs of main tansisiors ate configured 10 provide emphasis and de-emphasis onthe positive and nega- tive output nodes, A delay inverter is configured to delay and invert each ofa pair of differential input signals to provide delayed and inverted differential signals. A pull down booster fs coupled to the postive and negative outpot nodes and is ‘configured to provide, only during the transitions of the dif {erential input signals, an additional curent path from the supply voltage through the frst or scond resistor w ground, ‘the seditonal current pais in addition toa curren pals roma the supply voltage through te first or seeond resistor and at least some ofthe fst and second pairs of main transistors. DETAILED DESCRIPTION [0014] Certain terms are used throughout the following

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