Aslk Pro Manual v103 PDF

Analog
System
Lab Kit PRO
MANUAL
Table of contents

Introduction 9 2.1.1 Inverting Regenerative Comparator 24

2.1.2 Astable Multivibrator 24
2.1.3 Monostable Multivibrator (Timer) 25
Analog System Lab 10
2.2 Exercise Set 2 26
Organization of the Analog System Lab Course 11

Lab Setup 12
System Lab Kit ASLK PRO - An overview 13
Hardware 13
Software 13
Experiment 3: 27
Getting to know ASLK PRO 14 Study the characteristics of integrators and differentiator circuits
Organization of the Manual 16

3.1 Brief theory and motivation 28
3.1.1 Integrators 28
Experiment 1: 17 3.1.2 Differentiators 28
Study the characteristics of negative feedback amplifiers and 3.2 Specifications 28
design of an instrumentation amplifier 3.3 Measurements to be taken 28
3.4 What should you submit 29
3.5 Exercise Set 3 - Grounded Capacitor Topologies
1.1.1 Unity Gain Amplifier 18
of Integrator and Differentiator 30
1.1.2 Non-inverting Amplifier 19

1.1.3 Inverting Amplifier 19
1.3 Measurements to be taken 20 Experiment 4: 31
1.4 What should you submit 21 Design of Analog Filters
1.5 Other related ICs 21

4.2 Specification 33
Experiment 2: 23 4.3 Measurements to be taken 33
Study the characteristics of regenerative feedback system with 4.4 What should you submit 33
extension to design an astable and monostable multivibrator 4.5 Exercise Set 4 34

Analog System Lab Kit PRO page 3

Table of contents
Experiment 5: 35 Experiment 8: 47

Design of a self-tuned filter Automatic Gain Control (AGC) Automatic Volume Control (AVC)
5.1.1 Multiplier as a Phase Detector 36
8.2 Specifications 48
5.2 Specification 37
8.3 Measurements to be taken 48
5.3.1 Transient response 37

5.4.1 Exercise Set 5 38
Experiment 9: 51
Experiment 6: 39
DC-DC Converter
Design a function generator and convert it to Voltage-Controlled 9.1 Brief theory and motivation 52
Oscillator/FM Generator 9.2 Specification 52
9.3.1 Time response 52
9.3.2 Transfer function 52

Experiment 7: 43 Experiment 10: 55

Design of a Phase Lock Loop (PLL) Design a Low Dropout (LDO) regulator
7.1 Brief theory and motivation 44 10.1 Brief theory and motivation 56
7.2 Specifications 44 10.2 Specifications 56
7.3 Measurements to be taken 45 10.3 Measurements to be taken 56
7.4 What should you submit 45 10.4 What should you submit 57
7.5 Exercise Set 7 45 10.5 Exercise Set 10 57

page 4 Analog System Lab Kit PRO

Table of contents
Experiment 11: 59 14.2 Specifications 72

To study the parameters of an LDO integrated circuit 14.3 Measurements to be taken 72
A ICs used in ASLK PRO 75
Experiment 12: 63
A.1 TL082: JFET-Input Operational Amplifier 76
To study the parameters of a DC-DC Converter using on-board
Evaluation module A.1.1 Features 76
A.1.2 Applications 76
12.1 Brief theory and motivation 64 A.1.3 Description 76
12.2 Specifications 65 A.1.4 Download Datasheet 76
12.3 Measurements to be taken 65 A.2 MPY634: Wide Bandwidth Analog Precision Multiplier 77
12.4 What should you submit 65 A.2.1 Features 77
A.2.2 Applications 77
Experiment 13: 67 A.2.3 Description 77

A.2.4 Download Datasheet 77
Design of a Digitally Controlled Gain Stage Amplifier
A.3 DAC 7821: 12 Bit, Parallel, Multiplying DAC 78
13.1 Brief theory and motivation 68 A.3.1 Features 78
13.2 Specifications 68 A.3.2 Applications 78
13.3 Measurements to be taken 68 A.3.3 Description 78
13.4 What should you submit 68 A.3.4 Download Datasheet 78
13.5 Exercise Set 13 69 A.4 TPS40200: Wide-Input, Non-Synchronous Buck
DC/DC Controller 79
Experiment 14: 71 A.4.1 Features 79
Design of a Digitally Programmable Square and Triangular wave A.4.2 Applications 79
generator/oscillator A.4.3 Description 79
14.1 Brief theory and motivation 72 A.4.4 Download Datasheet 79

Table of contents List of figures
A.5 TLV7250: Micropower Low-Dropout Voltage Regulator 80 Signal Chain in an Electronic System 10
A.5.1 Features 80 Analog System Lab Kit PRO 13
A.5.2 Applications 80 Picture of ASLK PRO 15
A.5.3 Description 80 1.1 An ideal Dual-Input, Single-Output OP-Amp and its I-O
A.5.4 Download Datasheet 80 characteristic 18
A.6 Transistors: 2N3906, 2N3904, BS250 81 1.2 A Unity Gain System 18
A.6.1 2N3906 Features, A.6.2 Download Datasheet 81 1.3 Magnitude and Phase response of a Unity Gain System 19
A.6.3 2N3904 Features, A.6.4 Download Datasheet 81 1.4 Time Response of an Amplifier for
A.6.5 BS250 Features, A.6.6 Download Datasheet 81 a step input of size Vp 19
A.7 Diode: 1N4448 Small Signal Diode 82 1.5 (a) Non-inverting amplifier of gain 2,
A.7.1 Features 82 (b) Inverting amplifier of gain 2 19
A.7.2 Download Datasheet 82 1.6 Negative Feedback Amplifiers 19
1.7 Frequency Response of Negative Feedback Amplifiers 20
B Introduction to Macromodels 83 1.8 Outputs VF1 , VF2 and VF3 of Negative Feedback
Amplifiers of Figure 2.6 for Square-wave Input VG1 20
B.1 Micromodels 84 1.9 Instrumentation Amplifiers with (a) three and (b) two
B.2 Macromodels 84 operational amplifiers 20
2.1 Inverting Schmitt-Trigger and
its Hysteresis Characteristic 24
C Activity - Convert your 2.2 Symbol for an Inverting Schmitt Trigger 24
PC/laptop into an Oscilloscope 87 2.3 Non-inverting Schmitt Trigger
and its Hysteresis Curve 24
C.1 Introduction 88
2.4 Astable Multivibrator and its characteristics 25
C.2 Limitations 88
2.5 Trigger waveform 25
2.6 Monostable Multivibrator and its outputs 25
D Analog System Lab Kit PRO 3.1 Integrator 28
Connection Diagrams 89 3.2 Differentiator 28
3.3 Frequency Response of integrator and differentiator 29
3.4 Outputs of integrator and differentiator for
Bibliography 99 square-wave and triangular-wave inputs 30

List of figures
3.5 Circuits for Exercise 3 30 12.2 Simulation waveforms - TP3 is the PWM waveform
4.1 A Second-order Universal Active Filter 32 and TP4 is the switching waveform 65
4.2 Magnitude and Phase Response of 13.1 Circuit for Digital Controlled Gain Stage Amplifier 68
LPF, BPF, BSF, and HPF filters 32 13.2 Equivalent Circuit for simulation 69
5.1 Analog Multiplier 36 13.3 Simulation output of digitally controlled Oscillator when
5.2 A Self-Tuned Filter based on a Voltage Controlled the input pattern for the DAC 69
Filter or Voltage Controlled Phase Generator 36 was selected to be 0x800
5.3 Output of the Self-Tuned Filter 14.1 Circuit for Digital Controlled Oscillator 72
based on simulation 37 14.2 Circuit for Simulation 73
6.1 Function Generator 40 14.3 Simulation Results 73
6.2 Function Generator Output 40 A.1 TL082 - JFET-Input Operational Amplifier 76
6.3 Voltage-Controlled Oscillator (VCO) 41 A.2 MPY634 - Analog Multiplier 77
7.1 Phase Locked Loop (PLL) and its characterisitics 44 A.3 DAC 7821 - Digital to Analog Converter 78
7.2 Sample output waveform for A.4 TPS40200 - DC/DC Controller 79
the Phase Locked Loop (PLL) Experiment 44 A.5 TPS7250 -Micropower Low-Dropout Voltage Regulator 80
7.3 Block Diagram of Frequency Optimizer 45 A.6 2N3906 PNP General Purpose Amplifier 81
8.1 Automatic Gain Control (AGC)/ A.7 2N3906 NPN General Purpose Amplifier 81
Automatic Volume Control (AVC) 48 A.8 BS250 P-Channel Enh. Mode Vertical DMOS FET 81
8.2 Input-Output Characteristics of AGC/AVC 48 A.9 1N4448 Small Signal Diode 82
8.3 AGC circuit and its output 49 C.1 Buffer circuit needed to interface an Analog Signal to
9.1 DC-DC Converter and PWM waveform 52 Oscilloscope 88
9.2 (a) SMPS Circuit (b) Ouptut Waveforms 53 D.1 OP-Amp 1A connected in Inverting Configuration 90
10.1 Low Dropout Regulator (LDO) 56 D.2 OP-Amp 1B connected in inverting configuration 90
10.2 A regulator circuit and its simulated outputs - line D.3 OP-Amp 2A can be used in both inverting
regulation and load regulation 56 and non-inverting configuration 91
11.1 Schematic diagram of on-board evaluation module 60 D.4 OP-Amp 2B can be used in both inverting
11.2(a) Line regulation 61 and non-inverting configuration 91
11.2(b) Load regulation 61 D.5 OP-Amp 3A can be used in unity gain configuration
12.1 Schematic of the on-board EVM 64 or any other custom configuration 92

= a- HsV0i $ 0 kbs12 + s 2+ s l
VV02i b1 + ~0 Q ~ + 2 l ~0 Qs ~
s V204 ~s 02 b1 + ~ 2 l $ H0
2
=
b1 + ~0sQ +=~ 21l s 2 0 $ H 2
0
Vi
b1 + V~04V022il $ H00b1 + + ~s2 l 0s
b 2l
b1 + s~ Vi 2 l $ Hs 02
V04 s =
0
+~
0 + b1 + l
= ~ 0Q
V04 b1 + 2l ~
V s s2 0
i
+
10 Q ~0 2
Vi =
b1 +1~~ 2l 1
~0sQ ~0 ~ 1s 02-
List of figures
2Q 2
introduction
+
0Q 1~ -0
~0 1 - 0 H 0 Q 2Q 2
2Q 1
2
~0 H1 -
0 Q 2Q 2 1 0-Q 1 2
H
1 1Q
4
1H
-0 Q d1z- 4Q 2
4Q1
2
d~
dz1 - 4Q 2 dz
dd~ d~~ = ~0
z
D.6 OP-Amp 3B can be used in unity gain configuration 3.1 Plot of Magnitude and Phase w.r.t. ~
Input
d~= ~Frequency
0
~-=2Q ~0 29
~
or any other custom configuration 92 3.2 Plot of Magnitude and Phase w.r.t. -
Input
~ 2=Q~Frequency
0 - 2Q 0
29
~
~00
D.7 Connections for analog multiplier MPY634 - SET I 92 -~20Q
3.3 Variation of Peak to Peak value of output
~~
0 0
~H
0 0Q
D.8 Connections for analog multiplier MPY634 - SET II 93 w.r.t. Peak value of Input ~ H~
H00 Q 0Q 29
0 = 1 kHz
D.9 Connections for analog multiplier MPY634 - SET III 93 4.1 Transfer Functions of Active Filters~ = 1 kHz ~Q
H00 Q 0 ==11kHz32
D.10 Connections for A/D converter DAC7821 - DAC I 94 4.2 Frequency Response of a BPF with Q ~0= =11 kHz , Q~=0 =1 10 kHz
33
D.11 Connections for A/D converter DAC7821 - DAC II 95 4.3 Frequency Response of a BSF with ~ Q0 = ~ 10 kHz
= 110 kHz , Q = 10 33
0 =
5.1 Variation of output amplitude with Q~input
0= =10 10 kHz Q f==10
frequency 1 kHz37
D.12 Connections for TPS40200 Evaluation
Qf= = 10
1 kHz Voltagef =
f 1
= 10 kHzkHz
step-down DC/DC converter 96 6.1 Change in frequency as a function of Control 41
f = 1 kHz
10 kHz f =410 $ VpkHz
D.13 Connections for TP7250 low-dropout linear voltage reg.97 7.1 Output Phase as a function of Input Frequency r $ H $ Q 45
Vp kHz 4 $ Vp
0
f= 4 $ 10
D.14 MOSFET socket 97 7.2 Control Voltage as a function of Input
r4 Frequency
$ H$ 0V$p Q r V$pH0 $ Q 45
8.1 Transfer characteristic of the AGC circuit

Vrp $ H0 $ Q Vp~0 = 2 $ r48 $ 10 4 rad/s
D.15 Bipolar Junction Transistor socket 97
Vp0 = 2 $ r
~
9.1 Variation of output voltage with reference $ 10~4H
voltage =
0 =
0 rad $ r $ 10 4 rad/s
2/s10
D.16 Diode sockets 98
in a DC-DC converter
~
H00 = 10 _=t i10
2 $ r $ 10Hy40 rad /=s sin _100rt i + 0.1 sin
53
D.17 Trimmer-potentiometers 98
yH _0 t=i =10 sin _ y
100 _ trit i
=+sin 0.1_100 t i +r0.1
sin _r200 t i sin _
D.18 Main power supply 98 9.2 Variation of duty cycle with reference voltage
y _ t i = sin _100rt i + 0.1 sin _200rt i
D.19 General purpose area (2.54mm / 100mills pad spacing) 98 in a DC-DC converter 53
10.1 Variation of Load Regulation with Load Current
in an LDO 56
10.2 Variation of Line Regulation with Input Voltage
List of tables 11.1

in an LDO
Line regulation
57
61
11.2 Load regulation 61
12.1 Variation of the duty cycle of PWM waveform
1.1 Plot of Peak to Peak amplitude of output
with input voltage 66
Vpp w.r.t. Input Frequency 21
12.2 Line regulation 66
1.2 Plot of Magnitude and Phase variation
12.3 Load regulation 66
w.r.t. Input Frequency 21
13.1 Variation in output amplitude with bit pattern 68
1.3 Plot of DC output voltage and phase variation
14.1 Varying the bit pattern input to the DAC 72
w.r.t. DC input voltage 21
B.1 Operational Amplifiers available from Texas Instruments85
2.1 Plot of Hysteresis w.r.t. Regenerative Feedback 25

Introduction
What you need to know before you get started

Analog System Lab
introduction
Although digital signal processing is the most common form of processing signals,
analog signal processing cannot be completely avoided since the real world is
analog in nature. Consider a typical signal chain (Figure below). Typical signal chain
1 A sensor converts the real-world signal into an analog electrical signal.
This analog signal is often weak and noisy.
2 Amplifiers are needed to strengthen the signal. Analog filtering may be

necessary to remove noise from the signal. This “front end” processing
improves the signal-to-noise ratio. Three of the most important building
blocks used in this stage are (a) Operational Amplifiers, (b) Analog
multipliers and (c) Analog Comparators.
3 n analog-to-digital converter transforms the analog signal into a

A
stream of 0s and 1s.
4 he digital data is processed by a CPU, such as a DSP, a microprocessor,

T
or a microcontroller. The choice of the processor depends on how
intensive the computation is. A DSP may be necessary when real-
time signal processing is needed and the computations are complex.
Microprocessors and microcontrollers may suffice in other applications.
5 igital-to-analog conversion (DAC) is necessary to convert the stream of

D
0s and 1s back into analog form.
Figure: Signal Chain in an Electronic System
6 he output of the DAC has to be amplified before the analog signal can
T
drive an external actuator.
It is evident that analog circuits play a for an undergraduate or a postgraduate in the colleges focus on the circuit of choices of integrated circuits keeping
crucial role in the implementation of an curriculum. As part of the lab course, design aspect, ignoring the issues in mind the diverse requirements
electronic system. the student will build analog systems encountered in system design. In the of system designers. As a student,
using analog ICs and study their macro real world, a system designer uses you must be aware of these diverse
The goal of the Analog System Lab models, characteristics and limitations. the analog ICs as building blocks. The offerings of semiconductors and select
Course is to provide students an Our philosophy in designing this lab focus of the system designer are to the right IC for the right application. We
exposure to the fascinating world course has been to focus on system optimize system-level cost, power, and have tried to emphasize this aspect
of analog and mixed-signal signal design rather than circuit design. We performance. IC manufacturers such as in designing the experiments in this
processing. The course can be adapted feel that many Analog Design classes Texas Instruments offer a large number manual.

Organization of the Course
introduction
In designing the lab course, we have assumed that there are about 12 during a semester. We have designed 14 experiments which can be carried out either individually or
by groups of two students. The experiments in Analog System Lab can be categorized as follows.
Part I - Learning the basics Part II - Building analog systems
In the first part, the student will be exposed to the Part-II concentrates on building analog systems using the blocks mentioned above.
operation of the basic building blocks of analog
systems. Most of the experiments in the Analog First, we introduce integrators and differentiators which are essential for implementing filters that can band-
System Lab Course are centered around the following limit a signal prior to the sampling process to avoid aliasing errors.
two components.
We then introduce the analog comparator, which is a mixed-mode device - its input is analog and output is digital.
The OP-amp TL082, a general purpose JFET- In a comparator, the rise time, fall time, and delay time are important apart from input offset.
input operational amplifier, made by Texas A function generator is also a mixed-mode system that uses an integrator and a regenerative comparator as
Instruments. building blocks. The function generator is capable of producing a triangular waveform and square waveform as
outputs. It is also useful in Pulse Width Modulation in DC-to-DC converters, switched-mode power supplies, and
Wide-bandwidth, precision analog multiplier Class-D power amplifiers.
MPY634 from Texas Instruments.
The analog multiplier, which is a voltage or current controlled amplifier, finds applications in communication
Using these components, the student will build circuits in the form of mixer, modulator, demodulator and phase detector. We use the multiplier in building Voltage
gain stages, buffers, instrumentation amplifiers and Controlled Oscillators, Frequency Modulated waveform generators, or Frequency Shift Key waveform generators
voltage regulators. These experiments bring out in modems, Automatic Gain Controllers, Amplitude Stabilized Oscillators, Self-tuned Filters and Frequency Locked
several important issues, such as measurement of Loop using voltage controlled phase generators and VCOs and multiplier as phase detector are built and their lock
gain- bandwidth product, slew-rate, and saturation range and capture range.
limits of the operational amplifiers.
In the Analog System Lab, the frequency range of all applications has been restricted to 1-10 kHz, with the
following in mind - (a) The macromodels for the ideal device can be used in simulation, (b) A PC can be used
in place of an oscilloscope. We have also included an experiment that can help the student use a PC as an
oscilloscope. We also suggest an experiment on the development of macromodels for an OP-Amp.
What is our goal?
At the end of Analog System Lab, we believe you will have the following know- 2. You will learn how to develop a macromodel for an IC based on its terminal
how about analog system design. characteristics, I/O characteristics, DC-transfer characteristics, frequency
response, stability characteristic and sensitivity characteristic.
1. You will learn about the characteristics and specification of analog ICs used in 3. You will be able to make the right choice for an IC for a given application.
electronic systems. 4. You will be able to perform basic fault diagnosis of an electronic system.

Lab Setup
introduction
The setup for the Analog System Lab is very simple and requires the following. In all the experiments of Analog System Lab, please note the following.
1 ASLK PRO and the associated Lab Manual from Texas Instruments India - the 1 When we do not explicitly mention the magnitude and frequency of the input
lab kit comes with required connectors. Refer to Chapter 1.4 for an overview of waveform, please use 0 to 1V as the amplitude of the input and 1 kHz as the
the kit. frequency.
2 Oscilloscope. We provide an experiment that helps you build a circuit to directly 2 Always use sinusoidal input when you plot the frequency response and use
interface analog outputs to an oscilloscope (See Chapter C). square wave input when you plot the transient response.
3 Dual power supply with the operating voltages of ±10V. 3 Precaution! Please note that TL082 is a dual OP-Amp. This means that the IC
has two OP-Amp circuits. If your experiment requires only one of the two ICs, do
4 Function generators which can operate in the range on 1 to 10 MHz and capable not leave the inputs and output of the other OP- Amp open; instead, place the
of generating sine, square and triangular waves. second OP-Amp in unity-gain mode and ground the inputs.
5 A computer with installed circuit simulation software. 4 Advisory to Students and Instructors. We strongly advise that the student
performs the simulation experiments outside the lab hours. The student must
bring a copy of the simulation results to the class and show it to the instructor at
the beginning of the class. The lab hours must be utilized only for the hardware
experiment and comparing the actual outputs with simulation results.

System Lab Kit overview
introduction
Hardware
ASLK PRO has been developed at Texas Instruments India. This kit is designed for The kit has a provision to connect ±10V DC power supply. The kit comes with the
undergraduate engineering students to perform analog lab experiments. The main necessary short and long connectors.
idea behind ASLK PRO is to provide a cost efficient platform or test bed for students
to realize almost any analog system using general purpose ICs such as OP-Amps and This comprehensive user manual included with the kit gives complete insight of how
analog multipliers. to use ASLK PRO. The manual covers exercises of analog system design along with
brief theory and simulation results.
Refer to Appendix A for the details of the integrated circuits that are included in ASLK
PRO. Refer to Appendix D for additional details of ASLK PRO.
Software
The following software is necessary to carry out the experiments suggested in this
manual.
1. TINA or PSpice or any powerful simulator based on the SPICE Simulation Engine
2. FilterPro - A software program for designing analog filters
3. SwitcherPro - A software program for designing power supplies
Analog System Lab Kit PRO
We will assume that you are familiar with the concept of simulation and are able to
simulate a given circuit.
ASLK PRO comes with three general-purpose operational amplifiers (TL082) and three
wide-bandwidth precision analog multipliers (MPY634) from Texas Instruments. We FilterPro is a program for designing active filters. At the time of writing this manual,
have also included two 12-bit parallel-input multiplying digital-to-analog converters FilterPro Version 3.1 is the latest. It supports the design of different types of filters,
DAC7821, a wide-input non-synchronous buck-type DC/DC controller TPS40200, and namely Bessel, Butterworth, Chebychev, Gaussian, and linear-phase filters. The
a low dropout regulator TPS7250 from Texas Instruments. A portion of ASLK PRO is software can be used to design low-pass filters, high-pass filters, band-stop filters,
left for general-purpose prototyping which can be used for carrying out mini-projects. and band-pass filters with up to 10 poles. The software can be downloaded from [9].

Getting to know ASLK PRO
introduction
The Analog System Lab kit ASLK PRO is divided into many sections. Refer to the photo of ASLK PRO when you read the following description.
1 There are three TL082 OP-Amp ICs labelled 1, 2, 3 on ASLK PRO. Each of these LDO or DC/DC converter located on the board. Using Tri-state switches you
ICs has two amplifiers, which are labelled A and B. Thus 1A and 1B are the two can set 12-bits of input data for each DAC to desired value. Click the Latch
OP-AMps on OP-AMP IC 1, etc. The six OP-amps are categorized as below. Data button to trigger Digital-to-analog conversion.
4 e have included a wide-input non-synchronous DC/DC buck

W
converter TPS40200 from Texas Instruments on ASLK PRO. The
OP-Amp Type Purpose
converter provides an output of 3.3V over a wide input range
1A TYPE I Inverting Configuration only of 5.5-15V at output currents ranging from 0.125A to 2.5A.
Using Vout SEL jumper you can select output voltage to be either 5V or
1B TYPE I Inverting Configuration only
3.3V. Another jumper allows you to select whether input voltage is provided
2A TYPE II Full Configuration from the board (+10V), or externally using screw terminals.
2B TYPE II Full Configuration

5 e have included two transistor sockets on the board, which are needed in
W
3A TYPE III Basic Configuration designing an LDO regulator (Experiment 10), or custom experiments.
3B TYPE III Basic Configuration

6 specialized LDO regulator IC (TPS7250) has been included on the
A
board, which can provide a constant output voltage for input voltage ranging
from 5.5V to 11V. Ground connection is internally provided to the IC. Using
Thus, the OP-amps are marked TYPE I, TYPE II and TYPE III on the board. The ON/OFF jumper you can enable or disable LDO IC. Another jumper allows
OP-Amps marked TYPE I can be connected in the inverting configuration only. you to select whether input voltage is provided from the board (+10V), or
With the help of connectors, either resistors or capacitors can be used in the externally using screw terminals.
feedback loop of the amplifier. There are two such TYPE I amplifiers. There
are two TYPE II amplifiers which can be configured to act as inverting or non- 7 here are two 1kX trimmers (potentiometer) in the kit to enable the designer
T
inverting. Finally, we have two TYPE III amplifiers which can be used as voltage to obtain a variable voltage if needed for a circuit. The potentiometers are
buffers. labeled P1 and P2. These operate respectively in the range 0V to +10V, and
-10V to 0V.
2 Three analog multipliers are included in the kit. These are wide-bandwidth
precision analog multipliers from Texas Instruments (MPY634). Each 8 The kit has a screw terminals to connect ±10V power supply. All the
multiplier is a 14-pin IC and operates on internally provided ±10V supply. ICs on the board are internally connected to power supply. Please refer to
Appendix D for schematics of ASLK PRO.
3 here are two digital-to-analog converters (DAC) provided in the
T
kit, labeled DAC I and DAC II. Both the DACs are DAC7821 from Texas 9 have included two diode sockets on the board, which can be used as
We
Instruments. They are 12-bit, parallel-input multiplying DACs which can be rectifiers in custom laboratory experiments.
used in place of analog multipliers in circuits like AGC/AVC. Ground and power
supplies are provided internally to the DAC. DAC Logic Supply Jumper can 10 The top right portion of the kit is a general-purpose area which can be
be used to connect logic power supplies of both DAC I and DAC II to either used as a proto-board. ± 10V points and GND are provided for this area.

4 5
introduction
6
10
9
7
8
3
2
1 Photo of ASLK PRO 1 1

Organization of the Manual
introduction
There are 14 experiments in this manual and the next 14 chapters are devoted are asked to use the simulation software. For each of the experiments, we have
to them, We recommend that in the first cycle of experiments, the instructor clarified the goal of the experiment and provided the theoretical background.
introduces the ASLK PRO and ensure that all the students are familiar with a The Analog System Lab can be conducted parallel to a theory course on Analog
simulation software. A warm-up exercise can be included, where the students Design or as a separate lab that follows a theory course.
The student should have the following skills to pursue Analog System Lab:
1. Basic understanding of electronic circuits
2. Basic computer skills required to run the

simulation tools
3. Ability to use the oscilloscope
4. Concepts of gain, bandwidth, transfer function,

filters, regulators and wave shaping

Chapter 1
Experiment 1
Study the characteristics of negative feedback
amplifiers and design of an instrumentation amplifier

V0 =A0 $ (V1 - V2) (1.1)
Goal of the experiment
experiment 1
The goal of this experiment is two-fold. In the first part, we will understand V1 - V2 = V0 (1.2)
the application of negative feedback in designing amplifiers. In the second
A 0
In the above equations, A0 isV A0 $ (AV11 -

00 =open-loop
Vthe -gain; V
V22))for real amplifiers, A0 is in the
part, we will build an instrumentation amplifier.
range 10 to 10 and hence V1Vcs V2 . A1unity
0 = =A0 $ (V0A
V =AV $= (VA -$ (VV)- V ) + V00 feedback circuit is shown in the Figure
5 6
V V
V110- -"V V122 =
0 00 10 21 2
1.2. It is easy to see that, 0
V - VV - V V
= VA = A 0 0 =
as A A000 " 3
1.1 Brief theory andVV =motivation V0s
1 21 2
V A A0 0 0
0
0
0
V
V 0 =
A
A00 (1.3)
=
V1 + A1 + A V = 1 + A A0
_1 + s ~d1i_1 + s ~d2i
V V
s s 0 0
A
V s
s = 1 + 0 A 0
1.1.1 Unity Gain Amplifier V " V1 as" A1 as" A3 " 3 V

0 0
0 0
s s
V0 "
0
1 as A 0 " 3
A A V s " 1 as 1 A0 " 3 (1.4)
_1 + _s1 ~ + si_1~+i_s1 ~
+ si ~ i
0 0
A=A=
TV s =
1-1 ) 1 A A
d1 d1 d2 d2
An OP-Amp [8] can be used in negative feedback mode to build unity gain amplifiers, V0 =A0 $ (V V2+ A00
A = _1 +
~dd11ii__1 ~dd22ii1
T =1 an1ideal OP-Amp is assumed A =
V=0 _below,
T = While
non-inverting amplifiers and inverting amplifiers. In OP-amps, closed loop gain A is frequency
1 + sswhere ~ 1+ + ss ~
1 + 11 A +1 A
_1 of1
to have infinite open-loop gain and infinite bandwidth, real OP-Amps1have 1 finite dependent, as shown in the equation
numbers for these parameters. Therefore, it is_1important
= =
+ 1_1 A
V 1 - V2 =
~i ~ iare called the dominant 1 A 0 + s A0 ~d1 + s A0 ~d2 + s
2
A0 ~
+ 1+ Asto+
A understand
s A+~s +
~ A~ s some
A+~s +As~ A~ and A 0 poles+ the OP-
2 2
0
V 0 = A $
0
( V
0
V2)
1 -function
d1 0
T
T
d1
= 0 d2 0 d2
1 0 d1 0 d2 d1 d2
V
limitations of real OP-Amps, such as finite Gain-Bandwidth Product 1 (GB1). Similarly, amp. This 0transfer
V0 V0 =AA0 0=$ (11V1+
is =
typical
-11V2A
OP-Amp
) that V 1
O
`1 amplifier
+ `_1s +GB GBij$ ~ has
ij internal frequency A S
= =
_s+ +
`1Vmore _ sabout 11 s 2 GB $ ~d2ij
the slew rate and saturation limits of an operational are
s equally
GB A~
+ s A+~simportant.
+GBs $~ = compensation. Please
0 d2 0
2
d2
2
d2 d2 view
VV 1 + A0know + GB + s A1.2: 0 ~d2 +
AV0 0 V1 - V2==_11 + 11 A
0s
Given an OP-amp, how do we measure these parameters?
GB =GB A= ~A~ V1recorded
the - V2 =lecture [17] to get to= Figure
_ AA3
0 d1 0 d1
0
0+s A0 ~Gain s A0 ~d2 + s 22 A
GB GB frequency compensation.
" 1 asGB A0 = " + A Unity d1 +System
00 ~d1 A0 + s A0 ~d1 + s A0 ~d2 + s A00 ~
~
1 1 V0 A0 Vs 1
T= T=
Vs = 1 + A0 V0 GB=A0 1
` _ 0 ~d2 +s 2 GB $ ~d2ij
1 + s1 ~ + sQ ~ + sQ +~s ~ = 1= AA0
` (1.5)$ ~d2ij
2 22 2
_
0 0 0 0
V
_10 + s ~d1i_1 + s 1~d2i
+V SS
Q=Q= 1 1 A = s + 1
1 +
0
+ s
s GB
GB +
+ s
s A
A ~ + s
2
GB
V ~ ~ 1 GB 1 GB V 0
" 1 as A " 3
0 d 2
2
+ + d2 d2
V T 1=as
GB A
= A000 s~
0
V = A [V -V ] GB GB A A ~ ~ Vs V =A $ (V - V ) " A "dd~ 13
V 1
o o 1 2 d2
V
d2
1GB =1 + ~ 1 0 Q + s 2 ~02
0 0 1 2
-V
~ =~ GB = $~
0 GB $ ~ 0 d2
V-V =
d2
T V= s
A0+ 1GBA 0
A 1
_ i _ i
01
SS
Q Q
WeAcan= now write the transfer GB
Q function T for aAunity-gain
1 2
amplifier as,
0
_1 + s ~d1i+ _11 + s ~d2i

1V + s A ~ A 1 = + s= ~
1 1 = d 1 d 2
~ 1 1GB 0 0
_ A0 ~d1 ~d2i
p=p= V 1+A d 2
2Q 2 Q
1 = T = GB 1A s 0
~ ~ 0 0 T= V V " 1 as A " 3 1 + T 1 = A11

10 ++
+
s
ss ~ A
~ 0 ~
0 Qd1+
Q ++sss~ 2 A
0
~
2 d2 2
~ 2 d2 + s
00~
2
0
Figure 1.1: An ideal Dual-Input, Single-Output ~ ~ OP-Amp

~ ~ and its I-O characteristic 1 + 1 A T = ~ =1 AGB $ ~11d12
0 s 0 (1.6)
0 0 A 1 0+
_1 + s= ~ i_1 + Q s ~=i
0
A= Q
` 1GB $ ~d2ij
=
_
V V 1 d2
~ s +A011~d2 +GB
_ d2 + ~d2A0 ~d1 ~d2i
d1 d2
p p
= 1 + Q s GB +
~ GB2s
2
+1 + 1 A0 + _10 d11+ A
1 =
V $ GB
V 1
$ GB 1
Since the frequency and transient response of an amplifier are impacted by these
p p 1T = 1 A s A ~ s
GB
d2
A + ~
0 A s
0+s A A0 ~~ d2 s A0 ~d2 + s A0 ~d1 ~
2
parameters, we can measure the parameters ifQwe 2Q have
1 2 1the frequency and transient GB = A0p~d1+ 1 1 1 GB d1 +
= ~ + $$s ~
_1 + 1 A + s A~ =s2AQGB
= ~Add22~ ~ 1i
2 2 =
` =+ d2ij
=
_
response of the amplifier; you can obtain these response characteristics by applying ~ ~00 + GB (1.7) 2
A` ~ +
s A0 ~d2 +s GB $ ~d2ij
0 0 d1 0 d2 0 d1 d2
=
10 +s_ sGBGB
p11 p11
sinusoidal and square wave inputs respectively. We invite the reader to view the 1 GB
s GB +~ s 1 A ~ d2 + s 2
GB $ ~
Q 0 2
recorded lecture [16]. ~ ~ `1 + _ s GB + s Q $ ~ i+ j
_1 - 1_1 4-Q1 i4Q i
0 0 2
2
GB 2
A ~
=GB0= AdT1~=, also 1 0 d2 d2
The term GB known

~
=
p A~ as
0~ 11d1gain 2bandwidth
0the product of the operational
0 d1
dV dV
An OP-Amp can be considered as a Voltage Controlled
0
Voltage Source
0
(VCVS) with amplifier, is one of the 1 +
most s
p = 2Q=~
important 0Q + s
parameters ~ 2
0 in OP-Amp negative feedback
dt dt GB GB 21Qbe rewritten as
the voltage gain tending towards infinity. V For finite
V output voltage, the input circuit. The above transfer 1GBfunction
V
~ p can
p p
voltage is practically zero. This is the basic theory of OP-Amp in the negative T= Q =
1 + s ~1Q + s ~ ~ 0
T= ~d02 11 1GB 2 2
2 p $ GB
0 0
feedback configuration. Figure 1.1 shows a differential-input, single-ended-output 1 T V

~ ~+
1 = s ~0 Q += s ~ 2
Q+ GB 00 A ~d2 2
OP-Amp which uses dual supply !Vss for biasing. ~ 1 GB ~ ~0
+ A ~ 1 + s1 ~0 Q + s ~0
2 d2
GB 1
Q = ~ = GB ~0$ ~= GB Qpp 2
V
V $ ~d2 1 d2
~ 1 Q = GB 2 0 d2
page 18 Q
d2
Q + V
p p1 $ ~1d2 1 Analog
GB 1 GB System Lab Kit PRO
GB A V~ pd$2 GB 1 +
1 GB A ~d2
GB = A= 0 ~d1
Vs 1 + A0
GB V0
" 1 as A0 " 3
Vs 1 V =A $ (V - V )
T= 0 0 1 2
s ~0 Q + s V ~ A
experiment 1
where 1A+= 2 2
called slew rate. It can therefore be determined by applying a square wave of Vp at
_ i _ i
0 A V$ (V - V )
V =A V -VV) ==
=A0 $ (V - V 0
$ (V - V ) 0 0
V =
1
0 0
A A $ (V - V ) certain high frequency and increasing the magnitude of the input.
2
1
1
20
2
0 1 2
V =A $ (V - V )
0 0 1 V =A V$ (V A
2 - V )
= $ (V - V 1
0
1 + 0
) s ~ d 1 1
1 + s ~
V V -A
d 2 2
V
0 0 0 1 2
Q= V - V =V V=A $ (V - V ) V - V = AV =
0 0
V = 1
0
A V
2
1 2
0
0 1 20
0
V-V = V V - V V= VV ~AdV
0 0 1 2 0
1 20
V- AV = A
1 2
A
0
0 - A =
V T =AV -AV+
1
2 1 V 2 1 1
GB V A
V
02 V
1 +
A
0 0
0 R 0 0
0
s
2R 0
1
0
2 0
0
0
V
=0 A 0 V VVA
=
= 1 GB
+AA 1 0
+
= A
1 AA ~Vd2= 1 + AVV "V 1=asVV1A=+"1A+A3A
0
s 0
0
01
00
02
0 s
0
0
s
s
0
0 0
0
V s 1+A 0V V1V+ = A 1V A A s V " 1 as A "V 3" 1 as A A" 3

0 0
s 0
+A=" 3 0 0
R 0
R
V " 1 as A " 3 V~"0 = " 1 GB
asV $ 1~+ d2A
0 s
V A =V V1 " 1 as A " 3
_ i
0
_ i
V
0 0
0 0
_A"1 1+as1A "A3 V d2i

s 0
0 V A=
1Vas " " 0
3 s 0 1 V
+ s ~ 1 + s ~
0 s s 0 I
V 0
V 1V as A "A3 0
A= A V V s d1 d2 O O
A s= A0 ~d1A+ 1s A~s0 ~~ A ss ~ A0 ~d1 ~
0
_ di2_1+
2
i
s s 0
AV= 0+ _ i_ i
0 0
A Q _1 + s ~ i_A
V
1+s ~ i
s 0 0 I
1 + 1 A_1 + s ~ i_1 + s ~ i
0
1 + s
T ~
= 1A +1= s
+ +
_1 + s ~ i_1 + s ~ _i1A+=s _1~A i=
+ _s ~
1 + si_1~ isA~ i
0 s 0
A= A= d1 0 d2
d1 d2 d1 d2
1 1T=
d1 d2
1
_1 + s ~ i_1 + s 1~+i1 A= T1 =
d1 d2 d1 d2 0
1 + T
T =1 =
T 1` 2ij 1
1
Tp==T 1 1 =
=1A + _ s GB1+
+ 1 A1
d1 d2
_ s A ~ +s A ~ ~ i
T= 1 + 11 A
d1 d2
1 1 1
A 2+ 1s A A ~ 2
= s A0 ~d=2 +s GB $ 1~dFigure
1 +1 A 1 +21Q
= A 1 + + 1 + 0 0 d1 0 d2 0 d1 d2
_ A ~ ~ i amplifier of gain 2, (b) Inverting amplifier of gain 2

1+
_
1= _1 1 A1 + 1s A 1 +i sNon-inverting
1.5:
~~~(a)
1 A ~ ~ _1i +
ij + s A ~ ~ i
+ A ~ + s 1A ~ ++ s= + 1 1 A s 1A
= +~ 1 A
+ s+ As A
~ ~+ s+ sA A 2 2
_1 + 1 A + s A ~ +
~ _1s+GB 1~s iA ~ + s 1A ~ `~ 1 +i _ s 1GB + s A ~ 1+s GBs $ ~A ~
20 0 d02 d1 0 0 d1 d2 d2 0 d1 d2
= =0 + 0 d1 0
=1 _~
A A =
++ ssA A0A~
~ ~d+
A~ ~ i
1 0
2 A + s A ~
0
+ d1 0 d2
2
0 d1 d2
0 0 d2 0 2d1
d02 d2
2
0 d1 d2
_1 + 1 A0 + s A0 ~ d1 ~d22i
0 0 d1 0 d02 0 0 d1 d1 d2 0 d2 0 d21 d2
1 += 1 A + s A 1~ + s= A ~ + s =
2 `1 + _ s GB
A+0`~ _~ ~dd22ij+s 2 GB
1
$ ~d2ij
0 0 d1 0 d2 d1 d2 0
` j
d1 + s GB A0 ~ s d2+
1A0A
1 =
_ i
=d2+ s0 ~
` GB $ ~d2ij
s1=
_
d2GB
+s+ sGBA$0~
= ~ = ~
`1 + _ s GB + s A0 ~d`21++s _ s`GB
GB 1 + s
i
GB
j
+ s A 1
~ + s GB
2ij GB GB
$ ~ 1 s GB s A 0 ~d2 +s
1 d2ij
2
0=2 + +
~d_1 s`1GB
0 d 2 d 2
GB $ ~+ d2s A 0 ~d2 +s
2
GB 1$ ~
j
= A ~
_ d2i
GB = A10+ + s A0 ~d2 +s= GBGB 2 dA ~
0 $d~ = 0 d 1
s GB s A 0 ~d2 +s GB GB
$ ~ = A 0 ~d1
1.1.2 Non-inverting Amplifier
2
GB = A0 ~d1 GB A0 ~d1 A ~ + +
Vp =GBGB
T =GB = A0 ~d1 1 T =GB GB 1
= 0 d1 GB
2 11 + s ~0 Q +1s ~0
2 2
GB GB GB
1 Vp $ TGB= 1 GB1 + 1 s ~ 0 Q +
T = s 2
1 + s Q~=
~ 0 T =
0 Q +T 1s = +~s 012~0 Q +1s 2 ~A022non-inverting
T = T 1 + s1 ~0 Q2 1+ s2 2 ~02
2
T= ~d2 1 +1s ~GB amplifier with a gain of 2 is shown in Figure 1.5 (a).
s 1~0TQs+~s1 Q~0 s 2 1~12 + A 1 ~0 Q + s ~0
2
1 + s ~0 Q + s 2 ~02 1 + = 1
Figure 1.3: Magnitude Q= Qand
1 =~Phase
+ = 0 response of2 a
+ 0 Q =Unity Gain System
Q = GB 1d2
1 d2 1 + 1~s d2~ 0Q + s
1 ~0 GB
2
Q= 1 QQ=2Q GB ~d2 1 Q GB
~0+=A GB~$dGB
=~d2 + 1 GB
~d2 ~d2A 1~d2 GB
and
~d2 1 GB
GB + A ~d2
~2 GB
=d 2
GB + GB
1
Q~=
+
A d2 +~GB
GB
A 1 ~GB
~
d 2 d2
d+
1
~d12 A~
2
GB
0 =
GB
~GBd2Q$ ~~d2 0 = GB $ GB
2
~d2
+A ~
d2 1.1.3 Inverting Amplifier
~0 = GB $ ~d2 p 1 ~ 1
0 =
~0 = ~GB $ ~GB
GB $ ~ d2 A
GB + A ~ d 2
1
~ 0 = GB $ ~ d2
$ ~d2 $ ~d2 Q p =Q Q
Q ~ 0 =~0 = GB
d2
0 =
Q Q GB $ ~d2 2Q An inverting amplifier with a gain of 2 is shown in Figure 1.5 (b).
Q~10 1 ~ p= 1
Q is the2Qquality factor _and = 24QQis ithe

p1 =Q Q p= 0 1
1 2 Q p 2 Q
=
p= p = p 2Q1 2
1- 2~Q0 1
p=
1 damping ~factor, 0 and~ ~ ~00 is the
~
2Qnatural
~0
frequency ~0 When
of the system. ~ the frequency
dV0~ p 12Q response
~ = 0 ~ ~is plotted Vp ~with ~0 magnitude
0
0
~0 0
~ ~0
vs ~ ~0 and phase vs ~ ~0, ~
dt
it appears
Vp ~0 ~ ~0
2Q as shown in Figure
Vp 1.3.Vp $ GB
Vp 1 Unity gain Non-inverting amp Inverting amplifier
Vp Vp Vp R2 R4
Vp~0 Vp $ GB 1 Q 2Vp1$ GB 1
If one
Vp $ applies
GB 1 a step of peakV p V p $ GB 1
voltage V to the unity gain amplifier, and 2 Vp $ GB 1 slew
if
Vp $ GB V1
p
p $ GB 1 1 p 1Q12 1 R1 R3
rate, then the output appearsQas 2~ ~shown
1 in
Vp 0$ GB 1Figure 2.4 if Q 2
2 or . 2 1
Q21 Q 2 1Q 22 1 Q2 VF1 VF2 VF3
2 2112 p11 p~ 10 1 2 VG1
Q21
_1 - i
p
Q ispapproximately
11 equal
p to 1 pV
1 the total
1~ p number
10 2 of visible peaks~in the step Q1
1 4presponse
~
2 1
and U1 U2 U3
+
_ i
0
_ i
0
the frequency of ringing is p 1 . 1 ~20
_1 - 1p2 ~ 40Q i
~0 ~0 dV
_1 1 4Q 2i
1 - 1 4 Q 2 0
1 - 1 4 Q
_1 - 1 4Q 2i _1 - 1 _41V Q i$ GB ~1
2
dt
dV0 - 1 4Q 2i dV0 dV0 -
dtdV0 _rate 1 - 1 4Q i
0
V dt dV0
Slew-rate is known as the
dV0maximum
2 p
dV0 dt
dt
at which the output ofdttheVOP-AmpsQ 2dt dV 1
0is V V p
dt
p dt
p
Vp Vp 2 Vp Figure 1.6: Negative Feedback Amplifiers

capable of rising; in other words, Vp slew
Vp
rate is the maximum value that p11 dVo/dt
can attain. In this experiment, as we go
on increasing the amplitude of the step ~0
input, at some amplitude the_1rate - 1at 4Q 2i Figure 1.6 shows all the three negative feedback amplifier configurations. Figure
which the output starts rising remains 1.7 illustrates the frequency response (magnitude and phase) of the three different
constant and no longer increases dV0 with Figure 1.4: Time Response of an negative feedback amplifier topologies. Figure 1.8 shows the output of the three types
the peak voltage of input; thisdtrate is Amplifier for a step input of size Vp of amplifiers for a square-wave input, illustrating the limitations due to slew-rate.
Vp
1.2 Exercise Set 1 1.3 Measurements to be taken
experiment 1
1 Design the following amplifiers - (a) a unity gain amplifier, (b) a non-inverting 1 Transient response - Apply a square wave of fixed magnitude and study the
amplifier with a gain of 2 (Figure 1.5(a)) and an inverting amplifier with the effect of slew rate on unity gain, inverting and non-inverting amplifiers.
gain of 2.2 (Figure 1.5(b)).
2 Frequency Response - Obtain the gain bandwidth product of the unity gain
2 Design an instrumentation amplifier using three OP-Amps with a controllable amplifier, the inverting amplifier and the non-inverting amplifier from the
differential-mode gain of 3. Refer to Figure 1.9(a) for the circuit diagram. frequency response.
Assume that the resistors have 1% tolerance and determine the Common
Mode Rejection Ratio (CMRR) of the setup and estimate its bandwidth. We 3 DC Transfer Characteristics - Study the saturation limits for an OP-Amp.
invite the reader to view the recorded lecture [18].
3 Design an instrumentation amplifier using two OP-Amps with a controllable

differential-mode gain of 5. Refer to Figure 1.9 for the circuit diagrams of the
instrumentation amplifiers and determine the values of the resistors. Assume
that the resistors have 1% tolerance and determine the CMRR of the setup
and estimate its bandwidth.
Figure 1.8: Outputs VF1, VF2 and VF3 of Negative Feedback

Amplifiers of Figure 1.6 for Square-wave Input VG1
4 Determine the second pole of an OP-Amp and develop the macromodel for the
given OP-Amp IC TL082. See Appendix B for an introduction to the topic of
analog macromodels.
Figure 1.7: Frequency Response of Negative Feedback Amplifiers

1.4 What should you submit 1.5 Other related ICs
experiment 1
1 Submit the simulation results for Transient response, Frequency response and Specific ICs from Texas Instruments which can be used as instrumentation Amplifiers
DC transfer characteristics. are INA114, INA118 and INA128. Additional ICs from Texas Instruments which can
be used as general purpose OP-Amps are OPA703, OPA357, etc. See CHAPTER 2,
2 Take the plots of Transient response, Frequency response and DC transfer EXPERIMENT 1.
characteristics from the oscilloscope and compare it with your simulation
results.
S. No. Input Frequency Magnitude Variation Phase Variation
3 Apply square wave of amplitude 1V at the input. Change the input frequency
and study the peak to peak amplitude of the output. Take the readings in 1
Table 1.1 and compute the slew-rate.
2
nR
V1
R R R 3
R
R
R
R 4
nR VO
R V1 VO
V2 Table 1.2: Plot of Magnitude and Phase variation w.r.t. Input Frequency
R
V2 R
S. No. DC Input Voltage DC Output Voltage Phase Variation
1
Figure 1.9: Instrumentation Amplifiers with (a) three
and (b) two operational amplifiers
2
S. No. Input Frequency Peak to Peak Amplitude of output (Vpp)
3
1
4
2
Table 1.3: Plot of DC output voltage and phase variation w.r.t. DC input voltage
3
Table 1.1: Plot of Peak to Peak amplitude of output Vpp w.r.t. Input frequency
Further Reading
4 Frequency Response - Apply sine wave input to the system and study the
magnitude and phase response. Take your readings in Table 1.2. Datasheets of all these ICs are available at http://www.ti.com.
An excellent reference about operational amplifiers is the “Handbook of
5 DC transfer Characteristics - Vary the DC input voltage and study its effect on Operational Amplifier Applications” by Carter and Brown [5].
the output voltage. Take your readings in Table 1.3.

experiment 1
Notes on Experiment 1:

Chapter 2
Experiment 2
Study the characteristics of regenerative feedback
system with extension to design an astable and
monostable multivibrator

V0 =V0-=A-0 $ A _V0 i$ - _Vib- V0b i V0 i
1
A 0$ _ i - 0 i
V0 V0 A $
0 A $ V 1 bV
Vi =- V0 = -
Vi =- 10-1A-0 $ Ab0 $ b
V0 = -bA0=$ _VV0i - R1bR VA01i0 $ 1
R11R+2 R21 - A0 V$ 0b= - A0 $ _Vi - bV0 i
bVR = =-
i1+
V0 V0 = - A0 $ _Vi - bV0 i
Goal of the experiment 0 $ _Vi -A
=- A00 $ b = 1 R1 , it becomes
$ 0biA0=$ b1
experiment 2
However,
V0 = - Vi Awhen b1b0 V -
= V0
=- A0 $ 1
R1 + R2
0 0$ _ bi -1b1V0 i
unstable as amplifier
AR $ b 1 as
1 output V
satu- 1 -VA0 0 $ b A $ 1
V0 = - AA 0
$V
i
=- 0
V0 b = A0 R$ 1 + R12A0 $ b = 1
1
=- R V i 1 - A0 $ b
The goal of this experiment is to understand the basics of hysteresis and rates.Vi When V0 1A- 0 $A
Ab0A00$0$$ &b 1&
b 1the 11 region b =of 1
R1 + R2 b = R1
= -bA=0 $ _Viof 0 iss circuit
A 0 $ b=- = A
1 $ b 1
the need of hysteresis in the switching circuits. V0operation R-
V i1 this
b+VV + Vss - 0
1 A is $regenerative
b
A0 $ b = 1 R1 + R2
- A0 $ _Vi - bV0 i
comparator. RA10+ $ bRThis 21 1 A0 $ b & 1
1is the
V0 b =1 - V R V0 =mixed-mode A0 $ b = 1
=-AA0 $0 b $ A0=$ b1 & R1is-
ss
+ VR Vss 2 A0 $ b 1 1
Vicircuit. Output
1 - Ab 0$ b 1+stable ss
V0 onlyA in two 1 A0 $ b 1 1
A $ b $V b= 1
V =- $ A $b & 1
stages AR 0 $1 b V 1
+ ss and 01 ss
- $ V ss
. When
V the 1input
0
-0 A0 $ b
b= ss i
A0 $ b & 1
RA1 + R2 A0 $V 1
is large 0$ b negative
- V& 1 bss Vvalue ss 1
b $ Vss output
b = saturates
R1 + Vss
2.1 Brief theory and motivation Figure
0$ b = 1
Aat
ss
R R + Vss 2.2: Symbol for an Inverting
+ Vss bas A $2b$ b&$ Vb
$ Vss0input2V$ssin
1ss$ increased
Vss 1+
output
2 V
- ss
A $ b = 1 - Vss Schmitt Trigger
d$ ln d 1 +nbb$ nVss
0 $ b 1 at
Aremain 1
- Vss Vss + VssTuntil =T22=$$input $sslnreaches
1+b
0
bRC
2 $ $VRC b $ Vss
Aat this& 1 - Vssit changes Ato0 $ stable b1 - 1 1b-1 state
0$ b
b $ Vpoint Vb
2.1.1 Inverting Regenerative Comparator + ss . Now when
V
Vss
2 $ b $ Vss
ss
b $ Vxss the =xTRC = input

=RC $2ln$ d$RC
A is 0
ln
$
d b dn1 -
$ ln 2 $ bnit$ Vss
1
decreased
b &1
11+ssb
nb
V ss
1b-
$ ln d + ss .nThus
can change state only 1at + V 1 - b hysteresis of $ b $ Vss is seen around 0. This kind
2
- Vss T Vss2 t$ RC
- ss 1 - bTn= a2 MOSFET
In the earlier experiment we had discussed the use of only negative feedback. Let b of
2 $ b $ V=
comparator
ss +txx
is a +must =x 1RC $Vbln d driving
-while 1
$ RC $ ln d as a switch
1+b
n in ON-OFF controllers
$ Vss 1= -2b$ RC $ ln d 1 + b n
d $ lnnbd$ ln n Vdssb n n
$
Vss T = 2 $ RC $xln=dxt1RC
2 b $ Vss 1 + b 1 1 + b T
us now introduce the case of regenerative positive feedback as shown in Figure 2.1. SMPS (Switched
x = RC $ ln Mode Power 1 + Supply),
b pulse width modulators 1 -andb class-D audio
$ ln d 1type n Schmitt1 trigger is shown in
+1 RC x
= -- b 1$ +
d 1n+ b
b bfor xthis = RC
n+ xtrigger is as shown ind 1Figure n
The reader will benefit by listening to the recorded lecture at [20]. power amplifiers. The symbol inverting 1- b RC $ ln
2 $ b $ xVss tRC +Tx=!21$V!RC $ ln V
ln dbSchmitt
x=
Figure=2.2. The $ ln d non-inverting
1x1V =n RC1ss$ - - b 2.3.
V0 = - A0 $ _Vi - bV0 i
b t
b$dln d Rn1 n
1 - b1 R
+ b $
x $ ln d 1 - b b!nR
x= x RC 1b+ $=
RC ln 1 2 1 b $ V ss t+x
=
+ b$ ln d b n
(2.1) T = 2t $+RC = 11V+b1R-2 b 1+b
R1 + R2
Rb1 b= T R=1 2 $ RC $ ln d 1 - b n
x =1RC
x = RC $ ln d n
1+b
! 1VA0 $ _Vi - bV0 i
! 1tV+1xR11 +
V0 1 x = x
RC = $ lnRC d $ ln d
RbR n n R1 + RV20 = - b
1 d x = nRC $ ln d
A $ 1 - 2 1b
n
Vi =- 0 1 - A0 $ b b= R 1 + b 1 ! 1V
x= RR RC $Rln
1 + R2
2
t + x ! 1V R b b1= - b R1
t R+2 xV0 =- A0 $ b1
R1 !R1V R2 R + R R
1 2
= R 1R
R $ lnRRd21 + R2f = n fR1= =1 1,5
b= 1+ 1 b
R1 1+ 2
x = RC 1,5VkHz
kHz
1 A0 $ b
1
b+V= = SS
x = RC $ ln dR2
1 -
n
b R T1 T +V i 1 + b R
VI
SS
R1 + R2 ! 1V R1 R R1 xR=
b=
xf4=
1+ Rms 2 1
4 ms= 1,5 kHz b R1
VI = R2
R2R1 R1 1 RC T ! 1Vb = R
A 0 $ b =VO1 V
+ b=
RR1 + Rf 2=R2T = 1,5
RC x= kHz 4 ms R1 + R2 R
O
R1 f = 1 = 1,5 kHz
b =
A SS $ b
-V0 11 R1
f =
x=
1 R 1,5 kHz
=
4 ms RC -VSS RA
0$ b = 1
1 + R2
x =
T
4 ms
f = 1 = 1,5 kHz
T
R2 TRC R1
0 $ _kHz i - bV0 i
1 x = 4 ms
AR02 $ b & 1 R x = 4 ms fV =0 = T- =A1,5 VR
2 A 0$ b 1 1
RC
RC
R1 xV =0 4 msA $ 1
RC
+ Vss f = 1 =Figure 1,5 kHz Vi =- 0 1 R- A0 $A b $b & 1
T RC 2.3: Non-inverting 1 0 1,5 Schmitt Trigger and its Hysteresis Curve
b=
R 1 f = = kHz
x = 4 ms T
- Vss R1 + R2
+ V ss
RC A0 $ b = 1 x = 4 ms
Figure 2.1: Inverting Schmitt-Trigger and its Hysteresis Characteristic
b $ Vss 2.1.2 Astable Multivibrator
A0 $ b 1 1 RC - ss V
A $b & 1
Vss 0
A00 $$ __V V00 ii

+ V b $ Vss
An astable multivibrator is shown in Figure 2.4. The square and the triangular
V00 = -A -b
Vii - bV
ss
2V$ b= $ V-
ss waveforms shown
-V in the figure
ss
Vss are both generated using the astable multivibrator.
V
V00 =- A 11 (2.2) We refer to b $ as
V the regenerative feedback. The time period of the multivibrator is
0$
Vii 2 $ RC $ ln11 d- $ bn
ss
V =- A $ 1 +0 b given by V 2 $ b $ Vss
-1 A
0
T= A 0$ b
ss
- b
=n 2 $ RC $ ln d n
2$b$V
b
R
R11
ss
1+b
b=
ln dR2
1 - bn
1T (2.4)
T = 2 $ RC $ ln d
=R (2.3) +b
1 + R2 1 1-b
x = RCR1$ + 1-b
b = RC $ ln d n
A 0$ b = 1 x = RC $ ln d
1
n 1
A0 $ b = 1 1 -x
t+x 1 - bSystem
A b 1
A00 $$ b 1 11 t+x
page 24 Analog Lab Kit PRO
1+b x = RC $ ln d n
1 + tb + x
V0 = - A0 $ _Vi - bV0 i
2.1.3 MonostableV00Multivibrator = - AA00$$_Vi -1b(Timer)
V0 i
experiment 2
Vi =-
V 0
1 - 1A0 $ b
The circuit diagram for a monostable=- A $
multivibrator
R1 to1 the
0 is shown in 2.6. The trigger
waveform shown in Figure b V2.5i =is applied 0$ b
- Amonostable. The negative edge
triggers the monostable, which producesR1 +
R1 R
the 2
squareV = - A $ _V - bV iin Figure
waveform shown
0 A $ _ V - bV i
V = - 2.6.
0 i 0 0 0 i 0
bA= 0$ b = 1
R1 + R2 V =- A $V 0 1 V A $ 1 0
1 - A $ b V =-
0 0
i 1-A $b 0 i 0
+V SS A0 $ b = 11 b=
R b=
R 1 1
R +R R +R
1 2 1 2
V R
A0 $ b V &O
11 C
A $b = 1 0 A $b = 1 0
V = - A $ _ V - bV i V = - A $ _ V - b V i
0 0 i 0 0 0 i A $b 1 1
0 0 A $b 1 1 0
V 0 -V 1 V
SS
+AV0 ss$ b C&
0 1 1 A $ b & 1 A $b & 1
A $ =- A $
V =-
0 0
0 0
i 1-A $b V 0 1-A $b
i 0
b
R R
= RR1 1 R
2
b
+ VRss
- = R 1R
+V +V
ss ss
1+ 2 1+ 2 - Vss - Vss
A0 $ b = 1 A0-b$ bV$=Vss ss1 b $ Vss b $ Vss Figure 2.5: Trigger waveform
A0 $ b 1 1 A0 $ b 1 1 Vss Vss
bss$ Vss
V
& 1 2.4: Astable
A0 $ b Figure &1
A0 $ b Multivibrator 2 $ b $ V
and its characteristics
ss 2 $ b $ Vss
+ Vss + V2Vss$ b $ Vss
ss
T = 2 $ RC $ ln d
1+b
n T = 2 $ RC $ ln d
1+b
n +VSS
- V - V 1 b
The monostable remains in the “on” state until it is triggered; at this time, the circuit 1 - b
-
$ ln d The $n
ss ss
2ss $ b $ Vss equal to 1x .=+ bequation
ln d 1 for
R
1 - bn
switches
b $ Vssto the “off” state
b $ Vfor
T =a period 2 $ RC RC x= is RC $ ln d 1 n
shown C VC
1-b
11t ++ -x b
2 $ RC $ ln d1 n 1 b
below.Vss Vss Trigger V
b t+x C D
2$T =
lnbd 1x =-RC nb$ ln d +b n x = RC(2.5)
2 $ b $ Vss b$V -VSS
$ ln d n
ss
1+b
1 + b x = RC 1$ +
T = 2 $ RC $ ln d Tn = 2 $ RC $ ln d n1 - b b R
x+=xRC1$ ln d ! 1V n
1-b 1-b 1 ! 1V R
x = RC $ ln d n x = RC $ ln d
1 - bt,n the next
1 t 1 -b b R1 R1
After triggering the 1 -monostable
b at time =
trigger
R1 + Rpulse mustbbe = applied
R1 + R2
1 +$ bln d n
2
after t + x . The formula for t +tx+ is xgiven below. 1 +R1b R1

x = RC
x = RC $ ln d n x = RC $ ln d n 1 bb
1+b R R2
=V RC $ ln d n
2
b b +R
! 1V ! 1!x
V 1
R
b 1
R1 R1 f = = 1,5 kHz
T f = 1 = 1,5 kHz
T
b=
R1 + R2
b= !
b R11 V
+ R2 R1
=R R x = 4 ms x = 4 ms
1+
R1 R1 2
S. No. Regenerative
R2 b FeedbackR1 RC RC
Hysteresis
R2
R1 = R1 + R2
R R
1
f = 1 = 1,5 kHz f =R112 = 1,5 kHz
T T
2 x = 4 ms x= R42 ms
RC RC
3 Rf 1 1,5 kHz
=T =
4 1 1,5 kHz
xf == T4 ms =
Table 2.1: Plot of Hysteresis w.r.t. Regenerative Feedback Figure 2.6: Monostable Multivibrator and its outputs
RC= 4 ms
x
Analog System LabRC Kit PRO page 25
T = 2 $ RC $ ln d 1n+ b
ln db n
1-b
T = 2 $ RC $ ln d n
1+b
ln db n
2 $ b $ Vss 1 + b Vss T = 2 $ RC1$ + T = 2 $ RC1$ -
d 1n- b
x = RC $ ln d
1 - bn
1 - b T = 2 $ RC $ ln 1 b 1
T = 2 $ RC $ ln d 1n
-
x = RC $ ln d n
1+b 2 $ b $ V 1 - b 1
1 + bx = RC $ ln d 1 d 1n- b n
ss
db n ln db 1 n
1
x = RC $ 1ln- x = RC $ ln x = RC1$ -
1 - b T = 2 $ RC $ ln d n 1-b t+x
x d1 - b n
1 1-b t+x
2.2 Exercise Set 2 t +$ ln
x = RC 1-b t+x
x = RC $ ln d n
t+x 1+b
x = RC $ ln d n
t + x
1 + b x = RC $ ln d 1 - b n
experiment 2
1 1+b
ln db n
b
x = RC $ ln d n
t+x 1+b b d1 + b n
d nb
x = RC1$ + x = RC $ ln
b x = RC $ ln b ! 1V
d n circuit with
1+b b ! 1V
1 Design a regenerative
x = RC lnfeedback
! 1$ V b
t x
+ the hysteresis of ! 1V . Obtain the c) Vary the regenerative feedback
! 1V and see the variation in R1 the
1 + b ! 1V R1 b=
DC transfer characteristics
! 1V b of
R1 the system. RC $ ln d the hysteresis
x =Estimate n b=
and Rsee1 how hysteresis, hysteresis bis=directly
R + R2 1
proportional
R to regenerative
R1 + R2
it can be controlled by = varying
R R the regenerative b
feedback R .
1 R1 + R2
feedback. b1 = R1
b = R1 1
R 1+ 2 ! 1V
b=
R
R11 + R2
R1 R1 + R2
R1 + R2 R1 R2
R1 R2
2 Vary either R1 or R2 in order to vary b = . Apply R1 the triangular Rwaveform
R1 + R2 R2
2 with 3 Design an astable multivibrator using charging
R
R2 and discharging R of capacitor
the peak voltage
R2 of
R 10V at a given frequency
R1 to both circuits and
R observe the C through resistance R between input and R output of the Schmitt trigger.
1 1,5 See
R f = = kHz
output waveform.
R 1 1 1,5 kHz Figure 2.4. Assume that frequency f = 1 = 1,5 kHz . T
R 1f = 1,5 Tf = 1 = 1,5 kHz
f = = 1,5 kHz
T
2
f = = T =kHz x = 4 ms T
x = 4 ms
1 1,5 kHz Tx = 4 ms
R for DC transfer characteristics.
a) Sfubmit
= T x= the
= 4simulation
ms results x = 4 ms
Design a monostable multivibrator for = x 4 ms and estimate RC using the
RC
x = 4RC ms f = 1 = 1,5 kHz RC RC formula 2.5. RC
T
b) TRC
ake the plots of DC transfer characteristics from oscilloscope and
x = 4 ms
compare it with simulation results.
RC

Chapter 3
Experiment 3
Study the characteristics of integrators and
differentiator circuits

A = GB s
V - 1
Goal of the experiment 3.1.2 Differentiators 0 sCR
Vi = a1 + 1 + s k
experiment 3
GB $ RC GB
The goal of the experiment is to understand the advantages and A differentiator circuit that uses an OP-Amp is shown in Figure 3.2.
disadvantages of using integrators or differentiators as a building block in
C N th
solving N th order differential equations or building an N th order filter. V0 A = GB s
- sRC (3.1)
Vi =
b1 + GB + GB l
A = GB s A = GB s
s s 2 $ RC V0 - 1
= sCR
V0 - 1 V0 - 1
sCR
Vi a1 + GB 1$ RC +
3.1 Brief theory and motivation
sCR =
a1 + GB 1$ RC + GB k
=
a1 + GB 1$ RC + GB k
Vi s Vi s
= - sRC C
(3.2)
b1 + ~0 Q + ~02 l
C C s s2 V0
= - sRC
b1 + GB + s GB
Vi s 2
$
V0 - sRC V0 - sRC
Integrators Vand= differentiators can be used as a buildingVi block
= for sfilters.
s 2 $ Filters
b1 +block
s s $ RC
l b RC
l
2
i
form the essential +in analog signal processing to 1 + signal
improve + to ~0 - sRC
GB GB GB GBnoise =
b1 + ~0 Q + ~0
s s2
ratio. An OP-Amp= can - be
sRCused to construct an integrator or
= a differentiator.
- sRC This The output of the differentiator remains at input offset (approximately 0). However,
b1 + ~0 Q + the l b1 + ~blocks 2l
~at GB
experiment is to understands s 2 advantage of integrators as building s sinstead
2
any sudden disturbance the input causes it to ring at natural frequency ~0 .
+~
~02 0Q 0
of differentiators. Differentiators are rejected because of their poor high-frequency ~ GB
~0
noise response.
~0 Vpp
~ GB ~ GB Vpp
Vpp Vpp Vp R Vp
Vp
C
Vp Vp $ T
C Vpp = Vp $ T
Vpp = Vp $ T
V
V pp =
2 $ RC
Vpp = Vp $ T 2 $ RC
I
2 $ RC T =1 f
2 $ RC VO = -SCRVI
T =1 f
VI
R T =1 f T =1 f f
f VO = -Vf I/SCR
f
Figure 3.2: Differentiator
Figure 3.1: Integrator

3.2 Specifications
Fix the RC time constant of the integrator or differentiator so that the phase shift
3.1.1 Integrators and magnitude variation of the ideal block remains unaffected by the active device
N th parameters.
An integrator
N circuit that uses an OP-Amp is shown in Figure 3.1.
th
Assuming A = GB s , A = GB s
- 1 3.3 Measurements to be taken

- 1
V0 sCR
=
N th Vi a1 + GB 1V 0 +
$ RC =GB
s
k sCR
Vi a 1 + s k 1
A =CGB s Transient Response - Apply the step input and square wave input to the
1+
V0
V0 Vi = - sCR
1- sRC GB $ RC GB integrator and study the output response. Apply the triangular and square
a1 +bto l
= s s 2
$ RC input to the differentiator and study the output response.
GB + sGBk practice.
Vi 1 +1 C
The output goes GBsaturation
$ RC + GBin For making it work a high valued resistance
- sRC
across C must=be added V in0 order to bring the
- sRCOP-Amp to the active region where it 2 Frequency Response - Apply the sine wave input and study the phase error
b 2l
s s 2
=
b l
can act Vas an 1 + sRC
integrator. + and magnitude error for integrator and differentiator.
0 - ~0 QVi ~0 s s 2 $ RC
Vi =~0
b1 + GB + GB l
s s $ RC 1 + +
2
GB GB
page 28 ~ GB - sRC Analog System Lab Kit PRO
= - sRC
b + + 2 l=
Vpp 1 s s2
2
V0 b1 + GB + GB - sRCl
C - sRC2 =
Vi =
b1 + ~0 Q + ~02 l
V0 - sRC
b1 + l=
s s $ RC s s2
Vi =
b + GB + s GB
V0 GB + GB - sRC - sRC s 2
$R
b l
1
Vi = s s 2
b1 + GB $ ~l0~0 Q ~02
- sRC s s 2
1
RC+ +
= + - sRC
b1 + ~0 Q + ~ l
s s 2 ~0 GB ~ GB =
b1 + ~0 Q + ~0
3.4 What should you submit = - 0 sRC
2
b1 + ~0 Q + ~02 l pp
s s2
experiment 3
~0 s ~ GB s 2
V
~0
~ GB ~0 Vpp Vp
1 Simulate the integrator and differentiator and obtain the transient response 4 Transient response - Apply the
Vpp Vp squareV waveVpas
~ GB
$ T an input to integrator, vary
~ GB pp =
and phase response. the peak amplitude of the square wave and 2 $obtain
RC the peak to peakVpp value
Vp Vp $ T
of output wave. Vpp is directlyVproportional
pp =
2 $ RCT = 1tof peak voltage of input Vp and is
2 Take the plots of transient response and phase response on an oscilloscope given by Vpp = VpV$pT , where T = 1 f , f being the input frequency.
2 $ RC Vpp = Vp $ T
and compare it with simulation results. T = 1 f Vpp = Vp $ T f 2 $ RC
Figure 3.4 shows sample output waveforms obtained through simulation. f
2 $ RC T = 1
f T =1 f f
S. No. Input Frequency Magnitude Phase
f
1
Table 3.1: Plot of Magnitude and Phase w.r.t. Input Frequency
S. No. Input Frequency Magnitude Phase
2
N th Figure 3.3: Frequency Response of integrator and differentiator
3
A = GB s
4
V0 - 1
= sCR
Vi a1 + GB 1$ RC + GB s
k
5 S. No. Peak Value of input Vp Peak to Peak value of output
C
Table 3.2: Plot of Magnitude andV0 Phase w.r.t.
- sRCInput Frequency 1
Vi =
b1 + GB + s GB
s $ RC
l
2
3 Frequency Response - Apply a sine wave to the integrator (similarly to the

- sRC
2
differentiator) and vary the input frequency= to obtain phase and magnitude
b1 + s + s 2l
2
error. Prepare a Table of the form 3.1. Figure 3.3 ~ shows

0 Q the
~ 0 typical frequency 3
response for integrators and differentiators.
~0 For an integrator, the plot shows
a phase lag which is proportional to ~ GB . The magnitude decreases with 4
increasing frequency. For the differentiator,
Vpp the phase will change rapidly at
natural frequency in direct proportion Vtop quality factor. The magnitude peaks Table 3.3: Variation of Peak to Peak value of
at natural frequency and is directly proportional to the quality factor. output w.r.t. Peak value of Input
Vpp = Vp $ T
2 $ RC
T =1 f
f
3.5 Exercise Set 3 - Grounded
experiment 3
C1
R2
R1
C2 Capacitor Topologies of Integrator
+ VF1 VF2
and Differentiator
U1 U2
Determine the function of the circuits shown in Figure 3.5. What are the advantages
and disadvantages of these circuits when compared to their conventional
counterparts?
C R
R R
VI R VO = sCRVI/2
R
VI
R VO = 2VI/SCR R
R C
Figure 3.5: Circuit for Exercise 3
Figure 3.4: Outputs of integrator and differentiator

for square-wave and triangular-wave inputs

Chapter 4
Experiment 4
Design of Analog Filters

N2
N2
~ 20 = 1 RC
~ 20 = 1 RC
~ 0 = 1 RC
H
H000 = 1 RC
~
Goal of the experiment H
experiment 4
HV0300 +H
VV03i = + H00 s 2
Low Pass Filter VV03i = b1 + +s H0+ s 2 l s
Vii = bb1 + ~0ssQ + s 022 l
VV03 = 1 + ~+0 Q H0 ~022
s 2l
To understand the working of four types of second order filters, namely, Low
b1 +b H 2 ~02 l
2 ~
Pass, High Pass, Band Pass, and Band Stop filters, and study their frequency +
~00 $Qs 22 l~0
~0 Qs+
bH s 0022 l
characteristics (phase and magnitude).
bb H s 2l 2
V01 0$ ~
02 l s 2
VV01i = 0$ ~
High Pass Filter VV01i = b1 + 0ss ~+ H $ ~
s 22 l
i = b s 0022 l
VV01 = 1 + ~0 Q +
bb11 + s 2l
0
4.1 Brief theory and motivation s ~

k 002 l
Vi ~0sQ + ~
+a-~ 0Q + s~
a s0 k
~HH0Q $ s0 ~
a sk2
N th
0
V - 0$ ~
a 0 $ ~0 ks 2
02
VV02i = H 0$ ~
b + 0sQ ~ + s 22 l
N th
Second order filters
N
(or
N22
biquard
th
filters) are important
N since they are the building
th
V 02 =
- H s
-
= b11 + ~ s 0022 l
N th
N th
VV 1
Band Pass Filter V02i =
N
bb1 + s 2l
N 2 2 in the construction
blocks N 2 2of N order filters, for N 2 2 . When N is odd, the N order
th th i
sQ +0 ~
02 l
N22 N22
filter can be realizedNusing N N -2 1 second order filters
N and one first order filter. When V ~ sQ2 + ~
b l
N 2 N2 2 i 0
2 + ~ s + ~
b11 + ~ s 0022 l $$ H
N N 0
N- is 1even, we need N - 1 second order filters. Please N - 1listen to the recordedN lecture 1 +~ 0sQ 2
$ H
~
b 2 l H02
NN 2 00
N2- 1 for a detailed explanation V04 2
b1 + s~ 0 l$ H
at [19] 2 2 N - 1of active filters. 2 N-1 0
2 N-1 V 04 = + ~ s
i = b1 + ~02 + s 222 l
N2 N ~ =21 RC N VV i = s0
Vi = b1 + 0s + ~ s 0022 l
2N 2
0 2
2 N
VV04
s
bb11 ++ 1~0 Q + ~022 ll
Second
2 = 1 RC order filter can ~ be= 1used
HRCNto construct four different types of filters. TheNtransfer 04
~ Q
~ 0 0 0
~ = 1 RC 2 Band Stop Filter
functions
~ = 1 RCfor the different filter
H
0
2
V ~ types are
+ HshownHin Table 4.1, where ~ = 1~RC
2 and
0
Vi ~0sQ + ~ s
0 H 0
= = 03
1 RC 0
= 1 RC
0
~ Q ~
+bH+ ~ Q + ~ lV
H is the low frequency gain V of the transfer s function. The filter names are often
0 0 0
s 2
~ 1
V
0
+H V 1i
HFilter),
H
H Filter),
0
~
0
1 - 2Q 12 0 0
03
V =
abbreviated
0
asHLPFs (Low-pass
= 03
HPF
0
(High-pass Filter),+BPFH (Band Pass2
- 1
b1 +(Band l b1 + lsHl we
0 0 0 03 0 0
+ V = 0
b1 describe lV = V active
s 2
s s
+b H~ $+
2
03
i
V =BSF sQ +
0 i
V s
2
s V + H 2 03 0
~0 1 - 2Q 12 2
b1 + ~ l
i
b = s + +s l
and Stop
~s Filter). V~
In this H
=Q experiment, will + ~ Q +a~universal ~0 Hof10 Active
Q- 2Q
2 03 0 2 0 03 2 0
i
Table 4.1: Transfer functions Filters
00 2
b l b l
0 0
+ V ~ 2
1 +
i
b H $ ~s l Q
V V 2
V bH $ l s~ Q
0 0 2
Q
~ provides ~ all the four
2
= 01 i s s 0 2
s s H 2
Q
b l
filter, which s 2
filter
s functionalities.
2
Figure 4.1 shows a ~
second Q ~ i 2
b l
0 0
1 + + s~ s 2 1 + 2 + 0 0 0
b H $ ~filter
l V realized H Q
2
~ Q ~ 2
1
bH $ ~ l s
V
0 2
1i
~ + 0
+ 2 0 H $ 0 0
s 2 0
00
order
V = universal using two ~ Qintegrators.
s ~ V = Note that~ thereV are different 1H-0 Q 1 2
2
bs Hl $ ~ l V bH $ ~ l
01 0 01 0 2
=
b l b
0 2 0 2 0 01 0 0 2
V ~ Q a-~H $ k
s V
b l
s 2
s 2 2
01
i
=
outputs 1 +of the
0
circuit
+ that 1 i
realize LPF, HPF, sBPF and BSF s
functions. s 2 01 0 0
1 - 4Q 12
b1 + ~ Q + ~ l
+ + 0 2
= i 2
bV1 +=~ Q + ~ l s
V s s 1 + + V
1 - 4Q
2
i ~ Q ~ V V = 01 0
~
2
00
~ Q ~
0
V s s 2 01 2 0
12
Va- H $b1 +k s +s ~ l b1 + ~ Q + ~ l
0 0 i
a k
02 0 0
1
0
= s s 2
s d z -
2
4Q
b l
2
a k
H
0
$ s 0 s i
s 2 i 2
- 0
a- H $ ~ k V =
0
V02
0
s 0 02 1i
+ ~
~~ Q ~ V Q+ 0
-
0 H $
~ 2 0
2
a- H $ k s
s
0 0
dz 0
2
4Q 2
b1 +V02~0 Qb1++a~-0s2H
0
s 2 2 0 $ k Vi = a~
-0H02$ ~ k
= z
Vi = b1 + ~0sQ + ~ 2l
V02 0
s ~0 s 2 Vi
0
s
l l $~
00 02
d~
b l
0
s s 2 V02 = V02 z
i
s
b1 + ~0 Q2 + ~ C l d~
bV1i + ~0 Q + ~ s 02 l s 2
s = H00 1 + + V = s s 0
~ Q ~ d~= ~0
2
b l b l ~
0
V ~ 2 i
b1 + ~s02 l $ H0
04Vi
Vb1i + 2 l $ Hs0~0 Q s ~02
0 0
2
= s C 2s
0 2
b1 + ~02 l $ H0R
s s 2
d~= ~0
b10 + ~0 Q +2 ~02 lV04 ~
0
1 + + s 2 1 + +
b 2 l $ H20
0Q
s2 ~ ~02
b + ~02 l s0 ~ =Q~
V04 1 V04 ~
s b1s+
+1~ 2 l~02 l $ H0 Vi b1 + ~02 l $ H0
+ 1 $ H
= = -2 0
Vi = b1 + ~0sQ + ~s02 l b1~+
R 2 s
2
~ ~0
V04 s~0 s Vi =
b
=
2l
i
s s 2 V04 = V04 2Q
-~20Q
b1 + ~0 Q + ~02 l
VR~10 Q
b 2l
0 04 - 1 + + V s s2
V =
1H0 Q b1 +
2Q 2 0
s
+ ~2l
s 2 R ~ 0Q ~ 0
i
V1 +=
b01 + ~0 Q0 + ~02 l
+~ s s2 -~20Q
~0 1 -
1 ~ 1 BPF
-
i
~ 0Q
1
i
~ Q -
~0 1 - 2Q 2
1 2 0
2Q 2 ~
LPF
0 0 1-
2Q 2 ~0 1 - HPF
1 ~~
0 0
H0 Q 2Q H0 Q ~ 10- 11-2 1 2 ~ 0 2Q1 2- 1 2 ~~
0 0
H0 Q1 4Q 2Q H0 Q 2Q ~
H0
Q
1 - 12
4 Q
1
1 - dz2 H0 Q
4 Q 1- 1 2
H0Q
H0 Q ~
H00 Q
1- 1 2 1
1- 4Q 0
dz 4Q 2 dz
d~
1~- 1 2 R dz R 4Q1 - H00 Q
~ = 11 kHz
dd~ z d~
~ = 0 4Q
dz 4Q 2 H00 Q
~ = kHz
d ~
~d~ = ~0 ~ = ~0-Q•R
d
2Q z
d~
d z ~ 0 = 1 kHz
Q = 1
Q0 =11 kHz
~
~ = ~0
~ = ~0 ~d0~ d~
- 2Q - 2Q ~0~ = ~0 ~ = ~0
Q0==
=1110
-BSF
2Q ~ = ~0
-~20Q ~0
VI ~0 - 2Q ~
Q0= kHz
~0~0 ~0 H0- Q2Q
R/H~ ~0 ~0 - 2Q ~ = 10 kHz
~0
0
0
~0
~0 ~ =10
Q00= 10 kHz
H0 Q H0 Q ~0 = 1 kHz
~0 H0 Q ~0 ~ =
Q 10 10 kHz
= 10
H0 Q H0 Q
~0 = 1 kHz QH=0 Q
~0 = 1 kHz 1
~0 = 1 kHz H0 Q Qf = 110
= kHzBPF, BSF, and HPF filters
~0 = 1 kHz
Q=1 Figure
Q =4.1:
1 ~A0~=
Second-order
101kHz Universal Active Filter ~0 = 1 kHz Qf=
Figure 4.2: Magnitude and Phase response=of1LPF,
kHz
0 = kHz Q=1 ~ 0 = 1 kHz
Q=1
~0 = 10QkHz 10 Q=1 ff = 110kHz
kHz
~0 = 10 kHz =
Q=1 ~0 = 10 kHz Q=1 = 110kHz
f Analog
= kHz
~ 0 = 10 kHz
page 32 Q = 10 f = 1 kHz ~0 = 10 kHz
f= System Lab Kit PRO
Vp kHz
10
Q = 10 ~0 = 10 kHz Q = 10 ~0 = 10 kHz
Q = 10
f = 1 kHz f = 10 kHz
f = 1 kHz Q = 10 f=4 $10 kHz
a- H0 0 $ ~0 k 0 b1 + ~0+ l 02 N2sb1- l
i b1 + s 1~~0s202lQs 2 ~02
~ QQ ~~0V0 V= =0 + +
1Hb+ 2l
Q ~02~
Vi = ~0 Q ~00N
b s s 2l b 01$ + 2 l l
V02 +
VV03i = N a- + k 1 +s 2Hs $ + ~s0 Q N th N22
a k b l
s 2 N
b l
i
+++
VV02i = b21 + s ~ 0H
2 l
V02 b l a k
H s $ s s 2 2
s V ~ 2 Q H ~ s
Vi V02bsH0 N $1s 2s2 2ls
0
- ~ 00Q ~ 1 + H $ V $ H 03 ~ Q ~ 02
b10 + s 02 l V04 =
$ N - 1 2 = s 02
H $ 0
b11+
-
2 l2
+ 1 + H 0 0 00 0
~02 s~20VV04012 = N22
01
0
s 022 0
~0~0 = 2
N
Vi = ~ 0 b= l2$0lH
2
b10 +~1~
0
s0
b l
0 2
b1 + ~ +~
2l
=~ Q ~
Q2 + Vi = 2Vi V0122 ~
b l
1 00sRC si i = +~220~
l 02 bb1+ V0i 20042ll = H
1= RC
s~b01=+1s~RC l
~ Hs0 $ +
b1 +~0 Q022sl2 $ H
i-+
V01b1 + ~0+
+ 2V V ss ssV = V 2Q Q s ~ 0s
s V 1 + 0
b1H+ +H0~$ s20s2lQ

~00 s ~ s 2
1 NQ + Q 2 ~ ~ N N-1
V04 H0 b H0~ 2l
i
+~ +~ 2
2 +
b l
= ~0 Q Q2 ~02 ~
0 2 0 0 0
~00Q
Va01b- k + s202l2
~ ~02
VV01i = V03b1 + s ~ l0 $ H02 0 b11b1++~0sQ2 l+$ H~002 l
$ 2
4.4 What you should submit
V V 0 Q~0 Q
0
s
Frequency Response of Filters s s s 2
~V0 1 - a-2H
1 0 $ Vs021k +0 $ ~Q
H000 bs1 +~~ 0 0 l $ H0
i
i
1H N-1
VV04i = b1 += s~02 + +ss H 2 l
0
i Va H20 $ s ks s ~0 s s 2
0 = =RC V03= 1~ H N
experiment 4
Vi = bV ss 022 l s
~ 2
1b1bV l
~ V 1 ~
s b1 + 03 ~20lQ +~
-
1i + ~b0s1Q++ ~ l Vi = 21Q a- H s s Vski2 H=0 Q
2Q ~
Vi 0V022 VV 1 - =
-
s ~0 0s2 l20
0 2 2
b1 + 1~ 0 Q + ~0 l+
0
2 2 04 2 02
i 4 sQ 2
2
V020 Q b + ~ Q0 $ + ~0 2 l b1 + H0 + V~i 20=
+~0 + +2H
l
04
= + N
~0 Q ~0 b1 + s 2 Vbi + + ~2 lQs +s ~ 2 l s
~~ 0Q ~02 H s 1 -~ Vi02Q 21 + ~
= 0~0 2Q ~ 0 = 1 RC
b01in 2l
Q
a- k phase
~ 0Q
2
d z s 1 s
0 Q$aH k
~0 1 - ~02 2
s s2 Vi =1 of LPF,
2
b l b l
0
b l V02s ~02 s22 b H10 $ ~02 l

0
The magnitude 2 Q H
2
0 $ and response s BPF, s1 -BSF, 1 and V03HPF filters H 0+ Q are
H0~shown - H~ 0$ +
0 2
s 0+
b + peaks 2 l04
V 1 ~ H 00 $ 1~- 1 + +
1~0 Q ~02 4Q1 V s i V=
2 d ~ 1 + ~ Q ~ ~ = 1 RC H
b s -l$2H
0
~0 = 1V-
b l
02 2 0 0 0 0
~02 $H ~0 21s 2 Simulate the circuits and obtain the Steady-State response and Frequency
bV1i + + s 2 l sdz
0 41
Vi H0 Q -
Qfilter =
+00 ~20lsQ2 +b+~0s02 2l~l02 l response.
Figure 4.2. Note thats 2the low-pass frequency response at
2
Vi ~
i Qs b1
01
2=Q 2
s 2 Q 2
~ = 10
~+ = V 011 00 + 1
1H-0 Q 1 2 ~b10 Q+ ~~ l b12~

1 s s
~d02~ V04 H0 Q b
1 + s 2l$ V
V Vi V042 - 1 =+
HbsV0101Q+~
2 2 dz =
04 0
Q 2 ~ ~+ 2
s2Q H $2 02
H0 V03 + H0
+QV
2
b l
04
H0 Vi =
b + ~2l
0 + s s -
0 b 0 $+ 2 lVi + s l
=
b
0Q ~0 d~i ~s0 2Q s s2
hasb a2+value l equal
4Q 1 + + V = 0~0 Q ~
bH1at l $sH00Q + ~02 l
s
b1 1+ ~
1 s 2
= di 2z
H V + H 1 +
402Q ~02a- H0 $ ~0 k~ =V~
0
~ 0Q ~ 1 s s 2
b1Q+2 ~0 Q +~~=02 l~0

2
and s to i1 - . The phase sensitivityV01~0 d1~-is 1maximum
03 0
1
2 1 - 2 a- 0 $ ~k
1 $ H ~ = ~ Q
b 2l
d04z1 - s s ~~ 0 2+
2
0 0Q
0 2 0 0
0
Vi s s2
~0 Q ~0 b H0 $ 2 l
V 4 = ~0 V2V04Q 2~
22 s
1 1
~bH 2l s
= V 0
V 4 Q ~ Take the plots of the Steady-State response and Frequency +
response + from the s 2
bV1i + 1Q+given ss 2 l s-2 2dQz a- sHs202l$ ~0 koscilloscope and compare it with simulation results.
dV~
d ~2 Q 1 - 2Q 2 s =1+ s
Qb21bV
= s
d~= ~0 and~b0is + ~ 2 l~0. This
i 02 0
z 2
- 0
~10 + =1~ V-i0 di 2z=
l
i
V01s 2 ~0
b $ i =2 l
~ +~
0 by
1
information ~ 0 about phase variation
0H Q0 ~ Q0VQ can ~be
1 +
02+used
0 s +
+
~0 b1 + + ~2l
1 - ~ Q ~
1 -~~a0- k 1next
~0 Q 0~0 d~ H Q - 2HQ01Q d~s Vi =~0 Q ~ 2 H 0V s s2
b l
0 0
2 Q 2 0
s 0
s 2
V01
to
-02=tune 1 0- the 1 filter sto 2 a desired frequency ~0 . This is demonstrated
2 1in the
2 b1 + l $ H0
~ H 0 $ kHz
Q~
4Q 2 Vi d=z ~10Q-=Vs1104 2 sb2
~021 +2 2 l ~
~ 0 ~ =H ~ 1 V 0 = 1 + + = ~ 0Q
b 2l
~ 0Q0
1- 4Q~0~ = ~1- s 2
Vi N th 0
Q ~0 $ H0 Q ~0 s s
02 0 2 2
experiment. V04 2Q
b1 + ~40Q Q~02 l s b1 + ss2 2 l $ H
3 Frequency Response - Apply a sine wave input and vary a k
-~20Q ~02 H 0Q
0
1its+input + frequency H $ s
H0 QVi = H Q 2Q 1 N22~ Q ~ -
s2 - 1 - + 2
b1 + ~0 Q + ~~020 l=~10 kHz4Q 2 QH2 = 0Q

N th 0 0 0
bV1104+=~0 Q + ~~020 l to obtain the phase and magnitude error. Use Table
0
~~ s dz - 4.2 and 4.3V02to=snote your ~0 2
Q0 =Vi10 a- HV0i $ ~0 kb1 + s + s l
0 0 0
~0 = 1 kHz d~dH z0~ 2~0kHz
b0 10=+ l $4given
1 d ~ s N 2 2 N
Q 1 b1 + s + readings. 2l
H00 1Qthe
~
For - 4Q bandpass filter, the~dmagnitude response The nature of graphs should be as shown V above.
0z
Q~==1~peaks at ~ = and is Vi0 2 by
2 d~ ~~ ~1 02- H s2 02
= ~0 Q ~02
b l
1 Q = 1 V Q = 1~ kHz
10 0 V s1 s2
N N
2 0 Q ~0b1 + ~02 l $ H0
0 =. 1
~
The 1 -
kHzbandstop d ~ 0 04
~ 0Q ~ -
2Q filter shows H0 Q a null magnitude response at 2Q = d.z 0 Q s 2Q 2
i
H Q 1 1
=Q10 kHz Vi - bQ1 +
~
2l
~dz 0 2 ~ = ~ - 0 + + s2
f =1 s1HkHz
0 0 0 2
~ 10 = ~ ~-0 2 = + 1 ~ 2
~ 0 = kHz N 1 V
b1N+ ~ l 0
~d
Q0= ~ =11 kHzH0 Q
0
~ - 2Q ~
0 d~ Q H0 ~ Q~00 1 - 2Q 2 - s $H
042
~0 = 1 kHz Vi02 =
0
b1 + ~0 Q + ~02 l
~ = ~0 1 Q =-10 2Q Q~ =0 10 ~0 ~ ~00f== 1~10
~kHz
10 0 = 1 kHz
= kHz ~0 1 2 s s2
Q0=
~ = 110 1
kHz- ~ ~ 1 - H Q V 04 2
Q = 1 2 1 - N =
b1 + RCs l
4Q 2 ~ 0 0
2Q Q 1 0
f = 1 kHz H0 ~ QQ0 = 10 p = 4Q Vi ~0 =s 1 +
2
- 2Q f = 1 kHz
0
4- $2 VQ 2
1 2
~
Q~ 0== 10
10 dzkHz ~00= 10 kHz H0 Q H0HQf Qr 1$ HkHz 1~-02 1 2
4.2 Specification
0 ~ f = 10 kHz = d~ 0z
~ $ 0Q= 101kHz - 4Q 2 ~~ 0Q 0
f = 10 kHz ~0 = 1 kHz 0
Band Pass ~ 0 = 1 RC
BandH 2Q
1 Stop
0 0
d~
Q
~ f 0= = 110 kHz QH= 0 Q10 ~0 = 1 kHz
4 $ Vp 1 -~f0 1= Vp ~d0 ~ dz
kHzQ = 10 ~0 1 - V 2 H0 Q H
~ = ~ 4 $ V Q =41Q 2 110~ kHz H 2 Q +
2=$ r ~d0$ 10 ~ 4 rad/s S.No. Input Frequency Phase Magnitude Phase Magnitude
0 03 0
Vi = 1 - 1 s
0 p
f 0=Q110kHz ~0 H
+ 0 b +4~ Q0 Q + ~02 l
H kHz r$H f~= 0 = 1 kHz
1 kHz rQ$ = H01$ Q dz~0 Q =0 Q s2
0$ Q = 4 1$ V f = 1 kHz H 0Q
-kHz 2Q V = 10 kHz
-
p
2Q ~ = ~0 V 03 H 1 2
f = 10 H 10 =
b11+ - 4sQ 2 +dsz 2 l
~ 4
Design ~ $ V1 kHz Q
a0 Band Pass and a Band Stop filter. For the BPF, assume 1 ~ p 0 = 10 kHz d~ =
= V f = 10 kHz r $ H $ Q 10 kHzand
kHz
= 0~ 1 1
0 p p 0
f== 1 Vi 2
~0 Q ~0 b H0 $ s 2 l
~0 = 100 ~ kHz
p y_ t i -_100
r 4$ H$ V $p Q 2 $ .r $ 10~4 rad =Q~ /sV0 10
= 0
2Q rt i 0.1 sin _200rt i 2
Q = 01.~ For
0 the BSF, assume ~0 = ~402= $ $Vr10
p $ 10 kHz 4
radand /s ~Q0 = = 10 Q ~ =41sin
= $ p~4 0
V + Vs012 d ~ ~
b H0 $ V~i 02= l = ~0 s
Vrp $ H0 $ Q f =Q 1=kHz 10 0
dz 0
rQ$10 H010 $Q kHz - 2Q ~0 =~2H0 r
b 2l
~0 = 10 kHz H0 = = Hf0= =110 $= r$ H $ 10 0 $kHzQrad/s 2 ~
Vp0 = 2H$0rQ$ 10 4 rad/s f kHz 0 Q 10 ~ V d ~ 1 s2
f_= t isin
1
_100 rt i +H0.1 10=_p200 r0 tQi
~ Vp ~f0 = 10 kHzV = 0
+ +
_ i _ i = _sin i
01
= ~ Q ~
b1 + ~ Q + ~ ~2 l
Q = 10 f= = sin 1 kHz y0.1 10 kHz 0 = sin Vi ~ = ~0 s 22Q 0 0
~$0r=$ 10 1 kHz y t 100 r t 200 r t Q 10 - s
- 2Q 0 V02 s= 00 a- 0 ~0 k
~ 2 4
rad / s + ~ ~ = 1 H kHz
H00 = 10 4f $= Vp 10 kHz
y0_$tQi f= ~0 =_100 rt$1i10 /s _3200rt i H $ s
0
~0 = 2 $ r $ 10 rad/s 4 0
4.3 Measurements to be taken

2$r 4
radsin
f = 1 kHz
H_0 t=i = Q=1
sin _100rt i + 0.1 sin _H
f = 10 kHz
i
4 $ Vp Q=sin 1 1kHz ~0 = + 0.1
kHz
~0 a- H0 V $i k 1
10 H 0Q r$H 4 $ V =
~0 b + + ~2l
y 2000 = r t
10 r $ H0 $ Q p
H0 = 10 ~ 0
s s2
y _ t i = sin _100rt i + 0.1 sin _y200 t isin _100rt iV+
f = 10~kHz 0 = 10 kHz 4 $ Vp V=p r $ H0 $f~ Q= V02
r_ t$ iHr= p 0.1 sin _200rt i
~ 1 kHz 0 = 10 10QkHz =kHz 1
_$ Vt4iprad _100 rt i +40.1 sin _200rt i
= ~ Q
b1 + ~0 Q + ~02 l
0$ Q
0
Vi ~0 s Hs0 Q 2 0 0
~01V=p 2 $ rQ$4y10 =0 = sin
b l
4 $ VQ p = 10
Q4 = = 10 ~ /s 10 kHz s2 $ H
V ~ 0 = 2 $ r $ 10 rad/s H Q ~ = 1 kHz
+
r $ H0 $ Q p
H0 ~ 0 = 2r$ $rH$ 010 $ Q4 rad/s 0 0
~0 2 0
sV204, Q
V1 b 2il $ H=
Steady State Response =(Try 10
~0 =- 2Apply $ r $ 10a4 rad square wave ~ input and
f = 1 kHz 0 = 10 kHzVf = 1 kHz Q = 10 =0 1
b1 + ~0 Q + ~02 l
H/s0 = 10 Table 4-2: Frequency Response of a BPF with ~0 = 1 1+kHz
y _10 tHioutputs.
= sinf _= i +1 0.1 sin _200rt i
p
0 = 10
p
~0 V s s2
to both BPF and BSF circuits and observe the V04
y _ t i = sin _100rt i + 0.1~sin _2002 $ rrt$ i10 rad/s
f = 10 kHz Q = 100 10 t=
rf kHz kHz =
_ t i = sin 4 $_100 i +kHz 0.1 sin _200rt i b1 + ~0 Q + ~02 l 1
~0 = 2 $ r $ 10 rad/s 4
H0 = 10 0 =
4
Vi Q = 1 s ~0s = 2 10 kHz
rt10
H0 = 10
4 $ Vp
y _ t i = sin _ 100 r t i + 0.1 sin _200 f= r t 1iykHz Hr0 =
Vpf = ~ 0 = 10 ~
kHz Q 1 = - 10
$ H10
0

r $ H0 $ Q Band Pass output will output the fundamental frequency 0 $ Qof the
2Q 2
y _ t i =Vpsin _100r t i + 0.1wave sin _200 rt i
1
V_pt i = rsin $ H_100 $ Qrt i + 0.1 sin _200rt i
f = 10 kHz 4 $ Vp ~ 1 - H
square multiplied by the gain at the centre y frequency. Q = 210 f 0=Q1 kHz
0The
0
Q2
~0 = 2 $ ramplitude $ 10 4 rad/s at this frequency is given by 4 $ Vp , where ~0 = 2V$p ris$ 10 therad/s
4 H f
0 Q= 1 kHz 1 f-= 10 1 kHz
r $ H0 $ Q Band Pass Band Stop 4Q 2
H0 = 10 peak amplitude of the input square wave. Vp H0 = 10 ~0 = 2 $ r $ 10 4 rad/s 1 -f =110 kHzdz 4 $ Vp
S.No. Input Frequency Phase Magnitude 4Q 2
Phase Magnitude

~0 = 2 $ r $ 10 y _ trad
4
i =/ssin _100rt i + 0.1 sin _200rt i
H 0 = 10 dz 4 $ V p d ~ r $ H0 $ Q
The Band Stop filter’s output will carry all the harmonics of the Vp
y _ t i = sin _100r1t i + 0.1 sin _200rt i d~ r $ H 0 $ Q ~ = ~0
H0 = 10
~=V - 2~ Q0 = 2 $ r $ 10 rad/s
4
square wave, other than fundamental. This illustrates the application ~p0
of BSF as a distortion analyzer. y _ t i = sin _100rt i + 0.1 sin _200rt i ~0H40 rad
2 - 2Q~0 = 2 $ r $ 10 = 10 /s
y _ t i = sin _100rt i + 0.1 si
~0 H0 = 10 ~ 0
2 Frequency Response - Apply the sine wave input and obtain the magnitude 3
~0
H0 Q
and the phase response. H0 Q ~0 = 1 kHz
4 ~0 = 1 kHz Q=1
Q=1 ~0 = 10 kHz
Table 4-3: Frequency Response of a BSF with ~0 = 10 kHz , Q = 10
Q = 10 f = 1 kHz
Analog System Lab Kit PRO f = 1 kHz page 33
f = 10 kHz
f = 10 kHz 4 $ Vp
H0 Q ~0 = 1 kHz
~0
~0 = 1 kHz Q=1
H0 Q
Q=1 ~0 = 10 kHz
~0 = 1 kHz
~0 = 10 kHz Q = 10
4.5 Exercise Set 4
Q=1
Related Circuits
experiment 4
Q = 10 f = 1 kHz
~0 = 10 kHz
f = 1 kHz f = 10 kHz
Q = 10
1 Higher
f = 10 kHz
f = 1 kHz
order filters are normally 4 $ Vp designed by cascading second order filters
The circuit described in Figure 4.1 is a universal active filter circuit. While
and, ifp needed, one first- order r $ H0filter.
$ Q Design a third order Butterworth Lowpass
4$V this circuit can be built with OP-Amps, a specialized IC called UAF42 from
f=
r $ H10
Filter 0 $ QkHz
using FilterPro and Vp
obtain the frequency response as well as the
Vp 4 $ Vp response of the ~ $ r $ 10 rad/s Texas Instruments provides the functionality of the Universal Active Filter.
transient filter.
0 = 2The specifications are bandwidth of the filter
4
r $ H0 $ Q We encourage you to use this circuit and understand its function.

~0 = 2 $ r $ 10 4 rad/s and H0 = 10.
Vp
H0 = 10 y _ t i = sin _100rt i + 0.1 sin _200rt i Datasheet of UAF42 is available from http://www.ti.com.
~0 = 2 $ r $ 10 4 rad/s
2 y _
Design
t i = a
sin _100 r i+
notcht filter
0.1 _200rt i filter) to eliminate the 50Hz power
(band-stop
sin Also refer to the application notes [7], [11], and [12].
H0 = frequency.
life 10 In order to test this circuit, synthesize a waveform
y _ t i = sin _100rt i + 0.1 sin _200rt i Volts and use it as the input to the filter.
What output did you obtain?

Chapter 5
Experiment 5
Design of a self-tuned filter

Vyy l
V = V V cos z p p
RC V
V yyr # Vx 2V RC
0
Vrr # VxxRCK # V #KV +=pdV

r
av
V =RC V + KV#=V V+ K+#KV #+VK+#KV ## VV +
V rry # #VV V#+xxrVr Vp=+Vp + K # dVz+ K # V + K # V # V + p x offset y
x 0 xy x 0 yx yy 0 x y
pd
#
0 offset
p V = V +p K # V + K # V + V
V K y ## V
V K 0 offset x x y y 0 x
0
y
offset x x y y 0 x y
y r pd
Goal of the experiment p V through the low-pass V

V yyr ## V
V
p
experiment 5
V
After passing filter,
rr the high
z = 90 c
frequency component gets x
Vrr V
x
V V out and V only the average value x

filtered of output V remains. x y
RC V
V r = VV #V Vyy ~V Vr y av
The goal of this experiment is to learn the concept of tuning a filter. The idea V #VV V #V V0r0 =
V = V 0+ K # V
Vxxx # + K y V rr K
# + #V #V +p
r
y
x r x
y
0
V #V
is to adjust the RC time constants of the filter so that in phase response of V #VV# V V # V V
V 0 =
= V
VV xxp ##V pVl
V yy V V rr V r x y r
0 offset x x
r x
y y 0 x y
0 = VV pp V #pplV cos z (5.3)

y r
p V 0 ~ = V $ RC 0
c
a lowpass filter, the output phase w.r.t. input is exactly 90 at the incoming V V # V V V 00 = 2Vr cos z
ø
y r r
y r r
V2Vpp Vrrppll cos

V r
frequency. This principle is utilized in distortion analyzers and spectrum V d~ 1 ~

dVz
x 0 0
V =VV # V VV = V # V V V
V 0 =
0 = dV cos z = V RC = V r
r0 x y r
r
=2 V
0 x y c r c
analyzers, such self tuned filters are used to lock on to the fundamental V av
V = Vl # V V V V l K pd = 2VdV V=rravavV # VdzV y
0 x y r
V = V V cosVz = 2V cosVz# V K pd zavV V ldV

0 x y r
d
p p
frequency and harmonics of the input. dV (5.4) p p
0
2V V V l
cos z dV V # V K
pd
= VdV d=z av cos z
0
r p p
r r x
p p c
V = dV K pd = 2 V d z d z ~ 0
0
dz
2 V d
K pdpdpd Kd
pd av r
K = av y r
K = z= dV dV = d~ $ dV
r pd 0
dz dz pd
K = dV K
av
V av pd
c 0 c

r
K
zVpdpdphase c dzVVand= is measured
pd
K is called dzthe sensitivity of the K =V 90 90 detector + H in Volts/radians. pd pd 0 0
V =Vz Kc
= b1 + ~ Q + ~ l
c # s s 0 x y r 2
K
z = 90c z = 90 pd
pd i
V z l
Vavavcos
V
= z90
= zc c= is90used 2
2z
For 90 c 0 0
V z = 90c , V becomes V0.= This Vinformation to tune the~voltage controlled
p p
V b~ Q l
av 0
av r
r
av V
In order to design self-tuned filters and filter
~ V (VCF) automatically.
~ The voltage-controlled filter, along with phase detector, is av
K = dV V
V~ av z = tan 0
av 0 av -1 0
d~ d1 - b ~ ln
0
other analog systems in subsequent called a self-tuned filter. See Figure 5.2. of the VCF is given by
pd
~
av
z 00 ~ ~ 2
~ = V K
0 r
~ = V
0 c
c
experiments, we need to introduce ~
0
V $ RC VccV $ RCdzV 0 0
~ ~
V $ RCV 0 ~ = r r pd
c
d~ ~ = 1V $ RC c~0 = V
0 c 0
one more building block, the Analog d~~ 1
= V RCz==V90~
0
= = = V $ RC
c = - 2Q ~ 0 r
0 0 0 r
0
multiplier. The reader will benefit dV d~ V RC 1 V ~dV 0

0
V d~$VRC
r 1d~ ~ c c r c 0
rr Vcc=
0 0
= c 0 r
from viewing the recorded lecture at

dz dV
Therefore,
= dz
V RC = V
V ~
~ d~ ~0 =
0 = 0 V $ RC
dV 1 V RC dz ~ V
- 20Q V
0
av
c r c
dV== ~
r c
d
c
dV dz dV ~ 00 = V drrz$ RC 1 c
c =dVVr RCV = Vcc000

c 0 c
[21]. In ASLK RC PRO, we have used to Figure 5.1: Analog Multiplier
dz dV dz d~ dz dz d~ d dV
dV ~ V 1
RC = 0~ V
c
MPY634 analog
V = V multiplier
+ K # V from Texas dV =
$ dV = $ ~ = d V ~ c 0
c0
= r 1
dz r dz1 kHz = d~ 0
~ c c 0 0 c
c av
RC +K #
0 V +K #V #V +p offset
RC x dzd~ dz
x dV d~ d~ dV V d
$
y y $ RC
dV
ddV zz c
0 = V
dVVr RC =
r RC
x
$
d~ dV Vc
= y
V c
c 0 cc 0
0
0
c r 0
Instruments.
V = V +p K ReferV +to K Figure
# V + 5.1, K # which
V # V shows the symbol of an analog multiplier. V dV = d+ ~VH dV +dH~ 1 c ~ 0 00 0c 0 c
# RC p
+ RC + K # V s+VK=#sV # V s+ dV
b + lzcc
0 0 0
RC p =s V c = V Q +H c c
V = V + K # VV =
0 offset x x y y
V b1 +
0
+ H 1 l ~ dQz+ ~dV
x
dV d
d
y
z
RC =
0 offset x
i
x y y i 0 2x y
c
2
r c0 0
zb1Now Q0 ~ l
p V V = V + K # V +RC = +~ V
0 0 2
b1 + ~ + ~ ldV~ radians/sec/Volts.
K # V V+ = K V# V + #K V+ #p ~ $sQ $+ V s 2
Q zc +H
2
x 0 V + K # V + Kp# V # V + p
offset
The V
x
sensitivity s VCFsis
of
x y
dz
dV
y 0
dz 0
d~~ ~
offsetx yx x y y 0 x y 0 0 2 0 0 i 0 i
b~ Ql
i
V RCV 0 V = pV offset + K x # V x + K y # V y + K 0 # V
V = V p+ K # V + K # V + K # V # V + p x # V y + p (5.1)
b~ Ql
~ Q d
dV c = d $ d 0 0r
2
c
r 0 0
2
0 $ dV b~ c~ l
y 0
zzcd= ~
x
z =b tan ~
l
0
dz dddV
dV
d
offset
z ~ d dd
d ~ z
z
x
ddV ~
0 x y y 0 x yx
0 -1 0 r
V =VV# V+ K # V + K # V + z = tan 00 d ~ -1
d1 - b ~ ln d1 - b ~ ldV
r
V 0
dn~ dV
K # VV# V + p V = c$c 0 Q
z = tan$$ + H0
p
r
p x
~ cc0
V00 cc+=
y offset x 2
0 x x y
~~ Q y
dV 0 xx y y 2 0
z = tan =
H d d~ ~00 +dV
r 0 c
r
0 c -1
-cc00b ~ ln 2
-1
d1H
V # V p isV a#non-linear ~
dd1z- b ~ ln V = Vi =
where V term in V and V . For a precision multiplier, V # V and V
dV = dV 2
b11d~z+ 0+ s 2 l
0
r x y yr ~ x V 0 y r x 0
r
2
0 0
r
s s 22
b s 2200022 l
VxV V #isVthe referenceV voltageV #ofVthe multiplier. Hence, forV precision
V # V , Vwhere z 2Q ~ b1V s s
+l ~+
2
sH
0
d
y r x
r r x #V = - 2Q ~ d~ = - y
VV+00ii ~ Q +
=
r
+ x
H 0
+ ~
y r
0 i
0 2
b 1dz+ ~20QQV~+r ~022 ll

amplifiers, . d ~ d z = ~ =~ Q 0
0
~bQ
0 0
V V = VV # #V V V -s 2 Q ~ 0
Vr
V
0
V #V V #V yx yr
V r
dz d~ = - 2dQz ~ V ii b ~ d l s
0
00 Q ~s
0
~0bQ~rr ~
Q ll 0
y r x y r r 0
y = - 2 Q V 1 + + 0
r 0
b~
V = V #VV#VV = VV V l cos z V #V V rp p
V = V # V V dV = - 2Q VdV c c
0
0 x r y r
0x dz y z = tan r r 0 x y r c -1
dV = -
c
In Experiment 4, if we replace the integrator with a multiplier followed by integrator,
d1 - b ~ l-n1
2 V Q
= - 2V = 0 V
~~00 Q
c
r #
z = tan=--11 b ~0 r l2
VVVl# Vz V
r ~ 2
V V l cos z V =dV0
c
V = Vthe
b~ ~rlr22
cos p V xdV
py = V #V V r V V = V #V V
0 x y r av c
av rc
then circuit becomes a Voltage Controlled Filter (or a Voltage Controlled Phase
r 0 x y r p p
0
2V K = av V = V 0 r
- 1 d1 - b
~r0r220 llnn
av0 R11
dz z = tan
0
r
d=zV V l cos z
pd 2V V = 0 1 kHz
1 kHz av
V VV V l r
b~
V = V #VV self-tuned VF3
Q
d
K = dVVyK#
Generator). ThisV rforms2V the basic circuit for
p p
V = 2V cos zfilter. See Figure 5.2.dV The ~00 ~
C1 R5
r rp
Q
0 x y p
C2
av 0
- 2Q ~tan 1 kHz
z C3
0
Q 1 kHz Q d~ = z
1
pd K = r
=
= tan
-
1 -
av U1•U2 0
- bb ~
~r0 ln
outputdof Vz =theV self-tuned
# V V dV filter for a square-wave
pd
V V l r pd U1•U2
2Q V H $ Q $ d
input, including the control voltage
d z R10
ln
0 x y r 0 R3
dV1
p p
V = cos zdV Q R2
~
av
z K c = 2V Q H $ Q $ V 0
z av R1
VV=
K = 90 K = H $Q$V d
waveform,
pd V l cos zin
r isV shown dzFigure 5.3. The figure brings
p p
pd
dz out the aspect ofKautomatic
dV = - dz
r pd
1- pd 0 i 0
VF1
i
c U1•U2
R4
+
K = dVK ~
0
2VK H $Q$V V3
V = 0 dz = - 2Q ~0 0
0 i
= 90candVself-tuning.
av
z
control av r pd z = 90 c pd 0 0 i c
dz pd U3
V
K 0= ~= z =
dV V x # y V V r av
dd~ ~z = - 2Q ~0 U1
Uav
2
1 kHz dd
U4
V
dz 90c K z = 90c V z000 = - 2Q ~00
av pd 0
pd av
R8 R6 R9
5.1.1KVVMultiplier
~ 0
~ =VVp Vpl V pd
asza Phasez = 90cV Detector av c
~ Q dd~ ~zz00 = - 2Q ~0 av 0
= - 2Q Vc
0
0 =c ~
V $ RC cos r
R7
dV c = - 2Q Vcc
V $ RCd~ =2V1r = ~
z = 90 V ~ ~ = V
~ = z VF2
c 0 +
0
r
RCV V
0
V $ RC
0
av
H $ Q $ VdVd
dzcc = - 2Q Vc
0
0
c
VG1 0 i
V 1 dV ~ V ~ V r
d~the circuit
In of FiguredV
= Vav5.1,
av c
the output of the ~ = multiplier
00
is
r
d~ 1
c
~
c
0
V
dV
VdV av = =0- 2Q Vc c U5
av c= 0
0
$ RC
= V~K z
= 0
RCpd =V
d V $ RC 0 0
dV V
r
dV = V RC = V av c r
d=zV RC = V
c r0 c
dV d ~ 1 ~ ~ = ~ ~
c c r c
V $dRC 1
zd~ dV8 B
VavavkHz =0
_ i
0 0
=
11VFilter
0
dz c 0 0
~V=dz = VVdVpdz Vp$ld$~ cos z d~ cos dV = V RC = V

~
c
t z
c dz
(5.2)
r c
kHz
r
0 c r c
dV c
K0pddV=V $ dRC
2 V
0
- =
r
d
1
z = + ~ dV 0
Figure 5.2: A Self-Tuned 0
based on a Voltage Controlled Filter 0
c
dz ddz~ d~ dV
$ V= 1 =+~H
r dV
c V0
dV
RC V 0
dz dz d~
c
or Voltage
c
kHz
11QControlled
kHz Phase Generator
r c
dV = d~ z
dV dV=V90
= RC c V
0
0 dz
c
= d~ $ dV
0
0 Q c 0
b1 + ~ l
c
V d z 0c
ds z d ~s
c r
d z d z dV c 2 c 0 c
d ~
V 0 dz + H dV = d~ +
~ Q dV
$ i
dV 0 = $ V +H
0
2 c
Q
QH00 $$ Q Q $$ V Vii Analog System Lab Kit PRO 0
V = 36dV s z d~d~ dV
ddV H
b1 +V~ l
0 0
page =
c 2 0 0 c0
b l
s dz c 0 c
V =d~ b ~ Q sl
i
+V c
~ + H = $ V s s 0 i 0 i
2
av
Q ~ V
d~ =dV 0 + H 1 + + r 0
H0 $$ Q Q $$ V
2
dz dz 0
s
dV
V i s
0
-1 s 0
~Q ~ 0
2 c
H 0
i
0
Vi c
0
2 0 0
2
Vr # Vx zK= 90c V
Vy # Vr pd av
Vy # Vr z
V = 90 c ~ av 0
Vr # Vx ~V ~ = V 0av c
Vr ~ V
V $ RC 0
r
# Vrx # Vy Vr
0
V0y = Input~voltage
= V $ RC= d~ 1 ~ 0
c
experiment 5
0 0
V dV = V RC = V
r
V0 = Vx # Vy Vr S.No. Input Frequency ~ = c c r c
= V $ RC = VOutput Amplitude
d ~ 1 ~ 0
Vr Vp Vpl
0 0
dz r
V0 = Vp Vpl cos z d~ V RC
dV 1 ~ dV
c
0
r c
0
1 z = V RC = V
V00 =
V = V2 V#rr Vcosy Vr
z d dV
dz dz d~ c r c
c
V
2xdV dVdz
dV = d~ dV
$ c
0
av z
ddV dz d~ c 0 c
K pd =VpdV 2
K0pd== dVzpavl cos z
0
= $ V +H
c
dVdz d~ dz dV
0 0
V =
V $ dH~ b ~ Q+~ l
c 0 c
= s s 0 2
z
i
K pd 2 dV r
V dV= d~ dV + 1 + 0 c 0 0c 2
b1 + ~ + +~ l
3 VV s H s 2 0 0
b~ Ql
i
K dV ~ 0 0
V =
b l
pd av RC Q
s s
2
0 2
r
K pd =
~b Q
i
0
Ql
1
z = 90dcz V = V + K # V + K # V + K # V # V + p 4 + +
~ ~ z = tan 2 -1 0
d1 - b ~ ln
0 r 0
~ 2
z = 90c 0
RC
offset x x
z = tan
y
~~
b ~~Q l
y 0 x y
-1 0
r
r
Kavpd
V tan d1 - bwith ~~lninput frequency
0
p 0 r
2
V = V +K #V +K #V +K #V #V +p z =amplitude
Table 5.1: Variation of output dz -1
Vav x V
0 offset x x
d1 - b
y
l n
y
d
0
~ =-
x
2Q ~
y
0 2
r 0
~0= 90c V p
z dz
= - 2Q ~
~
dz
0
0
~0 y
V d~dz 2Q V
0
5.2 Specification dV = -
0 c
x
V # = - 2Q ~
av
~0 = Vc V # V Vr
c
V
V
V
y
x d z
d~
=- 2 Q V V =0
0
c
0
av
c
dVdz
~ V r $ RC V # V
c
Figure 5.3: Output~

0 = Vr $ RC
y
r
r
x V dV= =
0 - 2Q V 1 kHz c
dof~the Self-Tuned
1V VFilter based on simulation
0 av c
# V~0
r
0 Assume that the input frequency is 1 V kHz= and
0 design a high- Q Band pass filter
~c0 = VVrc1RC V ==
y r av
ddV V #~ V 0V
~ 0 ==
0
V= r V c
x y
whose
r
centre frequency gets tuned toQ1 kHz . H $Q$V 0 i
ddV zc Vr V$ rRC RCV =V V=VVV

l c p p
cos z
0
2V # V V
0
r
x y r HQ$ Q $ V 0 i
d~ zc 0 1K V==dVV~V0l cos z
dV avp H $Q$V
= pd
= dz2VV
0
p 0 i
ddV
dV dVzr RC
r
zcc then
If we consider the low-pass output, pdK d K~= 0 dV
c
av
dzc = dd~ z0z$ =ddV

$ K~
pd
dV 90cc0 dz
dVc d~0V dV=
c
pd
5.3.1 Transient response
V 0
av
+ zH =090c
dV0iz= dz ~+dsV~
Vi c==b1d+ V s 22 l
V 0 H s2
$ s 0+ Apply a square wave input and observe the amplitude of the Band Pass output for
b1 + ~0 QV + $ RC 2 l
av
dV ~ 0~
0~ 0= dV
~Q c 0 ~ 0
c
fundamental and its harmonics.
~
r
Vi = - 1 ddVzsbbd~~~V0 VQ r l
V0 d~ H
+~==~
0 1
0 r V 0 ~ 0
l
= V c
b 1 2l ~
RC
0
$ RC
c
s 2 r r c
z = tan - 1 ~ 1 + Q +
~0=QV~ 0
= V 5.4 What should you submit 0
d1 - b~ r $ ln
0 dV 2RC
z = tan dV c
~ c 0 r c
ddV1bdV db~~r0ldV
~d+z0 Hlnd~
r
d z d z d z
=~
d~
2 0
c - ~0 Q
c 0 c
zdz -1 V =
= tan V dV = d~s2 $ dV s
0 dz 1 Simulate the circuits and obtain the transient response of the system.
0 0
b10+~r + l
2Q V~=b0 ~~0 Ql~+ns H~ s
z0 = - 2dQ1 V-
2
~
dd~
i c 0 c
2
then = - 2 Take the plots of transient response from oscilloscope and compare it with
0 0 0 0
dd~ b1 +b ~ Q l+ l
2
i r
z 0
~ simulation results.
00
2
z =Vtan 0
z
-1
d
dzc = - 2 Q
d1 - bb~ ~ lQn l
c ~~ 2
dV =--22QQ zV~
= c 0
r r
3 Measure the output amplitude of the fundamental (Band Pass output) at

d
dV ~ 0 = tan -1 00
d1 - b ~ ln
Vav = 0 c
dz
2Q ~
~ varying input frequency at fixed input amplitude.
r
2
Vdavz= 0 d~ = -0
0
0
1dV kHz = - 2Qdz Vdzc

Hence, sensitivity of VCF(KVCF) cis equal to =2Q- 2VQ. ~ Output amplitude should remain constant for varying input frequency within
1 kHz dV d=~- c 0
c 0
V
Qav = 0 av V = dz0 the lock range of the system.
For varying input frequencyQ the output phasedV = - 2 Q V
will always lock to the input phase c
1 kHz c
1HkHz
with 90˚ phase difference between 0 $ Q the
$ VitwoQif V = 0. av
H0 $ Q $ Vi 1 kHz
Q 0 H $Q$V i
Analog System Lab Kit PRO Q page 37

H0 $ Q $ Vi H0 $ Q $ Vi
d1 - b ~r ln
~2
0
dz
2Q ~0
d~0 = -
5.4.1 Exercise Set 5

dz
2Q Vc
dVc = -
experiment 5
Vav = 0 Related Circuits

1 kHzself-tuned filter you designed. The lock range
Determine the lock range of1the
is defined as the range of input
Q frequencies where the amplitude of the output Texas Instruments also manufactures the following related ICs - Voltage-
voltage remains constant at H0 $ Q $ Vi controlled amplifiers (e.g. VCA820) and multiplying DAC (e.g. DAC7821).
Refer to http://www.ti.com for application notes.

Chapter 6
Experiment 6
Design a function generator and convert it to
Voltage-Controlled Oscillator/FM Generator

f = _1 4RC i $ _ R2 R1i
1kHz
! Vss 1 _R R i
4RC # 2 1
f = _1 4RC i $ _ R2 R1i Vc
experiment 6
Sensitivity of the VCO is the important parameter and is given as KVCO , where it is
given as ! Vss f l =
Vc $ R2 df
To understand a classic mixed mode circuit that uses two-bit A to D Converter 4
f = _1 4RC i $ _ R2 R1i
$ RC $ V r $ R1 dVc
1V
along with an analog integrator block. The architecture of the circuit is similar
Vc $ R2 df l R2 f
to that of a sigma delta converter. f l = K VCO =
4 $ RC $ Vr $ R1dVc = 4RC $ Vr V1 = Vc Hz Volts
1kHz (6.1)
=_4RC $2V V = Vc
r 1 i $ _ R2 R1i
df l R f 10kHz
KVCO = Hz Volts
fdV=c 1 4RC
where f = _1 4RC i $ _ R2 R1i
6.1 Brief theory and motivation 1kHz 1kHz
_ RMODEM.
2 R1i As a VCO, it can be used in Phase Locked Loop
VCO is an1important analog circuit as it is used in FSK/FM generation and constitutes
_ R12 R1i
4RC # part
the modulator of#the
The feedback loop is made up of a two-bit A/D converter (at ! Vss levels), also
4 RC
(PLL). ItVcis a basic building block forming sigma delta converter. It can also be used
called Schmitt trigger, and an integrator. The circuit is also known _1 a4RC
f = as i $ _ R2 R1i as reference
function Vc
KVCO oscillator for a Class D amplifier.
generator and is shown in Figure 6.1. The output of the function generator Vc $ R2 is df
shown in Figure 6.2.
fl =
4 $ RC $ Vr $ R1 dVc KVCO
df l R f V
1
KVCO =
dV = 4RC $2V V = Vc Hz Volts
1kHz
df
The function generator produces a square wave at the Schmitt Trigger output c
and r 1
! Vss f = _1 4RC i $ _ R2 R1i 10kHz dVc
a triangular wave at the integrator output with the frequency of oscillation equal
to f = _1 4RC i $ _ R2 R1i . The function generator circuit can be converted as a linear
kHz 1V
1
VCOf lby using the
V $R multiplier integrator combination as shown in Figure1 _R R i
6.3.
= 4 $ RCc $ V2 $ R
r 1
4RC # 2 1 1kHz
df l R2 f V c
KVCO = Hz Volts 10kHz
dVc = 4RC $ Vr V1 = Vc KVCO
f = _1 4RC i $ _ R2 R1i df
1kHz VG dVc
1V
1 _R R i C
4RC # 2 1
+
1kHz
Vc 10kHz
R
KVCO U 1•U2
VF1
10
df VF2
dVc
1V R1 U1 R2 Figure 6.2: Function Generator Output
U2
1kHz
10kHz
6.2 Specifications
Figure 6.1: Function Generator Design of a function generator which can generate square and triangular wave for
a frequency of 1 kHz. ! Vss
f = _1 4RC i $ _ R2 R1i
! Vss 6.3 Measurements to be takenfl = Vc $ R2
4 $ RC $ Vr $ R1
f = _1 4RC i $ _ R2 R1i
The frequency of oscillation of the VCO becomes df l R2 f
K = Hz Volts
dVc = 4of
Determine the frequency ofVCOoscillations $ Vr V1 =and
RCsquare Vc triangular wave. Frequency of
Vc $ R2 oscillation should be equalfto= _1 4RC i $ _ R2 R1i . Convert the function generator into a
fl = Voltage Controlled Oscillator
1kHz(VCO) or FM/FSK generator also called “mod of modem.”
4 $ RC $ Vr $ R1
1 _R R i
df l R2 f 4RC # 2 1
page 40 KVCO = = = Hz Volts Vc Analog System Lab Kit PRO
dVc 4RC $ Vr V1 Vc
KVCO
6.4 What should you submit
experiment 6
1 Simulate the circuits and obtain the Transient response of the system.
C
R2
R1
VC R1
! Vss
f = _1 4RC i $ _ R2 R1i
fl = Vc $ R2
4 $ RC $ Vr $ R1
df l R2 f
Figure
K VCO = 6.3:
dVc =Voltage-Controlled
4RC $ Vr V1 = Vc
Hz Oscillator
Volts (VCO)
f = _1 4RC i $ _ R2 R1i
2 1
Take the plots kHzof time response from oscilloscope and compare it with
simulation results.
1 _R R i
4RC # 2 1
Vc
3 Vary the control voltage of the VCO and see the effect on the frequency of
KVCO
the output waveform also measure the sensitivity (KVCO) of the VCO which is
nothing but df . Use Table 6.1 to note your readings.
dVc
1V
1kHz
S.No. Control Voltage (Vc)
10kHz Change in Frequency
Table 6.1: Change in frequency as a function of Control Voltage
6.5 Exercise Set 6

Apply 1V, 1kHz square wave over 2V DC and observe the FSK for a VCO which is
designed for 10kHz frequency.

experiment 6

Chapter 7
Experiment 7
Design of a Phase Lock Loop (PLL)

Vc dVc ~=
Vc V
~ =
KVCO 4Vr $ RC d~ ~ = Vc c dVc
4Vr $ RC V dV 4
V $ RC
rV$r RC
~= d c
~ V c V
d~ Vc 4Vr $ RC= c
~ dV ~c Vc ~ = 4V $ cRC
dVc = Vr $ RC d~
dVc Vr $ RC
Vc
=
dVc Vr $ RC
r
d~ Vc
~
~= Vc Vc dVc = V~r $ RC Vc KVCO
~ = Vc ~ Vc dVc = Vr $ RC
4Vr $ RC
Goal of the experiment KVCO = no ~ Vc ~ Vc KVCO = ~ Vc ~0Q
experiment 7
When
d~ Vinput
c voltage is applied to the K VCO = ~ the
system, Vc system oscillates~atVthe c
free
~
dV = V $ RC K ~
VCO = ~ Vc V K
running frequency of the VCO, given by
0Qc r
0 Q CQ
~ 0 Q with corresponding control voltage VCO = ~ Vof c
~CQ Vc ~ V K V
The goal of this experiment is to make you aware of the functionality of V . If the input is applied to the system Vwith
0Q CQ VCO 0
CQ the same frequency as ~ 0Q , the PLL
the Phase Lock Loop commonly referred to as PLL which is primarily used K0VCO continue
will
V = ~ Vc to run VCQ at theV0 free running d~frequency
Vi V and the phase differenceVCQ between
0
the
~i 0Q two signals V0 and Vi as 90˚ since dVc Vref is 0 (already explained in Experiment 5
for a frequency synthesizer in high frequency stable clock generators. From V Vi Vc V0
a crystal of some kHz range, it is possible to generate waveform of GHz of
Vref
VCQ Chapter 6). As the
Vi frequency
Vref of input
~ = 4signal
V $ r is changed, the control Vvoltage
RC will
KV # 2 # A0 # KVCO
r
pdref i
frequency range using a PLL. change

V0 correspondingly, so as to lock
d~ the output Vc frequency to the input frequency.
r
K pd a# result, A there
Vref K pd # r # A0 #
KVCO is a change = V $ RC
dVKc VCO K pdr # r # Abetween
Vref
As
Vi 2 # 0# r
2 of phase difference 2 0 # KVCO the two signals away
K pd #of input A KVCO ~ Vc for which output frequenciesKgets r
from 90˚. The range
Vref 2 # 0 #frequencies pd # locked A K
2 # 0 # VCO
to the input is called the lock range of=the
KVCO ~ system.
Vc The lock range is defined as
7.1 Brief theory and motivation K pd # r # A0 # KVCO on either side of ~0Q .
2
VCQ
KVCO in experiment number 5 if we replace the

In the loop of self-tuned filter studied 7.2 Specifications Vi
V0
Voltage Control Filter (VCF) with Voltage Control Oscillator (VCO) (discussed KVCO in
d~ Vref
experiment 6) then it becomes PLL as K shown in Figure 7.1. The readerKwill d~benefit Design a PLL to get locked to frequency of 1 kHz.
dV c VCO
from viewing the recorded lecture at [22].
VCO
d~ dVc K pd # r # A0 # KVCO
d~ K U4 2
~ =dVc
Vc VCO
dVc ~ = Vc R4 C2
VF3
V1
4cVr $ RC U4
+
d ~ V C
4=V r $Vis
RC + 2
The sensitivity of the PLL is given by K~VCO and c equal to
R4 VF3
dVc , where =d~ ,
~ C1
VG1
4V=r $ RCVc
4 Vr $ RC +
d~ dd~~ VVcc ~=
Vc d~ dVc VV c r $ RC C1 +
frequency of oscillation of VCO. Hence dV= c =
dVc dVc VrVVr$c$RC RC , which is nothing
4Vr $ RCbut
dV = Vc $ RC
c~ V r
VG1
R5
U3
V1
d~ Vc ~ VKc VCO = ~ Vc R1
~ ~ =Vc4Vr $ RC = V $ RC R5 U3 -
R
~ Vc dV c r
KVCO~= ~ Vc +
V2
1
VF2
R2
-
dK~VCO = ~VcVc ~ Vc 0 Q + U1 VF2 R2

= V $ RC + + U2
KVCO~dV
~=
c
0Q
Vc
~ r
Vc K VCO = ~ Vc
~0Q VCQ (7.1) V2
U2
VCQ VCQ V0 R3
VF1
~0Q U1 VF1
~0Q KVVCO = ~ Vc V0 Vi R3
0
~0Q Voltage
VCQ
Vc Control Vi Vref
VCQ V V i V0
(Output)
CQ
Vref
VO
VrefR Vi K pd # r # A0 # KVCO
VCO V0 V 0
r
2
K pd # r # A0 # KVCO
VKi pd # 2 # A0 # KVCO Vref 2
VI
Vi V
ref
C
K pd # r # A0 # KVCO
10.00
2
Input Frequency r
Vref K pd # 2
W(Input)
# A0 #Vref=0
KVCO
5.00
r
K pd # A K
2 # 0 # VCO
Output
0.00
-5.00
-10.00
0.00 10.00m 20.00m 30.00m
Time (s)
Figure 7.1: Phase Locked Loop (PLL) and its characteristics Figure 7.2: Sample output waveform for the Phase Locked Loop (PLL) Experiment

7.3 Measurements to be taken 7.5 Exercise Set 7
experiment 7
1 Measure the lock range of the system and measure the change in the phase of Design a Frequency Synthesizer to generate a waveform of 1MHz frequency from a
the output signal as input frequency is varied within the lock range. 100kHz crystal as shown in Figure 7.3.
2 Vary the input frequency and obtain the change in the control voltage and plot
the output. A sample output characteristic of the PLL is shown in Figure 7.2.
7.4 What you should submit

Figure 7.3: Block Diagram of Frequency Optimizer
1 Simulate the circuits and obtain the characteristics of the system.
2 Take the plots of characteristics from oscilloscope and compare it with

simulation results.
3 Measure the change in the phase of the output signal as input frequency is
varied within the lock range.
4 Vary the input frequency and obtain the change in the control voltage. Use
Table 7.2 to record your readings.
S.No. Input Frequency Output Phase
Table 7.2: Control Voltage as a function of Input Frequency
S.No. Input Frequency Control Voltage
Table 7.1: Output Phase as a function of Input Frequency

experiment 7

Chapter 8
Experiment 8
Automatic Gain Control (AGC) Automatic Volume
Control (AVC)

Goal of the experiment 8.3 Measurements to be taken
experiment 8
In the front-end electronics of a system, we may require that the gain of the Transfer Characteristics - Plot the input versus output characteristics for the AGC/AVC.
amplifier be adjustable, since the amplitude of the input keeps varying. Such
a system can be designed using feedback. This experiment demonstrates
one such system. 8.4 What you should submit
1 Simulate the circuit of Figure 8.1 and obtain the Transfer Characteristic of the
system. Assume that the input comes from a function generator; use a sine
8.1 Brief theory and motivation wave input of a single frequency.
2 Build the circuit shown on Figure 8.1. Plot/print the transfer characteristic
The reader will benefit from the recorded lectures at [25]. Another useful reference using the oscilloscope and compare it with simulation results.
is the application note on Automatic Level Controller for Speech Signals using PID
Controllers [2].
In the signal chain of an electronic system, the output of the sensor can vary
depending on the strength of the input. To adapt to wide variations in the magnitude
of the input, we can design an amplifier whose gain can be adjusted dynamically.
This is possible when the input signal has a narrow bandwidth and the control
system is called Automatic Gain Control or AGC. Since we may wish to maintain the
output voltage of the amplifier at a constant level, we also use the term Automatic
Volume Control (AVC). Figure 8.1 shows an AGC circuit. The typical I/O characteristics
of AGC/AVC circuit is shown in Figure 8.2. As shown in Figure 8.2, 2the
Vr Voutput
ref value
of the system remains constant at 2Vr Vref beyond input voltage Vpi = 2Vr Vref .
Vpi = 2Vr Vref Figure 8.2: Input-Output Characteristics of AGC/AVC
S.No. Input Voltage Output Voltage

]
] VC
Vpi•sinωt
]
2
VI =Vpi•sinωt VR ] VC•Vpi 1
1
R VR VR
VC 2
C
2
Vref=
VOP 3
2VR
4
Figure 8.1: Automatic Gain Control (AGC)/Automatic Volume Control (AVC)
Table 8.1: Transfer characteristic of the AGC circuit
3 Plot the output as a function of input voltage. Enter sufficient number of
8.2 Specification readings in Table 8.2. Does the output remain constant as the magnitude of
the input is increased? Beyond what value of the input voltage does the gain
begin to stabilize? We have included sample output waveform for the AGC
Design AGC/AVC system to maintain the peak amplitude of the sine wave at 2V. circuit in Figure 8.3.

experiment 8
R3 VF2 R4 Notes on Experiment 8:
+ C1
V2
U1 U2
R1
VF1
VXVY VXVY R2
+
10 10
VG1
+ V1
Figure 8.3: AGC circuit and its output
8.5 Exercise Set 8

Determine the lock range for the AGC, which is defined as the range of input values
for which output voltage remains constant.

experiment 8

Chapter 9
Experiment 9
DC-DC Converter

_1 _1 V-ref VrefVpiVpi
T = T = 2 2-
T T
T =T 1= 1f f Vp
Vav Vav f
experiment 9
between ! V !
ss V ss depending upon the value of ref . Hence circuit becomes SMPS system
V
where Vav V=av - Vp
=V-ref V$ refVss$ VVssp .Vp x
=
1 _1 V V i
- ref p
The goal of the experiment is to design a high-efficient DC-DC converter using x x T 2 f
Vref Vref T
a general purpose OP-Amp and a comparator and study its characteristics. If we replace LC filter with MOSFET, and apply audio input as ref to the comparator
T T V
T T of the MOSFET amplified audio
atxoutput
x T = 1 output
f
= 2 _1 - Vref Vpi
We also aim to study the characteristics of a DC-DC converter IC, and for then is obtained,
x 1 this is Class D
this purpose we selected the wide-input non synchronous buck DC/DC Power Amplifier operation. V av T
T
controller TPS40200 from Texas Instruments. This IC is included in ASLK ! Vss
PRO as evaluation module. T =1 f
Vav = - Vref $ Vss Vp
9.2 Specifications x
T
Vref
Vav
! Vss
x T Vp Vav = - Vref $ Vss Vp

Design a DC-DC converter which has 10 kHz oscillator whose ftriangular x wave output
with peak amplitude Vp is fed to a comparator whose otherVrefinput Vref is connected to
T
Vref (reference voltage). x T
T = 2 _ - ref pi
x 1 1 V V
The reader will benefit from viewing the recorded lecture at [24]. Also refer to the T
application note, Design Considerations for Class-D Audio Power Amplifiers [15].
Vp
9.3 Measurements to be taken T =1 f
Vav
Function generator
f Vp is the basic block for DC-DC converter. VThe p Vp
triangular output Vp
! Vss
of the function Vp
Vref f generator with peak amplitude Vp and frequency f f is fed to the
9.3.1 Time response f
comparator f
x whose 1 _1 other input is connected to the reference voltage
Vref Vref.
Vref The output Vref
i
V f
V V x
T =2 -
ref
of this comparator is the PWM (Pulse width modulation) waveform 1whose 1duty cycle Obtain the time response x of 1 _the system and plot Vref versus T Vref .
_1x -=Vref pi Vref Vpi ref Vpi
ref p
_
Vref x
T = 2 _ - ref pi , where T is time xperiod
x 1 = 1V- = 1 - V
is given by 1 _1of triangular
2 T wave 2 and is
T = 2 _ - ref pi
T 1 V V T T 2 x 1 1 xV T V
= - VTref Vpi T V T
equal to T =T1 f . This duty cycle is directly proportional T 2 to reference voltage Vref. p
If we connect
Vav Tthe = 1lossless
f low-pass filter (LC filter)
T at the output T = 1offTthe = 1comparator
f 9.3.2 Transfer function
f T =1 f T
as shown !inVFigure 9.1, it is possible to get stable DC voltage
T =1 f V av withV high
av efficiency Obtain the V ref versus Vav characteristics. T =1 f
ssVav
T = 2 _ - ref pi
Vav ! Vss ! Vss x 1 1 !VVss V Vav
Vav = !-VssVref $ Vss Vp
! Vss Vav = - Vref $ V-
av = ss Vref
p $ Vss Vp Vav = - Vref $ Vss Vp ! Vss
x Vav = - Vref $ Vss Vp T
V Vav = - Vref $ Vss Vp
T ref Vav = - Vref $ Vxss VVrefp x V x
x Tx Vref T =1 f V
T T ref
T ref x
T x Vav Vref
Vref x T x T x T T
x T T
x T ! Vss x T
x
+VSS Vref
Function
T
L x T
Generator Vg VO
Vav
-VSS C RL
Vref
Figure 9.1: DC-DC Converter and PWM waveform

9.4 What should Vyou submit
experiment 9
VF1 L R1
VF2
p +
VG1
1 Simulate the circuits and obtain the
f time response and transfer characteristics U2
of the system. Vref
T = 2 _ and
x 1 1 V Vi
- ref p
2 Take the plots of transfer characteristics time response from oscilloscope R3 R4 C1 R2
T
and compare it with simulation results. Vp
T =1 f f
3 Plot the average output voltage Vav as a function of reference voltage Vref and
Vp
obtain the plot; the plot will be linear. Vp
T = 2 _ - ref pi
! Vss x 1 1 V V
f f
U1
4 Plot the duty cycle Vref as a function x
of reference voltage Vref and obtain T the
+
Vrefincluded the typical output waveform
T = 29.2- refx Tpi
1 _1We V
plot, the plot will be xlinear. have 1 1 VT =V1off V2
T = 2 _ - Vrefav pi
TV x
the SMPS circuit in Figure
T T
! Vss
T =1 f
S.No. Reference Voltage OutputTVoltage
= 1Vp f Vav = - Vref $ Vss Vp
Vav Vav f
x
1 ! Vss ! Vss Vref
V
T ref Figure 9.2: (a) SMPS Circuit (b) Output Waveforms
x T
_1 - Vref Vpi
Vav = - Vref $ Vss Vp Vav = -x Vref 1$ Vss Vp
2 T = 2
x x
V V
T ref T ref T
3 x T x T T =1 f
Vav
4
! Vss
- Vref $ Vss Vp
Vav =converter
Table 9.1: Variation of output voltage with reference voltage in a DC-DC
x
Vref
T
S.No. Reference Voltage Duty Cycle x T
Table 9.2: Variation of duty cycle with reference voltage in a DC-DC converter
9.5 Exercise Set 9

Perform the same experiment with the specialized IC for DC-DC converter from
Texas Instrument TPS40200 and compare the characteristics of both systems.

experiment 9

Chapter 10
Experiment 10
Design a Low Dropout (LDO) regulator

Goal of the experiment 10.3 Measurements to be taken
experiment 10
The goal of this experiment is to design a Low Dropout regulator using 1 V0 = Vref _1 +
Output Characteristics R2 R1i the load regulation of the system. Load regulation
- Measure
general purpose OP-Amp and PMOS and study its characteristics with is given by dV0 V0 when Io is varying from minimum to maximum value.
extension to study characteristics of TPS7250 IC. We aim to design a V0 V0 = Vref _1 + R2 R1i
linear voltage regulator with high efficiency which is used in low noise high 2 V0
dV0= V ref _
Transfer Characteristics1 + -R 20 RV1i0 the line regulation of the system. Line regulation
Measure
dV
efficiency applications. is given by dV
dI0 0V when V0 is varying from minimum to maximum value.
V0 dV0 V0 = Vref _1 + R2 R1i
3 Measure thedVripple
0
rejection
dI0 by applying the ripple input voltage and measuring
dV0 V0
the output ripple
dI0 voltage.
10.1 Brief theory and motivation dV
V0
4 Measure the output impedance of the LDO, which is given by dI 0 . We have shown
0
the sample output of load regulation and line regulation in Figure 10.2.
LDO is used to produce regulated voltage for high efficiency low noise applications.
Please view the recorded lectures at [23] for a detailed description of voltage
regulators. In case of DC-DC converter switching takes place (as shown by PWM S.No. Reference Voltage Output Voltage
waveform) and switching is a source of noise but in LDO no switching takes place
1
hence it is used as voltage regulator in low noise high efficient systems. As shown
in the circuit below LDO uses PMOS along with OP-Amp so that power dissipation in
2
OP-Amp is minimal and efficiency is high. The regulated output voltage is given by
V0 = Vref _1 + R2 R1i.
3
dV0 V0 VUN
+
V0 4
dV0
dI0
Table 10.1: Variation of Load Regulation with Load Current in an LDO
R
Vref
R2 10k
VF1
R 10k
R2 R6 10k
R2
VO = Vref [1+ ]
R1
R4 10k R5 2k
R1 RL Z1
+
V1
D1
R3 10k
Figure 10.1: Low Dropout Regulator (LDO)
10.2 Specifications
Figure 10.2: A regulator circuit and its simulated
Generate 3V output when input voltage is varying from 4V to 5V.
outputs - line regulation and load regulation

experiment 10
2 Take the plots of output characteristics, transfer characteristics and ripple rejection
from the Oscilloscope and compare it with simulation results.
3 Obtain the Load Regulation - Vary the load such that load current varies and obtain
the output voltage, see the point till where output voltage remains constant.
After that output will fall as the load current increases.
4 Obtain the Ripple Rejection - Apply the input ripple voltage and see the output
ripple voltage, with the input ripple voltage output ripple voltage will rise.
5 Obtain the Line Regulation - Vary the input voltage and plot the output voltage as
a function of the input voltage. Until the input reaches a certain value, the output
voltage remains constant; after this point, the output voltage will rise as the input
voltage is increased.
6 Calculate the output impedance.
Input resistance (ohms) S.No. Input Voltage Line Regulation
S.No. Ripple Input Voltage Ripple Output Voltage
4
Input voltage (V)
Figure 10.3: Variation of Line Regulation with Input Voltage in an LDO
10.4 What should you submit 10.5 Exercise Set 10

1 Simulate the circuits and compute the output characteristics, transfer Perform the same experiment with the specialized IC for LDO from Texas Instrument
characteristics, and ripple rejection. TPS7250 and compare the characteristics of both systems.

experiment 10

Chapter 11
Experiment 11
To study the parameters of an LDO integrated circuit

experiment 11
The regulator can be enabled/disabled using the ON/OFF jumper JP7. The “Enable”
pin (EN) must never be left floating. Connecting a shorting jumper wire between pins
The ASLK Pro kit includes an on-board voltage regulator evaluation module 1 (GND) and pin 2 (EN) of JP7 enables the regulator. Connecting a jumper wire between
TPS7250. The goal of this experiment is to study the parameters of the pins 2 (EN) and pin 3 (VIN) disables the regulator. Output voltage is available on screw
Low Dropout Regulator (LDO) IC TPS7250 from Texas Instruments using terminal CN4, or Vout pin header, and the typical load current is 200mA.
the on-board evaluation module.
11.2 Specifications
11.1 Brief theory and motivation To study the parameters (Line regulation, Load regulation) of LDO TPS7250 using the
on-board evaluation module.
TPS7250 evaluation module helps us evaluate the operation and performance of
the TPS7250 family of linear regulators. The linear regulator TPS7250 from Texas
Instruments is capable of 200mA output current at 5V fixed output voltage level.
It is a low quiescent current, low noise, high PSRR, fast start-up LDO with excellent
line and transient response. See Figure 11.1 for the schematic diagram of the
evaluation module. 1 Obtain the Line Regulation: Vary the input voltage (from 5.5V to 11V in steps of
0.5V) and plot the output voltage as the function of the input voltage for a fixed
The input supply voltage VIN is fed at screw terminal CN3 and falls in the range output load.
5.5V to 11V. The leads to the input supply must be as short as possible and must
be twisted to reduce EMI transmission. The capacitor C102 improves the transient 2 Obtain the Load Regulation: Vary the load (within the permissible limits) such that
response of the regulator. The capacitor C101 helps to reduce the ringing on input load current varies and obtain the output voltage for a fixed input voltage. Plot
when supply wires are too long. the output voltage as function of the load current.
HD118
VOUT
CN4
@250mA
VOUT 5 V
OUT OUT
VOUT
IC1
R4 R101 GND
C103
4K7 247K 1 8
SENSE OUT 10uF
VCC+10 HD117
TPS7250
2 7 VIN
LD4 PG OUT JP6
CN3
VIN 5.5 -10 V

3 6 IN
GND IN
REG IN
VIN
4 5
EN IN
C101 C102
GND
1u F 100nF
HD116
GND
JP7
ENABLE OFF
ON
Figure 11.1: Schematic diagram of on-board evaluation module

11.4 What should you submit?
experiment 11
1 Simulate the circuit using a simulator such as PSPICE Capture (version 15.7 or 2 Vary the input voltage for constant load and observe the output voltage. Use
higher) or Cadence 16.0. The typical characteristics will be of the form as shown Table 11-1 for taking the readings for line regulation.
in Figure 11-2(a) and Figure 11-2(b).
S.No. Input voltage (VIN) Output voltage (VOUT)

1.8032V
1
1.8028V 3
VOUT 4
Table 11.1: Line regulation

1.8024V
3 Vary the load so that load current varies; observe the output voltage for
constant input voltage. Use Table 11-2 for taking the readings for load
regulation.
1.8020V
3.0V 3.5V 4.0V 4.5V 5.0V 5.5V
S.No. Load current (IOUT) Output voltage(VOUT)
VIN
1
Figure 11.2(a): Line regulation
2
1.8040V
4
VOUT
Table 11-.2: Load regulation
1.8035V
1.8030V
21.5mA 30.0mA 40.0mA 50.0mA 60.0mA 70.0mA
IOUT
Figure 11.2(b): Load regulation

experiment 11

Chapter 12
Experiment 12
To study the parameters of a DC-DC Converter using
on-board Evaluation module

experiment 12
P–channel Power FET and Schottky diode to produce a low cost buck converter. The
regulated output of the EVM is resistance-selected and can be adjusted within the
The goal of the experiment is to configure the on-board evaluation module limited range by making the changes in the feedback loop, as shown below.
TPS40200 on the ASLK PRO Kit as a switched mode power supply that
can provide a regulated output voltage of 5V or 3.3V for an input whose
range is 6V-15V. Vout = Vref
b
Vref = 0.7V
R209
12.1 Brief theory and motivation V =V b =
b
V = 0.7V
R209 + R207
out
ref
R
Vout = Vin $ duty cycle
ref
The TPS40200 evaluation module included on ASLK PRO. Kit uses the TPS40200 The feedback factor b = can
R +changed
be R by changing feedback resistance R209 to
209
non synchronous buck converter to provide a resistor-selected, 3.3V or 5V output that adjust the output. ButVin =
ASLK TP 209 207
V $ duty cycle not have the provision of changing R209.

PRO, we
205 do out in
delivers up to 2.5A from up to 16V input bus. See Figure 12-1 for a schematic diagram We can therefore achieve this task by connecting an external resistance of suitable
of the EVM. The evaluation module operates from a single supply and uses the single
TP TP207 the ground.
value between the terminals TP8 and
205
TP 207
1MX 1MX
R R209 209
HD142 VCC+10 TP1 TP 208
Vin JP9
HD122
J TP208 201
CN5
VIN 6 – 15V
VIN
TP
DC/DC IN J201 203
C201 C203 C204 R202 TP 204

HD120 220uF TP3 220nF 220nF 0.03
VIN
TP2
R201
100K HD121 C205 R203
R TP203 201
U4 1K
SRC
470pF C
RC 1
RC VDD
8
TP204 213
TPS40200
4
SS 2 7 ISNS
SS ISNS
R204 Q101
COMP 3
COMP DRV
6 DRV GATE 3 FDC5614P R201
0E
4 5
FB GND
1
2
5
6
C213
470pF
R210
1M
C214
470nF
C208
100nF TP4
HD126
C213 TP5
HD128
HD143
VOUT
DRAIN
VOUT 3.3V or 5V
R 205 CN6
@ 0.125 – 2.5A
100K L201
VOUT
33uH
C207 C202
R3
33pF 68pF
D201 4K7
C209 C210 C211 C212 VOUT
MBRS340
TP6 R 206 TP7 330uF 330uF 10uF 10uF
C206
25.5E LD3
4.7nF
HD124 HD127
FB
TP8 TP9
HD123 HD125
JP8
R207 R208
3.3V
5V
100K 49.9
R211 R209
41K2 27K4
Figure 12.1: Schematic of the on-board EVM

What should be the value of the external 12.4 What should you submit?
experiment 12
resistance for the regulated output of 5V?
The unregulated input is connected at screw terminal CN5. Output load is connected 1 What should be the value of the external resistance to be connected between
Vout = Vref waveform can be observed at the terminal
to screw terminal at CN6.The switching TP8 and Ground to configure the evaluation module to generate regulated
b
TP4.The evaluation module has a switching frequency of 200 kHz. This frequency output voltage of 5V?
is decided by the combination of R201 and C213. The duty cycle of thisVwaveform
Vref = 0.7V Vout = ref
varies linearly with the input voltage for a constant output voltage, bas shown 2 Simulate the configured circuit using a simulator. The typical waveforms will
below.
b=
R209 Vref = 0.7V be of the form shown in Figure 12.2.
R209 + R207 b=
R209
R209 + R207
1.00
Vout = Vin $ duty cycle Vout = Vin $ duty cycle
TP205 TP3
TP205
The output ripple voltage can be measured across terminals TP5 and TP7 by simply
TP207
0.00
TP207
placing the oscilloscope probes. The oscilloscope must be set for 1M X impedance, 20.00
AC coupling. The same terminals can be used for the measurement Rof209the regulated TP4
1MX
output DC voltage using a voltmeter. TP208
-10.00
R209 J201 10.00
TP203
12.2 Specifications TP208 TP204
Vin
J201 R201 10.00

5.01
In this experiment, we wish to study the line and load regulation for the TPS40200
C213
integrated circuit when it isTP
configured
203 to generate a 5V DC output. Vout
TP204 4.98
10.00m 10.02m 10.05m 10.07m 10.10m
R201
12.3 Measurements
C213 to be taken Figure 12.2: Simulation waveforms - TP3 is the PWM waveform
and TP4 is the switching waveform
Configure the on board evaluation module to generate constant 5V DC output by
making the changes in the feedback path using the available terminals.
3 Configure the on board evaluation module to generate a regulated output
1 Obtain the Line Regulation: Vary the input voltage from 10V to 15V in steps voltage of 5V, and observe the waveforms mentioned in Figure 12.2 and
of 0.5V and plot the output voltage as the function of the input voltage for a compare with the simulation results.
constant output load.
4 Vary the input voltage for a regulated output voltage of 5V and observe the
2 Obtain the Load Regulation: Vary the load (within the permissible limits) such change in the duty cycle of the PWM waveform. Use Table 12.1 to record the
that load current varies and obtain the output voltage for constant input readings. Compare the readings with simulation results and plot the graph
voltage. Plot the output voltage as a function of the load current. between the input voltage and duty cycle. Is the plot linear?

S.No. Input voltage (Vin) Duty cycle
experiment 12
1 Notes on Experiment 12:

2
Table 12.1: Variation of the duty cycle of PWM waveform with input voltage
5 Vary the input voltage for a fixed load and observe the output voltage. Use
Table 12.2 for taking the readings for line regulation
S.No. Input voltage (Vin) Output voltage (Vout)
Table 12.2: Line regulation
6 Vary the load so that load current varies; observe the output voltage for a
fixed input voltage. Use Table 12.3 for taking the readings.
S.No. Load current Output voltage (Vout)
Table 12.3: Load regulation

Chapter 13
Experiment 13
Design of a Digitally Controlled Gain Stage Amplifier

Goal of the experiment 13.2 Specifications
experiment 13
The goal of the experiment is to design a negative feedback amplifier whose To study the variation in gain when the bit pattern applied to the input of the DAC is
gain is digitally controlled using a multiplying DAC. changed.
_ A11 A10 ... A0i _ A11 A10 ... A0i

Vout = Vin $ R2 $ 114096
R1 Vout = Vin $ R2 $ 114096
13.1 Brief theory and motivation / An 2 n R1
0
/ An 2 n
0
Apply a 100 Hz sine waveVinof 100mV peak amplitude at Vin and measure the output
More and more, we see the trend of using Digital Signal Processors and/or voltage amplitude. Select R2 R1 to be 2.2. Vary the input bit
R2 pattern
R1 _ A11 A10 ... A0i and
Microcontrollers to control the behavior of the front-end signal conditioning circuits measure the amplitude of the output voltage. Vout = Vin $ R2 $ 114096
R1
in an instrumentation or RF system. Examples of such systems are Automatic Gain / An 2 n
Control system and Automatic Voltage Control systems. In this experiment, we will 0
demonstrate the use of a multiplying DAC to control the gain of a programmable gain
amplifier; we include an exercise at the end of this chapter to illustrate the use of a
13.4 What should you submit? Vin
R2 R1
microcontroller for controlling the gain of a programmable gain amplifier.
1 The circuit of Figure 13.1 cannot be directly simulated, since the macro-model for
See Figure 13.1 for the circuit of an inverting amplifier; the gain of this amplifier DAC7821 is not available at the time of writing. For the purpose of simulation,
can be digitally controlled by changing the bit pattern presented to the input of the we will use the macro model of a different 12-bit DAC, the MV95308. Simulate
multiplying DAC, DAC7821. the circuit schematic shown in Figure 13.2, which is equivalent to the circuit
of Figure 13.1. Observe the output waveforms for different bit patterns. The
typical simulation waveforms are of the form shown in Figure 13.3.
VDD
Use the circuit shown in Figure 13.1 for practical implementation of the Digital
C1 2 programmable gain stage amplifier.
RFB VDD
IOUT1
R2 DAC7821 VREF Apply the sine wave of fixed amplitude and vary the bit pattern, as shown
TL082
IOUT2 GND in Table 13.1. Note the Peak to Peak amplitude of the output. Compare the
3
simulation results with the practical results.
R1
VIN
VOUT
TL082
S.No. BIT Pattern Peak to Peak Amplitude of the output

Figure 13.1: Circuit for Digital Controlled Gain Stage Amplifier
1 100000000000
Let the 12-bit input pattern to DAC be given by _ A11 A10 ... A0i. The expression for the
2 010000000000
_ A11 A10 ... A0i out = in R1 /
output voltage of the negative feedback amplifier
V is given
V $ R2 by$ 114096
An 2 n 3 001000000000
0
Vout = Vin $ R2 $ 11V4096 in
4 000100000000
R1 R R n
/ An 2 2 1
0 Table 13.1: Variation in output amplitude with bit pattern

Vin
R2 R1
+ V1 R4 1k
experiment 13
J1
5V
0 E J1
+ 1 R2 J2
V2
10V 2 A R3 1k
3 TL082
4 RO R1 TL082 VOUT
5
+ V3 6 RI J2
10V 7 + J1
8 GND VIN
9
J2
10
11
MV95308
Figure 13.2: Equivalent Circuit for simulation
500.00m
Output
Amplitude(volts)
-500.00m
100.00m
Input
Amplitude(volts)
-100.00m
0.00 5.00m 10.00m 15.00m 20.00m
Time(s)
Figure 13.3: Simulation output of digitally controlled gain stage amplifier

when the input pattern for the DAC was selected to be 0x800
13.5 Exercise Set 13

Design a digitally programmable non-inverting amplifier whose gain varies
from 6.4 and above.

experiment 13

Chapter 14
Experiment 14
Design of a Digitally Programmable Square and
Triangular wave generator/oscillator

Goal of the experiment 14.2 Specifications
experiment 14
To design a digitally controlled oscillators where the oscillation frequency of Design a Digitally Programmable Oscillator that can generate square and triangular
the output square and triangular wave forms is controlled by a binary pattern. waveforms with a maximum frequency of 400 Hz.
Such systems are useful in digital PLL and in FSK generation in a MODEM.

14.1 Brief theory and motivation Implement the Digitally programmable Square and Triangular wave generator using
the circuit as shown in Figure 14.1.Observe the frequency of Oscillations of system
In Experiment 6, we used an analog multiplier in conjunction with an integrator to and vary it by varying bit pattern input to the DAC.
build a VCO. In this experiment, we will use a multiplying DAC7821 (instead of a
multiplier) and an integrator to implement a digitally controlled square and triangular
wave generator. See Figure 14.1 for the circuit schematic of a digitally programmable
square and triangular wave generator. VOUT is the square wave output and the
14.4 What Should you Submit
output of the integrator is the triangular waveform.
1 Simulate the circuit using any simulator and observe the frequency of oscillation
VDD of the square and triangular waveforms. See Figure 14.2 for the result of
C 1u
simulation. The typical simulation waveforms are of the form shown in Figure
C1
RFB VDD 14.3. For this simulation, we used the macro-model of MV95308 since the
IOUT1 macro-model for the DAC is not available at the time of writing.
R 1k DAC7821 VREF
TL082
IOUT2 GND
TL082
Vary the bit pattern input to the DAC in manner specified in Table 14.1 and
2 note down the change in the frequency of oscillations and compare the
practical results with the simulation results.
Plot a graph where the x-axis shows the analog equivalent of the bit pattern
VOUT
TL082 3 and the y-axis shows the frequency of oscillations. Note that the 12-bit input
to the DAC is interpreted as an unsigned number.
R2
R1
S.No. BIT Pattern Peak to Peak Amplitude of the output
1 100000000000
Figure 14.1: Circuit for Digital Controlled Oscillator
2 010000000000
Frequency of oscillations of digital programmable oscillator is given by

3 001000000000
11
/A 2 n
4RC b + R1 l 4096
n 4 000100000000
f= 1 $ 1 R2 $ 0
Table 14.1: Varying the bit pattern input to the DAC
Q = 10
C 1u
experiment 13
V tri
J1 + V1
5V R4 1k
0 E J2
+ V2
1 R 1k J2
10V 2 A J2
3 TL082 R3 1k
4 RO TL082
5 TL082
+ V3 6 RI J1
10V 7 J1
8 GND V squ J1
9
J2 R2
10
11 R1
MV95308
Figure 14.2: Circuit for Simulation
10.00
V squ
-10.00
3.00
V tri
-3.00
0.00 25.00m 50.00m 75.00m 100.00m
Time(s)
Figure 14.3: Simulation Results

/A 2
f = 1 $ b1 + R2 l $ 0
n
n
4RC R1 4096
Design a digitally programmable band-pass filter with Q = 10 and gain of 1 at
the centre frequency.

experiment 14

Appendix A
ICs used in
ASLK PRO
Texas Instruments Analog ICs used in ASLK PRO

JFET-Input Operational Amplifier TL082
appendix A
A.1.1 Features A.1.2 Applications A.1.4 Download Datasheet

• Low Power Consumption • Input Buffer http://www.ti.com/lit/gpn/tl082
• Wide Common-Mode and Differential Voltage Ranges • High-Speed Integrators
• Input Bias and Offset Currents • D/A Converters
• Output Short-Circuit Protection • Sample And Hold Circuits
• Low Total Harmonic Distortion...0.003% Typ
• High Input Impedance...JFET-Input Stage
• Latch-Up-Free Operation
• High Slew Rate...13 V/μs Typ
• Common-Mode Input Voltage Range Includes VCC+
Figure A.1: TL082 - JFET-Input Operational Amplifier
A.1.3 Description
The TL08x JFET-input operational amplifier family and bipolar transistors in a monolithic integrated within the TL08x family. The C-suffix devices are
is designed to offer a wider selection than any circuit. The devices feature high slew rates, low characterized for operation from 0˚C to 70˚C. The
previously developed operational amplifier family. input bias and offset currents, and low offset I-suffix devices are characterized for operation
Each of these JFET-input operational amplifiers voltage temperature coefficient. Offset adjustment from -40˚C to 85˚C. The Q-suffix devices are
incorporates well-matched, high-voltage JFET and external compensation options are available characterized for operation from -40˚C to 125˚C.

MPY634 Wide Bandwidth Analog Precision Multiplier
appendix A
• Wide Bandwidth: 10MHz Typ • Precision Analog Signal Processing http://www.ti.com/lit/gpn/mpy634
• 0.5% Max Four-Quadrant Accuracy • Modulation And Demodulation
• Internal Wide-Bandwidth Op Amp • Voltage-Controlled Amplifiers
• Easy To Use • Video Signal Processing
• Low Cost • Voltage-Controlled Filters And Oscillators
X Input X1 +VS +15V

±10V FS
±12V PK
X2 O ut VO UT, ±12V PK
+15V
MPY634 (X1 – X2) (Y1 – Y2)
470k Ω = + Z2
50kΩ SF Z1 10V
1kΩ
–15V
O ptional O ffset Y1 Z2
Trim C ircuit O ptional
S umming
Y Input Y2 –VS –15V Input,
±10V FS Z, ±10V PK
±12V PK
Figure A.2: MPY634 - Analog Multiplier
A.2.3 Description
The MPY634 is a wide bandwidth, high accuracy, divider, square-rooter, and other functions while It is capable of performing frequency mixing,
four-quadrant analog multiplier. Its accurately maintaining high accuracy. The wide bandwidth balanced modulation, and demodulation with
laser-trimmed multiplier characteristics make it of this new design allows signal processing excellent carrier rejection. An accurate internal
easy to use in a wide variety of applications with at IF, RF, and video frequencies. The internal voltage reference provides precise setting of
a minimum of external parts, often eliminating output amplifier of the MPY634 reduces design the scale factor. The differential Z input allows
all external trimming. Its differential X, Y, and Z complexity compared to other high frequency user-selected scale factors from 0.1 to 10 using
inputs allow configuration as a multiplier, squarer, multipliers and balanced modulator circuits. external feedback resistors.

12 Bit, Parallel, Multiplying DAC DAC 7821
appendix A
A.3.1 Features • Industry-Standard Pin Configuration A.3.4 Download Datasheet

• 4-Quadrant Multiplication
• 2.5V to 5.5V supply operation http://www.ti.com/lit/gpn/dac7821
• Fast Parallel Interface: 17ns Write Cycle
• Update Rate of 20.4MSPS A.3.2 Applications
• 10MHz Multiplying Bandwidth
• 10V input • Portable Battery-Powered Instruments
• Low Glitch Energy: 5nV-s • Analog Processing
• Extended Temperature Range: -40˚C to +125˚C • Waveform Generators
• 20-Lead TSSOP Packages • Programmable Amplifiers and Attenuators
• 12-Bit Monotonic • Digitally Controlled Calibration
• 1LSB INL • Programmable Filters and Oscillators
• Read back Function • Composite Video
• Power-On Reset with Brownout Detection • Ultrasound
Figure A.3: DAC 7821 - Digital to Analog Converter
A.3.3 Description
The DAC7821 is a CMOS 12-bit current output to read the contents of the DAC register via the DB external reference input voltage (VREF) determines
digital-to-analog converter (DAC). This device pins. On power-up, the internal register and latches the full-scale output current. An integrated feedback
operates from a single 2.5V to 5.5V power supply, are filled with zeroes and the DAC outputs are at resistor (RFB) provides temperature tracking and
making it suitable for battery-powered and many zero scale. The DAC7821 offers excellent 4-quadrant full-scale voltage output when combined with an
other applications. This DAC operates with a fast multiplication characteristics, with a large signal external current-to-voltage precision amplifier. The
parallel interface. Data read back allows the user multiplying and width of 10MHz. The applied DAC7821 is available in a 20-lead TSSOP package.

TPS40200 Wide-Input, Non-Synchronous Buck DC/DC Controller
appendix A
A.4.1 Features • 700 mV 1% Reference Voltage A.4.4 Download Datasheet
• External Synchronization
• Input Voltage Range 4.5 to 52 V • Small 8-Pin SOIC (D) and QFN (DRB) Packages http://www.ti.com/lit/gpn/tps40200
• Output Voltage (700 mV to 90% VIN)
• 200 mA Internal P-Channel FET Driver
• Voltage Feed-Forward Compensation A.4.2 Applications
• Undervoltage Lockout
• Programmable Fixed Frequency (35-500 kHz) • Industrial Control
Operation • DSL/Cable Modems
• Programmable Short Circuit Protection • Distributed Power Systems
• Hiccup Overcurrent Fault Recovery • Scanners
• Programmable Closed Loop Soft Start • Telecom
Figure A.4: TPS40200 - DC/DC Controller
A.4.3 Description
The TPS40200 is a flexible non-synchronous feature extends the flexibility of the device, allowing to input voltage change. The internal 700mV
controller with a built in 200-mA driver for P-channel it to operate with an input voltage up to 52V without reference is trimmed to 1%, providing the means to
FETs. The circuit operates with inputs up to 52V with dissipating excessive power. The circuit operates accurately control low voltages. The TPS40200 is
a power-saving feature that turns off driver current with voltage-mode feedback and has feed-forward available in an 8-pin SOIC, and supports many of the
once the external FET has been fully turned on. This input-voltage compensation that responds instantly features of more complex controllers.

Micropower Low-Dropout (LDO) Voltage Regulator TPS7250
appendix A

• Available in 5-V, 4.85-V, 3.3-V, 3.0-V, and 2.5-V • Wireless Handsets http://www.ti.com/lit/gpn/tps7250
Fixed-Output and Adjustable Versions • Smart Phones, PDAs
• Dropout Voltage <85 mV Max at IO = 100 mA • MP3 Players
(TPS7250) • ZigBeeTM Networks
• Low Quiescent Current, Independent of Load, 180 • BluetoothTM Devices
mA Typ • Li-Ion Operated Handheld Products
• 8-Pin SOIC and 8-Pin TSSOP Package • WLAN and Other PC Add-on Cards
• Output Regulated to ±2% Over Full Operating
Range for Fixed-Output Versions
• Extremely Low Sleep-State Current, 0.5 mA Max
• Power-Good (PG) Status Output
TPS7250
5 2
VI IN PG PG
6 1
IN SENSE 250 k
7
OUT VO
0.1 F 4 8
EN OUT
CO
GND +
10 F
3
CSR = 1 
Figure A.5: TPS7250 -Micropower Low-Dropout (LDO) Voltage Regulator
A.5.3 Description
The TPS72xx family of low-dropout (LDO) voltage series devices are ideal for cost-sensitive designs to the load current. Since the PMOS pass element
regulators offers the benefits of low-dropout and for designs where board space is at a premium. is a voltage-driven device, the quiescent current is
voltage, micropower operation, and miniaturized A combination of new circuit design and process very low (300 mA maximum) and is stable over the
packaging. These regulators feature extremely low innovation has enabled the usual pnp pass transistor entire range of output load current (0 mA to 250 mA).
dropout voltages and quiescent currents compared to to be replaced by a PMOS device. Because the PMOS Intended for use in portable systems such as laptops
conventional LDO regulators. Offered in small-outline pass element behaves as a ue resistor, the dropout and cellular phones, the low-dropout voltage and
integrated-circuit (SOIC) packages and 8-terminal voltage is very low – maximum of 85 mV at 100 mA micropower operation result in a significant increase
thin shrink small-outline (TSSOP), the TPS72xx of load current (TPS7250) – and is directly proportional in system battery operating life.

2N3906, 2N3904, BS250 Transistors
A.6.1 2N3906 Features A.6.3 2N3904 Features A.6.5 BS250 Features
• PNP General Purpose Transistor • NPN General Purpose Transistor • P-CHANNEL ENHANCEMENT MODE VERTICAL
• Collector-Emiter Breakdown Voltage: • Collector-Emiter Breakdown Voltage: DMOS FET
V(BR)CEO = 40V V(BR)CEO = 40V • Drain-Source Voltage: VDS = -45V
• Collector-Base Breakdown Voltage: • Collector-Base Breakdown Voltage: • Continuous Drain Current ID = -230 mA
V(BR)CBO = 40V V(BR)CBO = 60V @ TAMB = 25°C
• hFE: 100 @ IC = 10mA DC, VCE = 1V DC • hFE: 100 @ IC = 10mA DC, VCE = 1V DC • Gate-Source Voltage: VGS = ±20 V
• Transition Frequency: f = 100MHz @ VCE = 20V DC, • Transition Frequency: f = 100MHz @ VCE = 20V DC, • Static Drain-Source on-State Resistance:
IC = 10mA DC IC = 10mA DC RDS(ON) = 14Ω @ VGS = -10V, ID = -200mA
• Gate-Source Threshold Voltage:
VGS(TH) Min -1V; Max: -3.5V @ ID=-1mA, VDS=VGS
E B C E B C DGS
Figure A.6: 2N3906 Figure A.7: 2N3906 Figure A.8: BS250
PNP General Purpose Amplifier NPN General Purpose Amplifier P-Channel Enhancement
Mode Vertical DMOS FET
A.6.2 Download Datasheet A.6.4 Download Datasheet A.6.6 Download Datasheet

http://61.222.192.61/mccsemi/ http://61.222.192.61/mccsemi/ http://www.diodes.com/datasheets/BS250P.pdf
up_pdf/2N3906(TO-92).pdf up_pdf/2N3904(TO-92).pdf

DIODE 1N4448 Small Signal Diode
Figure A.9:
1N4448 Small Signal Diode
A.7.1 Features
• Breakdown Voltage: VR = 100V @ IR = 100μA
• Forward Voltage: VF = 620-720mV @ IF = 5mA
• Reverse Leakage: IR = 25uA @ VR = 20V
• Total Capacitance: CT = 4pF, VR = 0, f = 1MHz
• Reverse Recovery Time: tRR = 4nS @ IF = 10mA, VR = 6.0V, RL = 100Ω
A.7.2 Download Datasheet

http://www.fairchildsemi.com/ds/1N/1N914.pdf

Appendix B
Introduction to
Macromodels

Simulation models are very useful in the design phase of an electronic system. intensive. As the number of nodes in the circuit increases, the memory requirement
appendix B
Before a system is actually built using real components, it is necessary to perform will be higher and the convergence of the simulation can take longer.
a ‘software breadboarding’ exercise through simulation to verify the functionality
of the system and to measure its performance. If the system consists of several A macromodel is a way to address the problem of space-time complexity mentioned
building blocks B1, B2, ..., Bn, the simulator requires a mathematical representation above. In today’s electronic systems we make use of analog circuits such as
of each of these building blocks in order to predict the system performance. Let us operational amplifiers, data converters, PLL, VCO, voltage regulators, and so on.
consider a very simple example of a passive component such as a resistor. Ohm’s law The goal of the system designer is not only to get a functionally correct design,
can be used to model the resistor if we intend to use the resistor in a DC circuit. But but also to optimize the cost and performance of the system. The system-level
if the resistor is used in a high frequency application, we may have to think about cost and performance depend on the way the building blocks B1, B2,..., Bn have
the parasitic inductances and capacitances associated with the resistor. Similarly, been implemented. For example, if B1 is an OP-Amp, we may have several choices
the voltage and current may not have a strict linear relation due to the dependence of operational amplifiers. Texas Instruments offers a large number of operational
of the resistivity on temperature of operation, skin effect, and so on. This example amplifiers that a system designer can choose from. Refer to Table B.1. As you
illustrates that there is no single model for an electronic component. Depending will see, there are close to 2000 types of operational amplifiers available! These
on the application and the accuracy desired, we may have to use simpler or more are categorized into 17 different bins to make the selection simpler. However,
complex mathematical models. you will notice that 240 varieties are available in the category of Standard Linear
amplifers! How does a system designer select from this large collection? To
We will use another example to illustrate the above point. The MOS transistor, understand this, you must look at the characteristics of a standard linear amplifier
which is the building block of most integrated circuits today, is introduced at the - these include the number of operational amplifiers in a single package, the
beginning of the course on VLSI design. In a digital circuit, the transistor may be Gain Bandwidth Product of the amplifier, the CMRR, Vs (min), Vs (max), and so
simply modeled as an ideal switch that can be turned on or off by controlling the on. See http://tinyurl.com/ti-std-linear. The website allows you to specify these
gate voltage. This model is sufficient if we are only interested in understanding parameters and narrow your choices.
the functionality of the circuit. If we wish to analyze the speed of operation of the
circuit or the power dissipation in the circuit, we will need to model the parasitics But how does one specify the parameters for the components? The overall
associated with the transistors. If the same transistor is used in an analog circuit, system performance will depend on the way the parameters for the individual
the model that we use in the analysis would depend on the accuracy which we want components have been selected. For example, the gain-bandwidth product of an
in the analysis. We may perform different kinds of analysis for an analog circuit - operational amplifier B1 will influence a system-level parameter such as the noise
DC analysis, transient analysis, and steady-state analysis. Simulators such as SPICE immunity or stability. If one has n components in the system, and there are m
require the user to specify the model for the transistor. There are many different choices for each component, there are m·n possible system configurations. Even
models available today for the MOS transistor, depending on the desired accuracy. if we are able to narrow the choices through some other considerations, we may
The level-1 model captures the dependence of the drain-to-source current on the still have to evaluate several system configurations. Performing simulations using
gate-to-source and drain-to-source voltages, the mobility of the majority carrier, micromodels will be a painstaking and non-productive way of selecting system
the width and length of the channel, and the gate oxide thickness. It also considers configurations.
non-idealities such as channel length modulation in the saturation region, and the
dependence of the threshold voltage on the source-to-bulk voltage. More complex
models for the transistor are available, which have more than 50 parameters.
B.2 Macromodels
A macromodel is a mathematical convenience that helps to reduce simulation
B.1 Micromodels complexity. The idea is to replace the actual circuit by something that is simpler,
but is nearly equivalent in terms of input characteristics, output characteristics, and
If you have built an operational amplifier using transistors, a straight-forward way feedforward characteristics. Simulation of a complete system becomes much more
to analyze the performance of the OP-Amp is to come up with the micromodel of the simple when we use macromodels for the blocks. Manufacturers of semiconductors
OPAMAP, where each transistor is simply replaced with its corresponding simulation provide macromodels for their products to help system designers in the process of
model. Micromodels will lead to accurate simulation, but will prove computationally system configuration selection. The macromodels can be loaded into a simulator.

Characteristic Number of Varieties
appendix B
1 Standard Linear Amplifier 240 Notes on Appendix B:
2 Fully Differential Amplifier 28
3 Voltage Feedback 68
4 Current Feedback 47
5 Rail to Rail 14
6 JFET/CMOS 23
7 DSL/Power Line 19
8 Precision Amplifier 641
9 Low Power 144
10 High Speed Amplifier (≥50MHz) 182
11 Low Input Bias Current/FET Input 38
12 Low Noise 69
13 Wide Bandwidth 175
14 Low Offset Voltage 121
15 High Voltage 4
16 High Output Current 54
17 LCD Gamma Buffer 22
Table B.1: Operational Amplifiers available from Texas Instruments
As you can guess, there is no single macromodel for an IC. A number of macromodels
can be derived, based on the level of accuracy desired and the computational
complexity that one can afford. A recommended design methodology is to start
with a simple macromodel for the system components and simulate the system. A
stepwise refinement procedure may be adopted and more accurate models can be
used for selected components when the results are not satisfactory.

appendix B
Notes on Appendix B:

Appendix C
Activity
Convert your PC/laptop into
an Oscilloscope

C.1 Introduction
appendix C
In any analog lab, an oscilloscope is required to display the student on a full-edged lab. In this chapter, we should be about 1 volt AC; hence it is essential to
waveforms at different points in the circuit under will review a solution for a PC-based oscilloscope. The protect the sound card from over voltages. A buffer
construction in order to verify circuit operation and, if components on the ASLK PRO can be used to build amplifier circuit is required to protect the sound card
necessary, redesign the circuit. High-end oscilloscopes the interface circuit needed to convert the PC into an from overvoltages. Two copies of such a circuit are
are needed for measurements and characterization oscilloscope. needed to implement a dual-channel oscilloscope. The
in labs. Today, solutions are available to students for One of the solutions for a “PC oscilloscope” is Zelscope buffer amplifier circuit is shown in Figure C.1 and has
converting a PC into an oscilloscope. These solutions [33] which works on personal computers running been borrowed from [32].
require some additional hardware to route the analog Microsoft Windows XP. The hardware requirements for
signals to the PC for observation; they also require the PC are modest (300+ MHz clock, 64+ MB memory).
software that provides the graphical user interface to It uses the sound card in the PC for converting the Limitations
convert a PC display into an oscilloscope. Since most analog signals into digital form. The Zelscope software,
students have access to a PC or laptop today, we have which requires about 1 MB space, is capable of using • Not possible to display DC voltages (due to input
designed the Analog System Lab such that a PC-based the digitized signal to display waveforms as well as capacitor of sound card blocks DC)
oscilloscope solution can be used along with ASLK the frequency spectrum of the analog signal. At the • Low frequency range (10 Hz-20 kHz)
PRO. We believe this will reduce the dependence of ‘line in’ jack of the sound card, the typical voltage • Measurement is not very accurate
+12V
R2 D1
47k 1/2W 1N914
C1
BNC 0.1uF
C3
100pF
TI082
R1 C2 D2 IVoutl<12V
1M 20pF 1N914 RS
RCA
27k
R4 R6
3k 100k
Zin=1M R3 D3
IVinl<150V 4.7k 1N914
S1
-12V
Figure C.1:
Buffer circuit
needed to
interface an
Analog Signal
to Oscilloscope

Appendix D
Connection
diagrams

OP AMP TYPE I - A - INVERTING OP AMP TYPE I - B - INVERTING
appendix D
HD21 R15 HD21 R15 R25 HD25 R25 HD25
R15 10K R15 10K 10K R25 10K R25
HD19 R14 HD19 C14 R14HD20

C14 HD20 HD8 C24 HD8 R24 C24 HD7 R24 HD7
R14 4K7 R14 4K7 C14 C14 C24 C24 4K7 R24 4K7 R24
1uF 1uF 1uF 1uF
HD17 R13 HD17 C13 R13HD18

R13 2K2 R13 2K2 C13 C13 C23 C23 2K2 2K2
0.1uF 0.1uF 0.1uF 0.1uF R23 R23
HD15 R12 HD15 C12 R12HD16

R12 1K R12 1K C12 C12 C22 C22 1K 1K

0.1uF 0.1uF 0.1uF 0.1uF R22 R22
HD13 R11 HD13 C11 R11HD14

R11 1K R11 1K C11 C11 C21 C21 1K 1K

0.01uF 0.01uF 0.01uF 0.01uFR21 R21
VCC+10 VCC+10 VCC+10 VCC+10

C10 HD10 C10 HD10 HD119 HD119
0.1uF +10V 0.1uF +10V +10V +10V

HD24 HD24
2 OPAMP1A 2 OPAMP1A OPAMP1B 6 OPAMP1B 6
HD11 HD11 HD23 HD26 HD23 HD26 OP1B IN- OP1B IN-
1 1 7 7
OP1A IN- OP1A IN- HD22 HD22
3 3 5 5
HD9 HD9 OP1A OUT OP1B OUT
OP1A OUT OP1B OUT GND GND
OP1 OP1 OP1 OP1
GND GND
C20 HD12 C20 HD12 HD181 HD181
0.1uF -10V 0.1uF -10V -10V -10V
VCC-10 VCC-10 VCC-10 VCC-10
Figure D.1: OP-Amp 1A connected in Inverting Configuration Figure D.2: OP-Amp 1B connected in inverting configuration

OP AMP TYPE II - A - FULL OP AMP TYPE II - B - FULL
appendix D
HD41 R35 HD41 R35 R45 HD63 R45 HD63
R35 1K R35 1K 1K R45 1K R45
HD45 R34 HD45 R34 R44 HD65 R44 HD65
R34 2K2 R34 2K2 2K2 R44 2K2 R44
HD44 C33 HD44 HD43 C33 HD43

HD64 C43 HD64 HD57 C43 HD57
R33 R33 R43 R43
R33 10K R33 C33 10K C33

C43 10K C43 R43 10K R43
0.01uF 0.01uF 0.01uF 0.01uF
HD42 C32 HD42 HD47 C32 HD47

HD66 C42 HD66 HD56 C42 HD56
R32 R32 R42 R42
R32 4K7 4K7 4K7 4K7

0.1uFR32 C32 0.1uF C32
C42 0.1uF C42 R42 0.1uF R42
HD40 C31 HD40 HD46 C31 HD46

HD58 C41 HD58 HD55 C41 HD55
R31 R31 R41 R41
R31 1K 1K 1K 1K
1uF R31 C31 1uF C31
C41 1uF C41 R41 1uF R41
VCC+10 VCC+10 VCC+10 VCC+10

C30 HD37 C30 HD183HD37 HD183
0.1uF +10V 0.1uF +10V +10V +10V

HD53 HD53
2 OPAMP2A 2 OPAMP2B
OPAMP2A 6 OPAMP2B 6
HD38 HD38 HD52 HD62 HD52 HD62 OP2B IN- OP2B IN-
1 1 7 7
OP2A IN- OP2A IN- HD51 HD51
3 3 5 5
HD36 HD36 OP2A OUT OP2B OUT OP2 OP2A OUT OP2B OUT OP2 OP2B IN+ OP2B IN+
OP2 OP2
OP2A IN+ OP2A IN+
C40 HD39 C40 HD180HD39 HD180
0.1uF -10V 0.1uF -10V -10V -10V
VCC-10 VCC-10 VCC-10 VCC-10

HD54 HD54
HD35 C34 HD35 HD33 C34 HD33

HD60 C44 HD60 HD61 C44 HD61
R36 R36 R46 R46
GND GND
R36 1K 1K 1K 1K
1uF R36 C34 1uF C34C44 1uF C44 R46 1uF R46
HD31 C35 HD31 HD30 C35 HD30

HD48 C45 HD48 HD59 C45 HD59
R37 R37 R47 R47
R37 10K 10K 10K 10K

0.1uFR37 C35 0.1uF C35C45 0.1uF C45 R47 0.1uF R47
HD32 C36 HD32 HD34 C36 HD34

HD50 C46 HD50 HD49 C46 HD49
R38 R38 R48 R48
R38 2K2 2K2 2K2 2K2

0.1uFR38 C36 0.1uF C36C46 0.1uF C46 R48 0.1uF R48
Figure D.3: OP-Amp 2A can be used in both inverting Figure D.4: OP-Amp 2B can be used in both inverting
and non-inverting configuration and non-inverting configuration

OP AMP TYPE III - A - BASIC ANALOG MULTIPLIER - SET I
appendix D
VCC+10
C59 HD67
0.1uF +10V
2 OPAMP3A
HD70 HD72
1
OP3A IN-
3
HD69 OP3A OUT
OP3
OP3A IN+
C58 HD68
0.1uF -10V
VCC-10
HD75
VCC+10 VCC+10 VCC
HD90
VCC+10 GND U1
VCC+10
+10V HD84
1 14
C59 HD67 X1 X1 +VS
HD179 C71 C81
HD83
100nF 2 13 100nF
HD86 X2 X2 NC
Figure D.5: OP-Amp 3A can be used in unity
0.1uF +10V gain configuration
+10V
HD89
3 12
or any other26 custom configuration
OPAMP3A
OPAMP3B
GND NC OUT OUT
HD70
HD73 HD72
HD74 HD82 HD88
OP3A IN-
OP3B IN- 3
5
1
7
SF
4
SF MPY634 Z1
11
Z1
HD69
HD71 OP3A OUT
OP3B OUT HD87
OP3
OP3 VCC-10 5 10 VC
OP3A IN+
OP3B IN+ NC Z2 Z2
OP AMP TYPE III - HD182
B
C58 - BASIC
HD68 HD85
Y1
HD81
6
Y1 NC
9
-10V -10V HD80

0.1uF -10V 7 8
Y2 Y2 -VS
C72 C82
VCC-10
VCC-10 100nF 100nF
HD75
GND VCC-10
VCC+10
HD179
+10V
6 OPAMP3B
HD73 HD74
7
OP3B IN-
5
HD71 OP3B OUT
OP3
OP3B IN+
HD182
-10V
VCC-10
Figure D.6: OP-Amp 3B can be used in unity gain configuration

or any other custom configuration Figure D.7: Connections for analog multiplier MPY634 - SET I

ANALOG MULTIPLIER - SET II ANALOG MULTIPLIER - SET III
appendix D
0 VCC+10
VCC+10 VCC+10
VCC+10 VCC+10
VCC+10 VCC+10
VCC+10
HD106
HD106 HD112
HD112
U2 U2 U3 U3
+10V
+10V HD96
HD96 +10V
+10V HD105
HD105
1 1 14 14 1 1 14 14
X1 X1 X1 X1 +VS+VS X1 X1 X1 X1 +VS+VS
C81C81 C91C91
HD95
HD95 HD104
HD104
100nF
100nF 2 2 13 13 100nF
100nF 2 2 13 13
HD93
HD93 X2 X2 X2 X2 NC NC HD108
HD108 X2 X2 X2 X2 NC NC
89
HD89 HD103
HD103 HD111
HD111
3 3 12 12 3 3 12 12
OUT
OUT GND
GND NC NC OUT
OUT OUTOUT GND
GND NC NC OUT
OUT OUTOUT
88
HD88 HD94
HD94 HD101
HD101 HD102
HD102 HD110
HD110
Z1 Z1 SF SF
4 4
MPY634
SF SFMPY634Z1 Z1 11 11 Z1 Z1 SF SF
4 4
MPY634
SF SFMPY634Z1 Z1 11 11 Z1 Z1
87
HD87 HD100
HD100 HD109
HD109
VCC-10
VCC-10 5 5 10 10 VCC-10
VCC-10 5 5 10 10
Z2 Z2 NC NC Z2 Z2 Z2 Z2 NC NC Z2 Z2 Z2 Z2
HD97
HD97 HD92
HD92 HD107
HD107 HD99
HD99
6 6 9 9 6 6 9 9
Y1 Y1 Y1 Y1 NC NC Y1 Y1 Y1 Y1 NC NC
-10V
-10V HD91
HD91 -10V
-10V HD98
HD98
7 7 8 8 7 7 8 8
Y2 Y2 Y2 Y2 -VS-VS Y2 Y2 Y2 Y2 -VS-VS
C82C82 C92C92
100nF
100nF 100nF
100nF
0 VCC-10
VCC-10 VCC-10
VCC-10
Figure D.8: Connections for analog multiplier MPY634 - SET II Figure D.9: Connections for analog multiplier MPY634 - SET III

DAC I
appendix D
VCC+5
VCC+5
VCC+5 VCC+5
LDO OUT R51
DA1
10K
DC/DC VOUT HD137 HD153 HD171 HD138
CS A 1 20
JP3 IOUT1 IOUT1 RFB RFB C52
CS HD151 HD169 100nF CS
2 19
T1 IOUT2 IOUT2 VREF VREF
C51
100nF 3 18
GND VDD
HD184
DBA11 4 17
DB11 R/W
R/W
DBA10 5 16 CS A
DB10 CS
DBA9 6 DAC7821 15 DBA0
R54
DB9 DB0 10k
DBA11
DBA10
DBB11
DBB10
DBA2
DBA1
DBA0
DBA9
DBA8
DBA7
DBA6
DBA5
DBA4
DBA3
DBB9
DBB8
DBA8 7 14 DBA1
DB8 DB1
DBA7 8 13 DBA2
DB7 DB2
HD144 HD145
DBA6 9 12 DBA3
DB6 DB3
DBA5 10 11 DBA4
DB5 DB4
DBA11
DBA10
DBB11
DBB10
DBA2
DBA1
DBA0
DBA9
DBA8
DBA7
DBA6
DBA5
DBA4
DBA3
DBB9
DBB8
VCC+10
HD176
+ 1 2 3 4 5 6 7 8 9 10 11 12 +1 2 3 4
+10V
HD136
VCC+5 _ GND VCC+5 _

VCC-10
SW1 HD175 SW2
R52 R53 R62
220R 220R -10V 220R
Figure D.10: connections for analog-to-digital converter DAC7821 - DAC I

DAC II
appendix D
VCC+5
VCC+5 VCC+5 VCC+5
R61
DA2
10K
1 HD138 HD154 HD172
CS B 1 20
RFB C52 IOUT1 IOUT1 RFB RFB C62
9 100nF CS HD152 HD170 100nF
2 19
VREF T2 IOUT2 IOUT2 VREF VREF
C61
100nF 3 18
GND VDD
HD184 HD185
DBB11 4 17
DB11 R/W
R/W R/W
DBB10 5 16 CS B
DB10 CS
R54
DBB9 6 DAC7821 15 DBB0
R64
10k DB9 DB0 10k
DBB11
DBB10
DBB2
DBB1
DBB0
DBB7
DBB6
DBB5
DBB4
DBB3
DBB9
DBB8
DBB8 7 14 DBB1
DB8 DB1
DBB7 8 13 DBB2
DB7 DB2
HD145
DBB6 9 12 DBB3
DB6 DB3
DBB5 10 11 DBB4
DB5 DB4
DBB11
DBB10
DBB4
DBB3
DBB2
DBB1
DBB0
DBB9
DBB8
DBB7
DBB6
DBB5
VCC+10 VCC+10
HD176 HD178
+ 1 2 3 4 5 6 7 8 9 10 11 12
+10V +10V
HD136 HD135
GND VCC+5 _ GND

VCC-10 VCC-10
HD175 SW2 HD177
R62 R63
-10V 220R 220R -10V
Figure D.11: connections for analog-to-digital converter DAC7821 - DAC II

DC/DC CONVERTER
appendix D
HD142 VCC+10 TP1

HD122
Vin JP9
CN5
VIN 6 – 15V
VIN
DC/DC IN
C201 C203 C204 R202

HD120 220uF R201 TP3 220nF 220nF 0.03
HD121 C205 R203
VIN 100K
TP2
U4 1K
SRC
470pF
RC 1 8
RC VDD
TPS40200
4
SS 2 7 ISNS
SS ISNS
Q101
R204
COMP 3 6 DRV GATE 3 FDC5614P
COMP DRV
0E
4 5
FB GND
1
2
5
6
C213 R210 C214 C208 HD143
470pF 1M 470nF 100nF TP4 TP5
VOUT
HD126 HD128
DRAIN
VOUT 3.3V or 5V
R205 CN6
@ 0.125 – 2.5A
100K L201
VOUT
33uH
C207 C202
R3
33pF 68pF
D201 4K7
C209 C210 C211 C212 VOUT
MBRS340
TP6 R206 TP7 330uF 330uF 10uF 10uF
C206
25.5E LD3
4.7nF
HD124 HD127
FB
TP8 TP9
HD123 HD125
JP8
3.3V R207 R208
5V 100K 49.9
R211 R209
41K2 27K4
Figure D.12: Connections for TPS40200 Evaluation step-down DC/DC converter

LDO REGULATOR
appendix D
HD118
VOUT
CN4
@250mA
VOUT 5 V
OUT OUT
VOUT
IC1
R4 R101 GND
C103
4K7 247K 1 8
SENSE OUT 10uF
VCC+10 HD117
TPS7250
2 7 VIN
LD4 PG OUT JP6
CN3
VIN 5.5 -10 V

3 6 IN
GND IN
REG IN
VIN
4 5
EN IN
C101 C102
GND
1uF 100nF
HD116
GND
JP7
ENABLE OFF
ON
Figure D.13: Connections for TP7250 low-dropout linear voltage regulator
TRANSISTOR SOCKET (MOSFET) TRANSISTOR SOCKET (BJT)
HD115B HD141B
HD115B HD141B
DRAIN COLLECTOR
DRAIN COLLECTOR
D
C
D
C
HD114B HD140B
HD114B HD140B
2
2
2
2
MOSFET SOCKET TRANSISTOR SOCKET
MOSFET SOCKET TRANSISTOR SOCKET
G 1 BG 11 B 1
3
GATE BASE
3
3
GATE BASE
E
S
E
S
HD113B HD139B
HD113B HD139B
SOURCE EMITTER
SOURCE EMITTER
Figure D.14: MOSFET socket Figure D.15: Bipolar Junction Transistor socket

DIODES TRIMMERS
appendix D
VCC+10 VCC-10
HD76B HD78B HD131 HD133

D2
+10V -10V
D2A D2K HD132 HD134

P1 P2
1K 1K
S1 S2
HD77B HD79B
D1
HD129 HD130
GND GND
D1A D1K
Figure D.16: Diode sockets Figure D.17: Trimmer-potentiometers
POWER SUPPLY GENERAL PURPOSE AREA
CN1
HD29
VCC+10 VCC+10
+10V
HD28
+10V
CN2
GND
HD27
VCC-10 VCC-10
-10V
-10V
R1
VCC+10
6K8
LD1
R2
VCC-10
6K8
LD2
Figure D.18: Main power supply Figure D.19: General purpose area (2.54mm / 100mills pad spacing)

Bibliography
List of references and related articles for
further reading

Bibliography 1 of 2
[01] ADCPro (TM) - Analog to Digital Conversion Evaluation Software. Free. Available from http://focus.ti.com/docs/toolsw/folders/print/adcpro.html
[02] F. Archibald. Automatic Level Controller for Speech Signals Using PID Controllers. Application Notes from Texas Instruments.
Available from http://focus.ti.com/lit/wp/spraaj4/spraaj4.pdf
[03] High-Performance Analog. Available from www.ti.com/analog
[04] Wide Bandwidth Precision Analog Multiplier MPY634, Burr Brown Products from Texas Instruments,
Available from http://focus.ti.com/lit/ds/sbfs017a/sbfs017a.pdf
[05] B. Carter and T. Brown. Handbook Of Operational Amplifier Applications. Texas Instruments Application Report. 2001.
Available from http://focus.ti.com/lit/an/sboa092a/sboa092a.pdf
[06] B. Carter. Op Amp and Comparators - Don’t Confuse Them! Texas Instruments Application Report, 2001.
Available from http://tinyurl.com/carteropamp-comp
[07] B. Carter. Filter Design in Thirty Seconds. Application Report from Texas Instruments. Downloadable from http://focus.ti.com/lit/an/sloa093/sloa093.pdf
[08] B. Carter and R. Mancini. OPAMPS For Everyone. Elsevier Science Publishers, 2009.
[09] FilterPro (TM) - Active Filter Design Application. Free software. Available from http://tinyurl.com/lterpro-download
[10] Thomas Kuehl and Faisal Ali. Active Filter Synthesis Made Easy With FilterPro V3.0. Tutorial presented in TI Technology Days 2010 (May), USA.
Available from http://www.ti.com/ww/en/techdays/2010/index.shtml.
[11] J. Molina. DESIGN A 60Hz NOTCH FILTER WITH THE UAF42. Application note from Burr-Brown (Texas Instruments), 2000.
Available from http://focus.ti.com/lit/an/sbfa012/sbfa012.pdf
[12] J. Molina. DIGITALLY PROGRAMMABLE, TIME-CONTINUOUS ACTIVE FILTER, 2000.

Application note from Burr-Brown (Texas Instruments), http://focus.ti.com/lit/an/sbfa005/sbfa005.pdf
[13] George S. Moschytz. From Printed Circuit Boards to Systems-on-a-chip. IEEE Circuits and Systems magazine, Vol 10, Number 2, 2010.
[14] Phase-locked loop. Wikipedia entry. http://en.wikipedia.org/wiki/Phaselocked loop
[15] R. Palmer. Design Considerations for Class-D Audio Amplifiers. Application Note from Texas Instruments.
Available from http://focus.ti.com/lit/an/sloa031/sloa031.pdf
[16] K.R.K. Rao. Electronics for Analog Signal Processing - Part II. OPAmp in Negative Feedback.
Recorded lecture available through NPTEL. http://tinyurl.com/krkrao-nptel-lec7 and http://tinyurl.com/krkrao-nptel-lec8

Bibliography 2 of 2
[17] K.R.K. Rao. Electronics for Analog Signal Processing - Part II. Frequency Compensation in Negative Feedback.
Recorded lecture available through NPTEL. http://tinyurl.com/krkrao-nptel-lec16 and http://tinyurl.com/krkraonptel-lec17
[18] K.R.K. Rao. Electronics for Analog Signal Processing - Part II. Instrumentation Amplifier.
Recorded lecture available through NPTEL. http://tinyurl.com/krkrao-nptel-lec11
[19] K.R.K. Rao. Electronics for Analog Signal Processing - Part II. Active Filters.
Recorded lecture available through NPTEL. http://tinyurl.com/krkraonptel-lec12
[20] K.R.K. Rao. Electronics for Analog Signal Processing - Part II. Positive Feedback (Regenerative).
Recorded lecture available through NPTEL. http://tinyurl.com/krkrao-nptel-lec9
[21] K.R.K. Rao. Analog ICs. Self-Tuned Filter. Recorded lecture available through NPTEL. http://tinyurl.com/krkrao-nptel-ic-lec23
[22] K.R.K. Rao. Analog ICs. Phase Locked Loop. Recorded lecture available through NPTEL. http://tinyurl.com/krkrao-nptelic-lec24,
http://tinyurl.com/krkrao-nptel-ic-lec25, http://tinyurl.com/krkraonptel-ic-lec26, and http:// tinyurl.com/krkrao-nptel-ic-lec27
[23] K.R.K. Rao. Electronics for Analog Signal Processing - Part II. Voltage Regulators. Recorded lecture available through NPTEL.
http://tinyurl.com/krkrao-nptel-26, http://tinyurl.com/krkrao-nptel-27, and http:// tinyurl.com/krkrao-nptel-28
[24] K.R.K. Rao. Electronics for Analog Signal Processing - Part II. Converters. Recorded lecture available through NPTEL. http://tinyurl.com/krkrao-nptel-28,
[25] K.R.K. Rao. Electronics for Analog Signal Processing - Part II. AGC/AVC. http://tinyurl.com/krkrao-nptel-33, http://tinyurl.com/krkrao-nptel-34,
http://tinyurl.com/krkrao-nptel-35, http://tinyurl.com/krkrao-nptel-36
[26] K.R.K.Rao. Analog Ics Voltage Controlled Oscillator. Recorded lectures available from links: http://tinyurl.com/krkrao-vco-1, http://tinyurl.com/krkrao-vco-2
[27] Thomas Kugesstadt. Active Filter Design Techniques. Texas Instruments. Available from http://focus.ti.com/lit/ml/sloa088/sloa088.pdf
[28] Oscilloscope Solutions from Texas Instruments - Available from http://focus.ti.com/docs/solution/folders/ print/437.html
[29] PC Based Test and Instrumentation. Available from http://www.pctestinstruments.com/
[30] SwitcherPro (TM) - Switching Power Supply Design Tool. http://focus.ti.com/docs/toolsw/folders/print/switcherpro.html
[31] Texas Intruments Analog eLAB - SPICE Model Resources. Macromodels for TI analog ICs are downloadable from http://tinyurl.com/ti-macromodels
[32] How to use PC as Oscilloscope. Available from http://www.trickswindows.com
[33] Zelscope: Oscilloscope and Spectrum Analyzer. Available from http://www.zelscope.com

These materials are for academic and
training usage: for teaching and learning
purposes only. The materials are not
warranted in any way for production use.
Copyright © Texas Instruments 2012.

Analog
System
Lab Kit PRO
MANUAL
Authors
K.R.K. Rao and C.P. Ravikumar
Editor in Chief
Zoran Ristić
Assistant Editor
Miodrag Veljković
Cover Design
Danijela Krajnović
Graphic Design/DTP
Aleksandar Nikolić
Special Thanks to
Harmanpreet Singh
for his help in performing the additional experiments
(Experiments 11-14) included in the new release of ASLK Pro.
Publisher
MikroElektronika Ltd. Analog System Lab Kit PRO Manual
ver. 1.03b
www.mikroe.com
June 2012. 0 100000 019382

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Analog

Introduction 9 2.1.1 Inverting Regenerative Comparator 24

Organization of the Manual 16

2.1 Brief theory and motivation 24

Analog System Lab Kit PRO page 3

Experiment 5: 35 Experiment 8: 47

Experiment 7: 43 Experiment 10: 55

page 4 Analog System Lab Kit PRO

Experiment 11: 59 14.2 Specifications 72

Experiment 13: 67 A.2.3 Description 77

Analog System Lab Kit PRO page 5

page 6 Analog System Lab Kit PRO

Analog System Lab Kit PRO page 7

8.1 Transfer characteristic of the AGC circuit

List of tables 11.1

page 8 Analog System Lab Kit PRO

Analog System Lab Kit PRO page 9

2 Amplifiers are needed to strengthen the signal. Analog filtering may be

3  n analog-to-digital converter transforms the analog signal into a

4  he digital data is processed by a CPU, such as a DSP, a microprocessor,

5  igital-to-analog conversion (DAC) is necessary to convert the stream of

page 10 Analog System Lab Kit PRO

Part I - Learning the basics Part II - Building analog systems

Analog System Lab Kit PRO page 11

page 12 Analog System Lab Kit PRO

Analog System Lab Kit PRO page 13

4  e have included a wide-input non-synchronous DC/DC buck

2B TYPE II Full Configuration

3B TYPE III Basic Configuration

page 14 Analog System Lab Kit PRO

1 Photo of ASLK PRO 1 1

Analog System Lab Kit PRO page 15

1. Basic understanding of electronic circuits

2. Basic computer skills required to run the

3. Ability to use the oscilloscope

4. Concepts of gain, bandwidth, transfer function,

page 16 Analog System Lab Kit PRO

Analog System Lab Kit PRO page 17

In the above equations, A0 isV A0 $ (AV11 -

1.1.1 Unity Gain Amplifier V " V1 as" A1 as" A3 " 3 V

_1 + s ~d1i+ _11 + s ~d2i

~ ~ 0 0 T= V V " 1 as A " 3 1 + T 1 = A11

Figure 1.1: An ideal Dual-Input, Single-Output ~ ~ OP-Amp

The term GB known

feedback configuration. Figure 1.1 shows a differential-input, single-ended-output 1 T V

V s 1+A 0V V1V+ = A 1V A A s V " 1 as A "V 3" 1 as A A" 3

_A"1 1+as1A "A3 V d2i

_ A ~ ~ i amplifier of gain 2, (b) Inverting amplifier of gain 2

Q is the2Qquality factor _and = 24QQis ithe

Vp Vp 2 Vp Figure 1.6: Negative Feedback Amplifiers

3 Design an instrumentation amplifier using two OP-Amps with a controllable

Figure 1.8: Outputs VF1, VF2 and VF3 of Negative Feedback

Figure 1.7: Frequency Response of Negative Feedback Amplifiers

page 20 Analog System Lab Kit PRO

Analog System Lab Kit PRO page 21

page 22 Analog System Lab Kit PRO

Analog System Lab Kit PRO page 23

b $ Vxss the =xTRC = input

A00 $$ __V V00 ii

after t + x . The formula for t +tx+ is xgiven below. 1 +R1b R1

page 26 Analog System Lab Kit PRO

Analog System Lab Kit PRO page 27

Figure 3.1: Integrator

Introduction 9 2.1.1 Inverting Regenerative Comparator 24

Organization of the Manual 16

2.1 Brief theory and motivation 24

Experiment 5: 35 Experiment 8: 47

Experiment 7: 43 Experiment 10: 55

Experiment 11: 59 14.2 Specifications 72

Experiment 13: 67 A.2.3 Description 77

8.1 Transfer characteristic of the AGC circuit

2 Amplifiers are needed to strengthen the signal. Analog filtering may be

3 n analog-to-digital converter transforms the analog signal into a

4 he digital data is processed by a CPU, such as a DSP, a microprocessor,

5 igital-to-analog conversion (DAC) is necessary to convert the stream of

4 e have included a wide-input non-synchronous DC/DC buck

1. Basic understanding of electronic circuits

2. Basic computer skills required to run the

3. Ability to use the oscilloscope

4. Concepts of gain, bandwidth, transfer function,