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Sagar Mukherjee
Dept. of ECE
MCKV Institute of Engineering
What does HDL stand for?
• type Std_ulogic is (‘U’, ‘X’, ‘0’, ‘1’, ‘Z’, ‘W’, ‘L’, ‘H’, ‘-’);
• ‘U’ -- Uninitialized
• ‘X’ -- Forcing unknown
• ‘0’ -- Forcing zero
• ‘1’ -- Forcing one
• ‘Z’ -- High impedance
• ‘W’ -- Weak Unknown
• ‘L’ -- Weak Low
• ‘H’ -- Weak High
• ‘-’ -- Don’t care
• type std_logic is resolved std_ulogic;
• type std_logic_vector is array (integer range <>) of std_logic;
Built-In Operators
• Logic operators
• AND, OR, NAND, NOR, XOR, XNOR (XNOR in VHDL’93 only!!)
• Relational operators
• =, /=, <, <=, >, >=
• Addition operators
• +, -, &
• Multiplication operators
• *, /, mod, rem
• Miscellaneous operators
• **, abs, not
Entity Declaration
• An entity declaration describes the interface of the component. Avoid using
Altera’s primitive names which can be found at
c:/altera/91/quartus/common/help/webhelp/master.htm#
• PORT clause indicates input and output ports.
• An entity can be thought of as a symbol for a component.
Port Declaration
• PORT declaration establishes the interface of the object to
the outside world.
• Three parts of the PORT declaration
• Name
• Any identifier that is not a reserved word.
• Mode
• In, Out, Inout, Buffer
• Data type
• Any declared or predefined datatype.
• Sample PORT declaration syntax:
Architecture Declaration
• Architecture declarations describe the operation of the component.
• Many architectures may exist for one entity, but only one may be
active at a time.
• An architecture is similar to a schematic of the component.
Modeling Styles
• Behavioral
• Data flow
• Structural
Behavorial Style
Data flow Style
Structural Style
Sequential Style Syntax
• Component declarations
may be made inside
packages.
• Components do not have to
be declared in the
architecture body
Structural Statements
• The GENERIC MAP is similar to the PORT MAP in that it
maps specific values to generics declared in the
component.
Predefined Data Types
b <= “000000010010”;
Vector & Array assignments
• signal i: integer;
• signal r: real;
• i <= integer(r);
• r <= real(i);
Type Conversion (Same Base)
signal i:integer;
signal b:bit_vector(3 downto 0)
i<=bits2int(b);
b<=int2bits(i,4);
Simulate Design using Quartus II
• Altera’s Quartus II is a PLD design software suitable for high-
density FPGA designs.
• Schematic Editor, VHDL/Verilog Editor, Waveform Simulator.
library ieee;
Examples
use ieee.std_logic_1164.all;
entity OR_arch is
behavioral port( x: in std_logic;
y: in std_logic;
F: out std_logic
); Data flow
end OR_arch;
end OR_arch;
library ieee;
use ieee.std_logic_1164.all; More Example..
entity mux is
port( I: in std_logic_vector(1 downto 0);
s: in std_logic;
0: out std_logic
);
end mux;
process(S)
case S is
when "0" => O <= I(0);
when "1" => O <= I(1);
when others => O <= "ZZZ";
end case;
end mux;
Full Adder in Structural
library ieee,work; And the final Example
use ieee.std_logic_1164.all;
use work.all;
entity FA_1 is
port (M,N: in std_logic;
CIN: in std_logic;
SUM,COUT: out std_logic);
end FA_1;
architecture struct of FA_1 is
signal C_W: std_logic_vector(1 downto 0); Building block
signal S_W: std_logic;
component HA is
Half Adder!!
port (A,B: in std_logic ; library ieee;
C,S: out std_logic ); use ieee.std_logic_1164.all;
end component; entity HA is
begin port (A,B:in std_logic;
HA0:HA port map (A=> CIN, B => M, C,S:out std_logic);
S=> S_W, C=> C_W(0)); end HA;
HA1: HA port map (A=> S_W, B => N, architecture DF of HA is
S=> SUM, C=> C_W(1)); begin
COUT <= C_W(1) or C_W(0); S<=A XOR B;
end struct; C<=A AND B;
end DF;
library ieee;
use ieee.std_logic_1164.all;
entity DECODER is
port( I: in std_logic_vector(1 downto 0);
O: out std_logic_vector(3 downto 0)
);
end DECODER;
end process;
end behv;
library ieee ;
use ieee.std_logic_1164.all;
use work.all;
entity dff is
port( data_in: in std_logic;
D Flip Flop
clock: in std_logic;
data_out: out std_logic
);
end dff;
process(data_in, clock)
begin
end process;
end behv;
architecture siso_arc of siso is library IEEE;
use IEEE.STD_LOGIC_1164.all;
component d_flip_flop is
port( entity siso is
clk : in STD_LOGIC; port(
din : in STD_LOGIC; din : in STD_LOGIC;
reset : in STD_LOGIC; clk : in STD_LOGIC;
dout : out STD_LOGIC reset : in STD_LOGIC;
); dout : out STD_LOGIC
end component d_flip_flop; );
end siso;
signal s : std_logic_vector(2 downto 0);
Shift
begin
Register
u0 : d_flip_flop port map (clk => clk,din => din,reset => reset,dout => s(0));
u1 : d_flip_flop port map (clk => clk,din => s(0),reset => reset,dout => s(1));
u2 : d_flip_flop port map (clk => clk,din => s(1),reset => reset,dout => s(2));
u3 : d_flip_flop port map (clk => clk,din => s(2),reset => reset,dout => dout);
end siso_arc;
library ieee;
use ieee.std_logic_1164.all; architecture behv of ALU is
use ieee.std_logic_unsigned.all; begin
use ieee.std_logic_arith.all; process(A,B,Sel)
entity ALU is begin