library ieee;

use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity feu_roug is
Port ( CLK : in std_logic;
RAZ : in std_logic;
R : out std_logic;
V : out std_logic;
O : out std_logic;
R1 : out std_logic;
V1 : out std_logic;
O1 : out std_logic);
end feu_roug;
architecture COMPORT of feu_roug is
type T_ETAT is (A0,A1,A2,A3);
signal ETAT : T_ETAT;
begin
process (CLK, RAZ)
variable CMPT : integer range 0 to 31;
begin
if RAZ='1' then CMPT := 0;
ETAT <= A0;
elsif CLK'event and CLK='1' then
CMPT := CMPT+1;
case ETAT is
when A0 =>
if CMPT = 26 then
CMPT := 0;
ETAT <= A1;
else ETAT <= A0;
end if;
when A1 =>
if CMPT = 5 then
CMPT := 0;
ETAT <= A2;
else ETAT <= A1;
end if;
when A2 =>
if CMPT = 26 then
CMPT := 0;
ETAT <= A3;
else ETAT <= A2;
end if;
when A3=>
if CMPT = 5 then
CMPT := 0;
ETAT <= A0;
else ETAT <= A3;
end if;
end case;
end if;
end process;
R <= '1' when ETAT=A0 or ETAT=A1 else '0';
V1 <= '1' when ETAT=A0 else '0';
O1 <= '1' when ETAT=A1 else '0';
R1 <= '1' when ETAT=A2 or ETAT=A3 else '0';
V <= '1' when ETAT=A2 else '0';
O <= '1' when ETAT=A3 else '0';
end COMPORT;