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Color Television Chassis

Q552.2L
LA

19111_000_110519.eps
110711

Contents Page
1. Revision List 2 11. Styling Sheets
2. Technical Specifications, Diversity, and Connections2 Blockbuster/Emmy 32" 177
3. Precautions, Notes, and Abbreviation List 5 Blockbuster/Emmy 40" - 46" 178
4. Mechanical Instructions 9 Sundance 42" - 47" 179
5. Service Modes, Error Codes, and Fault Finding 22
6. Alignments 41
7. Circuit Descriptions 48
8. IC Data Sheets 54
9. Block Diagrams
Wiring diagram Blockbuster/Emmy 32" 65
Wiring diagram Blockbuster/Emmy 40" - 46" 66
Wiring diagram Sundance 42" - 47" 67
Block Diagram Video 68
Block Diagram Audio 69
Block Diagram Control & Clock Signals 70
Block Diagram I2C 71
Supply Lines Overview 72
10. Circuit Diagrams and PWB Layouts Drawing
B01 313912365213 73
B02 313912365213 84
B03 313912365213 93
B04 313912365213 101
B05 313912365213 106
B06 313912365213 107
B09 313912365213 111
313912365213 SSB Layout 112
B01 313912365214 114
B02 313912365214 126
B03 313912365214 135
B04 313912365214 143
B05 313912365214 148
B06 313912365214 149
B09 313912365214 153
313912365214 SSB Layout 154

©
Copyright 2011 Koninklijke Philips Electronics N.V.
All rights reserved. No part of this publication may be reproduced, stored in a
retrieval system or transmitted, in any form or by any means, electronic, mechanical,
photocopying, or otherwise without the prior permission of Philips.

Published by ER/TY 1167 BU TV Consumer Care, the Netherlands Subject to modification EN 3122 785 19112
2011-Jul-15
EN 2 1. Q552.2L LA Revision List

1. Revision List
Manual xxxx xxx xxxx.0
• First release.

Manual xxxx xxx xxxx.1


• Chapter 2: Table 2-1 updated (added CTNs).
• Chapter 4: added wiring diagrams; see section 4.1.
• Chapter 7: updated power supply connector overview; see
Table 7-1.
• Chapter 7: added Ambilight; see section 7.8.

Manual xxxx xxx xxxx.2


• Chapter 2: Table 2-1 updated (added CTNs).
• Chapter 4: added wiring diagrams; see section 4.1.
• Chapter 6: added white tone values; see section 6.3.1.

2. Technical Specifications, Diversity, and Connections


Index of this chapter: 2.1 Technical Specifications
2.1 Technical Specifications
2.2 Directions for Use For on-line product support please use the CTN links in Table
2.3 Connections
2-1. Here is product information available, as well as getting
2.4 Chassis Overview
started, user manuals, frequently asked questions and
software & drivers.
Notes:
• Figures can deviate due to the different set executions.
• Specifications are indicative (subject to change).

Table 2-1 Described Model Numbers and Diversity

SSB Ambilight 2 4 7 9 10
Mechanics Descriptions Schematics

B06 (non-DVBS-LVDS)

B09 (non-DVBS-conn.)
B03 (DC/DC / Class D)
Connection Overview

E (IR/LED/Keyboard)
Assembly Removal

B02 (PNX85500)
AL1 (Ambilight)

AL3 (Ambilight)
Wiring Diagram
3139 123 xxxxx

3104 313 xxxxx

Wire Dressing

LCD Removal

B01 (Tuner)

B05 (DDR)
Dressing

B04 (I/O)
Tuner
PSU

CTN Styling
32PFL6606D/77 Blockbuster 65213 - 2.3 4-1 4.3 4.3.7 7.2 7.4.1 9-1 - - 10-1 10-2 10-3 10-4 10-5 10-6 10-7 10-17
11-1 65214 10-9 10-10 10-11 10-12 10-13 10-14 10-15
32PFL7606D/78 Emmy 65213 64833 2.3 4-2 4.3 4.3.7 7.2 7.4.1 9-1 10-21 10-23 10-1 10-2 10-3 10-4 10-5 10-6 10-7 10-18
11-1 65214 10-9 10-10 10-11 10-12 10-13 10-14 10-15
40PFL6606D/77 Blockbuster 65213 - 2.3 4-3 4.3 4.3.7 7.2 7.4.1 9-2 - - 10-1 10-2 10-3 10-4 10-5 10-6 10-7 10-17
11-2 65214 10-9 10-10 10-11 10-12 10-13 10-14 10-15
40PFL6606D/78 Blockbuster 65213 - 2.3 4-3 4.3 4.3.7 7.2 7.4.1 9-2 - - 10-1 10-2 10-3 10-4 10-5 10-6 10-7 10-17
11-2 65214 10-9 10-10 10-11 10-12 10-13 10-14 10-15
40PFL7606D/77 Emmy 65213 64853 2.3 4-4 4.3 4.3.7 7.2 7.4.1 9-2 10-21 10-24 10-1 10-2 10-3 10-4 10-5 10-6 10-7 10-18
11-2 65214 10-9 10-10 10-11 10-12 10-13 10-14 10-15
40PFL7606D/78 Emmy 65214 64853 2.3 4-4 4.3 4.3.7 7.2 7.4.1 9-2 10-21 10-24 10-9 10-10 10-11 10-12 10-13 10-14 10-15 10-18
11-2
42PFL8606D/77 Sundance 65214 64853 2.3 4-5 4.4 4.4.8 7.2 7.4.1 9-3 10-22 10-26 10-9 10-10 10-11 10-12 10-13 10-14 10-15 10-20
11-3
42PFL8606D/78 Sundance 65214 64853 2.3 4-5 4.4 4.4.8 7.2 7.4.1 9-3 10-22 10-26 10-9 10-10 10-11 10-12 10-13 10-14 10-15 10-20
11-3
46PFL7606D/77 Emmy 65214 64873 2.3 4-6 4.3 4.3.7 7.2 7.4.1 9-2 10-21 10-25 10-9 10-10 10-11 10-12 10-13 10-14 10-15 10-19
11-2
46PFL7606D/78 Emmy 65213 64873 2.3 4-6 4.3 4.3.7 7.2 7.4.1 9-2 10-21 10-25 10-1 10-2 10-3 10-4 10-5 10-6 10-7 10-19
11-2 65214 10-9 10-10 10-11 10-12 10-13 10-14 10-15
47PFL8606D/78 Sundance 65214 64812 2.3 4-7 4.4 4.4.8 7.2 7.4.1 9-3 10-22 10-27 10-9 10-10 10-11 10-12 10-13 10-14 10-15 10-20
11-3

2.2 Directions for Use

You can download this information from the following websites:


http://www.philips.com/support
http://www.p4c.philips.com

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Technical Specifications, Diversity, and Connections Q552.2L LA 2. EN 3

2.3 Connections

REAR CONNECTORS SIDE CONNECTORS


1

2
10
13
3 (optional)

3 11
4

BOTTOM REAR CONNECTORS 11 (optional)


5 6 7 7 7 8 9

12

(3) (2) (1) ARC


HDMI
(optional)
19110_051_110421.eps
110716

Figure 2-1 Connection overview

Note: The following connector colour abbreviations are used 2.3.2 Rear Connections - Bottom
(acc. to DIN/IEC 757): Bk= Black, Bu= Blue, Gn= Green, Gy=
Grey, Rd= Red, Wh= White, Ye= Yellow. 5 - RJ45: Ethernet

2.3.1 Rear Connections 12345678

1 - CVI: Cinch: Video YPbPr - In, Audio - In


Gn - Video Y 1 VPP / 75 ohm jq 10000_025_090121.eps
Bu - Video Pb 0.7 VPP / 75 ohm jq 090121
Rd - Video Pr 0.7 VPP / 75 ohm jq
Figure 2-2 Ethernet connector
Rd - Audio - R 0.5 VRMS / 10 kohm jq
Wh - Audio - L 0.5 VRMS / 10 kohm jq
1 - TD+ Transmit signal k
2 - TD- Transmit signal k
2 - Service Connector (UART)
3 - RD+ Receive signal j
1 - Ground Gnd H
4 - CT Centre Tap: DC level fixation
2 - UART_TX Transmit k
5 - CT Centre Tap: DC level fixation
3 - UART_RX Receive j
6 - RD- Receive signal j
7 - GND Gnd H
3 - Cinch: Audio - In (VGA/DVI) 8 - GND Gnd H
Rd - Audio R 0.5 VRMS / 10 kohm jq
Wh - Audio L 0.5 VRMS / 10 kohm jq
6 - Cinch: S/PDIF - Out
Bk - Coaxial 0.4 - 0.6VPP / 75 ohm kq
4 - AV IN: Cinch: Video CVBS - In, Audio - In
Rd - Audio R 0.5 VRMS / 10 kohm jq
7 - HDMI 2: Digital Video, Digital Audio - In
Wh - Audio L 0.5 VRMS / 10 kohm jq
Ye - Video CVBS 1 VPP / 75 ohm jq 19 1
18 2

13 - Head phone (Output) (optional) 10000_017_090121.eps


090428
Bk - Head phone 32 - 600 ohm / 10 mW ot
Figure 2-3 HDMI (type A) connector

1 - D2+ Data channel j


2 - Shield Gnd H
3 - D2- Data channel j
4 - D1+ Data channel j
5 - Shield Gnd H
6 - D1- Data channel j
7 - D0+ Data channel j
8 - Shield Gnd H

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EN 4 2. Q552.2L LA Technical Specifications, Diversity, and Connections

9 - D0- Data channel j 10 - Ground Sync Gnd H


10 - CLK+ Data channel j 11 - n.c.
11 - Shield Gnd H 12 - DDC_SDA DDC data j
12 - CLK- Data channel j 13 - H-sync 0-5V j
13 - Easylink/CEC Control channel jk 14 - V-sync 0-5V j
14 - n.c. 15 - DDC_SCL DDC clock j
15 - DDC_SCL DDC clock j
16 - DDC_SDA DDC data jk 2.3.3 Side Connections
17 - Ground Gnd H
18 - +5V j
10 - SD-Card: Secure Digital Card - In/Out (optional)
19 - HPD Hot Plug Detect j
14
20 - Ground Gnd H GND
WP 12
7 - HDMI 1: Digital Video - In, Digital Audio with ARC - In/ GND 11
Out CD 10
19 1 8 DAT1/IRQ
18 2
7 DAT0/D0
10000_017_090121.eps 6 GND2
090428
5 CLOCK

Figure 2-4 HDMI (type A) connector 4 VDD


3 GND1
2 CMD/DI
1 - D2+ Data channel j
2 - Shield Gnd H 1 DAT3/CS

3 - D2- Data channel j 9 DAT2/NC

4 - D1+ Data channel j GND


5 - Shield Gnd H 13
10000_049_100210.eps
6 - D1- Data channel j 100210
7 - D0+ Data channel j
8 - Shield Gnd H Figure 2-6 SD-Card connector
9 - D0- Data channel j
10 - CLK+ Data channel j 1 - DAT3/CS Signal jk
11 - Shield Gnd H 2 - CMD/DI Signal k
12 - CLK- Data channel j 3 - GND1 Gnd H
13 - Easylink/CEC Control channel jk 4 - Vdd Supply k
14 - ARC Audio Return Channel k 5 - CLOCK Signal k
15 - DDC_SCL DDC clock j 6 - GND2 Gnd H
16 - DDC_SDA DDC data jk 7 - DAT0/D0 Signal jk
17 - Ground Gnd H 8 - DAT1/IRQ Signal jk
18 - +5V j 9 - DAT2/NC Signal jk
19 - HPD Hot Plug Detect j 10 - CD Signal j
20 - Ground Gnd H 11 - GND Gnd H
12 - WP Signal j
8 - Aerial - In 13 - GND Gnd H
- - F-type Coax, 75 ohm D 14 - GND Gnd H

9 - VGA: Video RGB - In 11 - USB2.0


1 5
10
6
11 15 1 2 3 4
10000_002_090121.eps 10000_022_090121.eps
090127 090121

Figure 2-5 VGA Connector Figure 2-7 USB (type A)

1 - Video Red 0.7 VPP / 75 ohm j 1 - +5V k


2 - Video Green 0.7 VPP / 75 ohm j 2 - Data (-) jk
3 - Video Blue 0.7 VPP / 75 ohm j 3 - Data (+) jk
4 - n.c. 4 - Ground Gnd H
5 - Ground Gnd H
6 - Ground Red Gnd H 12- HDMI : Digital Video, Digital Audio - In
7 - Ground Green Gnd H See 7 - HDMI 2: Digital Video, Digital Audio - In
8 - Ground Blue Gnd H
9 - +5VDC +5 V j

2.4 Chassis Overview

Refer to chapter Block Diagrams for PWB/CBA locations.

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Precautions, Notes, and Abbreviation List Q552.2L LA 3. EN 5

3. Precautions, Notes, and Abbreviation List


Index of this chapter: • Where necessary, measure the waveforms and voltages
3.1 Safety Instructions with (D) and without (E) aerial signal. Measure the
3.2 Warnings voltages in the power supply section both in normal
3.3 Notes operation (G) and in stand-by (F). These values are
3.4 Abbreviation List indicated by means of the appropriate symbols.

3.3.2 Schematic Notes


3.1 Safety Instructions
• All resistor values are in ohms, and the value multiplier is
Safety regulations require the following during a repair:
often used to indicate the decimal point location (e.g. 2K2
• Connect the set to the Mains/AC Power via an isolation
indicates 2.2 k:).
transformer (> 800 VA).
• Resistor values with no multiplier may be indicated with
• Replace safety components, indicated by the symbol h,
either an “E” or an “R” (e.g. 220E or 220R indicates 220 :).
only by components identical to the original ones. Any
• All capacitor values are given in micro-farads (P u10-6),
other component substitution (other than original type) may
nano-farads (n u10-9), or pico-farads (p u10-12).
increase risk of fire or electrical shock hazard.
• Capacitor values may also use the value multiplier as the
decimal point indication (e.g. 2p2 indicates 2.2 pF).
Safety regulations require that after a repair, the set must be
• An “asterisk” (*) indicates component usage varies. Refer
returned in its original condition. Pay in particular attention to
to the diversity tables for the correct values.
the following points:
• The correct component values are listed on the Philips
• Route the wire trees correctly and fix them with the
Spare Parts Web Portal.
mounted cable clamps.
• Check the insulation of the Mains/AC Power lead for
external damage. 3.3.3 Spare Parts
• Check the strain relief of the Mains/AC Power cord for
proper function. For the latest spare part overview, consult your Philips Spare
• Check the electrical DC resistance between the Mains/AC Part web portal.
Power plug and the secondary side (only for sets that have
a Mains/AC Power isolated power supply): 3.3.4 BGA (Ball Grid Array) ICs
1. Unplug the Mains/AC Power cord and connect a wire
between the two pins of the Mains/AC Power plug. Introduction
2. Set the Mains/AC Power switch to the “on” position For more information on how to handle BGA devices, visit this
(keep the Mains/AC Power cord unplugged!). URL: http://www.atyourservice-magazine.com. Select
3. Measure the resistance value between the pins of the “Magazine”, then go to “Repair downloads”. Here you will find
Mains/AC Power plug and the metal shielding of the Information on how to deal with BGA-ICs.
tuner or the aerial connection on the set. The reading
should be between 4.5 M: and 12 M:.
BGA Temperature Profiles
4. Switch “off” the set, and remove the wire between the
For BGA-ICs, you must use the correct temperature-profile.
two pins of the Mains/AC Power plug.
Where applicable and available, this profile is added to the IC
• Check the cabinet for defects, to prevent touching of any
Data Sheet information section in this manual.
inner parts by the customer.

3.3.5 Lead-free Soldering


3.2 Warnings
Due to lead-free technology some rules have to be respected
• All ICs and many other semiconductors are susceptible to by the workshop during a repair:
electrostatic discharges (ESD w). Careless handling • Use only lead-free soldering tin. If lead-free solder paste is
during repair can reduce life drastically. Make sure that, required, please contact the manufacturer of your soldering
during repair, you are connected with the same potential as equipment. In general, use of solder paste within
the mass of the set by a wristband with resistance. Keep workshops should be avoided because paste is not easy to
components and tools also at this same potential. store and to handle.
• Be careful during measurements in the high voltage • Use only adequate solder tools applicable for lead-free
section. soldering tin. The solder tool must be able:
• Never replace modules or other components while the unit – To reach a solder-tip temperature of at least 400°C.
is switched “on”. – To stabilize the adjusted temperature at the solder-tip.
• When you align the set, use plastic rather than metal tools. – To exchange solder-tips for different applications.
This will prevent any short circuits and the danger of a • Adjust your solder tool so that a temperature of around
circuit becoming unstable. 360°C - 380°C is reached and stabilized at the solder joint.
Heating time of the solder-joint should not exceed ~ 4 sec.
Avoid temperatures above 400°C, otherwise wear-out of
3.3 Notes tips will increase drastically and flux-fluid will be destroyed.
To avoid wear-out of tips, switch “off” unused equipment or
3.3.1 General reduce heat.
• Mix of lead-free soldering tin/parts with leaded soldering
• Measure the voltages and waveforms with regard to the tin/parts is possible but PHILIPS recommends strongly to
chassis (= tuner) ground (H), or hot ground (I), depending avoid mixed regimes. If this cannot be avoided, carefully
on the tested area of circuitry. The voltages and waveforms clear the solder-joint from old tin and re-solder with new tin.
shown in the diagrams are indicative. Measure them in the
Service Default Mode with a colour bar signal and stereo 3.3.6 Alternative BOM identification
sound (L: 3 kHz, R: 1 kHz unless stated otherwise) and
picture carrier at 475.25 MHz for PAL, or 61.25 MHz for It should be noted that on the European Service website,
NTSC (channel 3). “Alternative BOM” is referred to as “Design variant”.
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EN 6 3. Q552.2L LA Precautions, Notes, and Abbreviation List

The third digit in the serial number (example: 3.4 Abbreviation List
AG2B0335000001) indicates the number of the alternative
B.O.M. (Bill Of Materials) that has been used for producing the 0/6/12 SCART switch control signal on A/V
specific TV set. In general, it is possible that the same TV
board. 0 = loop through (AUX to TV),
model on the market is produced with e.g. two different types
6 = play 16 : 9 format, 12 = play 4 : 3
of displays, coming from two different suppliers. This will then format
result in sets which have the same CTN (Commercial Type
AARA Automatic Aspect Ratio Adaptation:
Number; e.g. 28PW9515/12) but which have a different B.O.M.
algorithm that adapts aspect ratio to
number. remove horizontal black bars; keeps
By looking at the third digit of the serial number, one can
the original aspect ratio
identify which B.O.M. is used for the TV set he is working with.
ACI Automatic Channel Installation:
If the third digit of the serial number contains the number “1” algorithm that installs TV channels
(example: AG1B033500001), then the TV set has been
directly from a cable network by
manufactured according to B.O.M. number 1. If the third digit is
means of a predefined TXT page
a “2” (example: AG2B0335000001), then the set has been ADC Analogue to Digital Converter
produced according to B.O.M. no. 2. This is important for
AFC Automatic Frequency Control: control
ordering the correct spare parts!
signal used to tune to the correct
For the third digit, the numbers 1...9 and the characters A...Z frequency
can be used, so in total: 9 plus 26= 35 different B.O.M.s can be
AGC Automatic Gain Control: algorithm that
indicated by the third digit of the serial number.
controls the video input of the feature
box
Identification: The bottom line of a type plate gives a 14-digit
AM Amplitude Modulation
serial number. Digits 1 and 2 refer to the production centre (e.g.
AP Asia Pacific
SN is Lysomice, RJ is Kobierzyce), digit 3 refers to the B.O.M. AR Aspect Ratio: 4 by 3 or 16 by 9
code, digit 4 refers to the Service version change code, digits 5
ASF Auto Screen Fit: algorithm that adapts
and 6 refer to the production year, and digits 7 and 8 refer to
aspect ratio to remove horizontal black
production week (in example below it is 2010 week 10 / 2010 bars without discarding video
week 17). The 6 last digits contain the serial number.
information
ATSC Advanced Television Systems
Committee, the digital TV standard in
the USA
ATV See Auto TV
Auto TV A hardware and software control
system that measures picture content,
and adapts image parameters in a
dynamic way
AV External Audio Video
AVC Audio Video Controller
AVIP Audio Video Input Processor
B/G Monochrome TV system. Sound
carrier distance is 5.5 MHz
BDS Business Display Solutions (iTV)
BLR Board-Level Repair
BTSC Broadcast Television Standard
Committee. Multiplex FM stereo sound
system, originating from the USA and
used e.g. in LATAM and AP-NTSC
countries
B-TXT Blue TeleteXT
10000_053_110228.eps
110228
C Centre channel (audio)
CEC Consumer Electronics Control bus:
Figure 3-1 Serial number (example) remote control bus on HDMI
connections
3.3.7 Board Level Repair (BLR) or Component Level Repair CL Constant Level: audio output to
(CLR) connect with an external amplifier
CLR Component Level Repair
If a board is defective, consult your repair procedure to decide ComPair Computer aided rePair
if the board has to be exchanged or if it should be repaired on CP Connected Planet / Copy Protection
component level. CSM Customer Service Mode
If your repair procedure says the board should be exchanged CTI Color Transient Improvement:
completely, do not solder on the defective board. Otherwise, it manipulates steepness of chroma
cannot be returned to the O.E.M. supplier for back charging! transients
CVBS Composite Video Blanking and
3.3.8 Practical Service Precautions Synchronization
DAC Digital to Analogue Converter
• It makes sense to avoid exposure to electrical shock. DBE Dynamic Bass Enhancement: extra
While some sources are expected to have a possible low frequency amplification
dangerous impact, others of quite high potential are of DCM Data Communication Module. Also
limited current and are sometimes held in less regard. referred to as System Card or
• Always respect voltages. While some may not be Smartcard (for iTV).
dangerous in themselves, they can cause unexpected DDC See “E-DDC”
reactions that are best avoided. Before reaching into a D/K Monochrome TV system. Sound
powered TV set, it is best to test the high voltage insulation. carrier distance is 6.5 MHz
It is easy to do, and is a good service precaution. DFI Dynamic Frame Insertion

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Precautions, Notes, and Abbreviation List Q552.2L LA 3. EN 7

DFU Directions For Use: owner's manual SDI), is a digitized video format used
DMR Digital Media Reader: card reader for broadcast grade video.
DMSD Digital Multi Standard Decoding Uncompressed digital component or
DNM Digital Natural Motion digital composite signals can be used.
DNR Digital Noise Reduction: noise The SDI signal is self-synchronizing,
reduction feature of the set uses 8 bit or 10 bit data words, and has
DRAM Dynamic RAM a maximum data rate of 270 Mbit/s,
DRM Digital Rights Management with a minimum bandwidth of 135
DSP Digital Signal Processing MHz.
DST Dealer Service Tool: special remote iTV Institutional TeleVision; TV sets for
control designed for service hotels, hospitals etc.
technicians LS Last Status; The settings last chosen
DTCP Digital Transmission Content by the customer and read and stored
Protection; A protocol for protecting in RAM or in the NVM. They are called
digital audio/video content that is at start-up of the set to configure it
traversing a high speed serial bus, according to the customer's
such as IEEE-1394 preferences
DVB-C Digital Video Broadcast - Cable LATAM Latin America
DVB-T Digital Video Broadcast - Terrestrial LCD Liquid Crystal Display
DVD Digital Versatile Disc LED Light Emitting Diode
DVI(-d) Digital Visual Interface (d= digital only) L/L' Monochrome TV system. Sound
E-DDC Enhanced Display Data Channel carrier distance is 6.5 MHz. L' is Band
(VESA standard for communication I, L is all bands except for Band I
channel and display). Using E-DDC, LPL LG.Philips LCD (supplier)
the video source can read the EDID LS Loudspeaker
information form the display. LVDS Low Voltage Differential Signalling
EDID Extended Display Identification Data Mbps Mega bits per second
(VESA standard) M/N Monochrome TV system. Sound
EEPROM Electrically Erasable and carrier distance is 4.5 MHz
Programmable Read Only Memory MHEG Part of a set of international standards
EMI Electro Magnetic Interference related to the presentation of
EPG Electronic Program Guide multimedia information, standardised
EPLD Erasable Programmable Logic Device by the Multimedia and Hypermedia
EU Europe Experts Group. It is commonly used as
EXT EXTernal (source), entering the set by a language to describe interactive
SCART or by cinches (jacks) television services
FDS Full Dual Screen (same as FDW) MIPS Microprocessor without Interlocked
FDW Full Dual Window (same as FDS) Pipeline-Stages; A RISC-based
FLASH FLASH memory microprocessor
FM Field Memory or Frequency MOP Matrix Output Processor
Modulation MOSFET Metal Oxide Silicon Field Effect
FPGA Field-Programmable Gate Array Transistor, switching device
FTV Flat TeleVision MPEG Motion Pictures Experts Group
Gb/s Giga bits per second MPIF Multi Platform InterFace
G-TXT Green TeleteXT MUTE MUTE Line
H H_sync to the module MTV Mainstream TV: TV-mode with
HD High Definition Consumer TV features enabled (iTV)
HDD Hard Disk Drive NC Not Connected
HDCP High-bandwidth Digital Content NICAM Near Instantaneous Compounded
Protection: A “key” encoded into the Audio Multiplexing. This is a digital
HDMI/DVI signal that prevents video sound system, mainly used in Europe.
data piracy. If a source is HDCP coded NTC Negative Temperature Coefficient,
and connected via HDMI/DVI without non-linear resistor
the proper HDCP decoding, the NTSC National Television Standard
picture is put into a “snow vision” mode Committee. Color system mainly used
or changed to a low resolution. For in North America and Japan. Color
normal content distribution the source carrier NTSC M/N= 3.579545 MHz,
and the display device must be NTSC 4.43= 4.433619 MHz (this is a
enabled for HDCP “software key” VCR norm, it is not transmitted off-air)
decoding. NVM Non-Volatile Memory: IC containing
HDMI High Definition Multimedia Interface TV related data such as alignments
HP HeadPhone O/C Open Circuit
I Monochrome TV system. Sound OSD On Screen Display
carrier distance is 6.0 MHz OAD Over the Air Download. Method of
I2 C Inter IC bus software upgrade via RF transmission.
I2 D Inter IC Data bus Upgrade software is broadcasted in
I2 S Inter IC Sound bus TS with TV channels.
IF Intermediate Frequency OTC On screen display Teletext and
IR Infra Red Control; also called Artistic (SAA5800)
IRQ Interrupt Request P50 Project 50: communication protocol
ITU-656 The ITU Radio communication Sector between TV and peripherals
(ITU-R) is a standards body PAL Phase Alternating Line. Color system
subcommittee of the International mainly used in West Europe (colour
Telecommunication Union relating to carrier = 4.433619 MHz) and South
radio communication. ITU-656 (a.k.a. America (colour carrier

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EN 8 3. Q552.2L LA Precautions, Notes, and Abbreviation List

PAL M = 3.575612 MHz and SVGA 800 × 600 (4:3)


PAL N = 3.582056 MHz) SVHS Super Video Home System
PCB Printed Circuit Board (same as “PWB”) SW Software
PCM Pulse Code Modulation SWAN Spatial temporal Weighted Averaging
PDP Plasma Display Panel Noise reduction
PFC Power Factor Corrector (or Pre- SXGA 1280 × 1024
conditioner) TFT Thin Film Transistor
PIP Picture In Picture THD Total Harmonic Distortion
PLL Phase Locked Loop. Used for e.g. TMDS Transmission Minimized Differential
FST tuning systems. The customer Signalling
can give directly the desired frequency TS Transport Stream
POD Point Of Deployment: a removable TXT TeleteXT
CAM module, implementing the CA TXT-DW Dual Window with TeleteXT
system for a host (e.g. a TV-set) UI User Interface
POR Power On Reset, signal to reset the uP uP Microprocessor
PSDL Power Supply for Direct view LED UXGA 1600 × 1200 (4:3)
backlight with 2D-dimming V V-sync to the module
PSL Power Supply with integrated LED VESA Video Electronics Standards
drivers Association
PSLS Power Supply with integrated LED VGA 640 × 480 (4:3)
drivers with added Scanning VL Variable Level out: processed audio
functionality output toward external amplifier
PTC Positive Temperature Coefficient, VSB Vestigial Side Band; modulation
non-linear resistor method
PWB Printed Wiring Board (same as “PCB”) WYSIWYR What You See Is What You Record:
PWM Pulse Width Modulation record selection that follows main
QRC Quasi Resonant Converter picture and sound
QTNR Quality Temporal Noise Reduction WXGA 1280 × 768 (15:9)
QVCP Quality Video Composition Processor XTAL Quartz crystal
RAM Random Access Memory XGA 1024 × 768 (4:3)
RGB Red, Green, and Blue. The primary Y Luminance signal
color signals for TV. By mixing levels Y/C Luminance (Y) and Chrominance (C)
of R, G, and B, all colors (Y/C) are signal
reproduced. YPbPr Component video. Luminance and
RC Remote Control scaled color difference signals (B-Y
RC5 / RC6 Signal protocol from the remote and R-Y)
control receiver YUV Component video
RESET RESET signal
ROM Read Only Memory
RSDS Reduced Swing Differential Signalling
data interface
R-TXT Red TeleteXT
SAM Service Alignment Mode
S/C Short Circuit
SCART Syndicat des Constructeurs
d'Appareils Radiorécepteurs et
Téléviseurs
SCL Serial Clock I2C
SCL-F CLock Signal on Fast I2C bus
SD Standard Definition
SDA Serial Data I2C
SDA-F DAta Signal on Fast I2C bus
SDI Serial Digital Interface, see “ITU-656”
SDRAM Synchronous DRAM
SECAM SEequence Couleur Avec Mémoire.
Colour system mainly used in France
and East Europe. Colour
carriers = 4.406250 MHz and
4.250000 MHz
SIF Sound Intermediate Frequency
SMPS Switched Mode Power Supply
SoC System on Chip
SOG Sync On Green
SOPS Self Oscillating Power Supply
SPI Serial Peripheral Interface bus; a 4-
wire synchronous serial data link
standard
S/PDIF Sony Philips Digital InterFace
SRAM Static RAM
SRP Service Reference Protocol
SSB Small Signal Board
SSC Spread Spectrum Clocking, used to
reduce the effects of EMI
STB Set Top Box
STBY STand-BY

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Mechanical Instructions Q552.2L LA 4. EN 9

4. Mechanical Instructions
Index of this chapter: Notes:
4.1 Cable Dressing • Figures below can deviate slightly from the actual situation,
4.2 Service Positions due to the different set executions.
4.3 Assy/Panel Removal Blockbuster/Emmy Styling (xxPFL6/
7xxx/xx series)
4.4 Assy/Panel Removal Sundance Styling (xxPFL8xxx/xx
series)
4.5 Set Re-assembly

4.1 Cable Dressing

Tape (150 m.m.) 2 ×


Tape (80 m.m.) 9 ×
Clamp (11 m.m.) 2 ×

19111_012_110519.eps
110519

Figure 4-1 Cable dressing 32PFL6606D/7x (Blockbuster)

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EN 10 4. Q552.2L LA Mechanical Instructions

Tape (150 m.m.) 4 ×


Tape (80 m.m.) 15 ×
Clamp (11 m.m.) 2 ×
19111_016_110520.eps
110520

Figure 4-2 Cable dressing 32PFL7606D/7x (Emmy)

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Mechanical Instructions Q552.2L LA 4. EN 11

Tape (150 m.m.) 1 ×


Tape (80 m.m.) 6 ×
Tape (50 m.m.) 2 ×
Clamp (11 m.m.) 2 ×
Stick-on Clamp 1 ×
19111_013_110519.eps
110519

Figure 4-3 Cable dressing 40PFL6606D/7x (Blockbuster)

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EN 12 4. Q552.2L LA Mechanical Instructions

Tape (150 m.m.) 3 ×


Tape (80 m.m.) 16 ×
Tape (50 m.m.) 2 ×
Clamp (11 m.m.) 2 ×
Stick-on Clamp 1 ×
19111_014_110519.eps
110519

Figure 4-4 Cable dressing 40PFL7606D/7x (Emmy)

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Mechanical Instructions Q552.2L LA 4. EN 13

19112_100_110712.eps
110712

Figure 4-5 Cable dressing 42PFL8606D/7x (Sundance)

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EN 14 4. Q552.2L LA Mechanical Instructions

Tape (150 m.m.) 5 ×


Tape (80 m.m.) 16 ×
Clamp (11 m.m.) 2 ×
Stick-on Clamp 1 ×
19111_015_110519.eps
110519

Figure 4-6 Cable dressing 46PFL7606D/7x (Emmy)

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Mechanical Instructions Q552.2L LA 4. EN 15

19112_101_110712.eps
110712

Figure 4-7 Cable dressing 47PFL8606D/7x (Sundance)

4.2 Service Positions Note: it is not necessary to remove the stand while removing
the rear cover.
For easy servicing of a TV set, the set should be put face down
on a soft flat surface, foam buffers or other specific workshop 1. Remove all screws of the rear cover.
tools. Ensure that a stable situation is created to perform 2. Lift the rear cover from the TV. Make sure that wires and
measurements and alignments. When using foam bars take flat coils are not damaged while lifting the rear cover from
care that these always support the cabinet and never only the the set.
display. Caution: Failure to follow these guidelines can
seriously damage the display! Additional instructions 40" and 46" sets
Ensure that ESD safe measures are taken. 40"and 46" sets have a dedicated method to open the bottom
catches when removing the rear cover.
Refer to Figure 4-8 and Figure 4-9 for details.
4.3 Assy/Panel Removal Blockbuster/Emmy
Styling (xxPFL6/7xxx/xx series)

For the 40" and 46" sets, additional instructions (rear cover
removal) apply. Refer to subsection Additional instructions 40"
and 46" sets.

The instructions apply to the 37PFL6606H/12 (Blockbuster -


European model) - without Ambilight. At time of publishing of
this manual, no data was available for the Ambilight models 1 1
(series xxPFL7606D/xx - Emmy).
19100_048_110216.eps
110216
4.3.1 Rear Cover
Figure 4-8 Bottom catches 40" and 46" sets -1-
Warning: Disconnect the mains power cord before you remove
the rear cover.

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EN 16 4. Q552.2L LA Mechanical Instructions

2 2
1

1
2

19100_049_110216.eps
110216

2 2
Figure 4-9 Bottom catches 40" and 46" sets -2-

It is advised to lay the set with front facing down before


19101_008_110407.eps
executing this operation. 110407
1. Remove all screws from the rear cover.
2. Use a round rod (diameter 2 mm) and insert it in one of the Figure 4-11 Main Power Supply
holes [1].
3. Push the catch located inside the rear cover away by 1. Unplug all connectors [1].
inserting the rod [2] through the hole and lifting the rear 2. Remove the fixation screws [2].
cover at the same time. 3. Take the board out.
4. Repeat the same procedure on the other hole. When defective, replace the whole unit.

4.3.2 Speakers 4.3.5 Small Signal Board (SSB)

Tweeters Refer to Figure 4-12 for details.


Each tweeter unit is mounted with two screws.
When defective, replace the whole unit.

Subwoofer
The central subwoofer is located in the centre of the set and is
secured by two bosses.
When defective, replace the whole unit. 2 2
1
4.3.3 Mains Switch

Refer to Figure 4-10 for details.


2 2

2 2

19101_007_110407.eps
110407

Figure 4-12 SSB


19100_047_110216.eps
110216
1. Unplug all connectors [1].
Figure 4-10 Mains switch 2. Remove the fixation screws [2].
3. Take the board out.
The mains switch is mounted on a plastic subframe and can be When remounting, ensure that the side shielding is positioned
removed without removing the subframe. correctly.
1. Use a screwdriver and push the switch out of its casing [1].
2. Unplug the connectors. 4.3.6 Keyboard Control, IR & LED Board
When defective, replace the whole unit.
Refer to Figure 4-13 and Figure 4-14 for details.
4.3.4 Main Power Supply

Refer to Figure 4-11 for details.

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Mechanical Instructions Q552.2L LA 4. EN 17

1. Remove the stand [1].


2. Remove the stand subframe [2].
3. Remove the screws [3], unplug the connector and take the
1 1 board out.
When defective, replace the whole unit.

1 1 4.3.7 LCD Panel

19101_009_110407.eps Refer to Figure 4-15 to Figure 4-17 for details.


110407

Figure 4-13 Keyboard control, IR & LED board [1/2] 1. Remove the SSB as described earlier.
2. Remove the PSU as described earlier.
3. Remove the tweeters with their subframes and subwoofer
as described earlier.
4. Remove the stand and -subframe as described earlier.
2 5. Remove the cables [1].
2 6. Remove the mains switch subframe [2].
7. Remove the keyboard control-, and IR & LED board as
described earlier.
8. Remove all remaining cables and subframes.
9. Use a screwdriver to release the catches [3] that secure the
panel.
10. Use a screwdriver to release the catches and remove the
sidewings [4] that secure the panel.
2 2 11. Take the panel out.
2 3 3 2 Remove the clamps from the panel before sending the panel in
for Service.

19101_006_110407.eps
110407

Figure 4-14 Keyboard control, IR & LED board [2/2]

19101_005_110407.eps
110407

Figure 4-15 LCD panel [1/3]

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EN 18 4. Q552.2L LA Mechanical Instructions

When defective, replace the whole unit.

Subwoofer
3 The central subwoofer is located in the centre of the set and is
secured by two bosses.
When defective, replace the whole unit.

4.4.3 Mains Switch

Refer to Figure 4-18 for details.

19101_004_110407.eps
110407

Figure 4-16 LCD panel [2/3] 1

19100_047_110216.eps
110216

Figure 4-18 Mains switch

The mains switch is mounted on a plastic subframe and can be


removed without removing the subframe.
1. Use a screwdriver and push the switch out of its casing [1].
2. Unplug the connectors.
When defective, replace the whole unit.
4
4.4.4 Main Power Supply

Refer to Figure 4-19 for details.

19101_003_110407.eps
110407
2 2

Figure 4-17 LCD panel [3/3]


1

4.4 Assy/Panel Removal Sundance Styling


(xxPFL8xxx/xx series)

The instructions apply to the 32PFL7406K/02 - European


model.
2 2

4.4.1 Rear Cover 1

Warning: Disconnect the mains power cord before you remove


19100_050_110216.eps
the rear cover. 110216
Note: it is not necessary to remove the stand while removing
the rear cover. Figure 4-19 Main Power Supply

1. Remove all screws of the rear cover. 1. Unplug all connectors [1].
2. Lift the rear cover from the TV. Make sure that wires and 2. Remove the fixation screws [2].
flat coils are not damaged while lifting the rear cover from 3. Take the board out.
the set. When defective, replace the whole unit.

4.4.2 Speakers 4.4.5 Small Signal Board (SSB)

Tweeters Refer to Figure 4-20 for details.


Each tweeter unit is mounted with one screw.

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Mechanical Instructions Q552.2L LA 4. EN 19

3. Remove the screws [3] and take the board out.


When defective, replace the whole unit.

4.4.7 Ambilight Units

The Ambilight units can be lifted from the subframes without


2 2 the use of tools.
1 Refer to Figure 4-23 for details.

2 2

2 2 1

19100_051_110216.eps
110216

Figure 4-20 SSB

1. Unplug all connectors [1]. 19100_054_110216.eps


2. Remove the fixation screws [2]. 110216
3. Take the board out.
When remounting, ensure that the side shielding is positioned Figure 4-23 Ambilight units
correctly.
1. Unplug the connector [1].
4.4.6 Keyboard Control, IR & LED Board 2. Carefully lift the board [2] and take the board out.
When defective, replace the whole unit.
Refer to Figure 4-21 and Figure 4-22 for details.

1 1
1

1
1 1

19100_052_110216.eps
110216

Figure 4-21 Keyboard control, IR & LED board [1/2]

3
2 2 2

19100_053_110216.eps
110216

Figure 4-22 Keyboard control, IR & LED board [2/2]

1. Remove the stand and the plastic support [1].


2. Unplug the connector [2].

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EN 20 4. Q552.2L LA Mechanical Instructions

4.4.8 LCD Panel

Refer to Figure 4-24 and Figure 4-25 for details.

4 4 4

2 2

1
4 4 4 4
2 2

19100_055_110216.eps
110216

Figure 4-24 LCD panel [1/2]

1. Remove the SSB as described earlier.


2. Remove the PSU as described earlier.
3. Remove the tweeters with their subframes and subwoofer
as described earlier.
4. Remove the stand and -support as described earlier.
5. Remove the cables [1].
6. Remove the stand subframe [2].
7. Remove the mains switch subframe [3].
8. Remove the Ambilight units together with their subframes
as described earlier.
9. Unplug the connector from the keyboard control-, and IR &
4
LED board as described earlier.
10. Remove all remaining cables and subframes. 19100_056_110217.eps
11. Use a screwdriver to release the clamps [4] that secure the 110217
panel and take the panel out.
Remove the clamps from the panel before sending the panel in Figure 4-25 LCD panel [2/2]
for Service.

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Mechanical Instructions Q552.2L LA 4. EN 21

4.5 Set Re-assembly

To re-assemble the whole set, execute all processes in reverse


order.

Notes:
• While re-assembling, make sure that all cables are placed
and connected in their original position.
• Pay special attention not to damage the EMC foams in the
set. Ensure that EMC foams are mounted correctly.

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EN 22 5. Q552.2L LA Service Modes, Error Codes, and Fault Finding

5. Service Modes, Error Codes, and Fault Finding


Index of this chapter: • All service-unfriendly modes (if present) are disabled, like:
5.1 Test Points – (Sleep) timer.
5.2 Service Modes – Child/parental lock.
5.3 Stepwise Start-up – Picture mute (blue mute or black mute).
5.4 Service Tools – Automatic volume levelling (AVL).
5.5 Error Codes – Skip/blank of non-favorite pre-sets.
5.6 The Blinking LED Procedure
5.7 Protections How to Activate SDM
5.8 Fault Finding and Repair Tips For this chassis there are two kinds of SDM: an analogue SDM
5.9 Software Upgrading and a digital SDM. Tuning will happen according Table 5-1.
• Analogue SDM: use the standard RC-transmitter and key
in the code “062596”, directly followed by the “MENU” (or
5.1 Test Points
“HOME”) button.
Note: It is possible that, together with the SDM, the main
As most signals are digital, it will be difficult to measure menu will appear. To switch it “off”, push the “MENU” (or
waveforms with a standard oscilloscope. However, several key "HOME") button again.
ICs are capable of generating test patterns, which can be Analogue SDM can also be activated by grounding for a
controlled via ComPair. In this way it is possible to determine moment the solder path on the SSB, with the indication
which part is defective. “SDM” (see Service mode pad).
• Digital SDM: use the standard RC-transmitter and key in
Perform measurements under the following conditions: the code “062593”, directly followed by the “MENU” (or
• Service Default Mode. "HOME") button.
• Video: Color bar signal. Note: It is possible that, together with the SDM, the main
• Audio: 3 kHz left, 1 kHz right. menu will appear. To switch it “off”, push the “MENU” (or
"HOME") button again.
5.2 Service Modes

Service Default mode (SDM) and Service Alignment Mode


(SAM) offers several features for the service technician, while
the Customer Service Mode (CSM) is used for communication
between the call centre and the customer.
SDM
This chassis also offers the option of using ComPair, a
hardware interface between a computer and the TV chassis. It
offers the abilities of structured troubleshooting, error code
reading, and software version read-out for all chassis.
(see also section “5.4.1 ComPair”).
19100_057_110217.eps
Note: For the new model range, a new remote control (RC) is 110217

used with some renamed buttons. This has an impact on the


activation of the Service modes. For instance the old “MENU” Figure 5-1 Service mode pad
button is now called “HOME” (or is indicated by a “house” icon).
After activating this mode, “SDM” will appear in the upper right
5.2.1 Service Default Mode (SDM) corner of the screen (when a picture is available).

Purpose How to Navigate


• To create a pre-defined setting, to get the same When the “MENU” (or “HOME”) button is pressed on the RC
measurement results as given in this manual. transmitter, the TV set will toggle between the SDM and the
• To override SW protections detected by stand-by normal user menu.
processor and make the TV start up to the step just before
protection (a sort of automatic stepwise start-up). See How to Exit SDM
section “5.3 Stepwise Start-up”. Use one of the following methods:
• To start the blinking LED procedure where only LAYER 2 • Switch the set to STAND-BY via the RC-transmitter.
errors are displayed. (see also section “5.5 Error Codes”). • Via a standard customer RC-transmitter: key in “00”-
sequence.
Specifications
5.2.2 Service Alignment Mode (SAM)
Table 5-1 SDM default settings
Purpose
• To perform (software) alignments.
Default
• To change option settings.
Region Freq. (MHz) system
• To easily identify the used software version.
Europe, AP(PAL/Multi) 475.25 PAL B/G • To view operation hours.
Europe, AP DVB-T 546.00 PID DVB-T • To display (or clear) the error code buffer.
Video: 0B 06 PID
PCR: 0B 06 PID How to Activate SAM
Audio: 0B 07 Via a standard RC transmitter: Key in the code “062596”
directly followed by the “INFO” or “OK” button. After activating
• All picture settings at 50% (brightness, color, contrast). SAM with this method a service warning will appear on the
• Sound volume at 25%. screen, continue by pressing the “OK” button on the RC.

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Service Modes, Error Codes, and Fault Finding Q552.2L LA 5. EN 23

Contents of SAM
• Hardware Info.
– A. SW Version. Displays the software version of the
main software (example: Q555X-1.2.3.4 =
AAAAB_X.Y.W.Z). Display Option
Code
• AAAA= the chassis name.
• B= the SW branch version. This is a sequential
number (this is no longer the region indication, as
39mm
the software is now multi-region).
PHILIPS 040

• X.Y.W.Z= the software version, where X is the

27mm
MODEL:
32PF9968/10
main version number (different numbers are not PROD.SERIAL NO:

compatible with one another) and Y.W.Z is the sub AG 1A0620 000001

(CTN Sticker)
version number (a higher number is always
compatible with a lower number). 10000_038_090121.eps
– B. STBY PROC Version. Displays the software 090819
version of the stand-by processor.
– C. Production Code. Displays the production code of Figure 5-2 Location of Display Option Code sticker
the TV, this is the serial number as printed on the back
of the TV set. Note that if an NVM is replaced or is • Store - go right. All options and alignments are stored
initialized after corruption, this production code has to when pressing “cursor right” (or the “OK” button) and then
be re-written to NVM. ComPair will foresee in a the “OK”-button.
possibility to do this. • Operation hours display. Displays the accumulated total
• Operation Hours. Displays the accumulated total of of operation hours of the screen itself. In case of a display
operation hours (not the stand-by hours). Every time the replacement, reset to “0” or to the consumed operation
TV is switched “on/off”, 0.5 hours is added to this number. hours of the spare display.
• Errors (followed by maximum 10 errors). The most recent • SW Maintenance.
error is displayed at the upper left (for an error explanation – SW Events. In case of specific software problems, the
see section “5.5 Error Codes”). development department can ask for this info.
• Reset Error Buffer. When “cursor right” (or “OK” button) – HW Events. In case of specific software problems, the
pressed here, followed by the “OK” button, the error buffer development department can ask for this info :
is reset. - Event 26: refers to a power dip, this is logged after
• Alignments. This will activate the “ALIGNMENTS” sub- the TV set reboots due to a power dip.
menu. See Chapter 6. Alignments. - Event 17: refers to the power OK status, sensed even
• Dealer Options. Extra features for the dealers. before the 3 x retry to generate the error code.
• Options. Extra features for Service. For more info • Test settings. For development purposes only.
regarding option codes, see chapter 6. Alignments. • Development file versions. Not useful for Service
Note that if the option code numbers are changed, these purposes, this information is only used by the development
have to be confirmed with pressing the “OK” button before department.
the options are stored, otherwise changes will be lost. • Upload to USB. To upload several settings from the TV to
• Initialize NVM. The moment the processor recognizes a an USB stick, which is connected to the SSB. The items are
corrupted NVM, the “initialize NVM” line will be highlighted. “Channel list”, “Personal settings”, “Option codes”,
Now, two things can be done (dependent of the service “Alignments”, “Identification data” (includes the set type
instructions at that moment): and prod code + all 12NC like SSB, display, boards),
– Save the content of the NVM via ComPair for “History list”. The “All” item supports to upload all several
development analysis, before initializing. This will give items at once.
the Service department an extra possibility for First a directory “repair\” has to be created in the root
diagnosis (e.g. when Development asks for this). of the USB stick.
– Initialize the NVM. To upload the settings, select each item separately, press
“cursor right” (or the “OK” button), confirm with “OK” and
Note: When the NVM is corrupted, or replaced, there is a high wait until the message “Done” appears. In case the
possibility that no picture appears because the display code is download to the USB stick was not successful, “Failure” will
not correct. So, before initializing the NVM via the SAM, a be displayed. In this case, check if the USB stick is
picture is necessary and therefore the correct display option connected properly and if the directory “repair” is present in
has to be entered. Refer to Chapter 6. Alignments for details. the root of the USB stick. Now the settings are stored onto
To adapt this option, it’s advised to use ComPair (the correct the USB stick and can be used to download into another TV
values for the options can be found in Chapter 6. Alignments) or other SSB. Uploading is of course only possible if the
or a method via a standard RC (described below). software is running and preferably a picture is available.
Changing the display option via a standard RC: Key in the This method is created to be able to save the customer’s
code “062598” directly followed by the “MENU” (or "HOME") TV settings and to store them into another SSB.
button and “XXX” (where XXX is the 3 digit decimal display • Download from USB. To download several settings from
code as mentioned on the sticker in the set). Make sure to key the USB stick to the TV, same way of working needs to be
in all three digits, also the leading zero’s. If the above action is followed as described in “Upload to USB”. To make sure
successful, the front LED will go out as an indication that the that the download of the channel list from USB to the TV is
RC sequence was correct. After the display option is changed executed properly, it is necessary to restart the TV and
in the NVM, the TV will go to the Stand-by mode. If the NVM tune to a valid preset if necessary. The “All” item supports
was corrupted or empty before this action, it will be initialized to download all several items at once.
first (loaded with default values). This initializing can take up to • NVM editor. For NET TV the set “type number” must be
20 seconds. entered correctly.
Also the production code (AG code) can be entered here
via the RC-transmitter.
Correct data can be found on the side/rear sticker.

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EN 24 5. Q552.2L LA Service Modes, Error Codes, and Fault Finding

How to Navigate How to Navigate


• In SAM, the menu items can be selected with the By means of the “CURSOR-DOWN/UP” knob on the RC-
“CURSOR UP/DOWN” key on the RC-transmitter. The transmitter, can be navigated through the menus.
selected item will be highlighted. When not all menu items
fit on the screen, move the “CURSOR UP/DOWN” key to Contents of CSM
display the next/previous menu items. The contents are reduced to 3 pages: General, Software
• With the “CURSOR LEFT/RIGHT” keys, it is possible to: versions and Quality items. The group names itself are not
– (De) activate the selected menu item. shown anywhere in the CSM menu.
– (De) activate the selected sub menu.
• With the “OK” key, it is possible to activate the selected
General
action.
• Set Type. This information is very helpful for a helpdesk/
workshop as reference for further diagnosis. In this way, it
How to Exit SAM is not necessary for the customer to look at the rear of the
Use one of the following methods: TV-set. Note that if an NVM is replaced or is initialized after
• Switch the TV set to STAND-BY via the RC-transmitter. corruption, this set type has to be re-written to NVM.
• Via a standard RC-transmitter, key in “00” sequence, or ComPair will foresee in a possibility to do this. The update
select the “BACK” key. can also be done via the NVM editor available in SAM.
• Production Code. Displays the production code (the serial
5.2.3 Customer Service Mode (CSM) number) of the TV. Note that if an NVM is replaced or is
initialized after corruption, this production code has to be
Purpose re-written to NVM. ComPair will foresee in a possibility to
When a customer is having problems with his TV-set, he can do this. The update can also be done via the NVM editor
call his dealer or the Customer Helpdesk. The service available in SAM.
technician can then ask the customer to activate the CSM, in • Installed date. Indicates the date of the first installation of
order to identify the status of the set. Now, the service the TV. This date is acquired via time extraction.
technician can judge the severity of the complaint. In many • Options 1. Gives the option codes of option group 1 as set
cases, he can advise the customer how to solve the problem, in SAM (Service Alignment Mode).
or he can decide if it is necessary to visit the customer. • Options 2. Gives the option codes of option group 2 as set
The CSM is a read only mode; therefore, modifications in this in SAM (Service Alignment Mode).
mode are not possible. • 12NC SSB. Gives an identification of the SSB as stored in
NVM. Note that if an NVM is replaced or is initialized after
When in this chassis CSM is activated, a test pattern will be corruption, this identification number has to be re-written to
displayed during 5 seconds (1 second Blue, 1 second Green NVM. ComPair will foresee in a possibility to do this. This
and 1 second Red, then again 1 second Blue and 1 second identification number is the 12nc number of the SSB.
Green). This test pattern is generated by the PNX51X0 • 12NC display. Shows the 12NC of the display.
(located on the 200Hz board as part of the display). So if this • 12NC supply. Shows the 12NC of the power supply.
test pattern is shown, it could be determined that the back end • 12NC 200Hz board. Shows the 12NC of the 200Hz Panel
video chain (PNX51X0 and display) is working.For TV sets (when present).
without the PNX51X0 inside, every menu from CSM will be • 12NC AV PIP. Shows the 12NC of the AV PIP board
used as check for the back end chain video. (when present).

When CSM is activated and there is a USB stick connected to Software versions
the TV set, the software will dump the CSM content to the USB • Current main SW. Displays the build-in main software
stick. The file (CSM_model number_serial number.txt) will be version. In case of field problems related to software,
saved in the root of the USB stick. This info can be handy if no software can be upgraded. As this software is consumer
information is displayed. upgradeable, it will also be published on the Internet.
Example: Q55xx1.2.3.4
When in CSM mode (and a USB stick connected), pressing • Stand-by SW. Displays the build-in stand-by processor
“OK” will create an extended CSM dump file on the USB stick. software version. Upgrading this software will be possible
This file (Extended_CSM_model number_serial number.txt) via ComPair or via USB (see section 5.9 Software
contains: Upgrading).
• The normal CSM dump information, Example: STDBY_83.84.0.0.
• All items (from SAM “load to USB”, but in readable format), • e-UM version. Displays the electronic user manual SW-
• Operating hours, version (12NC version number). Most significant number
• Error codes, here is the last digit.
• SW/HW event logs. • AV PIP software.
• 3D dongle software version.
To have fast feedback from the field, a flashdump can be
requested by development. When in CSM, push the “red” Quality items
button and key in serial digits ‘2679’ (same keys to form the • Signal quality. Bad / average /good (not for DVB-S).
word ‘COPY’ with a cellphone). A file “Dump_model • Ethernet MAC address. Displays the MAC address
number_serial number.bin” will be written on the connected present in the SSB.
USB device. This can take 1/2 minute, depending on the • Wireless MAC address. Displays the wireless MAC
quantity of data that needs to be dumped. address to support the Wi-Fi functionality.
• BDS key. Indicates if the set is in the BDS status.
Also when CSM is activated, the LAYER 1 error is displayed via • CI module. Displays status if the common interface
blinking LED. Only the latest error is displayed (see also module is detected.
section 5.5 Error Codes). • CI + protected service. Yes/No.
• Event counter :
How to Activate CSM S : 000X 0000(number of software recoveries : SW
EVENT-LOG #(reboots)
Key in the code “123654” via the standard RC transmitter. S : 0000 000X (number of software events : SW EVENT-
Note: Activation of the CSM is only possible if there is no (user) LOG #(events)
menu on the screen! H : 000X 0000(number of hardware errors)

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Service Modes, Error Codes, and Fault Finding Q552.2L LA 5. EN 25

H : 0000 000X (number of hardware events : SW EVENT- in this mode with a faulty FET 7U0X is done, you can destroy
LOG #(events). all IC’s supplied by the +1V8 and +1v1, due to overvoltage (12V
on XVX-line). It is recommended to measure first the FET
How to Exit CSM 7U0X or others FET’s on shortcircuit before activating SDM via
Press “MENU” (or "HOME") / “Back” key on the RC-transmitter. the service pads.

5.3 Stepwise Start-up


The abbreviations “SP” and “MP” in the figures stand for:
When the TV is in a protection state due to an error detected by • SP: protection or error detected by the Stand-by
stand-by software (error blinking is displayed) and SDM is Processor.
activated via shortcutting the SDM solder path on the SSB, the • MP: protection or error detected by the MIPS Main
TV starts up until it reaches the situation just before protection. Processor.
So, this is a kind of automatic stepwise start-up. In combination
with the start-up diagrams below, you can see which supplies
are present at a certain moment. Caution: in case the start-up

Mains
off Mains
on

- WakeUp requested
WakeUp
- Acquisition needed
requested
- Tact switch pushed

St by Semi Active
- stby requested and
no data Acquisition St by - St by requested
required - tact SW pushed

Tact switch
pushed
WakeUp
requested
- Tact switch pushed
(SDM)
- last status is hibernate
GoToProtection
after mains ON
Hibernate
GoToProtection

Protection

18770_250_100216.eps
100402

Figure 5-3 Transition diagram

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EN 26 5. Q552.2L LA Service Modes, Error Codes, and Fault Finding

Off
Mains is applied
Stand by or
Protection
Standby Supply starts running.
All standby supply voltages become available.

st-by μP resets

If the protection state was left by short circuiting the


Initialise I/O pins of the st-by μP:
SDM pins, detection of a protection condition during
- Switch reset-AVC LOW (reset state)
startup will stall the startup. Protection conditions in a
- Switch reset-system LOW (reset state)
- Switch reset-Ethernet LOW (reset state) playing set will be ignored. The protection mode will
not be entered.
- Switch reset-USB LOW (reset state)
- Switch reset-DVBs LOW (reset state)
- keep Audio-reset and Audio-Mute-Up HIGH

- Switch Audio-Reset high.


start keyboard scanning, RC detection. Wake up reasons are It is low in the standby mode if the standby
off. mode lasted longer than 10s.

Switch ON Platform and display supply by switching


LOW the Standby line.

+12V, +24Vs, AL and Bolt-on power


is switched on, followed by the +1V2 DCDC converter
Detect2 is moved to an interrupt. To be checked if
the detection on interrupt base is feasible or not or if
we should stick to the standard 40ms interval. 12V error:
Detect2 high received
No Layer1: 3
within 2 seconds?
Layer2: 16

Yes
Enter protection
Enable the DCDC converters
(ENABLE-3V3n LOW)

Wait 50ms

Enable the supply detection algorithm

Set I²C slave address


of Standby μP to (A0h)

Detect EJTAG debug probe


(pulling pin of the probe interface to An EJTAG probe (e.g. WindPower ICE probe) can be
ground by inserting EJTAG probe) connected for Linux Kernel debugging purposes.

EJTAG probe
Yes
connected ?

No

No No Cold boot?

Yes

Release AVC system reset Release AVC system reset Release AVC system reset
Feed warm boot script Feed cold boot script Feed initializing boot script
disable alive mechanism

18770_251_100216.eps
100216

Figure 5-4 “Off” to “Semi Stand-by” flowchart (part 1)

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Service Modes, Error Codes, and Fault Finding Q552.2L LA 5. EN 27

Reset-system is switched HIGH by the Reset-system is switched HIGH by the


AVC at the end of the bootscript AVC at the end of the bootscript

No

AVC releases Reset-Ethernet, Reset-USB and AVC releases Reset-Ethernet, Reset-USB and
This cannot be done through the bootscript, Reset-DVBs when the end of the AVC boot- Reset-DVBs when the end of the AVC boot-
the I/O is on the standby μP script is detected script is detected

Reset-Audio and Audio-Mute-Up are Reset-Audio and Audio-Mute-Up are


switched by MIPS code later on in the switched by MIPS code later on in the
Timing need to be updated if startup process startup process
more mature info is available.

Bootscript ready
No
in 1250 ms?

Yes

Set I²C slave address


of Standby μP to (60h)

RPC start (comm. protocol)


Timing needs to
be updated if more
Flash to Ram mature info is
No image transfer succeeded available.
within 30s?
Code =
Layer1: 2
Layer2: 15 Yes
Timing needs to be
updated if more
Code = mature info is
Switch AVC PNX85500 in SW initialization
Layer1: 2 No available.
reset (active low) succeeded
Layer2: 53
within 20s?

Wait 10ms Yes

Enable Alive check mechanism


Disable all supply related protections and
switch off the +3V3 +5V DC/DC converter.

MIPS reads the wake up reason Wait until AVC starts to


from standby μP. communicate
Wait 5ms

Startup screen shall only be visible when there is a coldboot to


an active state end situation. The startup screen shall not be
Wake up reason visible when waking up for reboot reasons or waking up to semi-
switch off the remaining DC/DC coldboot & not semi-
converters standby? standby conditions or waking up to enter Hibernate mode..

yes
Switch Standby I/O line high
3-th try?
and wait 4 seconds
The first time after the option turn on of the startup screen or
Startup screen cfg file when the set is virgin, the cfg file is not present and hence
present? the startup screen will not be shown.
Yes

yes
Blink Code as
error code
200Hz set? yes

No
Enter protection
85500 sends out startup screen 85500 sends out startup screen

No
200Hz Tcon has started up the
85500 starts up the display.
display.
No

To keep this flowchart readable, the exact Startup screen visible 85500 requests Lamp on
display turn on description is not copied
here. Please see the Semi-standby to On
description for the detailed display startup
Startup screen visible
During the complete display time of the
Startup screen, the preheat condition of
sequence.
100% PWM is valid. Initialize audio

initialize tuner and channel decoders

Initialize source selection

Initialize video processing IC’s

initialize AutoTV by triggering CHS AutoTV Init interface

Initialize Ambilight with Lights off.

Semi-Standby
18770_252_100216.eps
100216

Figure 5-5 “Off” to “Semi Stand-by” flowchart (part 2)

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EN 28 5. Q552.2L LA Service Modes, Error Codes, and Fault Finding

Constraints taken into account:


- Display may only be started when valid LVDS output clock can be delivered by the AVC.
- To have a reliable operation of the EEFL backlight, the backlight should be driven with a maximum PWM duty
cycle during the first seconds. Only after this first one or two seconds, the PWM may be set to the required output
level (Note that the PWM output should be present before the backlight is switched on). To minimize the artefacts,
the picture should only be unblanked after these first seconds.

The assumption here is that a fast toggle (<2s) can


only happen during ON->SEMI ->ON. In these states,
Semi Standby
the AVC is still active and can provide the 2s delay. A
transition ON->SEMI->STBY->SEMI->ON cannot be
Wait until previous on-state is left more than 2
made in less than 2s, because the standby state will
seconds ago. (to prevent LCD display problems)
be maintained for at least 4s.

Assert RGB video blanking


CPipe already generates a valid output and audio mute
clock in the semi-standby state: display
startup can start immediately when leaving
the semi-standby state.

Display already on?


(splash screen)

No

Switch on the display power by


The exact timings to switching LCD-PWR-ON low
switch on the
display (LVDS Yes
Wait x ms
delay, lamp delay)
are defined in the Initialize audio and video
display file. Switch on LVDS output in the 85500 processing IC's and functions
according needed use case.
Delay Lamp-on with the sum of the LVDS delay and
the Lamp delay indicated in the display file

Switch off the dimming backlight feature, set


the BOOST control to nominal and make sure
PWM output is set to maximum allowed PWM

Switch on LCD backlight (Lamp-ON)

Start POK line Wait until valid and stable audio and video, corresponding to the
detection algorithm requested output is delivered by the AVC
AND
the backlight has been switched on for at least the time which is
indicated in the display file as preheat time.
return

Switch Audio-Reset low and wait 5ms

A LED set does not normally need a


Release audio mute and wait 100ms before any other audio
preheat time. The preheat remains present
handling is done (e.g. volume change)
but is set to zero in the display file.

Restore dimming backlight feature, PWM and BOOST output


The higher level requirement is that audio and video
and unblank the video.
should be demuted without transient effects and that
the audio should be demuted maximum 1s before or
at the same time as the unblanking of the video.
Switch on the Ambilight functionality according the last status
settings.

Startup screen Option


and Installation setting
Photoscreen ON?

Yes

Display cfg file present


and up to date, according
correct display option?
No
No
Yes
Prepare Start screen Display config
file and copy to Flash

Active
18770_253_100216.eps
100216

Figure 5-6 “Semi Stand-by” to “Active” flowchart (EEFL or LED backlight 50/100 Hz only)

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Service Modes, Error Codes, and Fault Finding Q552.2L LA 5. EN 29

The assumption here is that a fast toggle (<2s)


can only happen during ON->SEMI ->ON. In
Semi Standby
these states, the AVC is still active and can
provide the 2s delay. If the transition ON->SEMI-
>STBY->SEMI->ON can be made in less than 2s, Wait until previous on-state is left more than 2
we have to delay the semi -> stby transition until seconds ago. (to prevent LCD display problems)
the requirement is met.

Assert RGB video blanking


and audio mute

There is no need to define the Backlight already on?


display timings since the timing (splash screen)
implementation is part of the Tcon. Yes

No Initialize audio and video


processing IC's and functions
according needed use case.
Request Tcon to Switch on the backlight in a
direct LED or
set Lamp-on I/O line in case of a side LED

Start POK line


detection algorithm

Wait until valid and stable audio and video, corresponding to


the requested output is delivered by the AVC.

return
Switch Audio-Reset low and wait 5ms

Release audio mute and wait 100ms before any other audio
The higher level requirement is that audio and handling is done (e.g. volume change)
video should be demuted without transient
effects and that the audio should be demuted
maximum 1s before or at the same time as the
unblank the video.
unblanking of the video.

Switch on the Ambilight functionality according the last status


settings.

Startup screen Option


and Installation setting
Photoscreen ON?

Yes

Display cfg file present


and up to date, according
correct display option?
No
No
Yes
Prepare Start screen Display config
file and copy to Flash

Active
18770_254_100216.eps
100216

Figure 5-7 “Semi Stand-by” to “Active” flowchart (LED backlight 200 Hz)

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EN 30 5. Q552.2L LA Service Modes, Error Codes, and Fault Finding

Active

Mute all sound outputs via softmute

Wait 100ms

Set main amplifier mute (I/O: audio-mute)

Force ext audio outputs to ground


(I/O: audio reset)
And wait 5ms

switch off Ambilight

Wait until Ambilight has faded out: Output power


Observer should be zero

Switch off POK line


detection algorithm

switch off LCD backlight


(I/O or I²C)

Mute all video outputs

Yes 200Hz set?

No

Wait x ms (display file)

Instruct 200Hz
The exact timings to
Tcon to turn off Switch off LVDS output in 85500
switch off the
the display
display (LVDS
delay, lamp delay)
Wait x ms
are defined in the
display file.

Switch off the display power by


switching LCD-PWR-ON high

Semi Standby
18770_255_100216.eps
100216

Figure 5-8 “Active” to “Semi Stand-by” flowchart

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Service Modes, Error Codes, and Fault Finding Q552.2L LA 5. EN 31

Semi Stand by

If ambientlight functionality was used in semi-standby


(lampadaire mode), switch off ambient light (see CHS
ambilight)

Delay transition until ramping down of ambient light is *) If this is not performed and the set is
finished. *) switched to standby when the switch off of
the ambilights is still ongoing, the lights will
switch off abruptly when the supply is cut.

transfer Wake up reasons to the Stand by μP.

Switch Memories to self-refresh (this creates a more


stable condition when switching off the power).

Switch AVC system in reset state (reset-system and


reset-AVC lines)
Switch reset-USB, Reset-Ethernet and Reset-DVBs
LOW

Wait 10ms

Disable all supply related protections and switch off


the DC/DC converters (ENABLE-3V3n)

Wait 5ms

Switch OFF all supplies by switching HIGH the


Standby I/O line

Important remarks:

release reset audio 10 sec after entering


standby to save power

Also here, the standby state has to be


maintained for at least 4s before starting
another state transition.
Stand by

18770_256_100216.eps
100216

Figure 5-9 “Semi Stand-by” to “Stand-by” flowchart

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EN 32 5. Q552.2L LA Service Modes, Error Codes, and Fault Finding

5.4 Service Tools 5.5 Error Codes

5.4.1 ComPair 5.5.1 Introduction

Introduction The error code buffer contains all detected errors since the last
ComPair (Computer Aided Repair) is a Service tool for Philips time the buffer was erased. The buffer is written from left to
Consumer Electronics products. and offers the following: right, new errors are logged at the left side, and all other errors
1. ComPair helps to quickly get an understanding on how to shift one position to the right.
repair the chassis in a short and effective way. When an error occurs, it is added to the list of errors, provided
2. ComPair allows very detailed diagnostics and is therefore the list is not full. When an error occurs and the error buffer is
capable of accurately indicating problem areas. No full, then the new error is not added, and the error buffer stays
knowledge on I2C or UART commands is necessary, intact (history is maintained).
because ComPair takes care of this. To prevent that an occasional error stays in the list forever, the
3. ComPair speeds up the repair time since it can error is removed from the list after more than 50 hrs. of
automatically communicate with the chassis (when the μP operation.
is working) and all repair information is directly available. When multiple errors occur (errors occurred within a short time
4. ComPair features TV software up possibilities. span), there is a high probability that there is some relation
between them.
Specifications
ComPair consists of a Windows based fault finding program New in this chassis is the way errors can be displayed:
and an interface box between PC and the (defective) product.
The ComPair II interface box is connected to the PC via an • If no errors are there, the LED should not blink at all in
USB cable. For the TV chassis, the ComPair interface box and CSM or SDM. No spacer must be displayed as well.
the TV communicate via a bi-directional cable via the service • There is a simple blinking LED procedure for board
connector(s). level repair (home repair) so called LAYER 1 errors
The ComPair fault finding program is able to determine the next to the existing errors which are LAYER 2 errors (see
problem of the defective television, by a combination of Table 5-2).
automatic diagnostics and an interactive question/answer – LAYER 1 errors are one digit errors.
procedure. – LAYER 2 errors are 2 digit errors.
• In protection mode.
– From consumer mode: LAYER 1.
How to Connect
– From SDM mode: LAYER 2.
This is described in the chassis fault finding database in
ComPair. • Fatal errors, if I2C bus is blocked and the set reboots,
CSM and SAM are not selectable.
– From consumer mode: LAYER 1.
TO TV
– From SDM mode: LAYER 2.
TO
UART SERVICE
TO
I2C SERVICE
TO
UART SERVICE • In CSM mode.
CONNECTOR CONNECTOR CONNECTOR
– When entering CSM: error LAYER 1 will be displayed
by blinking LED. Only the latest error is shown.
ComPair II
Multi • In SDM mode.
RC in function
RC out
– When SDM is entered via Remote Control code or the
hardware pins, LAYER 2 is displayed via blinking LED.
Optional Power Link/ Mode
Switch Activity I2C RS232 /UART
• Error display on screen.
– In CSM no error codes are displayed on screen.
– In SAM the complete error list is shown.
PC
Basically there are three kinds of errors:
• Errors detected by the Stand-by software which lead to
protection. These errors will always lead to protection and
an automatic start of the blinking LED LAYER 1 error.
(see section “5.6 The Blinking LED Procedure”).
ComPair II Developed by Philips Brugge
• Errors detected by the Stand-by software which not
Optional power
HDMI 5V DC lead to protection. In this case the front LED should blink
I2C only
the involved error. See also section “5.5 Error Codes, 5.5.4
Error Buffer”. Note that it can take up several minutes
10000_036_090121.eps
091118 before the TV starts blinking the error (e.g. LAYER 1
error = 2, LAYER 2 error = 15 or 53).
Figure 5-10 ComPair II interface connection • Errors detected by main software (MIPS). In this case
the error will be logged into the error buffer and can be read
Caution: It is compulsory to connect the TV to the PC as out via ComPair, via blinking LED method LAYER 1-2
shown in the picture above (with the ComPair interface in error, or in case picture is visible, via SAM.
between), as the ComPair interface acts as a level shifter. If
one connects the TV directly to the PC (via UART), ICs can be 5.5.2 How to Read the Error Buffer
blown!
Use one of the following methods:
How to Order • On screen via the SAM (only when a picture is visible).
ComPair II order codes: E.g.:
• ComPair II interface: 3122 785 91020. – 00 00 00 00 00: No errors detected
• Software is available via the Philips Service web portal. – 23 00 00 00 00: Error code 23 is the last and only
• ComPair UART interface cable for Q55x.x. detected error.
(using 3.5 mm Mini Jack connector): 3138 188 75051. – 37 23 00 00 00: Error code 23 was first detected and
error code 37 is the last detected error.
Note: When you encounter problems, contact your local – Note that no protection errors can be logged in the
support desk. error buffer.

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Service Modes, Error Codes, and Fault Finding Q552.2L LA 5. EN 33

• Via the blinking LED procedure. See section 5.5.3 How to content, as this history can give significant information). This to
Clear the Error Buffer. ensure that old error codes are no longer present.
• Via ComPair. If possible, check the entire contents of the error buffer. In
some situations, an error code is only the result of another error
5.5.3 How to Clear the Error Buffer code and not the actual cause (e.g. a fault in the protection
detection circuitry can also lead to a protection).
There are several mechanisms of error detection:
Use one of the following methods:
• Via error bits in the status registers of ICs.
• By activation of the “RESET ERROR BUFFER” command
in the SAM menu. • Via polling on I/O pins going to the stand-by processor.
• Via sensing of analog values on the stand-by processor or
• If the content of the error buffer has not changed for 50+
the PNX8550.
hours, it resets automatically.
• Via a “not acknowledge” of an I2C communication.

5.5.4 Error Buffer


Take notice that some errors need several minutes before they
start blinking or before they will be logged. So in case of
In case of non-intermittent faults, clear the error buffer before
problems wait 2 minutes from start-up onwards, and then
starting to repair (before clearing the buffer, write down the check if the front LED is blinking or if an error is logged.

Table 5-2 Error code overview

Monitored Error/ Error Buffer/


Description Layer 1 Layer 2 by Prot Blinking LED Device Defective Board
I2C3 2 13 MIPS E BL / EB SSB SSB
I2C2 2 14 MIPS E BL / EB SSB SSB
I2C4 2 18 MIPS E BL / EB SSB SSB
PNX doesn’t boot (HW cause) 2 15 Stby μP P BL PNX8550 SSB
12V 3 16 Stby μP P BL / Supply
Inverter or display supply 3 17 MIPS E EB / Supply
PNX51X0 2/9 21 MIPS E EB PNX51X0 200 Hz board
HDMI mux 2 23 MIPS E EB Sil9x87A SSB
I2C switch 2 24 MIPS E EB PCA9540 SSB
Channel dec DVB-S 2 28 MIPS E EB STV0903 SSB
Lnb controller 2 31 MIPS E EB LNBH23 SSB
Tuner 2 34 MIPS E EB DTT 71300 SSB
Main nvm 2 35 MIPS E EB STM24C64 SSB
Tuner DVB-S 2 36 MIPS E EB STV6110 SSB
T° sensor SSB/set 2 42 MIPS E EB LM 75 T° sensor
T° sensor LED driver/Tcon 7 42 MIPS E EB LM 75 T° sensor
PNX doesn’t boot (SW cause) 2 53 Stby μP P BL PNX8550 SSB
Display 5 64 MIPS E BL / EB Altera Display

Extra Info Other root causes for this error can be due to hardware
• Rebooting. When a TV is constantly rebooting due to problems regarding the DDR’s and the bootscript reading
internal problems, most of the time no errors will be logged from the PNX8550.
or blinked. This rebooting can be recognized via a ComPair • Error 16 (12V). This voltage is made in the power supply
interface and Hyperterminal (for Hyperterminal settings, and results in protection (LAYER 1 error = 3) in case of
see section “5.8 Fault Finding and Repair Tips, 5.8.7 absence. When SDM is activated we see blinking LED
Logging). It’s shown that the loggings which are generated LAYER 2 error = 16.
by the main software keep continuing. In this case • Error 17 (Invertor or Display Supply). Here the status of
diagnose has to be done via ComPair. the “Power OK” is checked by software, no protection will
• Error 13 (I2C bus 3, SSB bus blocked). Current situation: occur during failure of the invertor or display supply (no
when this error occurs, the TV will constantly reboot due to picture), only error logging. LED blinking of LAYER 1
the blocked bus. The best way for further diagnosis here, is error = 3 in CSM, in SDM this gives LAYER 2 error = 17.
to use ComPair. • Error 21 (PNX51X0). When there is no I2C communication
• Error 14 (I2C bus 2, TV set bus blocked). Current towards the PNX51X0 after start-up, LAYER 2 error = 21
situation: when this error occurs, the TV will constantly will be logged and displayed via the blinking LED
reboot due to the blocked bus. The best way for further procedure if SDM is switched on. This device is located on
diagnosis here, is to use ComPair. the 200 Hz panel from the display.
• Error 18 (I2C bus 4, Tuner bus blocked). In case this bus • Error 23 (HDMI). When there is no I2C communication
is blocked, short the “SDM” solder paths on the SSB during towards the HDMI mux after start-up, LAYER 2 error = 23
startup, LAYER error 2 = 18 will be blinked. will be logged and displayed via the blinking LED
• Error 15 (PNX8550 doesn’t boot). Indicates that the main procedure if SDM is switched on.
processor was not able to read his bootscript. This error will • Error 24 (I2C switch). When there is no I2C
point to a hardware problem around the PNX8550 communication towards the I2C switch, LAYER 2
(supplies not OK, PNX 8550 completely dead, I2C link error = 24 will be logged and displayed via the blinking LED
between PNX and Stand-by Processor broken, etc...). procedure when SDM is switched on. Remark: this only
When error 15 occurs it is also possible that I2C1 bus is works for TV sets with an I2C controlled screen included.
blocked (NVM). I2C1 can be indicated in the schematics as • Error 28 (Channel dec DVB-S). When there is no I2C
follows: SCL-UP-MIPS, SDA-UP-MIPS. communication towards the DVB-S channel decoder,

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EN 34 5. Q552.2L LA Service Modes, Error Codes, and Fault Finding

LAYER 2 error = 28 will be logged and displayed via the 2. Two short blinks of 250 ms followed by a pause of 3 s
blinking LED procedure if SDM is switched on. 3. Eight short blinks followed by a pause of 3 s
• Error 31 (Lnb controller). When there is no I2C 4. Six short blinks followed by a pause of 3 s
communication towards this device, LAYER 2 error = 31 5. One long blink of 3 s to finish the sequence (spacer).
will be logged and displayed via the blinking LED 6. The sequence starts again.
procedure if SDM is activated.
• Error 34 (Tuner). When there is no I2C communication 5.6.2 How to Activate
towards the tuner during start-up, LAYER 2 error = 34 will
be logged and displayed via the blinking LED procedure Use one of the following methods:
when SDM is switched on.
• Activate the CSM. The blinking front LED will show only
• Error 35 (main NVM). When there is no I2C
the latest layer 1 error, this works in “normal operation”
communication towards the main NVM during start-up, mode or automatically when the error/protection is
LAYER 2 error = 35 will be displayed via the blinking LED
monitored by the Stand-by processor.
procedure when SDM is switched “on”. All service modes
In case no picture is shown and there is no LED blinking,
(CSM, SAM and SDM) are accessible during this failure, read the logging to detect whether “error devices” are
observed in the Uart logging as follows: "<< ERRO >>>
mentioned. (see section “5.8 Fault Finding and Repair
PFPOW_.C: First Error (id19, Layer_1= 2 Layer_= 35)".
Tips, 5.8.7 Logging”).
• Error 36 (Tuner DVB-S). When there is no I2C • Activate the SDM. The blinking front LED will show the
communication towards the DVB-S tuner during start-up,
entire content of the LAYER 2 error buffer, this works in
LAYER 2 error = 36 will be logged and displayed via the
“normal operation” mode or when SDM (via hardware pins)
blinking LED procedure when SDM is switched “on”. is activated when the tv set is in protection.
• Error 42 (Temp sensor). Only applicable for TV sets
equipped with temperature devices.
• Error 53. This error will indicate that the PNX8550 has 5.7 Protections
read his bootscript (when this would have failed, error 15
would blink) but initialization was never completed because 5.7.1 Software Protections
of hardware problems (NAND flash, ...) or software
initialization problems. Possible cause could be that there
Most of the protections and errors use either the stand-by
is no valid software loaded (try to upgrade to the latest main
microprocessor or the MIPS controller as detection device.
software version). Note that it can take a few minutes
Since in these cases, checking of observers, polling of ADCs,
before the TV starts blinking LAYER 1 error = 2 or in SDM,
and filtering of input values are all heavily software based,
LAYER 2 error = 53.
these protections are referred to as software protections.
• Error 64. Only applicable for TV sets with an I2C controlled
There are several types of software related protections, solving
screen.
a variety of fault conditions:
• Related to supplies: presence of the +5V, +3V3 and 1V2
5.6 The Blinking LED Procedure needs to be measured, no protection triggered here.
• Protections related to breakdown of the safety check
5.6.1 Introduction mechanism. E.g. since the protection detections are done
by means of software, failing of the software will have to
initiate a protection mode since safety cannot be
The blinking LED procedure can be split up into two situations:
guaranteed any more.
• Blinking LED procedure LAYER 1 error. In this case the
error is automatically blinked when the TV is put in CSM.
Remark on the Supply Errors
This will be only one digit error, namely the one that is
The detection of a supply dip or supply loss during the normal
referring to the defective board (see table “5-2 Error code
overview”) which causes the failure of the TV. This playing of the set does not lead to a protection, but to a cold
reboot of the set. If the supply is still missing after the reboot,
approach will especially be used for home repair and call
the TV will go to protection.
centres. The aim here is to have service diagnosis from a
distance.
• Blinking LED procedure LAYER 2 error. Via this Protections during Start-up
procedure, the contents of the error buffer can be made During TV start-up, some voltages and IC observers are
visible via the front LED. In this case the error contains actively monitored to be able to optimise the start-up speed,
2 digits (see table “5-2 Error code overview”) and will be and to assure good operation of all components. If these
displayed when SDM (hardware pins) is activated. This is monitors do not respond in a defined way, this indicates a
especially useful for fault finding and gives more details malfunction of the system and leads to a protection. As the
regarding the failure of the defective board. observers are only used during start-up, they are described in
Important remark: the start-up flow in detail (see section “5.3 Stepwise Start-up”).
For an empty error buffer, the LED should not blink at all in
CSM or SDM. No spacer will be displayed. 5.7.2 Hardware Protections

When one of the blinking LED procedures is activated, the front The only real hardware protection in this chassis appears in
LED will show (blink) the contents of the error buffer. Error case of an audio problem e.g. DC voltage on the speakers. This
codes greater then 10 are shown as follows: protection will only affect the Class D audio amplifier (item
1. “n” long blinks (where “n” = 1 to 9) indicating decimal digit 7D10; see diagram B03A) and puts the amplifier in a
2. A pause of 1.5 s continuous burst mode (cyclus approximately 2 seconds).
3. “n” short blinks (where “n”= 1 to 9)
4. A pause of approximately 3 s, Repair Tip
5. When all the error codes are displayed, the sequence • There still will be a picture available but no sound. While
finishes with a LED blink of 3 s (spacer). the Class D amplifier tries to start-up again, the cone of the
6. The sequence starts again. loudspeakers will move slowly in one or the other direction
until the initial failure shuts the amplifier down, this cyclus
Example: Error 12 8 6 0 0. starts over and over again. The headphone amplifier will
After activation of the SDM, the front LED will show: also behaves similar.
1. One long blink of 750 ms (which is an indication of the
decimal digit) followed by a pause of 1.5 s

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Service Modes, Error Codes, and Fault Finding Q552.2L LA 5. EN 35

5.8 Fault Finding and Repair Tips • +5V-TUN supply voltage (5V nominal) for tuner and IF
amplifier.
Read also section “5.5 Error Codes, 5.5.4 Error Buffer, Extra
+3V3-STANDY (3V3 nominal) is the permanent voltage,
Info”.
supplying the Stand-by microprocessor inside PNX855xx.

5.8.1 Ambilight Supply voltage +1V1 is started immediately when +12V voltage
becomes available (+12V is enabled by STANDBY signal when
Due to degeneration process of the LED’s fitted on the ambi "low"). Supply voltages +3V3, +2V5, +1V8, +1V2 and +5V-TUN
module, there can be a difference in the color and/or light are switched "on" by signal ENABLE-3V3 when "low", provided
output of the spare ambilight modules in comparison with the that +12V (detected via 7U40 and 7U41) is present.
originals ones contained in the TV set. Via SAM => alignments
=> ambilight, the spare module can be adjusted. +12V is considered OK (=> DETECT2 signal becomes "high",
+12V to +1V8, +12V to +3V3, +12V to +5V DC-DC converter
5.8.2 Audio Amplifier can be started up) if it rises above 10V and doesn’t drop below
9V5. A small delay of a few milliseconds is introduced between
The Class D-IC 7D10 has a powerpad for cooling. When the IC the start-up of 12V to +1V8 DC-DC converter and the two other
is replaced it must be ensured that the powerpad is very well DC-DC converters via 7U48 and associated components.
pushed to the PWB while the solder is still liquid. This is needed
to insure that the cooling is guaranteed, otherwise the Class D- Description DVB-S2:
IC could break down in short time. • LNB-RF1 (0V = disabled, 14V or 18V in normal operation)
LNB supply generated via the second conversion channel
of 7T03 followed by 7T50 LNB supply control IC. It provides
5.8.3 AV PIP
supply voltage that feeds the outdoor satellite reception
equipment.
To check the AV PIP board (if present) functionality, a
• +3V3-DVBS (3V3 nominal), +2V5-DVBS (2V5 nominal)
dedicated testpattern can be invoked as follows: select the
and +1V-DVBS (1.03V nominal) power supply for the
“multiview” icon in the User Interface and press the “OK” silicon tuner and channel decoder. +1V-DVBS is generated
button. Apply for the main picture an extended source, e.g.
via a 5V to 1V DC-DC converter and is stabilized at the
HDMI input. Proceed by entering CSM (push ‘123654’ on the
point of load (channel decoder) by means of feedback
remote control) and press the yellow button. A colored signal SENSE+1V0-DVBS. +3V3-DVBS and +2V5-DVBS
testpattern should appear now, generated by the AV PIP board
are generated via linear stabilizers from +5V-DVBS that by
(this can take a few seconds).
itself is generated via the first conversion channel of 7T03.

5.8.4 CSM At start-up, +24V becomes available when STANDBY signal is


"low" (together with +12V for the basic board), when +3V3 from
When CSM is activated and there is a USB stick connected to the basic board is present the two DC-DC converters channels
the TV, the software will dump the complete CSM content to the inside 7T03 are activated. Initially only the 24V to 5V converter
USB stick. The file (Csm.txt) will be saved in the root of the USB (channel 1 of 7T03 generating +5V-DVBS) will effectively work,
stick. If this mechanism works it can be concluded that a large while +V-LNB is held at a level around 11V7 via diode 6T55.
part of the operating system is already working (MIPS, USB...) After 7T05 is initialized, the second channel of 7T03 will start
and generates a voltage higher then LNB-RF1 with 0V8. +5V-
5.8.5 DC/DC Converter DVBS start-up will imply +3V3-DVBS start-up, with a small
delay of a few milliseconds => +2V5-DVBS and +1V-DVBS will
be enabled.
Description basic board
If +24V drops below +15V level then the DVB-S2 supply will
The basic board power supply consists of 4 DC/DC converters
stop, even if +3V3 is still present.
and 5 linear stabilizers. All DC/DC converters have +12V input
voltage and deliver:
• +1V1 supply voltage (1.15V nominal), for the core voltage Debugging
of PNX855xx, stabilized close to the point of load; The best way to find a failure in the DC/DC converters is to
SENSE+1V1 signal provides the DC-DC converter the check their start-up sequence at power “on” via the mains cord,
needed feedback to achieve this. presuming that the stand-by microprocessor and the external
• +1V8 supply voltage, for the DDR2 memories and DDR2 supply are operational. Take STANDBY signal "high"-to-"low"
interface of PNX855xx. transition as time reference.
• +3V3 supply voltage (3.30V nominal), overall 3.3 V for When +12V becomes available (maximum 1 second after
onboard IC’s, for non-5000 series SSB diversities only. STANDBY signal goes "low") then +1V1 is started immediately.
• +5V (5.15V nominal) for USB, WIFI and Conditional After ENABLE-3V3 goes "low", all the other supply voltages
Access Module and +5V5-TUN for +5V-TUN tuner should rise within a few milliseconds.
stabilizer.
Tips
The linear stabilizers are providing: • Behavior comparison with a reference TV550 platform can
• +1V2 supply voltage (1.2V nominal), stabilized close to be a fast way to locate failures.
PNX855xx device, for various other internal blocks of • If +12V stays "low", check the integrity of fuse 1U40.
PNX855xx; SENSE+1V2 signal provides the needed • Check the integrity (at least no short circuit between drain
feedback to achieve this. and source) of the power MOS-FETs before starting up the
• +2V5 supply voltage (2.5V nominal) for LVDS interface and platform in SDM, otherwise many components might be
various other internal blocks of PNX855xx; for 5000 series damaged. Using a ohmmeter can detect short circuits
SSB diversities the stabilizer is 7UD2 while for the other between any power rail and ground or between +12V and
diversities 7UC0 is used. any other power rail.
• +3V3 supply voltage (3V3 nominal) for 5000 series SSB • Short circuit at the output of an integrated linear stabilizer
diversities, provided by 7UD3; in this case the 12V to 3V3 (7UC0, 7UD2 or 7UD3) will heat up this device strongly.
DC-DC converter is not present. • Switching frequencies should be 500 kHz ...600 kHz for
12 V to 1.1 V and 12 V to 1.8 V DC-DC converters,

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EN 36 5. Q552.2L LA Service Modes, Error Codes, and Fault Finding

900 kHz for 12 V to 3.3 V and 12 V to 5 V DC-DC Uart loggings reporting fault conditions, error messages, error
converters. The DVB-S2 supply 24 V to 5 V and 24 V to +V codes, fatal errors:
LNB DC-DC converters operates at 300 kHz while for 5 V • Failure messages should be checked and investigated.For
to 1.1 V DC-DC converter 900 kHz is used. instance fatal error on the PNX51x0: check startup of the
back-end processor, supplies..reset, I2C bus. => error
5.8.6 Exit “Factory Mode” mentioned in the logging as: *51x0 failed to start by itself*.
• Some failures are indicated by error codes in the logging,
check with error codes table (see Table “5-2 Error code
When an “F” is displayed in the screen’s right corner, this
means the set is in “Factory” mode, and it normally overview”).e.g. => <<<ERROR>>>PLFPOW_MERR.C :
First Error (id=10,Layer_1=2,Layer_2=23).
happens after a new SSB is mounted. To exit this mode, push
• I2C bus error mentioned as e.g.: “ I2C bus 4 blocked”.
the “VOLUME minus” button on the TV’s local keyboard for 10
seconds (this disables the continuous mode). • Not all failures or error messages should be interpreted as
fault.For instance root cause can be due to wrong option
Then push the “SOURCE” button for 10 seconds until the “F”
codes settings => e.g. “DVBS2Suppoprted : False/True.
disappears from the screen.
In the Uart log startup script we can observe and check the
enabled loaded option codes.
5.8.7 Logging
Defective sectors (bad blocks) in the Nand Flash can also be
When something is wrong with the TV set (f.i. the set is reported in the logging.
rebooting) you can check for more information via the logging
in Hyperterminal. The Hyperterminal is available in every Startup in the SW upgrade application and observe the Uart
Windows application via Programs, Accessories, logging:
Communications, Hyperterminal. Connect a “ComPair UART”- Starting up the TV set in the Manual Software Upgrade mode
cable (3138 188 75051) from the service connector in the TV to will show access to USB, meant to copy software content from
the “multi function” jack at the front of ComPair II box. USB to the DRAM.Progress is shown in the logging as follows:
Required settings in ComPair before starting to log: “cosupgstdcmds_mcmdwritepart: Programming 102400 bytes,
- Start up the ComPair application. 40505344 of 40607744 bytes programmed”.
- Select the correct database (open file “Q55X.X”, this will set
the ComPair interface in the appropriate mode). Startup in Jett Mode:
- Close ComPair Check Uart logging in Jet mode mentioned as : “JETT UART
After start-up of the Hyperterminal, fill in a name (f.i. “logging”) READY”.
in the “Connection Description” box, then apply the following
settings: Uart logging changing preset:
1. COMx => COMMAND: calling DFB source = RC6, system=0, key = 4”.
2. Bits per second = 115200
3. Data bits = 8
4. Parity = none
5.8.9 Loudspeakers
5. Stop bits = 1
6. Flow control = none
During the start-up of the TV set, the logging will be displayed. Make sure that the volume is set to minimum during
disconnecting the speakers in the ON-state of the TV. The
This is also the case during rebooting of the TV set (the same
audio amplifier can be damaged by disconnecting the speakers
logging appears time after time). Also available in the logging
is the “Display Option Code” (useful when there is no picture), during ON-state of the set!
look for item “DisplayRawNumber” in the beginning of the
logging. Tip: when there is no picture available during rebooting 5.8.10 PSL
you are able to check for “error devices” in the logging (LAYER
2 error) which can be very helpful to determine the failure cause In case of no picture when CSM (test pattern) is activated and
of the reboot. For protection state, there is no logging. backlight doesn’t light up, it’s recommended first to check the
inverter on the PSL + wiring (LAYER 2 error = 17 is displayed
5.8.8 Guidelines Uart logging in SDM).

Description possible cases: 5.8.11 Tuner

Uart loggings are displayed: Attention: In case the tuner is replaced, always check the tuner
• When Uart loggings are coming out, the first conclusion we options!
can make is that the TV set is starting up and
communication with the flash RAM seems to be supported. 5.8.12 Display option code
The PNX855xx is able to read and write in the DRAMs.
• We can not yet conclude : Flash RAM and DRAMs are fully Attention: In case the SSB is replaced, always check the
operational/reliable.There still can be errors in the data
display option code in SAM, even when picture is available.
transfers, DRAM errors, read/write speed and timing
Performance with the incorrect display option code can lead to
control. unwanted side-effects for certain conditions.

No Uart logging at all:


New in this chassis:
• In case there is no Uart logging coming out, check if the
startup script can be send over the I2C bus (3 trials to While in the download application (start up in TV mode + “OK”
button pressed), the display option code can be changed via
startup) + power supplies are switched on and stable.
062598 HOME XXX special SAM command (XXX=display
• No startup will end up in a blinking LED status : error
LAYER 1 = “2”, error LAYER 2 = “53” (startup with SDM option in 3 digits).
solder paths short).
• Error LAYER 2 = “15” (hardware cause) is more related to
a supply issue while error LAYER 2 = “53” (software cause)
refers more to boot issues.

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Service Modes, Error Codes, and Fault Finding Q552.2L LA 5. EN 37

5.8.13 SSB Replacement

Follow the instructions in the flowchart in case a SSB has to be


exchanged. See figure “SSB replacement flowchart”.

In st ru ct io n n o t e SSB rep lacem en t Q543.x, Q548.x, Q549.x, and Q55x.x

Before starting: ST AR T
- prepare a USB memory stick with the latest software
- download the latest Main Software (Fus) from www.p4c.philips.com
- unzip this file
- create a folder ”upgrades” in the root of a USB stick (size > 50 MB) and
save the autorun.upg file in this "upgrades" folder.
Note: it is possible to rename this file, e.g."Q54x_SW_version.upg"; this in Set is still oper ating?
case there are more than one "autorun.upg" files on the USB stick.
No

Yes

C onnect the U SB stick to the set,


go to SAM and save the current TV settings via “Upload to USB”

1. D isconnect the WiF i module fr om the PC I connector (only for Q549.x SSB)
2. Replace the SSB by a Service SSB.
3. Place the WiFi module in the PCI connector.
4. Mount the Service SSB in the set.

Start-up the set


Due to a possible wrong display option code in the received Service
SSB (NVM), it’s possible that no picture is displayed. Due to this
the download application will not be shown either. This tree enables you
to load the main software step-by-step via the UART logging on the PC
(this for visual feedback). Set behaviour?
No pictur e displayed Pictur e displayed
Set is starting up without software
upgrade menu appearing on screen

1) Start up the TV set, equiped with the Service SSB,


and enable the UART logging on the PC. Pictur e displayed
Set is starting up with software
upgrade menu appearing on screen
2) The TV set will start-up automatically in the
download application if main TV software is not loaded.

1) Plug the USB stick into the TV set and select


3) Plug the prepared USB stick into the TV set. Follow the the “autorun .upg” file in the displayed browser.
instructions in the UART log file, press “Right” cursor key to enter
the list. Navigate to the “autorun.upg” file in the UART logging
printout via the cursor keys on the remote control. When the
correct file is selected, press “Ok”.
2) Now the main software will be loaded automatically,
supported by a progress bar.
4) Press "Down" cursor and “Ok” to start flashing the main
TV software. Printouts like: “L: 1-100%, V: 1-100% and
P: 1-100%” should be visible now in the UART logging.

3) Wait until the message “Operation successful !” is displayed


5) Wait until the message “Operation successful !” is logged in and remove all inserted media. Restart the TV set.
the UART log and remove all inserted media. Restart the TV set.

Set the correct “Display code” via “062598 -HOME- xxx” where
“xxx” is the 3 digit display panel code (see sticker on the side
or bottom of the cabinet)

After entering the “Display Option” code, the set is going to


Standby
(= validation of code)

Restart the set


No

Connect PC via the ComPair interface to Service connector.


Saved settings
on USB stick?

Start TV in Jett mode (DVD I + (OSD)) Yes


Open ComPair browser Q54x
In case of settings reloaded from USB, the set type,
Go to SAM and reload settings serial number, display 12 NC, are automatically stored
via “Download from USB” function. when entering display options.
Program set type number, serial number, and display 12 NC
Program E - DFU if needed.

If not already done:


Check latest software on Service website. - Check if correct “display option” code is programmed.
Update main and Stand-by software via USB. - Verify “option codes” according to sticker inside the set.
- Default settings for “white drive” > see Service Manual.
Attention point for Net TV: If the set type and serial number are not
filled in, the Net TV functionality will not work. It will not be possible
to connect to the internet.
Check and perform alignments in SAM according to the
Service Manual. Option codes, colour temperature, etc.

Final check of all menus in CSM.


Special attention for HDMI Keys and Mac address.
Check if E - D F U is present.

End Q54x.E SSB Board swap – VDS


Updated 22-03-2010

H_16771_007a.eps
100402

Figure 5-11 SSB replacement flowchart

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EN 38 5. Q552.2L LA Service Modes, Error Codes, and Fault Finding

Set is st art in g u p in F act o ry m o d e

Set is starting up in F actory m ode?

Noisy picture with bands/lines is visible and the An “F” is displayed (and the HDMI 1
RED LED is continuous on. input is displayed).

- Press the “volume minus” button on the TVs local keyboard for 5 ~10
seconds

- Press the “SOURCE” button for 10 seconds until the “F” disappears
from the screen or the noise on the screen is replaced by “blue mute”

The noise on the screen is replaced


with the blue mute or the “F” is disappeared!

Unplug the mains cord to verify the correct


disabling of the Factory mode.

Program display option code


via “062598 MENU”, followed by
the 3 digits code of the display
(this code can be found
on a sticker on - or inside - the set).

After entering “display option” code, the set is


going in stand-by mode (= validation of code)

R estart the set

H_16771_007b.eps
100322

Figure 5-12 SSB replacement flowchart - Factory mode

2011-Jul-15 back to
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Service Modes, Error Codes, and Fault Finding Q552.2L LA 5. EN 39

18753_211_100811.eps
100811

Figure 5-13 SSB start-up

5.9 Software Upgrading For the correct order number of a new SSB, always refer to the
Spare Parts list!
Attention!
Software version numbers for 2011 sets are all defined below 5.9.2 Main Software Upgrade
number 0.40.x.x. This might confuse servicers who store
software versions for more than one set and/or platform on the • The “UpgradeAll.upg” file is only used in the factory.
same storage device (USB stick).
Automatic Software Upgrade
Always check the latest software version on the servicer In “normal” conditions, so when there is no major problem with
website in relation to the correct CTN!!! the TV, the main software and the default software upgrade
application can be upgraded with the “AUTORUN.UPG”
5.9.1 Introduction (FUS part of the one-zip file: e.g. 3104 337 05661 _FUS
_Q555X_ x.x.x.x_prod.zip). This can also be done by the
consumers themselves, but they will have to get their software
The set software and security keys are stored in a NAND-
Flash, which is connected to the PNX855xx. from the commercial Philips website or via the Software Update
Assistant in the user menu (see eUM). The “autorun.upg” file
must be placed in the root of the USB stick.
It is possible for the user to upgrade the main software via the
How to upgrade:
USB port. This allows replacement of a software image in a 1. Copy “AUTORUN.UPG” to the root of the USB stick.
stand alone set, without the need of an E-JTAG debugger. A
2. Insert USB stick in the set while the set is operational. The
description on how to upgrade the main software can be found
set will restart and the upgrading will start automatically. As
in the electronic User Manual. soon as the programming is finished, a message is shown
to remove the USB stick and restart the set.
Important: When the NAND-Flash must be replaced, a new
SSB must be ordered, due to the presence of the security keys!
Manual Software Upgrade
(CI +, MAC address, ...). In case that the software upgrade application does not start
Perform the following actions after SSB replacement:
automatically, it can also be started manually.
1. Set the correct option codes (see sticker inside the TV).
How to start the software upgrade application manually:
2. Update the TV software => see the eUM (electronic User 1. Disconnect the TV from the Mains/AC Power.
Manual) for instructions.
2. Press the “OK” button on a Philips TV remote control or a
3. Perform the alignments as described in chapter 6 (section
Philips DVD RC-6 remote control (it is also possible to use
6.5 Reset of Repaired SSB).
4. Check in CSM if the CI + key, MAC address.. are valid.

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EN 40 5. Q552.2L LA Service Modes, Error Codes, and Fault Finding

a TV remote in “DVD” mode). Keep the “OK” button


pressed while reconnecting the TV to the Mains/AC Power.
3. The software upgrade application will start.

Attention!
In case the download application has been started manually,
the “autorun.upg” will maybe not be recognized.
What to do in this case:
1. Create a directory “UPGRADES” on the USB stick.
2. Rename the “autorun.upg” to something else, e.g. to
“software.upg”. Do not use long or complicated names,
keep it simple. Make sure that “AUTORUN.UPG” is no
longer present in the root of the USB stick.
3. Copy the renamed “upg” file into this directory.
4. Insert USB stick into the TV.
5. The renamed “upg” file will be visible and selectable in the
upgrade application.

Back-up Software Upgrade Application


If the default software upgrade application does not start (could
be due to a corrupted boot sector) via the above described
method, try activating the “back-up software upgrade
application”.
How to start the “back-up software upgrade application”
manually:
1. Disconnect the TV from the Mains/AC Power.
2. Press the “CURSOR DOWN”-button on a Philips TV
remote control while reconnecting the TV to the Mains/AC
Power.
3. The back-up software upgrade application will start.

5.9.3 Stand-by Software Upgrade via USB

In this chassis it is possible to upgrade the Stand-by software


via a USB stick. The method is similar to upgrading the main
software via USB.
Use the following steps:
1. Create a directory “UPGRADES” on the USB stick.
2. Copy the Stand-by software (part of the one-zip file, e.g.
StandbyFactory_88.0.0.0.upg) into this directory.
3. Insert the USB stick into the TV.
4. Start the download application manually (see section “
Manual Software Upgrade”.
5. Select the appropriate file and press the “OK” button to
upgrade.

5.9.4 Content and Usage of the One-Zip Software File

Below the content of the One-Zip file is explained, and


instructions on how and when to use it.
• AmbiCpld_Q55XX_x.x.x.x_prod.zip. Contains the
program instruction and software content, needed to
upgrade the ambilight CPLD on the TV550 platform.
• BalanceFPGA_Q555X_x.x.x.x_prod.zip. Contains the
BalanceFPGA software in “upg” format.
• FUS_Q555X_x.x.x.x_prod.zip. Contains the
“autorun.upg” which is needed to upgrade the TV main
software and the software download application.
• PNX5130UPG_Q555X_x.x.x.x_prod.zip. Contains the
PNX5130 software in “upg” format.
• StandbySW_Q555X_x.x.x.x_prod.zip. Contains the
StandbyFactory software in “upg” format.
• ProcessNVM_Q55XX_x.x.x.x_prod.zip. Default NVM
content. Must be programmed via ComPair or can be
loaded via USB, be aware that all alignments stored in
NVM are overwritten here.

5.9.5 UART logging 2K10 (see section “5.8 Fault Finding and
Repair Tips, 5.8.7 Logging)

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Alignments Q552.2L LA 6. EN 41

6. Alignments
Index of this chapter: • EU/AP-PAL models: a PAL B/G TV-signal with a signal
6.1 General Alignment Conditions strength of at least 1 mV and a frequency of 475.25 MHz
6.2 Hardware Alignments • US/AP-NTSC models: an NTSC M/N TV-signal with a
6.3 Software Alignments signal strength of at least 1 mV and a frequency of 61.25
6.4 Option Settings MHz (channel 3).
6.5 Reset of Repaired SSB • LATAM models: an NTSC M TV-signal with a signal
6.6 Total Overview SAM modes strength of at least 1 mV and a frequency of 61.25 MHz
(channel 3).

6.1 General Alignment Conditions


6.3.1 White Point

Perform all electrical adjustments under the following


• Choose “TV menu”, “Setup”, “More TV Settings” and then
conditions:
“Picture” and set picture settings as follows:
• Power supply voltage (depends on region):
– AP-NTSC: 120 VAC or 230 VAC / 50 Hz (r 10%). Picture Setting
– AP-PAL-multi: 120 - 230 VAC / 50 Hz (r 10%). Contrast 100
– EU: 230 VAC / 50 Hz (r 10%). Brightness 50
– LATAM-NTSC: 120 - 230 VAC / 50 Hz (r 10%). Colour 0
– US: 120 VAC / 60 Hz (r 10%). Light Sensor Off
• Connect the set to the mains via an isolation transformer Picture format Unscaled
with low internal resistance.
• Allow the set to warm up for approximately 15 minutes. • In menu “Picture”, choose “Pixel Plus HD” and set picture
• Measure voltages and waveforms in relation to correct settings as follows:
ground (e.g. measure audio signals in relation to Picture Setting
AUDIO_GND). Dynamic Contrast Off
Caution: It is not allowed to use heat sinks as ground. Dynamic Backlight Off
• Test probe: Ri > 10 M:, Ci < 20 pF. Colour Enhancement Off
• Use an isolated trimmer/screwdriver to perform Gamma 0
alignments.
• Go to the SAM and select “Alignments”-> “White point”.
6.1.1 Alignment Sequence
White point alignment LCD screens:
• First, set the correct options: • Use a 100% white screen (format: 720p50) to the HDMI
– In SAM, select “Option numbers”. input and set the following values:
– Fill in the option settings for “Group 1” and “Group 2” – “Color temperature”: “Cool”.
according to the set sticker (see also paragraph 6.4 – All “White point” values to: “127”.
Option Settings).
– Press OK on the remote control before the cursor is In case you have a color analyzer:
moved to the left. • Measure, in a dark environment, with a calibrated
– In submenu “Option numbers” select “Store” and press contactless color analyzer (Minolta CA-210 or Minolta CS-
OK on the RC. 200) in the centre of the screen and note the x, y value.
• OR: • Change the pattern to 90% white screen. If a Quantum
– In main menu, select “Store” again and press OK on Data generator is used, select the “GreyAll” test pattern at
the RC. level = 230.
– Switch the set to Stand-by. • Adjust the correct x, y coordinates (while holding one of the
• Warming up (>15 minutes). White point registers R, G or B on 127) by means of
decreasing the value of one or two other white points to the
correct x, y coordinates (see Table 6-1 White D alignment
6.2 Hardware Alignments values - LED - Minolta CA-210, or 6-2 White D alignment
values - LED - Minolta CS-200). Tolerance: dx: r 0.002, dy:
Not applicable. r 0.002.
• Repeat this step for the other color temperatures that need
to be aligned.
6.3 Software Alignments • When finished press OK on the RC and then press STORE
(in the SAM root menu) to store the aligned values to the
Put the set in SAM mode (see Chapter 5. Service Modes, Error NVM.
Codes, and Fault Finding). The SAM menu will now appear on • Restore the initial picture settings after the alignments.
the screen. Select ALIGNMENTS and go to one of the sub
menus. The alignments are explained below. Table 6-1 White D alignment values - LED - Minolta CA-210
The following items can be aligned:
• White point Value Cool (9420K) Normal (8120K) Warm (6080K)
• Ambilight. x 0.282 0.292 0.320
y 0.298 0.311 0.345
To store the data:
• Press OK on the RC before the cursor is moved to the
left Table 6-2 White D alignment values - LED - Minolta CS-200
• In main menu select “Store” and press OK on the RC
• Switch the set to stand-by mode. Value Cool (11000K) Normal (9000K) Warm (6500K)
x 0.276 0.287 0.313
For the next alignments, supply the following test signals via a y 0.282 0.296 0.329
video generator to the RF input:

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EN 42 6. Q552.2L LA Alignments

If you do not have a color analyzer, you can use the default 6.4 Option Settings
values. This is the next best solution. The default values are
average values coming from production. 6.4.1 Introduction
• Select a COLOUR TEMPERATURE (e.g. COOL,
NORMAL, or WARM).
The microprocessor communicates with a large number of I2C
• Set the RED, GREEN and BLUE default values according
to the values in Table 6-3. ICs in the set. To ensure good communication and to make
digital diagnosis possible, the microprocessor has to know
• When finished press OK on the RC, then press STORE (in
which ICs to address. The presence / absence of these
the SAM root menu) to store the aligned values to the NVM.
• Restore the initial picture settings after the alignments. PNX51XX ICs (back-end advanced video picture improvement
IC which offers motion estimation and compensation features
(commercially called HDNM) plus integrated Ambilight control)
Table 6-3 White tone default setting 32" sets (Blockbuster)
is made known by the option codes.

White Tone e.g. 32PFL6606/xx Notes:


Colour Temp R G B • After changing the option(s), save them by pressing the OK
Normal t.b.d. t.b.d. t.b.d. button on the RC before the cursor is moved to the left,
Cool t.b.d. t.b.d. t.b.d. select STORE in the SAM root menu and press OK on the
Warm t.b.d. t.b.d. t.b.d. RC.
• The new option setting is only active after the TV is
Table 6-4 White tone default setting 40" sets (Blockbuster) switched “off” / “stand-by” and “on” again with the mains
switch (the NVM is then read again).
White Tone e.g. 40PFL6606/xx
Colour Temp R G B 6.4.2 Dealer Options
Normal 117 127 95
Cool 113 127 111 For dealer options, in SAM select “Dealer options”.
Warm 126 125 60 See Table 6-11 SAM mode overview.

Table 6-5 White tone default setting 32" sets (Emmy) 6.4.3 (Service) Options

White Tone e.g. 32PFL7606/xx From 2011 onwards, it is not longer possible to change
Colour Temp R G B individual option settings in SAM. Options can only be changed
Normal 112 127 85 all at once by using the option codes as described in section
Cool 106 127 100 6.4.4.
Warm 125 126 53
6.4.4 Opt. No. (Option numbers)
Table 6-6 White tone default setting 40" sets (Emmy)
Select this sub menu to set all options at once (expressed in
White Tone e.g. 40PFL7606/xx
two long strings of numbers).
Colour Temp R G B
An option number (or “option byte”) represents a number of
Normal 115 127 84
different options. When you change these numbers directly,
Cool 111 127 99
you can set all options very quickly. All options are controlled
Warm 125 127 49
via eight option numbers.
When the NVM is replaced, all options will require resetting. To
be certain that the factory settings are reproduced exactly, you
Table 6-7 White tone default setting 46" sets (Emmy) must set both option number lines. You can find the correct
option numbers on a sticker inside the TV set.
White Tone e.g. 46PFL7606/xx Example: The options sticker gives the following option
Colour Temp R G B numbers:
Normal 124 127 98 • 08192 00133 01387 45160
Cool 120 127 121 • 12232 04256 00164 00000
Warm 127 121 58 The first line (group 1) indicates hardware options 1 to 4, the
second line (group 2) indicate software options 5 to 8.
Every 5-digit number represents 16 bits (so the maximum value
Table 6-8 White tone default setting 42" sets (Sundance)
will be 65536 if all options are set).
When all the correct options are set, the sum of the decimal
White Tone e.g. 42PFL8606/xx
values of each Option Byte (OB) will give the option number.
Colour Temp R G B
Normal 125 125 127
Cool 106 108 127
Diversity
Warm 127 110 79
Not all sets with the same Commercial Type Number (CTN)
necessarily have the same option code!
Use of Alternative BOM => an alternative BOM number usually
Table 6-9 White tone default setting 47" sets (Sundance) indicates the use of an alternative display or power supply. This
results in another display code thus in another Option code.
White Tone e.g. 47PFL8606/xx Refer to Chapter 2. Technical Specifications, Diversity, and
Colour Temp R G B Connections.
Normal t.b.d. t.b.d. t.b.d.
Cool t.b.d. t.b.d. t.b.d. 6.4.5 Option Code Overview
Warm t.b.d. t.b.d. t.b.d.

Refer to the sticker in the set for the correct option codes.
Important: after having edited the option numbers as
described above, you must press OK on the remote control
before the cursor is moved to the left!

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Alignments Q552.2L LA 6. EN 43

6.4.6 Option Bit Overview Caution


When manipulating option codes, know what you’re doing.
For test purposes, please find below an overview of the Option Wrong option codes could damage the set.
Codes on bit level. With a bin/dec converter, you can calculate Prescribed option codes below are an example, not valid for all
the Option Code. sets and are subject to modification.
The correct option codes are always present on a sticker inside
the set!

Table 6-10 Option codes at bit level (Option 1 - Option 8)

Option & Bit Dec. Value Option Name Prescribed Value1) Description
Option 1 (prescribed value 327761))
Bit 15 (MSB) 32768 Video Store Streaming 11) 0 = OFF
1 = ON
Bit 14 16384 Multi App 001) 00 = none
01 = multi app (Multiview BASIC)
Bit 13 8192
10 = AVPIP + multi app (Multiview ENHANCED)
11 = future use
Bit 12 4096 Perfect Pixel 001) 00 = Pixel Plus HD
01 = Pixel Precise HD
Bit 11 2048
10 = Perfect Pixel HD
11 = future use
Bit 10 1024 Tuner Type 0001) 000 = TH2603 (Europe/AP)
001 = FA2307 (Brazil)
Bit 9 512
010 = VA1E1ED2411
Bit 8 256 011 = future use
100 = future use
101 = future use
110 = future use
111 = future use
Bit 7 128 PQ Profiles 0001) 000 = profile 0
001 = profile 1
Bit 6 64
010 = profile 2
Bit 5 32 011 = profile 3
100 = profile 4
101 = profile 5
110 = profile 6
111 = profile 7
Bit 4 16 DNM 011) 00 = Perfect Natural Motion
01 = HD Natural Motion
Bit 3 8
10 = future use
11 = future use
Bit 2 4 MOP AL 01) CPLD, not used in 2011
Bit 1 2 AL Optical Syst 001) 00 = 140 nit
01 = 200 nit
Bit 0 (LSB) 1
10 = future use
11 = future use
Option 2 (prescribed value 000011))
Bit 15 (MSB) 32768 AL Shop Mode 01) 0 = boost mode in shop is OFF
1 = boost mode in shop is ON
Bit 14 16384 AL settings storage location 01) 0 = stored in AL modules
1 = stored in SSB
Bit 13 8192 Wall Adaptive AL 01) 0 = OFF
1 = ON
Bit 12 4096 Sunset 01) 0 = OFF
1 = ON
Bit 11 2048 Ambient Light 00001) 0000 = none
0001 = 2-sided (3/3)
Bit 10 1024
0010 = 2-sided (4/4)
Bit 9 512 0011 = 2-sided (5/5)
Bit 8 256 0100 = 2-sided (6/6)
0101 = 2-sided (7/7)
0110 = 3-sided (5/5/5)
0111 = 3-sided (6/6/6)
1000 = 3-sided (3/6/3)
1001 = 3-sided (6/9/6)
1010 = 2-sided (8/8)
1011 = 3-sided (4/4/4)
1100 = 2-sided (1/1)
1101 = 2-sided (2/2)
1110 = future use
1111 = future use
Bit 7 128 FPGA3Dact/1Ddimm 01) 0 = OFF
1 = ON
Bit 6 64 AL Select 01) 0 = AL2k10
1 = AL2k11
Bit 5 32 3D Passive 01) 0 = 2D
1 = 3D passive
Bit 4 16 Smart Bit Enhancement (SBE) 01) 0 = off
1 = on (200 Hz board present)
Bit 3 8 Super Resolution 01) 0 = Super Resolution SD
1 = Super Resolution HD
Bit 2 4 Light Sensor LUT 001) 00 = Lut 0
01 = Lut 1
Bit 1 2
10 = Lut 2
11 = Lut 3
Bit 0 (LSB) 1 Light Sensor 11) 0 = OFF
1 = ON
Option 3 (prescribed value 154211))
Bit 15 (MSB) 32768 Side IO 01) 0 = not present
1 = present

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EN 44 6. Q552.2L LA Alignments

Option & Bit Dec. Value Option Name Prescribed Value1) Description
Bit 14 16384 AV3 0111) 000 = none
001 = CVBS
Bit 13 8192
010 = YPbPr
Bit 12 4096 011 = YPbPr/LR
100 = YPbPr/HV/LR
101 = CVBS/LR
110 = CVBS/Yc/LR
111 = future use
Bit 11 2048 AV2 111) 00 = Scart/CVBS/RGB/LR
01 = CVBS/LR
Bit 10 1024
10 = YPbPr/LR
11 = none
Bit 9 512 AV1 001) 00 = Scart/CVBS/RGB/LR
01 = CVBS/YC/YPbPr/HV/LR
Bit 8 256
10 = CVBS/YC/YPbPr/LR
11 = YPbPr/LR
Bit 7 128 3D Prepared 01) 0 = not prepared
1 = prepared
Bit 6 64 Sound in Stand 01) 0 = Sound in Cabinet
1 = Sound in Stand
Bit 5 32 Headphone 11) 0 = OFF
1 = ON
Bit 4 16 Seamless System 11) 0 = OFF
1 = ON
Bit 3 8 ViewPort 21_9/PQL 11) 0 = OFF
1 = ON
Bit 2 4 HDMI Side 11) 0 = OFF
1 = ON
Bit 1 2 HDMI 3 01) 0 = OFF
1 = ON
Bit 0 (LSB) 1 HDMI 2 11) 0 = OFF
1 = ON
Option 4 (prescribed value 022351))
Bit 15 (MSB) 32768 Cabinet 000011) Cabinet type
(no detailed info available)
Bit 14 16384
Bit 13 8192
Bit 12 4096
Bit 11 2048
Bit 10 1024 Region 0001) 000 = Europe (/02, /05 & /12)
001 = AP PAL multi
Bit 9 512
010 = AP NTSC
Bit 8 256 011 = Russian (/60)
100 = Latam (/78 & /77)
101 = Australia
110 = China (/93)
111 = future use
Bit 7 128 Display MSB 11) 0 = display option =< 255
1 = display option > 255
Bit 6 64 S Video 01) 0 = OFF
1 = ON
Bit 5 32 Video Store SD Card 11) 0 = OFF
1 = ON
Bit 4 16 Internet SW Upgrade 11) 0 = OFF
1 = ON (automatic software upgradable via internet)
Bit 3 8 Online Service 11) 0 = OFF
1 = ON (connection to internet provider Philips)
Bit 2 4 WiFi 01) 0 = OFF
1 = ON (wireless connection to ethernet; no link with “Ethernet op-
tion” bit “0”)
Bit 1 2 DLNA 11) 0 = OFF
1 = PC link
Bit 0 (LSB) 1 Ethernet 11) 0 = OFF
1 = Ethernet vonnector and HW present
Option 5 (prescribed value 438471))
Bit 15 (MSB) 32768 8 Days EPG 11) 0 = OFF
1 = ON (country dependent)
Bit 14 16384 DVBC Installation 011) 00 = OFF
01 = Country dependent
Bit 13 8192
10 = ON
11 = future use
Bit 12 4096 DVBT Installation 011) 00 = OFF
01 = Country dependent
Bit 11 2048
10 = ON
11 = future use
Bit 10 1024 DVB-S 01) 0 = OFF
1 = ON (ATSC/DVB should be ON)
Bit 9 512 DVB-C 11) 0 = OFF
1 = ON (ATSC/DVB should be ON)
Bit 8 256 DVB 11) 0 = analogue only
1 = DVBT (and C/S depending DVBC/S option)
Bit 7 128 Display Type 010001111) Display Type (ex.: 327)
Bit 6 64
Bit 5 32
Bit 4 16
Bit 3 8
Bit 2 4
Bit 1 2
Bit 0 (LSB) 1

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Alignments Q552.2L LA 6. EN 45

Option & Bit Dec. Value Option Name Prescribed Value1) Description
Option 6 (prescribed value 366151))
Bit 15 (MSB) 32768 E-sticker 11) 0 = OFF
1 = ON
Bit 14 16384 Hotel Mode 001) 00 = OFF
01 = 1V1
Bit 13 8192
10 = 1V2
11 = future use
Bit 12 4096 Virgin 01) 0 = ON
1 = OFF
Bit 11 2048 USB Time Shift 11) 0 = OFF
1 = ON
Bit 10 1024 Auto Store Mode 111) 00 = none
01 = PDC_VPS
Bit 9 512
10 = TXT page
11 = PDC_VPS_TXT
Bit 8 256 PVR 11) 0 = OFF
1 = ON
Bit 7 128 Ginga 001) 00 = OFF
01 = Country dependent
Bit 6 64
10 = ON
11 = future use
Bit 5 32 MHP 001) 00 = OFF
01 = Country dependent
Bit 4 16
10 = ON
11 = future use
Bit 3 8 Over the Air Download 011) 00 = OFF
01 = Country dependent
Bit 2 4
10 = ON
11 = future use
Bit 1 2 DVBC light 11) 0 = OFF
1 = ON (when DVBC Installation is OFF or when ON but selected
country is OFF, this option is used)
Bit 0 (LSB) 1 DVBT light 11) 0 = OFF
1 = ON (when DVBT Installation is OFF or Country depend to a
country is OFF, this option is used)
Option 7 (prescribed value 330241))
Bit 15 (MSB) 32768 Visual Identity 11) 0 = User Interface 2k10
1 = User Interface 2k11
Bit 14 16384 Red LED Config LUT 0001) 000 = LED config LUT 0
001 = LED config LUT 1
Bit 13 8192
010 = LED config LUT 2
Bit 12 4096 011 = LED config LUT 3
100 = LED config LUT 4
101 = LED config LUT 5
110 = LED config LUT 6
111 = LED config LUT 7
Bit 11 2048 Board Identifier 001) not used, should always be “00”
Bit 10 1024
Bit 9 512 Manet 01) 0 = all sets except Manet
1= Manet
Bit 8 256 Auto Power Down 11) 0 = OFF
1 = ON
Bit 7 128 Light Guide 01) 0 = OFF
1 = ON
Bit 6 64 E-box 01) 0 = integrated set
1 = e-box/monitor
Bit 5 32 Temp LUT 0001) 000 = temp lut 0
001 = temp lut 1
Bit 4 16
010 = temp lut 2
Bit 3 8 011 = temp lut 3
100 = future use
101 = future use
110 = future use
111 = future use
Bit 2 4 Temp Sensor 001) 00 = no temp sensor
01 = temp sensor in display
Bit 1 2
10 = temp sensor on additional board
11 = temp sensor in AL module
Bit 0 (LSB) 1 FAN 01) 0 = no fan
1 = fan(s) present)
Option 8 (prescribed value 000121))
Bit 15 (MSB) 32768 Test 8 01) -
Bit 14 16384 Test 7 01) -
Bit 13 8192 Test 6 01) -
Bit 12 4096 Test 5 01) -
Bit 11 2048 Test 4 (Trick Mode) 01) 0 = OFF
1 = ON
Bit 10 1024 Test 3 (XRay) 01) 0 = OFF
1 = ON
Bit 9 512 Test 2 (DBV-T light) 01) 0 = OFF
1 = ON
Bit 8 256 Test 1 (Monitor out) 01) 0 = OFF
1 = ON
Bit 7 128 not used 00001) -
Bit 6 64
Bit 5 32
Bit 4 16
Bit 3 8 WM DRM10 11) 0 = OFF
1 = ON

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EN 46 6. Q552.2L LA Alignments

Option & Bit Dec. Value Option Name Prescribed Value1) Description
Bit 2 4 HBBTV 11) 0 = OFF
1 = ON
Bit 1 2 DVB-T2 Installation 01) 0 = OFF
1 = ON
Bit 0 (LSB) 1 DVB-T2 01) 0 = OFF
1 = ON

Note In case of a display replacement, reset the “Operation hours


1). Example display” to “0”, or to the operation hours of the replacement
display.

6.5 Reset of Repaired SSB


6.5.1 SSB identification

A very important issue towards a repaired SSB from a Service


Whenever ordering a new SSB, it should be noted that the
repair shop (SSB repair on component level) implies the reset
correct ordering number (12nc) of a SSB is located on a sticker
of the NVM on the SSB.
on the SSB. The format is <12nc SSB><serial number>. The
A repaired SSB in Service should get the service Set type
ordering number of a “Service” SSB is the same as the ordering
“00PF0000000000” and Production code “00000000000000”.
number of an initial “factory” SSB.
Also the virgin bit is to be set. To set all this, you can use the
ComPair tool or use the “NVM editor” and “Dealer options”
items in SAM (do not forget to “store”).

After a repaired SSB has been mounted in the set (set repair
on board level), the type number (CTN) and production code of
the TV has to be set according to the type plate of the set. For
this, you can use the NVM editor in SAM. This action also
ensures the correct functioning of the “Net TV” feature and
access to the Net TV portals. The loading of the CTN and
production code can also be done via ComPair (Model number
programming).

After a SSB repair, the original channel map can be restored,


provided that the original channel map was stored on a USB
stick before repair was commenced and that basic functionality
of the TV, needed for this procedure, was not hampered as a
result of the defect. The procedure of “channel map cloning” is
clearly described in the (electronic) user manual. 18310_221_090318.eps
090319

6.6 Total Overview SAM modes

Table 6-11 SAM mode overview

Main Menu Sub-menu 1 Sub-menu 2 Sub-menu 3 Description


Hardware Info A. SW version e.g. “Q5551_0.9.1.0 Display TV & Stand-by SW version and CTN serial
B. Stand-by processor version e.g. “STDBY_83.84.0.0” number

C. Production code e.g. “see type plate”


Operation hours Displays the accumulated total of operation hours.TV
switched “on/off” & every 0.5 hours is increase one
Errors Displayed the most recent errors
Reset error buffer Clears all content in the error buffer
Alignment White point Colour temperature Normal 3 different modes of colour temperature can be
Warn selected

Cool
White point red LCD White Point Alignment. For values,
White point green see Table 6-3 White tone default setting 32" sets
(Blockbuster)
White point blue
Ambilight Select module
Brightness
Select matrix
Dealer options Virgin mode Off/On Select Virgin mode On/Off. TV starts up / does not
start up (once) with a language selection menu after
the mains switch is turned “on” for the first time (virgin
mode)
E-sticker Off/On Select E-sticker On/Off (USP’s on-screen)
Auto store mode None
PDC/VPS
TXT page
PDC/VPS/TXT
Option numbers Group 1 e.g. “00008.00001.15421.02239” The first line (group 1) indicates hardware options 1
to 4
Group 2 e.g. “44816.34311.33024.00000” The second line (group 2) indicates software options
5 to 8
Store Store after changing
Initialise NVM N.A.

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Alignments Q552.2L LA 6. EN 47

Main Menu Sub-menu 1 Sub-menu 2 Sub-menu 3 Description


Store Select Store in the SAM root menu after making any
changes
Operation hours display 0003 In case the display must be swapped for repair, you
can reset the “”Display operation hours” to “0”. So,
this one does keeps up the lifetime of the display
itself (mainly to compensate the degeneration
behaviour)
Software maintenance Software events Display Display information is for development purposes
Clear
Test reboot
Test cold reboot
Test application crash
Hardware events Display Display information is for development purposes
Clear
Test setting Digital info Current frequency: 538
QAM modulation: 64-qam Display information is for development purposes
Symbol rate:
Original network ID: 12871
Network ID: 12871
Transport stream ID: 2
Service ID: 3
Hierarchical modulation: 0
Selected video PID: 35
Selected main audio PID: 99
Selected 2nd audio PID: 8191
Install start frequency 000 Install start frequency from “0” MHz
Install end frequency 999 Install end frequency as “999” MHz
Default install frequency
Installation Digital only Select Digital only or Digital + Analogue before
Digital + Analogue installation

Development file Development 1 file version Display parameters DISPT5.0.9.29 Display information is for development purposes
versions Acoustics parameters ACSTS
5.0.6.20
PQ - TV550 1.0.27.22
PQS- Profile set
PQF - Fixed settings
PQU - User styles
Ambilight parameters PRFAM 5.0.5.2
Development 2 file version 12NC one zip software Display information is for development purposes
Initial main software
NVM version Q55x1_0.4.5.0
Flash units software
Temp com file version none
Upload to USB Channel list To upload several settings from the TV to an USB
Personal settings stick

Option codes
Alignments
Identification data
History list
All (options included)
Download from USB Channel list To download several settings from the USB stick to
Personal settings the TV

Option codes
Alignments
Identification data
All (options included)
NVM editor Type number see type plate NVM editor; re key-in type number and production
AG code see type plate code after SSB replacement

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EN 48 7. Q552.2L LA Circuit Descriptions

7. Circuit Descriptions
Index of this chapter: • removal of TCON from the SSB (comes with the display)
7.1 Introduction • changed power architecture
7.2 Power Supply • new USB hub (where applicable).
7.3 DC/DC Converters
7.4 Front-End Analogue and DVB-T, DVB-C; ISDB-T reception The Q552.2L LA chassis comes with the following stylings:
7.5 Front-End DVB-S(2) reception • Berlinale (series xxPFL58xx),
7.6 HDMI • Blockbuster (series xxPFL66xx),
7.7 Video and Audio Processing - PNX855xx • Emmy (series xxPFL76xx),
• Sundance (series xxPFL86xx).
Notes:
• Only new circuits (circuits that are not published recently) 7.1.1 Implementation
are described.
• Figures can deviate slightly from the actual situation, due
Key components of this chassis are:
to different set executions.
• PNX855xx System-On-Chip (SOC) TV Processor
• For a good understanding of the following circuit • TX26xx Hybrid Tuner (DVB-T/C, analogue)
descriptions, please use the wiring-, block- (see chapter
• STV6110AT DVB-S Satellite Tuner
9. Block Diagrams) and circuit diagrams (see chapter
• SII9x87 HDMI Switch
10. Circuit Diagrams and PWB Layouts).Where necessary, • TPA312xD2PWP Class D Power Amplifier
you will find a separate drawing for clarification.
• LAN8710 Dual Port Gigabit Ethernet media access
controller.
7.1 Introduction
7.1.2 TV550 Architecture Overview
The Q552.2L LA is part of the TV550 platform and uses the
(same) PNX855xx chipset. For details about the chassis block diagrams refer to chapter 9.
The major deltas versus its predecessor Q551 are: Block Diagrams. An overview of the TV550 2011 architecture
• support of DVB-T2 (“second generation” DVBT) can be found in Figure 7-1.
• implementation of “passive” 3D

19110_053_110421.eps
110421

Figure 7-1 Architecture of TV550 platform 2011

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Circuit Descriptions Q552.2L LA 7. EN 49

7.1.3 SSB Cell Layout

19110_052_110421.eps
110421

Figure 7-2 SSB layout cells (top view)

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EN 50 7. Q552.2L LA Circuit Descriptions

7.2 Power Supply Stand-by microcontroller and ENABLE-3V3n is the signal


coming from the Stand-by microcontroller.
7.2.1 Power Supply Unit
Diagram B03D contains the following linear stabilizers:
• +2V5 stabilizer, built around item no. 7UCO
All power supplies are a black box for Service. When defective,
• +5V-TUN stabilizer, built around items no. 7UA6 and 7UA7
a new board must be ordered and the defective one must be
returned, unless the main fuse of the board is broken. Always • +1V2 stabilizer, built around items no. 7UA3 and 7UA4.
replace a defective fuse with one with the correct
specifications! This part is available in the regular market. Diagram B08A contains the DVB-S2-related DC/DC
Consult the Philips Service web portal for the order codes of the converters and -stabilizers:
boards. • a +24V under-voltage detection circuitry is built around
item no. 7T04
• the switching frequency of the 24 to 14...20V switched
In this manual, no detailed information is available because of
design protection issues. mode converter is 350 kHz (item no. 7T03 and +V-LNB
lines)
• the output signal on the +V-LNB line goes to the LNBH23Q
7.2.2 Connector overview
(item no. 7T50)
• the LNBH23Q (item no. 7T50) sends a feedback signal via
Table 7-1 Connector overview the V0-CNTRL line
• the switching frequency of the +5V-DVBS to +1-DVBS
Connector switched mode converter is 900 kHz (item no. 7T00)
no. 1308 1316 1M95 • a delay line for the +2V5-DVBS and +1V-DVBS lines is
Descr. Mains to display to SSB created with item no. 3T03 (R=10k) and 2T06 (C=100n)
Pin CN1 CN2 CN4 • a 3.3V to 2.5V linear stabilizer is built around item no. 7T01
1 N Anode 1 +3V3stdby • a 5V to 3.3V linear stabilizer is built around item no. 7T02.
2 L n.c. Standby
3 - Cathode 1 GND1 Diagram B08B contains the DVB-S2 LNB supply:
4 - n.c. GND1 • the +V-LNB signal comes from item no. 7T03
5 - Anode 2 +12V • the V0-CTRL signal goes to item no. 7T03
6 - n.c. +12V • the LNB-RF1 goes to the LNB.
7 - Cathode 2 +Vsnd
8 - n.c. GND_SND
Figures gives a graphical representation of the DC/DC
9 - Anode 3 BL-ON-OFF
converters with its current consumptions:
10 - n.c. BL-DIM1 (Vsync)
11 - Cathode 3 BL-I-CTRL
+ 5V 5-TUN
12 - n.c. POK 196 m A
+ 5V + 5V 5-TUN + 5V -TUN
13 - Anode 4 +24V (AL2_DVBS) + 5V
2179 m A
+ 5V -TUN
196 m A
dc -dc s tabiliz er
14 - n.c. GND1
15 - Cathode 4 -

+ 12V + 3V 3 + 3V 3 + 2V 5
+ 3V 3 + 2V 5
2919 m A 2371 m A 450 m A
dc -dc s tabiliz er
7.3 DC/DC Converters

The on-board DC/DC converters deliver the following voltages + 1V 8


+ 1V 8 + 1V 8
+ 1V 2
+ 1V 2
2450 m A 550 m A
dc -dc s tabiliz er
(depending on set execution):
• +3V3-STANDBY, permanent voltage for the Stand-by
controller, LED/IR receiver and controls; connector 1M95
+ 1V 1
pin 1 + 1V 1
dc -dc
5100 m A

• +12V, input from the power supply for TV550 common


(active mode); connector 1M95 pins 6, 7 and 8 18770_226_100127.eps
• +24V, input from the power supply for DVB-S2 (in active 100426
mode); connector 1M09 pins 1 and 2
• +1V1, core voltage supply for PNX855xx; has to be started Figure 7-3 DC/DC converters
up first and switched "off" last (diagram B03B)
• +1V2, supply voltage for analogue blocks inside PNX855xx
• +1V8, supply voltage for DDR2 (diagram B03B) 7.4 Front-End Analogue and DVB-T, DVB-C;
• +2V5, supply voltage for analogue blocks inside PNX855xx ISDB-T reception
(see diagram B03E)
• +3V3, general supply voltage (diagram B03E) 7.4.1 Brazil region
• +5V, supply voltage for USB and CAM (diagram B03E)
• +5V-TUN, supply voltage for tuner (diagram B03E) The Front-End for the Brazil region consist of the following key
• +V-LNB, input voltage for LNB supply IC (item no. 7T50) components:
• +5V-DVBS, input intermediate supply voltage for DVB-S2
(diagram B08A)
• Hybrid Tuner with integrated SAW filter and amplifier
• +3V3-DVBS, clean voltage for silicon tuner and DVB-S2
• External ISDB-T channel decoder covering the Brazilian
channel decoder
digital terrestrial TV standard
• +2V5-DVBS, clean voltage for DVB-S2 channel decoder
• Bandpass filter
• +1V-DVBS, core voltage for DVB-S2 channel decoder.
• Amplifier
• PNX85500 SoC TV with integrated analogue demodulator.
A +12 V under-voltage detector (see diagram B03C) enables
the 12V to 3.3V and 12V to 5V DC/DC converters via the
Below find a block diagram of the front-end application for this
ENABLE-3V3-5V line, and the 12V to 1.8V DC/DC converter
region.
via the ENABLE-1V8 line. DETECT2 is the signal going to the

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Circuit Descriptions Q552.2L LA 7. EN 51

18770_236_100127.eps
100219

Figure 7-4 Front-End block diagram Brazil region

7.5 Front-End DVB-S(2) reception

The Front-End for the DVB-S(2) application consist of the


following key components:

• Satellite Tuner; I2C address 0xC6 (bridged via channel


decoder) 18770_243_100203.eps
• Channel decoder; I2C address 0xD0 100203
• LNB switching regulator; I2C address 0x14
• Amplifier Figure 7-6 HDMI input configuration
• PNX855xx SoC TV processor with integrated DVB-T and
DVB-C channel decoder and analogue demodulator. The following multiplexers can be used:
• Sil9187A (does not support “Instaport” technology for fast
Below find a block diagram of the front-end application for switching between input signals)
DVB-S(2) reception. • Sil9287B (supports “Instaport” technology for fast
switching between input signals).
The hardware default I2C addresses are:
• Sil9187A: 0xB0/0xB2 (random: software workaround)
• Sil9287B: 0xB2 (fixed).

The Sil9x87 has the following specifications:


• +5V detection mechanism
• Stable clock detection mechanism
• Integrated EDID
• RT control
• HPD control
• Sync detection
• TMDS output control
• CEC control
18770_237_100127.eps • EDID stored in Sil9x87, therefore there are no EDID pins
100219 on the SSB.

Figure 7-5 Front-End block diagram DVB-S(2) reception


7.7 Video and Audio Processing - PNX855xx
This application supports the following protocols:
• Polarization selection via supply voltage (18V = horizontal, The PNX855xx is the main audio and video processor (or
13V = vertical) System-on-Chip) for this platform. It has the following features:
• Band selection via “toneburst” (22 kHz): tone “on” = “high”
band, tone “off” = “low” band • Multi-standard digital video decoder (MPEG-2, H.264,
• Satellite (LNB) selection via DiSEqC 1.0 protocol MPEG-4)
• Reception of DVB-S (supporting QPSK encoded signals) • Integrated DVB-T/DVB-C channel decoder
and DVB-S2 (supporting QPSK, 8PSK, 16APSK and • Integrated CI+
32APSK encoded signals), introducing LDPC low-density • Integrated motion accurate picture processing (MAPP2)
parity check techniques. • High definition ME/MC
• 2D LED backlight dimming option
7.6 HDMI • Embedded HDMI HDCP keys
• Extended colour gamut and colour booster
• Integrated USB2.0 host controller
In this platform, the Silicon Image Sil9x87 HDMI multiplexer is • Improved MPEG artefact reduction compared with
implemented. Refer to figure 7-6 HDMI input configuration for PNX8543
the application. • Security for customers own code/settings (secure flash).

The TV550 combines front-end video processing functions,


such as DVB-T channel decoding, MPEG-2/H.264 decode,
analog video decode and HDMI reception, with advanced
back-end video picture improvements. It also includes next
generation Motion Accurate Picture Processing (MAPP2). The
MAPP2 technology provides state-of-the-art motion artifact
reduction with movie judder cancellation, motion sharpness
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EN 52 7. Q552.2L LA Circuit Descriptions

and vivid colour management. High flat panel screen combination with LED backlights for optimum contrast and
resolutions and refresh rates are supported with formats power savings up to 50%.
including 1366 × 768 @ 100Hz/120Hz and 1920 × 1080 @
100Hz/120Hz. The combination of Ethernet, CI+ and H.264 For a functional diagram of the PNX855xx, refer
supports new TV experiences with IPTV and VOD. On top of to Figure 7-7.
that, optional support is available for 2D dimming in

PNX85500x
MEMORY
CONTROLLER

TS input MPEG
CI/CA SYSTEM LVDS for
TS out/in for PROCESSOR PRIMARY flat panel display
PCMCIA VIDEO LVDS (single, dual or
OUTPUT quad channel)

DVB DVB-T/C
channel decoder
AV-PIP
SUB-PICTURE
VIDEO
CVBS, Y/C, 3D COMB
DECODER
RGB
SECONDARY VIDEO
VIDEO ENCODER analog CVBS
OUTPUT

Low-IF DIGITAL IF MPEG/H.264


VIDEO Motion-accurate
DECODER pixel processing

SCALER,
AUDIO DEMOD DE-INTERLACE
SSIF, LR
AND DECODE AND NOISE
REDUCTION

AUDIO DACS analog audio


SPDIF AUDIO IN
AUDIO DSP
I 2S
AUDIO OUT
HDMI SPDIF
HDMI 450 MHz
RECEIVER AV-DSP

SYSTEM 560 MHz DRAWING


CONTROLLER MIPS32 ENGINE
(8051) 24KEf CPU

DMA BLOCK

I2C PWM GPIO IR ADC SPI UART I 2C GPIO Flash USB 2.0 SD Ethernet
x8 Memory MAC
Card

18770_241_100201.eps
100219

Figure 7-7 PNX855xx functional diagram

7.8 Ambilight with the CPLD located on the SSB whereas the Slave Ambilight
module communicates via the PWM communication protocol
with the Master Ambilight module.
Sets in the xxPFL7606D/xx range are equipped with Ambilight.
The supply voltage of the modules is +24 V.
For the implementation of Ambilight, refer to Figure 7-8.
Refer to Figure 7-9 and Figure 7-10 for the Ambilight board
1 1 1 1
implementation.
M M M M
PNX85500 CPLD SPI 9
SPI 8 AmbiLight 8
PWM 8 AmbiLight
5 3 5 6

SSB

19111_009_110519.eps
110519

Figure 7-8 Ambilight configuration

The Ambilight implementation consists of 2 separate units in


the set, where the Ambilight module located on the right (seen
from the back of the set) acts as a Master and the module on
the left acts as a Slave.
The NVM is located on the Master Ambilight module. This
module communicates via the SPI communication protocol

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Circuit Descriptions Q552.2L LA 7. EN 53

AMBI-SPI-SDI

AMBI-SPI-SDO

EEPROM +24 V

AMBI-SPI-CLK LED PWM-R3


1M83

1M85
PWM-G3
Driver PWM-B3
AMBI-SPI-CLK CS-Local PWM-R4
OR PWM-G4
PWM-B4

AMBI-PWM-CLK

AMBI-BLANK

AMBI-PROG

AMBI-LATCH

19111_010_110519.eps
110519

Figure 7-9 Master Ambilight module

PWM-R3
+24 V
PWM-G3
+24 V
1M86

PWM-B3
+24 V
PWM-R4
+24 V
PWM-G4
+24 V
PWM-B4
+24 V

19111_011_110519.eps
110519

Figure 7-10 Slave Ambilight module

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EN 54 8. Q552.2L LA IC Data Sheets

8. IC Data Sheets
This chapter shows the internal block diagrams and pin electrical diagrams (with the exception of “memory” and “logic”
configurations of ICs that are drawn as “black boxes” in the ICs).

8.1 Diagram USB Hub B01C, USB2513B (IC 7F25)

Block diagram
To EEPROM or
To Upstream Upstream SMBus Master
24 MHz
VBUS USB Data SDA SCL
Crystal
3.3 V

Bus- Serial
Power Upstream Regulator PLL Interface
Detect/ PHY
Vbus Pulse
Serial
Repeater Interface Controller
Engine

3.3 V

Regulator
TT
#1
... TT
#x
Port
Controller

CRFILT

Routing & Port Re-Ordering Logic

PHY#1
Port #1
OC Sense
Switch Driver/
LED Drivers
... PHY#x
Port #x
OC Sense
Switch Driver/
LED Drivers

USB Data OC Port USB Data OC Port


Downstream Sense Power Downstream Sense Power
Switch/ Switch/
LED LED
Drivers Drivers

The ‘x’ indicates the number of available downstream ports: 2, 3, 4, or 7.


Note : The LED port indicators only apply to USB2513i.

Pinning information
SDA / SMBDATA / NON_REM[1]
SCL / SMBCLK / CFG_SEL[0]
HS_IND / CFG_SEL[1]
VBUS_DET

RESET_N

VDD33

NC

NC

NC
27
26
25
24
23
22
21
20
19

SUSP_IND / LOCAL_PWR / NON_REM[0] 28 18 NC

VDD33 29 17 OCS_N[2]

USBDM_UP 30 16 PRTPWR[2] / BC_EN[2]*

USBDP_UP 31
SMSC 15 VDD33
USB2512/12A/12B
XTALOUT 32 14 CRFILT
USB2512i/12Ai/12Bi
XTALIN / CLKIN 33 13 OCS_N[1]
(Top View QFN-36)
PLLFILT 34 12 PRTPWR[1] / BC_EN[1]*
Ground Pad
RBIAS 35 (must be connected to VSS) 11 TEST

VDD33 36 10 VDD33
1
2
3
4
5
6
7
8
9
USBDM_DN[1]

USBDM_DN[2]
USBDP_DN[1]

USBDP_DN[2]

VDD33

NC

NC

NC

NC

Indicates pins on the bottom of the device.

18770_301_100217.eps
100217

Figure 8-1 Internal block diagram and pin configuration

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IC Data Sheets Q552.2L LA 8. EN 55

8.2 Diagram Temp sensor & headphone B01J, LM75BDP (IC 7FD1)

Block diagram
VCC

LM75B
BIAS POINTER CONFIGURATION
REFERENCE REGISTER REGISTER

TEMPERATURE
BAND GAP COUNTER
REGISTER
TEMP SENSOR 11-BIT
SIGMA-DELTA
A-to-D TOS
TIMER
CONVERTER REGISTER
OSCILLATOR
COMPARATOR/ THYST
INTERRUPT REGISTER
POWER-ON
RESET OS

LOGIC CONTROL AND INTERFACE

A2 A1 A0 SCL SDA GND

Pinning information

SDA 1 8 VCC
SCL 2 7 A0
LM75BDP
OS 3 6 A1
GND 4 5 A2

18770_300_100217.eps
100217

Figure 8-2 Pin configuration

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EN 56 8. Q552.2L LA IC Data Sheets

8.3 Diagram NANDflash - conditional access B02A, PNX855xx (IC7S00)

Block diagram

PNX8550x
MEMORY
CONTROLLER

TS input MPEG
CI/CA SYSTEM LVDS for
TS out/in for PROCESSOR PRIMARY flat panel display
PCMCIA VIDEO LVDS (single, dual or
OUTPUT quad channel)

DVB DVB-T/C
channel decoder
AV-PIP
SUB-PICTURE
VIDEO
CVBS, Y/C, 3D COMB
DECODER
RGB
SECONDARY VIDEO analog CVBS
VIDEO ENCODER
OUTPUT analog Y/C
Low-IF
DIGITAL IF MULTI-
Direct-IF STANDARD Motion-accurate
VIDEO pixel processing
DECODER

SCALER,
AUDIO DEMOD DE-INTERLACE
SSIF, LR
AND DECODE AND NOISE
REDUCTION

AUDIO DACS analog audio


SPDIF AUDIO IN
AUDIO DSP
I2S
AUDIO OUT
HDMI SPDIF
HDMI 450 MHz
RECEIVER AV-DSP

SYSTEM 500 MHz DRAWING


CONTROLLER MIPS32 ENGINE
(8051) 24KEf CPU

Scatter/Gather
TS Demux

I2C PWM Px_x IR ADC SPI UART I2C GPIO Flash USB 2.0 SD Ethernet
x 10 Memory MAC
Card

Pinning information
ball A1 PNX8550xE
index area 2 4 6 8 10 12 14 16 18 20 22 24 26
1 3 5 7 9 11 13 15 17 19 21 23 25
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF

Transparent top view


18770_308_100217.eps
100217

Figure 8-3 Internal block diagram and pin configuration

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IC Data Sheets Q552.2L LA 8. EN 57

8.4 Diagram Audio B03A, TPA312xD2PWP (IC7D10)

Block diagram

TPA3120D2
1 F
0.22 F
LIN BSR
22 H 470 F
RIN ROUT
1 F 0.68 F
PGNDR

PGNDL 0.68 F
1 F
BYPASS LOUT
22 H 470 F
AGND BSL
0.22 F

PVCCL
AVCC
PVCCR

VCLAMP
Shutdown
SD 1 F
Control

MUTE
GAIN0

GAIN1
} Control

Pinning information
PWP (TSSOP) PACKAGE
(TOP VIEW)

PVCCL 1 24 PGNDL
SD 2 23 PGNDL
PVCCL 3 22 LOUT
MUTE 4 21 BSL
LIN 5 20 AVCC
RIN 6 19 AVCC
BYPASS 7 18 GAIN0
AGND 8 17 GAIN1
AGND 9 16 BSR
PVCCR 10 15 ROUT
VCLAMP 11 14 PGNDR
PVCCR 12 13 PGNDR

I_18020_142.eps
100402

Figure 8-4 Internal block diagram and pin configuration

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EN 58 8. Q552.2L LA IC Data Sheets

8.5 Diagram DC/DC B03B, TPS53126PW (IC7U03)

Block diagram

Pinning information
VBST1 1 28 DRVH1
NC 2 27 LL1
EN1 3 26 DRVL1
VO1 4 25 PGND1
VFB1 5 24 TRIP1
NC
TPS53124

6 23 VIN
GND 7 22 VREG5
TEST1 8 21 V5FILT
NC 9 20 TEST2
VFB2 10 19 TRIP2
VO2 11 18 PGND2
EN2 12 17 DRVL2
NC 13 16 LL2
VBST2 14 15 DRVH2

18310_300_090319.eps
100416

Figure 8-5 Internal block diagram and pin configuration

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IC Data Sheets Q552.2L LA 8. EN 59

8.6 Diagram DC/DC B03E, ST1S10PH (IC 7UD0)

Block diagram

ST1S10PH

Pinning information

DFN8 (4 × 4) PowerSO-8

I_18010_083.eps
110601

Figure 8-6 Internal block diagram and pin configuration

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EN 60 8. Q552.2L LA IC Data Sheets

8.7 Diagram DC/DC B03E, LD1117DT25 (IC 7UD2)

Block diagram
LD1117DT

Pinning information

DPAK

F_15710_166.eps
100402

Figure 8-7 Internal block diagram and pin configuration

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IC Data Sheets Q552.2L LA 8. EN 61

8.8 Diagram Ethernet & Service B04C, LAN8710A-EZKH (IC 7E10)

Block diagram
MODE0 HP Auto-MDIX
MODE1 Auto- 10M Tx 10M
MODE Control
MODE2 Negotiation Logic Transmitter TXP / TXN
Reset Transmit Section
nRST Control RXP / RXN
Management 100M Tx 100M
RMIISEL SMI Logic Transmitter
Control
MDIX
Control
TXD[0:3] XTAL1/CLKIN
TXEN PLL
100M Rx DSP System: Analog-to-
TXER XTAL2
TXCLK Logic Clock Digital
Data Recovery
Interrupt
Equalizer nINT
Generator
RMII / MII Logic

RXD[0:3]
RXDV 100M PLL
RXER Receive Section
RXCLK LED1
LED Circuitry
LED2
10M Rx Squelch &
CRS Logic Filters
COL/CRS_DV
Central
RBIAS
MDC 10M PLL Bias
MDIO
PHY
Address PHYAD[0:2]
Latches

Pinning information
VDD1A
RBIAS

RXDV

TXD3
RXN
RXP

TXN
TXP
32

31

30

29

28

27

26

25

VDD2A 1 24 TXD2

LED2/nINTSEL 2 23 TXD1

LED1/REGOFF 3 22 TXD0
SMSC
XTAL2 4 LAN8710/LAN8710i 21 TXEN

XTAL1/CLKIN 5 32 PIN QFN 20 TXCLK

VDDCR 6
(Top View) 19 nRST

RXCLK/PHYAD1 7 18 nINT/TXER/TXD4
VSS
RXD3/PHYAD2 8 17 MDC
10

11

12

13

14

15

16
9
RXD2/RMIISEL

RXD1/MODE1

RXD0/MDE0

CRS

COL/CRS_DV/MODE2

MDIO
VDDIO

RXER/RXD4/PHYAD0

18770_302_100217.eps
100217

Figure 8-8 Internal block diagram and pin configuration

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EN 62 8. Q552.2L LA IC Data Sheets

8.9 Diagram HDMI B04D, SII9x87B (IC 7EC1)

Block diagram

Pinning information

18770_303_100217.eps
100217

Figure 8-9 Internal block diagram and pin configuration

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IC Data Sheets Q552.2L LA 8. EN 63

8.10 Diagram Headphone B04E, TPA6111A2DGN (IC 7EE1)

Block diagram

VDD 8

VDD/2
2 IN 1− VO1 1

+
3 BYPASS

TPA6111A2

6 IN 2−
− VO2 7
+

5 SHUTDOWN Bias 4
Control

Pinning information
D OR DGN PACKAGE
(TOP VIEW)

VO1 1 8 VDD
IN1− 2 7 VO2
BYPASS 3 6 IN2−
GND 4 5 SHUTDOWN

18770_309_100217.eps
110602

Figure 8-10 Internal block diagram and pin configuration

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EN 64 8. Q552.2L LA IC Data Sheets

Personal Notes:

10000_012_090121.eps
090121

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Block Diagrams Q552.2L LA 9. EN 65

9. Block Diagrams
9-1 Wiring diagram Blockbuster/Emmy 32"
WIRING DIAGRAM 32" BLOCKBUSTER / EMMY

8M85
8M95

TO DISPLAY
8M59

SUPPLY
1316 1M95
10P 14P

1M95 1M59
1M86
18P

1M85
18P
14P 26P

LOUDSPEAKER SSB
(5213) B 3139 123 6521.x

1G50
41P
(1150)

MAIN POWER SUPPLY


32" PLDC-P005A
(1005)

*AMBILIGHT MODULE
*AMBILIGHT MODULE

1D38

SD-CARD
READER
3P
8G50

USB

(1161)
(1162)

1G51

AL
AL

51P
8G51
PHONE

TUNER

HDMI

1M83
26P
1M19
LCD DISPLAY

8P

ETHER
TO DISPLAY TO DISPLAY

SPDIF
NET

SPDIF
51P (1004) 41P
2P HDMI HDMI HDMI VGA
130
8
LOUDSPEAKER

LOUDSPEAKER
8308
(5216)

(5216)
INLET

C2 C1
MAINS
SWITCH

(8308) IR/LED/CONTROL BOARD J1


*AMBILIGHT ONLY APLICABLE FOR EMMY STYLING
(1108) 8P
1316 (PSU) 1M95 (PSU) 1308 (PSU) LEADING EDGE
1M95 (B03C) 1735 (B03A)
1D38 (B03A) 1M19 (B09A) 1M59 (B09A)
1. ANODE 1 1. +3V3STDBY 1. N 1. +3V3-STANDBY 1. LEFT-SPEAKER 1. LIGHT-SENSOR 1. AMBI-SPI-CLK-OUT 15. GND_AL
2. NC 2. STANDBY 2. L 2. STANDBY 2. GND-AUDIO 2. GND 2. GND 16. GND_AL
3. CATHODE 1 3. GND 3. GND 3. GND-AUDIO
RIGHT-SPEAKER 3. RC 3. AMBI-SPI-SDO-OUT 17. GND_AL
4. GND 4. GND 4. GND 4. RIGHT-SPEAKER 4. LED-2 4. AMBI-SPI-SDI-OUT-GI 18. GND_AL
5. ANODE 2 5. +12V 5. +12VIN 5. +3V3-STANDBY 5. V-AMBI 19. GND_AL
6. NC 6. +12V 6. +12VIN 6. LED-1 6. AMBI-PWM-CLK_B2 20. N.C.
7. CATHODE 2 7. +VSND 7. +24V-AUDIO-POWER 1G51 (B06B) 7. KEYBOARD 7. GND 21. +24V
8. NC 8. GND_SND 8. GND 1. +VDISP 8. +5V 8. AMBI-SPI-CS-OUTn_R2 22. +24V
9. ANODE 3 9. BL-ON-OFF 9. LAMP-ON 2. +VDISP 9. AMBI-LATCH1_G2 23. +24V
10. NC 10. BL-DIM1 10. BACKLIGHT-PWM_BL-VS 3. +VDISP 10. V-AMBI 24. +24V
11. CATHODE 3 11. BL-I-CTRL 11. BACKLIGHT-BOOST 4. +VDISP 11. AMBI-BLANK_R1 25. +24V
12. NC 12. POK 12. POWER-OK | 12. AMBI-PROG_B1 26. +24V
13. ANODE 4 13. +24V 13. +24V | 13. AMBI-LATCH2_DIS
14. NC 14. GND1 14. GND 51. CTRL-DISP 14. AMBI-TEMP
15. CATHODE 4
19110_008_110323.eps
110711

2011-Jul-15 back to
div. table
Block Diagrams Q552.2L LA 9. EN 66

9-2 Wiring diagram Blockbuster/Emmy 40" - 46"


WIRING DIAGRAM 40"- 46" BLOCKBUSTER / EMMY

TO DISPLY
SUPPLT

1316
10P

1M99
14P
8M95
1M86
18P

1M85
18P
1M95 1M59
MAIN POWER SUPPLY 14P 26P

40" PLDE-P008A
46" PLDG-P010A

1G50
41P
(1005)

8M59
SSB
B

*AMBILIGHT MODULE 24 LED


*AMBILIGHT MODULE 24 LED

3139 123 6521.x


(1150)

SD-CARD
READER
1D38
3P
1308
2P

USB
1G51

(1161)
(1162)

51P
PHONE

TUNER
LOUDSPEAKER 8G51

HDMI
(5213)

AL
8G50
AL

1M19
8P

ETHER

SPDIF
NET

SPDIF
HDMI HDMI HDMI VGA

1M83
26P
TO DISPLAY LCD DISPLAY TO DISPLAY
51P (1004) 41P

8308

INLET

LOUDSPEAKER LOUDSPEAKER
(5216) (5216)

MAINS C2 C1
SWITCH

(8308)
*AMBILIGHT ONLY APLICABLE FOR EMMY STYLING IR/LED/CONTROL BOARD J1
1316 (PSU) 1M95 (PSU) 1308 (PSU) (1108) 8P 1M95 (B03C) 1D38 (B03A) 1G51 (B06B) 1M59 (B09A)
1. ANODE 1 1. +3V3STDBY 1. N 1. +3V3-STANDBY 1. LEFT-SPEAKER 1. +VDISP 1. AMBI-SPI-CLK-OUT 15. GND_AL
2. NC 2. STANDBY 2. L LEADING EDGE 2. STANDBY 2. GND-AUDIO 2. +VDISP 2. GND 16. GND_AL
3. CATHODE 1 3. GND 3. GND 3. RIGHT-SPEAKER 3. +VDISP 3. AMBI-SPI-SDO-OUT 17. GND_AL
4. GND 4. GND 4. GND 4. +VDISP 4. AMBI-SPI-SDI-OUT-GI 18. GND_AL
5. ANODE 2 5. +12V 5. +12VIN | 5. V-AMBI 19. GND_AL
6. NC 6. +12V 6. +12VIN | 6. AMBI-PWM-CLK_B2 20. N.C.
7. CATHODE 2 7. +VSND 7. +24V-AUDIO-POWER 1M19 (B09A) 51. CTRL-DISP 7. GND 21. +24V
8. NC 8. GND_SND 8. GND 1. LIGHT-SENSOR 8. AMBI-SPI-CS-OUTn_R2 22. +24V
9. ANODE 3 9. BL-ON-OFF 9. LAMP-ON 2. GND 9. AMBI-LATCH1_G2 23. +24V
10. NC 10. BL-DIM1 10. BACKLIGHT-PWM_BL-VS 3. RC 10. V-AMBI 24. +24V
11. CATHODE 3 11. BL-I-CTRL 11. BACKLIGHT-BOOST 4. LED-2 11. AMBI-BLANK_R1 25. +24V
12. NC 12. POK 12. POWER-OK 5. +3V3-STANDBY 12. AMBI-PROG_B1 26. +24V
13. ANODE 4 13. +24V 13. +24V 6. LED-1 13. AMBI-LATCH2_DIS
14. NC 14. GND1 14. GND 7. KEYBOARD 14. AMBI-TEMP
15. CATHODE 4 8. +5V
19110_009_110323.eps
110711

2011-Jul-15 back to
div. table
Block Diagrams Q552.2L LA 9. EN 67

9-3 Wiring diagram Sundance 42" - 47"


WIRING DIAGRAM 42"- 47" SUNDANCE
LED
POWER
8M84

TEMP. SENSOR
TS (1027)

1316 1319

1T02
4P
10P 10P

1M09
8M99

4P

8M71
1M83
26P

1M84
8M59

26P
8M95

1M95 1M99 1M71 1M59


14P 4P 4P 26P

1M99
14P
MAIN POWER SUPPLY SSB
42" - 47" PLDHP018A B 3139 123 6521.x
(1150)
(1005)

1G50
41P
LOUDSPEAKER

AMBILIGHT MODULE
AMBILIGHT MODULE

(5213)

1D38
3P
1308
2P

(1163)
(1163)

USB
1G51
51P

TUNER

AL
AL

USB
1M20
11P

HDMI
ETHER
NET
HDMI HDMI HDMI VGA

1M83
8G50

26P
8G51

8308
8M21

INLET TO DISPLAY LCD DISPLAY TO DISPLAY


41P (1004) 51P

LOUDSPEAKER LOUDSPEAKER
(5216) (5217)
CN1 CN2
MAINS
SWITCH

(8308)
IR/LED/CONTROL BOARD J1 WIFI MODULE
(1108) 11P (1115) 1M59 (B09A)
1M95 (B03C)
1. +3V3-STANDBY 1. AMBI-SPI-CLK-OUT 15. GND_AL
1D38 (B03A) 1M20 (B09A) 2. STANDBY 2. GND 16. GND_AL
1735 (B03A) 1. LIGHT-SENSOR 3. GND 3. AMBI-SPI-SDO-OUT 17. GND_AL
1. LEFT-SPEAKER
1. LEFT-SPEAKER 2. LED-1 4. GND 4. AMBI-SPI-SDI-OUT-GI 18. GND_AL
2. GND-AUDIO
2. GND-AUDIO 3. LED-2 5. +12VIN 5. V-AMBI 19. GND_AL
3. RIGHT-SPEAKER
3. GND-AUDIO 4. GND 6. +12VIN 6. AMBI-PWM-CLK_B2 20. N.C.
1G51 (B06B) 4. RIGHT-SPEAKER 5. KEYBOARD 7. +24V-AUDIO-POWER 7. GND 21. +12V_AL
1. +VDISP 6. +3V3-STANDBY 8. GND 8. AMBI-SPI-CS-OUTn_R2 22. +12V_AL
2. +VDISP 7. RC 9. LAMP-ON 9. AMBI-LATCH1_G2 23. +12V_AL
3. +VDISP 1M71 (B09A) 1M99 (B03C) 8. +5V 10. BACKLIGHT-PWM_BL-VS 10. V-AMBI 24. +12V_AL
4. +VDISP 1. SCL-BL 1. GND_AL 9. SCL-SET 11. BACKLIGHT-BOOST 11. AMBI-BLANK_R1 25. +12V_AL
| 2. GND 2. +12V_AL 10. GND 12. POWER-OK 12. AMBI-PROG_B1 26. +12V_AL
| 3. SDA-BL 3. GND_AL 11. SDA-SET 13. +24V 13. AMBI-LATCH2_DIS
51. N.C. 4. +3V3 4. +12V_AL 14. AMBI-TEMP 19110_063_110711.eps
14. GND
110711

2011-Jul-15 back to
div. table
Block Diagrams Q552.2L LA 9. EN 68

Block Diagram Video


VIDEO
B01F TUNER B01K TUNER BRASIL B02 PNX85500 B06B VIDEO OUT - LVDS
7S00 1G50
PNX85537EB 1
7FE0
B02A VIDEO STREAM B02F LVDS 2
TC90517FG
1T01
FA2327 58 TS-FE-VALID R23 3
TNR_SER1_MIVAL
59 TS-FE-SOP R22 LOUT1 PX1
MAIN HYBRID TNR_SER1_SOP

DEMODULATOR
61 TS-FE-CLOCK T22
TUNER TNR_SER1_MICLK
IF AGC

(ISDB-T)
9 9 60 TS-FE-DATA T21 TO DISPLAY
4MHZ_REF TNR_SER1_DATA
18
3F80 IF- 29

25M4
1FE0
LOUT2 PX2 3
3F81 IF+ 19
30
RF IN 41
B02I ANALOG VIDEO N.C.
42 RESET-SYSTEMn
B02E

10 TUN-IF-P 2F75 PNX-IF-P AE12 1G51


IF-OUT1 TUNER_P
BANDPASS N.C.
51
11 TUN-IF-N 2F79 FILTER PNX-IF-N AF12 50
IF-OUT2 TUNER_N
I2C 49

PNX-IF-AGC AD12 40
IF_AGC
LOUT3 PX3

B01H HDMI B04D HDMI B04A ANALOGUE EXTERNALS A


TO DISPLAY
*7EC1
1E01

PNX85537
SII9187BC
SII9287BC 3E90 LOUT4 PX4 40
YPBPR1-PR AV3-PR AC15
PR_R_C1
1P05
4
1 DRX2+ 26 YPBPR1-SYNCIN1 3E87 AV3-Y AE15
YPBPR Y_G1 3
3 DRX2- 25
2
1

4 3E89
2

DRX1+ 24 YPBPR1-PB AV3-PB AD15


PB_B1 1
6 DRX1- 23 +VDISP
RXD
7 DRX0+ 22
9 DRX0- 21
18

B01C USB HUB


19

10 DRXC+ 20
HDMI SIDE 12 DRXC- 19
CONNECTOR B04B ANALOGUE EXTERNALS B
+5V-USB1
B02E CONROL 1P08
HDMI

1
1

3 2
1P04
1 ARX2+ 72
SWITCH 1E08
USB_DN
R26 USB-DM 9F26 USB1-DM 2

4
2 AV2-CVBS AB14 R25 USB-DP 9F25 USB1-DP 3
3 ARX2- 71 VIDEO CVBS-_Y2 USB_DP
4
1
2

4 ARX1+ 70 SIDE USB


6 ARX1- 69 CONNECTOR
RXA
7 ARX0+ 68 B02A FLASH B01B FLASH 7FL5
9 67 CY7C65631
18

ARX0-
19

10 ARXC+ 66 7F20 9 +5V-USB2


12 H27U4G8F2DTR-BC USB 1P07
HDMI 3 ARXC- 65 10

1
CONNECTOR 17 HUB 1

3 2
OPTIONAL B01I VGA 18 13 USB2-DM 2
21 3

4
XIO_D XIO-D(00-07) 14 USB2-DP
1P03 NAND 4

1FL5

24M
1 BRX2+ 8 FLASH SIDE USB
1E05 E21 NAND-CE1n 9
3 BRX2- 7 NAND_CE1 CONNECTOR
F21 NAND-RDY1n 7 22
1

1 R-VGA AF16 VGA_R


2

4 BRX1+ 6 NAND_RDY1
2 A21 NAND-WPn 19
6 BRX1- 5 G-VGA AD16 NAND_WP_
10

RESET-USBn
15

RXB VGA_G 42
5

7 4 3 B-VGA AE16 B02G


BRX0+ VGA_B VCC
9 BRX0- 3 13 H-SYNC-VGA AB18
18

HSYNC_IN 21,37
1

6
19

11

10 BRXC+ 2 14 V-SYNC-VGA AC18 +3V3


VSYNC_IN
B02B MEMORY
HDMI 2 12 BRXC- 1 A2
CONNECTOR VGA VREF_1 DDR2-VREF-CTRL2
V1 ONLY FOR 8000 SERIE
CONNECTOR VREF_2 DDR2-VREF-CTRL3

1P02
B05A DDR
1 CRX2+ 18
B02C HDMI_DV
3 CRX2- 17
62 HDMIA-RXC+ W25 DQ DDR2-D(0-31)
1

4 CRX1+ 16 TXC_P RXC_A_P


2

63 HDMIA-RXC- W26
6 CRX1- 15 TXC_N RXC_A_N 7B00 7B02 7B03 7B01

D(16-23)

D(24-31)
D(8-15)
RXC

D(0-7)
60 HDMIA-RX0+ V25
7 CRX0+ 14 TX0_P RX2_A_P H5PS1G83E H5PS1G83E H5PS1G83E H5PS1G83E
61 HDMIA-RX0- V26
9 CRX0- 13 TX0_N RX2_A_N
18

58 HDMIA-RX1+ U25 SDRAM SDRAM SDRAM SDRAM


19

10 CRXC+ 12 TX1_P RX1_A_P


59 HDMIA-RX1- U26
HDMI 1 12 CRXC- 11 TX1_N RX1_A_N 128Mx8 128Mx8 128Mx8 128Mx8
56 HDMIA-RX2+ T25
CONNECTOR TX2_P RX0_A_P
57 HDMIA-RX2- T26
RX0_A_N

VDDL
VREF

VDDL
VREF

VDDL
VREF

VDDL
VREF
9,27,64 TX2_N
+3V3-HDMI VCC33
3S0W W24
+3V3 RREF A1 E2 A1 E2 A1 E2 A1 E2

A DDR2-A(0-14)
+1V8
*6000/7000 SERIE MUX SII9187 NON INSTAPORT DDR2-VREF-DDR
8000 SERIE MUX SII9287 INSTAPORT

19110_005_110309.eps
110321

2011-Jul-15 back to
div. table
Block Diagrams Q552.2L LA 9. EN 69

9-4 Block Diagram Audio


AUDIO
B01F TUNER B01K TUNER BRASIL B02 PNX85500 B02D PNX85500: AUDIO B03A AUDIO
7S00 7D10
PNX85537EB TPA3123D2PWP
7FE0
TC90517FG B02A VIDEO STREAM CLASS D
1T01
FA2327 58 TS-FE-VALID R23
7S05 POWER
TNR_SER1_MIVAL LM324P AMPLIFIER
59 TS-FE-SOP R22
MAIN HYBRID TNR_SER1_SOP B02D AUDIO 5D07

DEMODULATOR
AD7 ADAC(1) 12 14 +AUDIO-L 5 1,3
61 TS-FE-CLOCK T22 ADAC_1 IN-L PVCC_L +24V-AUDIO-POWER
TUNER TNR_SER1_MICLK 10,12 5D08
IF AGC

(ISDB-T)
9 9 60 TS-FE-DATA T21 PVCC_R
4MHZ_REF TNR_SER1_DATA
18 1735
3F80 IF- 22 LEFT-SPEAKER 1
29 OUT-L

25M4
1FE0
AE7 ADAC(2) 10 8 -AUDIO-R 6
ADAC_2 IN-R
3F81 IF+ 19 2
30 7D15
RF IN B02G STANDBY A-PLOP
A-PLOP B04E
B02I ANALOG VIDEO 3
42 RESET-SYSTEMn
B02E AC19 AUDIO-MUTE-UP 4 MUTE
PO_7
15 RIGHT-SPEAKER 4
OUT-R
10 TUN-IF-P 2F75 PNX-IF-P AE12 A-STBY 2
IF-OUT1 TUNER_P SD RES
BANDPASS
2F79 1D38
11 TUN-IF-N FILTER PNX-IF-N AF12 7D11 7D03
IF-OUT2 TUNER_N 1
DETECT2 MAINS SWITCH A-STBY STANDBY &
B03C DETECT PROTECTION 5D03 2
PNX-IF-AGC AD12 3
IF_AGC SPEAKERS

B01H HDMI B04D HDMI B04A ANALOGUE EXTERNALS A B02D AUDIO B04E HEADPHONE B01J TEMP SENSOR + HEADPHONE
*7EC1
SII9187BCNU 7EE0-1 7EE0-2
SII9287BCNU 1E02 AB19 RESET-AUDIO A-PLOP B03A
PO_6
B04A

PNX85537
1P05 4 AUDIO-IN1-L AE10 AIN1_L
1 DRX2+ 26 AUDIO IN 7EE1
L+R 2 TPA6111A2DGN
3 DRX2- 25 AUDIO-IN1-R AF10
AIN1_R
1

4
2

DRX1+ 24
6 DRX1- 23 HEADPHONE
RXD AMPLIFIER
7 DRX0+ 22 5
9 DRX0- 21 SHUTDOWN 1328
18
19

10 DRXC+ 20 B04B ANALOGUE EXTERNALS B B02D PNX85500: AUDIO VO_1


1 AMP1 2
12 DRXC- 19 AF7 ADAC(3) 2
HDMI SIDE ADAC3 IN-1 7 AMP2 3
CONNECTOR VO_2
1E08 1
HDMI AD6 ADAC(4) 6 8
HEADPHONE
OUT 3.5mm
6 AUDIO-IN3-L AE9 ADAC4 IN-2 VDD +3V3
1P04 SWITCH AIN3_L
AUDIO IN
1 ARX2+ 72 L+R 4 AUDIO-IN3-R AF9
AIN3_R
3 ARX2- 71 B01C USB HUB
1
2

4 ARX1+ +5V-USB1
6 B02E CONROL 1P08
ARX1- 69
1E09 1
7 ARX0+ 68 RXA

1
2 AUDIO-IN4-L AD9 R26 USB-DM 9F26 USB1-DM 2
9 67
18

ARX0- USB_DN USB 1 SIDE

3 2
AIN4_L
19

R25 USB-DP 9F25 USB1-DP 3


10 ARXC+ 66 VGA USB_DP CONNECTOR
3 AUDIO-IN4-R AC9 4

4
HDMI 3 12 ARXC- 65 AUDIO AIN4_R
CONNECTOR 70 1
OPTIONAL B01B FLASH 7FL5
CY7C65631
1P03 7F20 9 +5V-USB2
H27U4G8F2DTR-BC USB
1 BRX2+ 8 10 1P07
1E10 1
3 BRX2- 7 2
+3V3
17 HUB
SPDIF-OPT B02A FLASH

1
1 +3V3 2
1

18 13 USB2-DM
2

4 BRX1+ 6 3 7S09 USB 2 SIDE

3 2
74LVC00 XIO_D XIO-D(00-07) 14 USB2-DP 3
6 BRX1- 5
RXB DIGITAL NAND CONNECTOR
8000 SERIES 2 21 4

4
7 BRX0+ 4 AUDIO 3 & FLASH
1E07 1 SPDIF-OUT-PNX AF5 E21 NAND-CE1n 9
SPDIF_OUT

1FL5
9 BRX0- 3 OUT

24M
NAND_CE1
18
19

10 1 SPDIF-OUT 4 F21 NAND-RDY1n 7


BRXC+ 2 B02G STANDBY NAND_RDY1
12 A21 NAND-WPn 19 22
HDMI 2 BRXC- 1 8 5 SEL-HDMI-ARC AF18 NAND_WP_ 21,37
6000/7000 SERIES P0_4 VCC +3V3
CONNECTOR
9,27,64 42 RESET-USBn
+3V3-HDMI VCC33 B02G
B02C HDMI_DV ONLY FOR 8000 SERIE
1P02
62 HDMIA-RXC+ W25
1 CRX2+ 18 TXC_P RXC_A_P
3 CRX2- 17 TXC_N
63 HDMIA-RXC- W26
RXC_A_N
B02B MEMORY B05A DDR
60 HDMIA-RX0+ V25
1

4 CRX1+ 16 TX0_P RX2_A_P


2

HDMIA-RX0- V26 DQ DDR2-D(0-31)


6 61
CRX1- 15 TX0_N RX2_A_N
RXC 58 HDMIA-RX1+ U25
7B00 7B02 7B03 7B01

D(16-23)

D(24-31)
7 CRX0+ 14 TX1_P RX1_A_P

D(8-15)
D(0-7)
59 HDMIA-RX1- U26 H5PS1G83EFR H5PS1G83EFR H5PS1G83EFR H5PS1G83EFR
9 CRX0- 13 TX1_N RX1_A_N
18

56 HDMIA-RX2+ T25
19

10 CRXC+ 12 TX2_P RX0_A_P


12 11
57 HDMIA-RX2- T26 SDRAM SDRAM SDRAM SDRAM
HDMI 1 CRXC- TX2_N RX0_A_N
CONNECTOR 128Mx8 128Mx8 128Mx8 128Mx8
14 5EC2 3S0W W24
ARC-eHDMI+ eHDMI+ RREF
+3V3

VDDL
VREF

VDDL
VREF

VDDL
VREF

VDDL
VREF
A1 E2 A1 E2 A1 E2 A1 E2

A DDR2-A(0-14)
+1V8
DDR2-VREF-DDR
A2
VREF_1 DDR2-VREF-CTRL2
V1
VREF_2 DDR2-VREF-CTRL3
*6000/7000 SERIE MUX SII9187 NON INSTAPORT
8000 SERIE MUX SII9287 INSTAPORT

19110_006_110309.eps
110321

2011-Jul-15 back to
div. table
Block Diagrams Q552.2L LA 9. EN 70

9-5 Block Diagram Control & Clock Signals


CONTROL + CLOCK SIGNALS
B01D SD-CARD B02A PNX85500 B05A DDR
7S00
PNX85537EB
1P09 B02E ETHERNET B02B MEMORY
DDR2-D(0-31)
DQ
1 SDIO-DAT3 W2 7B00 7B02 7B03 7B01

D(16-23)

D(24-31)
CC_DAT3

D(8-15)
D(0-7)
2 SDIO-CMD W6 H5PS1G83EFR H5PS1G83EFR H5PS1G83EFR H5PS1G83EFR

Pin9
CMD

Pin1
5 SDIO-CLK W1

Pin2
CLK

Pin3
Pin4
7 SDIO-DAT0 W5 SDRAM SDRAM SDRAM SDRAM

Pin6 Pin5
DAT_0

Pin8 Pin7
8 SDIO-DAT1 W4 128Mx8 128Mx8 128Mx8 128Mx8
DAT_1
9 SDIO-DAT2 W3
SD-CARD DAT_2
10 SDIO-CDn U6
CONNECTOR SDCD
12 SDIO-WP V6
SDWP
F8 E8 F8 E8 F8 E8 F8 E8
DDR2-A(0-13)
B04C ETHERNET + SERVICE A
DDR-CLK_N
CLK_N N5
7E10 N4 DDR-CLK_P
CLK_P
LAN8710A-EZK
ETH-RXD RXD
1N00
ETHERNET ETH-TXD TXD B06C AMBILIGHT CPLD 7GA0 B09A NON DVBS CONNECTOR BOARD
1 ETH-TXP 29 XC9572XL
2 ETH-TXN 28 7 ETH-RXCLK AA3 B02H POWER AF1 SENSE+1V1
RXCLK VDD_1V1 B03B
3 ETH-RXP 31 20 ETH-TXCLK AA2 AA15 SENSE+1V2 1M59
TXCLK VDDA_1V2 B03D
6 ETH-RXN 30 5 22 AMBI-SPI-CLK-OUT 1
27 AMBI-SPI-SDO-OUT 3

1E70
CPLD

25M
ETHERNET PNX-SPI-CSBn 5 23 AMBI-SPI-SDI-OUT_G1 4
CONNECTOR 4 PNX-SPI-CLK 41 29 AMBI-PWM-CLK_B2 6
RJ45 B02E CONTROL 8
PNX-SPI-SDI 40 30 AMBI-SPI-CS-OUTn_R2
TO AMBILIGHT
RESET-ETHERNETn PNX-SPI-SDO 39 31 AMBI-LATCH1_G2 9 MODULE
19
B02G
20 AMBI-BLANK_R1 11
19 AMBI-PROG_B1 12
B02A VIDEO STREAM B02G 13
B1K TUNER BRASIL GPIO_1
Y22 3D-LR 7 28 AMBI-LATCH2_DIS
7FJ0 AC5 PXCLK54 43 32 AMBI-TEMP 14
CLK_54_OUT

PNX85537
CXD2820R V22 PNX-SPI-CS-BLn 3
4 TS-FE-VALID R23 GPI0_7 VCCIO
TNR_SER1_MIVAL
IF+ 30 3 TS-FE-SOP R22
TNR_SER1_SOP 26
DEMODULATOR

B01F TS-FE-CLOCK T22 VIO


IF- 5 TNR_SER1_MICLK
29
B01F TS-FE-DATA T21
(ISDB-T)

7 AD5 BACKLIGHT-PWM 9GA0 BACKLIGHT-PWM_BL-VS


TNR_SER1_DATA
BL_PWM B03C OPTIONAL
19
B02E PNX85500: MIPS B01C USB HUB
25M4
1FE0

+5V-USB1

1
18 1P08

3 2
1
R26 USB-DM 9F26 USB-DM1 2

4
RESET-SYSTEMn USB_DN
B02E R25 USB-DP 9F25 USB-DP1 3
USB_DP
4 SIDE USB
AE4 RESET-SYSTEMn ONLY FOR 6000/7000 SERIE CONNECTOR
B01B FLASH RESET_SYS
U23 SELECT-SAW
B01K B02G
GPI0_11 B01F 7FL5
7F20
H27U4G8F2DTR CY7C65631
B02A FLASH B04C ETHERNET + SERVICE 9
NAND USB +5V-USB2
10
17 HUB

1
FLASH 9 NAND-CE1n E21 1P07
NAND_CE1

3 2
18 1
7 NAND-RDY1n F21
NAND_RDY1 2
19 NAND-WPn A21 1E06 13 USB-DM2

4
NAND_WP_ 3
Y23 RXD1-MIPS 2 21 14 USB-DP2
GPI0_2 4
UART SIDE USB

1FL5

24M
Y24 TXD1-MIPS 3 SERVICE CONNECTOR
XIO-D(00-07) XIO_D GPI0_3
1 CONNECTOR 22
VCC
12,37
+3V3 ONLY FOR 8000 SERIE

B02G PNX85500: STANDBY CONTROLLER B01E PNX85500-CONTROL


B09A CONNECTORS COMP B03C DC / DC B02G STANDBY
*1M20 1M19
V23 BOOST-PWM 9CH0 BACKLIGHT-BOOST
1 1 LIGHT-SENSOR AE26 GPIO_10 B03C
P5_1
4 2 B06C
7F52
7 3 RC AD19 P1_0 M25P05-AVMN6P
3 4 LED-2 9U41 LED2 AC25
PWM_1
TO IR / LED BOARD AND 6 5 7U43 AF24 PNX-SPI-CLK 6
+3V3-STANDBY SPI_CLK FLASH
KEYBOARD CONTROL 2 6 LED-1 LED1 AD26 AE22 PNX-SPI-WPn 3
PWM_0 P6_5 8
AF23 PNX-SPI-CSBn 1 VCC +3V3-STANDBY
SPI_CSB
5 7 KEYBOARD AD23 P5_0 AE23 PNX-SPI-SDO 5 512K
SPI_SDO
8 8 AF25 PNX-SPI-SDI 2
+5V SPI_SDI
1F51
SUNDANCE / INFINITY AE21 RXD-UP 3
P3_0
TXD-UP 1 LEVEL SHIFTED
B02G PNX85500: STANDBY CONTROLLER P3_1
AF21
FF04
DETECT2 AA22 AB20 SDM 2 FOR
B03C P3_2 P1_7
AA26 RESET-STBYn SDM 4 DEBUG USE
RESET-SYSTEMn AB22 RESET_IN
B02E P3_3 5 ONLY
AF22 SPI-PROG FF29
LCD-PWR-ONn AC20 P6_4
B03H P2_0 SPI-PROG
+3V3-STANDBY
7S20 RES
AE17 NCP303LSN28G
XTAL_IN
1 B03C DC / DC
1S02

RESET-STBYn
54M

2
INP OUTP

CONTROL
ENABLE-3V3-5V
3 B03E
AF17 GND ENABLE-1V8
XTAL_OUT
B03B B03D
B04D HDMI +12V
DETECT2
TO PIN: AD18 RESET-USBn +3V3-STANDBY B02G B03A
7EC0 P1_1 B01C
1P02-13 AD21 ENABLE-3V3n
EF
1P03-13 PCEC-HDMI CEC-HDMI AF19
P1_2 P2_7
1P04-13 7EC1 AF18 SEL-HDMI-ARC 1M95
P0_4 B02D
1
2

1P05-13 SII9187BCNU AE20 LAMP-ON 9


SII9287BCNU P2_2
B02C HDMI_DV BACKLIGHT-PWM_BL-VS 10
B06C TO
ARX-HOTPLUG 31 HDMIA-RX RX AE18 RESET-ETHERNETn BACKLIGHT-BOOST 11 POWER SUPPLY
1P02-19 HDMI P0_3 B04C B01E
18
19

BRX-HOTPLUG 35 AC21 POWER-OK 12


1P03-19 P2_6
CRX-HOTPLUG 41 SWITCH AF20 STANDBY 2
4x HDMI 1P04-19 3S0W W24 P2_3
CONNECTOR DRX-HOTPLUG 45 +3V3 RREF AB19 RESET-AUDIO
1P05-19 P0_6 B04E
AC19 AUDIO-MUTE-UP
P0_7 B03A
19110_007_110318.eps
110321

2011-Jul-15 back to
div. table
Block Diagrams Q552.2L LA 9. EN 71

9-6 Block Diagram I2C


I²C
B01E PNX85500: CONTROL B02E PNX85500: MIPS B01E PNX85500-CONTROL B01J TEMP SENSOR + B04D HDMI B01K TUNER BRAZIL
HEADPHONE
7S00 +3V3
PNX85537EB

3S6D

3S6E
B02E
B25 3S5Y SDA-SSB
3_SDA
A24 3S5Z SCL-SSB
3_SCL

3EC5

3EC3
3FD3

3FD4

3FE9

3FE8
+3V3 AIN-5V
ERR
PNX85537 13
1 2 53 54 46 45

3EC1-1

3EC1-3
3S6A
3S69
CONTROL 1P04
C25 3S56 SDA-UP-MIPS 7FD1 7EC1 7FE0
29 ARX-DDC-SDA 16

1
2
1_SDA LM75BDP SII9287B TC90517FG
C26 3S57 SCL-UP-MIPS SII9187A
30 ARX-DDC-SCL 15
1_SCL TEMP DEMODULATOR
7F52

18
19
SENSOR HDMI BIN-5V

3F60

3F59
M25P05-AVMN6P B02G B02G PNX85500: STANDBY MUX HDMI
CONTROLER
5 6 CONNECTOR 3

3ECA-1

3ECA-2
ERR
FLASH 6 PNX-SPI-CLK AF24 +3V3-STANDBY 42 ERR 1P03
8 SPI_CLK 23
3 PNX-SPI-WPn AE22 STANDBY 7F58 33 BRX-DDC-SDA 16

1
+3V3-STANDBY VCC

2
P6_5
M24C64

3S6W
512K 1 PNX-SPI-CSBn

3S6V
AF23
SPI_CSB 34 BRX-DDC-SCL 15
5 PNX-SPI-SDO AE23 ERR ERR 3S2F

18
SPI_SDO

19
15 53 AC23 EEPROM CIN-5V
2 PNX-SPI-SDI AF25 SPI_SDI MC_SDA (NVM) RES
3S2G HDMI
STANDBY AC24 CONNECTOR 2
MC_SCL B01H

3ECA-3

3ECA-4
SW ERR
1F52 HDMI
RES 3F63 1P02
35 3
39 CRX-DDC-SDA 16

1
DEBUG

2
+3V3-STANDBY 3F62 1
MAIN NVM ONLY
40 CRX-DDC-SCL 15
SW
B01B

18
FLASH

19
DIN-5V

3S1G

3S1H
1F51 HDMI
AE21 RXD-UP 3F65 3 uP
CONNECTOR 1

3FBF-2

3FBF-1
7F20 P3_0 LEVEL SHIFTED +3V3 1P05
AF21 TXD-UP 3F64 1 FOR DEBUG
H27U4G8F2DTR DRX-DDC-SDA 16
P3_1 43

1
HDMI

2
USE ONLY

3ECU-2

3ECU-4
CONNECTOR
FLASH RES 44 DRX-DDC-SCL 15
B02A B02C SIDE

18
Y25 DDCA-SDA

19
(4Gx16) DDC_A_SDA
FLASH Y26 DDCA-SCL
XIO-D(00-07) XIO_D DDC_A_SCL +3V3 B01I VGA
HDMI_DV B04C ETHERNET + SERVICE +5V-EDID +5V-VGA
MAIN

3S83

3S84
1E06

3ECP-3

3ECP-1
SW

3FC1

3FC2
Y23 RXD1-MIPS 3E53-4 3E53-3 1E05
3
GPIO_2 9FC1 12

10
47 VGA-SDA-EDID-HDMI

15
3E53-2 3E53-1 UART

5
Y24 TXD1-MIPS 2
GPIO_3 SERVICE EDID
48 VGA-SCL-EDID-HDMI 9FC3 15
1 CONNECTOR SW

1
B02I B02I

6
PNX85500: ANALOG VIDEO

11
AD25 3S5V-1 9FC2
B05A DDR
VGA_EDID_SDA
VGA-SDA-EDID VGA
3S5V-3 CONNECTOR
AD24 VGA-SCL-EDID 9FC4
VGA_EDID_SCL
RES RES
7B00 7B01
H5PS1G83EFR H5PS1G83EFR ANALOGUE
VIDEO
SDRAM SDRAM +3V3
B01F TUNER
128Mx8 128Mx8
3S6G
3S6F
D(8-15)
D(0-7)

B02B
B24 3S60 SDA-TUNER 3F75 TUN-P7
MEMORY 4_SDA
A23 3S61 SCL-TUNER 3F76 TUN-P6
DDR2-A(0-13) A 4_SCL

DDR2-D(0-31) DQ ERR
18 7 6
7B02 7B03
H5PS1G83EFR H5PS1G83EFR 1T01
D(16-23)

D(24-31)

TH2627
SDRAM SDRAM
128Mx8 128Mx8 MAIN
TUNER

ERR
34

B04C ETHERNET + SERVICE


B06B VIDEO OUT - LVDS
+3V3
3S6C
3S6B

1G51
7E10
B26 3S58 SDA-SET 9S12 SDA-DISP 3G2W 50
LAN8710A-EZK
2_SDA LVDS
A25 3S5W SCL-SET 9S11 SCL-DISP 3G2Y 49 CONNECTOR
11 ETH-RXD(0) Y5 2_SCL
RXD_0 +3V3
10 ETH-RXD(1) Y6
RXD_1 ERR +3V3 ERR
9 ETH-RXD(2) AB4 14 64
RXD_2 2 1
3S67

3S65

3S68

3S66

ETHERNET 8 ETH-RXD(3) AC1


RXD_3
3S81

3S80

7 ETH-RXCLK AA3
RXCLK 7S01 4 B09A DVBS CONNECTOR BOARD TS1 TEMP SENSOR
W21 RXD2-MIPS PCA9540B
GPIO_2 5 1M71 1T02
22 ETH-TXD(0) AA1 3C83 3124
TXD_0 W22 TXD2-MIPS 2 CHAN. 3 3 SDA-TEMP1
23 ETH-TXD(1) AA4 GPIO_3
TXD_1 MULTIPLEX. 3C81 3123
24 ETH-TXD(2) AB1 7 1 1 SCL-TEMP1
ETHERNET TXD_2
25 ETH-TXD(3) AB2 ERR
CONNECTOR TXD_3 8
20 ETH-TXCLK AA2 24
RJ45 TXCLK
1 2
RES
7104
9S13 SDA-BL LM75ADP

9S10 SCL-BL TEMP


SENSOR

SW Programmable via USB

19110_004_110309.eps
OPTIONAL 110321

2011-Jul-15 back to
div. table
Block Diagrams Q552.2L LA 9. EN 72

9-7 Supply Lines Overview


SUPPLY LINES OVERVIEW
B03C DC / DC B03A AUDIO B04A ANALOGUE EXTERNALS A B09A CONNECTORS COMP
B01H HDMI
+3V3-STANDBY +3V3-STANDBY +3V3 +3V3
1M99 1M99 1P05 B03c B03e
1 1 HDMI SIDE 18 DIN-5V 1M71
GND1 B04d TEMP
2 2 +12V_AL CONNECTOR +24V-AUDIO-POWER +24V-AUDIO-POWER +3V3 +3V3 4
+12V3 B03c SENSOR
3 3 B09a
3D09 B03e (OPTIONAL)
GND1 +AVCC
4 4
+12V3
5 5 +3V3-STANDBY +3V3-STANDBY
GND1
6 6
B01I VGA
B03c
+12V3 GND_AL 1E05 B04B ANALOGUE EXTERNALS B
B03e
+5V +5V
+5V-VGA
7 7 3D-LR
B02E
VGA 9
B04d
B03B DC / DC
1M19 1M20
N.C. CONNECTOR
8 8 +3V3 +3V3 5 6
GND1 TO
9 9 +12VIN +3V3-STANDBY +3V3-STANDBY
+12V3 B03c B03e IR/LED
8 8
BOARD
+12V +12V
ONLY 8000 SERIES B01J TEMP SENSOR + HEADPHONE B03c

PSU

5U02
+3V3 +3V3 +12V_AL +12V_AL
B03e B03c
7U03
1M95 1M95
TPS53126PW 7U02-1 12V/1V8
B04C ETHERNET + SERVICE
1 1 +3V3-STANDBY B01e,B02e, 1C87
3V3SB COVERSION +3V3 +3V3
2 2 STANDBY g,h,B03a,b,h, 12 B03e
STANDBY B02G B04d,e,B09a Dual 5U00 +1V8 5E08 +3V3-ET-ANA T 2.0A
3 3 ONLY 8000 SERIES
GND1 Synchronous 7U02-2 B02b,h,B03d,
GND1
4 4 B01K TUNER BRAZIL Step-Down B05a
B03c
+24V +24V
5 5 +12VIN Controller 14
+12V3 B03h 1M59
6 6
+12VD B01g
+1V2-BRA-VDDC +1V2-BRA-VDDC B04D HDMI 1C86 21
+12V3
+1V2-BRA-DR1 +1V2-BRA-DR1 12V/1V1 +3V3 +3V3 TO
7U01 T 2.0A 10
1U40 B01g COVERSION B03e AMBILIGHT
+12V 5EC0 +3V3-HDMI
B03b,d,e,g, 1 V-AMBI 5 MODULE
+3V3 +3V3 5U01 +1V1 B03f
7 7 T 3.0A +24V-AUDIO-POWER B09a B03e
+VSND B02h,g,B03e +3V3-STANDBY +3V3-STANDBY
B02d,B03a 5FE7 7U04
8 8 +3V3-BRA B03c
GND1
9 9 LAMP-ON 5FE4 23 +5V-VGA +5V-VGA
BL-ON-OFF B02G +3V3-BRA-FLT
10 10 BACKLIGHT-PWM_BL-VS B01I
BL-DIM1 B06C
11 11 BACKLIGHT-BOOST +5V +5V
BL-I-CTRL B01E +5V-EDID
12 12 POWER-OK B03e
POK B02G 7FE3

6EC1
13 13 +24V 5FE9 +2V5-BRA +5V +5V
IN OUT
+24V B09a COM B03e
14 14
GND1 B03D DC / DC 1P04
HDMI 3 AIN-5V
18
CONNECTOR
+1V8 +1V8
B03b 1P03
B02A PNX85500: NANDFLASH
7UA3 +1V2 B02g,h,
HDMI 2
18 BIN-5V
+3V3
CONDITIONAL ACCESS CONNECTOR
+3V3 B03e
+3V3 +3V3
B03e B03e
+5V 1P02
+5V HDMI 1 CIN-5V
18
B03e CONNECTOR
+12V
+5V +5V DIN-5V DIN-5V
B03e
B01A COMMON INTERFACE B02B PNX85500: SDRAM
3U16 +3V3
B01h

+1V8 +1V8 7UC0


B03b 3U15
+3V3 +3V3 +2V5
3S20 IN OUT
B03e
DDR2-VREF-CTRL3
COM B02d,h B04E HEADPHONE
CUA0 +2V5-LVDS
3S06 DDR2-VREF-CTRL2 B02h +3V3 +3V3
B03e
+5V5-TUN +5V5-TUN +3V3-STANDBY +3V3-STANDBY
B03e B03c
7UA6 +5V-TUN
B01B FLASH B02C PNX85500: DIGITAL VIDEO IN B01f

+3V3 +3V3 B03e


+3V3 +3V3 B05A DDR
+12V ENABLE-1V8 +12V
B03e B03c +1V8 +1V8
7UA0 B03b
3UA0 VOLT. +2V5-REF 3B20 DDR2-VREF-DDR
B01C USB HUB REG.
B02D PNX85500: AUDIO
+3V3 +3V3 +2V5 +2V5
B03e B03d
+5V +3V3 +3V3
B06A DISPLAY INTERFACING-VDISP
+5V
B03e
B03e B03E DC / DC
+VDISP-INT +VDISP-INT
3F32 +5V-USB1 3S11 +3V3-ARC
+1V1 +1V1 B03h
+T 7S08 B03b
3FL2 +5V-USB2 +2V5-AUDIO B02h +12V +12V
IN OUT B03c B01,a,b,c,d,e, 1G03
g,j,k, +VDISP
+T COM B06b
B02a,c,d,e,h,
+24V-AUDIO-POWER +24V-AUDIO-POWER 7UD1 T 3.0A
B03c B03c,f,g,h,
5UD3 5UD2 +3V3
3S0Z +24V-AUDIO-VDD IN OUT B04a,c,d,e,
B01D SD-CARD COM B06b,c,d,
7UD0 B09a
+3V3 +3V3 5UD0 5UD1 +5V5-TUN
IN OUT B03d
B03e
3F40 +3V3-SD
B02E PNX85500: MIPS COM
6UD0 B01,c,e,k,
+T +3V3
+5V
B03c,d,e, B06B VIDEO OUT - LVDS
+3V3
B03e B04d,B09a
+3V3 +3V3
+3V3-STANDBY +3V3-STANDBY B03e
B03c B03F TEMPSENSOR + AMBILIGHT
+VDISP +VDISP
B01E PNX85500: CONTROL
+3V3 +3V3
B06a

+3V3
B03e
+3V3 B02G PNX85500: STANDBY CONTROLLER B03b
1UM0
+3V3-STANDBY +3V3-STANDBY
5UM1 V-AMBI
B09a B06C AMBILIGHT CPLD
B03c +1V1 +1V1
B03b T 1.0A
+5V +5V +3V3 +3V3
B03e
B03e
5GA0 VINT
+3V3-STANDBY +3V3-STANDBY
B03c B03G FAN - CONTROL 5GA1 VIO
+3V3 +3V3
B01F TUNER
B03e
+12V +12V
B03c
+5V-TUN +5V-TUN B06D SPI-BUFFER
B03d
9F71 +5V-TUN-PIN
B02H PNX85500: POWER
+3V3 +3V3
B03H VDISP - SWITCH B03e
+1V1 +1V1
B03b
+1V2 +1V2 +3V3 +3V3
B03d B03e
+1V8 +1V8 +3V3-STANDBY +3V3-STANDBY
B03b B03c
+12VD +12VD
B01G TOSHIBA SUPPLY B03d
+2V5 +2V5 B03c
+2V5-AUDIO +2V5-AUDIO 7UU0 +VDISP-INT
+3V3 +3V3 B02d B06a
7FA3 +2V5-LVDS +2V5-LVDS
B03e B03d
5FA3 +1V2-BRA-VDDC
IN OUT B01k +3V3 +3V3 7UU2
COM
5FA4 B03e LCD-PWR-ONn
+1V2-BRA-DR1
B01k +3V3-STANDBY +3V3-STANDBY
B03c

19110_003_110309.eps
110321

2011-Jul-15 back to
div. table
Circuit Diagrams and PWB Layouts Q552.2L LA 10. EN 73

10. Circuit Diagrams and PWB Layouts


10-1 B01 313912365213
Common Interface

Common Interface
B01A B01A

FF05 3F07-3
CA-CD1n 3 6
+3V3
FF06 10K
3F07-4
CA-CD2n 4 5
10K
3F07-1
1 8
10K
3F07-2
2 7
10K
3F08-1
1 8
10K
3F08-4
CA-MOCLK 4 5
+3V3
FF07 10K
3F08-3
CA-MOVAL 3 6
10K
3F08-2
CA-MOSTRT 2 7
10K
RES 1 3F09-1 8
CA-MDO0
10K
RES 2 3F09-2 7
CA-MDO1
10K
RES 3 3F09-3 6
CA-MDO2
10K
RES 4 3F09-4 5 IF04
CA-MDO3
10K
RES 4 3F10-4 5
CA-MDO4
10K
RES 3 3F10-3 6
CA-MDO5
10K
RES 2 3F10-2 7
CA-MDO6
10K
RES 1 3F10-1 8
CA-MDO7
10K

FF08 3F12
CA-RDY +3V3
10K
2 3F11-2 7
10K
3 3F11-3 6 IF08
10K
4 3F11-4 5
FF09 10K
CA-VS1n 8 3F11-1 1
+3V3
10K

1X07 1X04 1X08 1X01


REF EMC HOLE EMC HOLE REF EMC HOLE REF EMC HOLE

3 2011-03-09

SPB SSB TV550 2 2010-12-23

3139 123 6521


2K11 4DDR BR SD

19110_010_110411.eps
110415

2011-Jul-15 back to
div. table
Circuit Diagrams and PWB Layouts Q552.2L LA 10. EN 74

Flash

Flash
B01B B01B

+3V3

2F20

2F21
100n

100n
7F20

12

37
NAND04GW3B2DN6F
Φ VCC
1
2
[FLASH] 3
4G × 16 4
5
XIO-D00 3F20-1 1 8 100R 29 6
0
XIO-D01 3F20-2 2 7 100R 30 10
1
XIO-D02 3F20-3 3 6 100R 31 11
2
XIO-D03 3F20-4 4 5 100R 32 14
3
XIO-D04 3F21-1 1 8 100R 41 IO 15
4
XIO-D05 3F21-2 2 7 100R 42 20
5
XIO-D06 3F21-3 3 6 100R 43 21
6
XIO-D07 3F21-4 4 5 100R 44 22
7
NC 23
24
IF21 25
NAND-CE1n
26
NAND-CLE 3F22-2 2 7 100R 16 27
CLE
NAND-ALE 3F22-3 3 6 100R 17 28
ALE
+3V3 3F23 10K 9 33
CE
XIO-OEn 3F22-1 1 8 100R 8 34
RE
XIO-WEn 3F22-4 4 5 100R 18 35
IF22 WE
NAND-WPn 19 38
WP
+3V3 3F24 7 39
R
40
2K2 B
NAND-RDY1n 45
IF23 46
47
48
10K
3F19 VSS

13

36
+3V3

3 2011-03-09

SPB SSB TV550 2 2010-12-23

3139 123 6521


2K11 4DDR BR SD

19110_011_110411.eps
110415

2011-Jul-15 back to
div. table
Circuit Diagrams and PWB Layouts Q552.2L LA 10. EN 75

USB Hub

USB Hub
B01C B01C
+3V3

USB-OVR1
3FL2
+5V
+T 0R3

100n
100n

100n

100n
1u0

10n

10n

10n

2FLA 1n0

2FLB 1n0

2FLC 1n0
4 3FL4-4 5 FL33
+5V-USB2

2FL2

2FLD
2FL5

2FL3
USB1

2FL1
100K

2FL4
2FL9
2FL8
1FL5 3FL4-3
1 3 3 6 1P08
+5V-USB1 FL43 1
24M 100K
USB1-DM FL36 2
4
2

1 3FL4-1 8
2FL6

2FL7

7FL5 FL37 3
12p

12p

USB1-DP

+3V3
11
15
19
23
27
33
39
55
CY7C65621-56LTXCT 4

3
7
100K
FL32 5 6 IFLF
IFL4 VCC 3FL4-2
21 35 2 7
XIN GREEN1
36
IFLG AMBER1 100K
22
XOUT USB-16-PBT-B-30-CU1-BRF
37
GREEN2

3FL7

9FL3
3FLD 10K 45 38

10K
+3V3 SELFPWR AMBER2 3F32
3FLE-1 +5V USB2
1 8 26 29 +T 0R3
+5V VBUSPOWER PWR1 IFLB 3F34-4
100K IFLA 30 9FLE 4 +5V-USB1 1P07
OVR1
46 +5V-USB2 1
3FLE-2 RESET 100K
2 7 31 USB2-DM FL40 2
IFL1 PWR2 3F34-3
9F26 17 32 3 6 USB2-DP FL41 3
100K D- OVR2
9F25 IFL2 18 4
D+ 100K
4 3FLE-4 5

FL42
25 IFLC 3FLA 10K 5 6
9FLC SPI_CS +3V3 3F34-2
100K 13 48 IFLD 3FLB 15K +3V3 2 7
9FLD DD1- SPI_SCK
14 49 IFLE 3FLC 10K
3FLE-3 DD1+ SPI_SD 100K
3 6
9 58 1 3F34-1 8 USB-16-PBT-B-30-CU1-BRF
100K DD2-
10 59 100K
3FLF DD2+
+3V3 60
10K 61 +3V3 RES 1 9FL1-1 8
9FLG

9FLH
9FLF

9FLJ

RESET-USBn 62 RES 2 9FL1-2 7


USB1-DM 63 RES 3 9FL1-3 6
USB1-DP 64 RES 4 9FL1-4 5
USB-DM 65
USB-DP 66 +5V 1 9FL2-1 8
USB2-DM 67 2 9FL2-2 7
USB2-DP 68 3 9FL2-3 6
USB-WIFI-DDn 69 4 9FL2-4 5
IFL3 53 70 (WIFI)
USB-WIFI-DDp VIA RES 3FLJ
51 RES 71 RES
72 +T 0R3 1F24
USB2-DM 9FLK 5 73 FL38 1
USB2-DP 9FLL 6 74 USB-WIFI-DDn FL39 2
42 75 USB-WIFI-DDp FL30 3
3FLG
+3V3 41 76 4

FL31
54 77 5
10K
USB-OVR1 1 NC 78 6 7
2 79
3FLH
+3V3 44 80 502386-0570
43 81
10K
52 82
GND
GND
HS
4
8
12
16
20
24
28
34
40
47
50
56

57

SCENARIO 1P07 1P08 1F24 3FLG 3FL2 3FL4 3FL7 3F32 3F34 7FL5 9FLE 9FLC/D 9F25/6 9FL2 9FL3 9FLF/G 9FLH/J 9FLK/L
1x USB N Y N N N N N Y N - N N Y N N N N N
1x USB + WIFI N Y Y Y N N Y Y Y CY7C65621 N N N Y N N Y N
2x USB Y Y N Y Y Y N Y Y CY7C65621 Y Y N N N Y N N
2x USB + WIFI Y Y Y N Y Y Y Y Y CY7C65631 N N N Y Y N Y Y

3 2011-03-09

SPB SSB TV550 2 2010-12-23

3139 123 6521


2K11 4DDR BR SD

19110_012_110411.eps
110415

2011-Jul-15 back to
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Circuit Diagrams and PWB Layouts Q552.2L LA 10. EN 76

SD Card

SD-Card
B01D B01D

3F40 FF45
+3V3 +3V3-SD
+T 0R3

22u 16V
2F40
+3V3

3F41-4 IF47 3F44-2


4 5 SDIO-DAT3 SDIO-DAT3 2 7 FF47
1P09-1
47K 3F41-3 100R 3F43-3
3 6 SDIO-CMD SDIO-CMD 3 6 FF48
1
47K 100R 2
+3V3-SD 3
3F45 RES 3F44-1 4
SDIO-CLK SDIO-CLK 1 8
5
FF49
10K 100R 6
7
2 3F41-2 7 SDIO-DAT0 SDIO-DAT0 2 3F43-2 7 FF41
8
47K 100R 9
1 3F41-1 8 SDIO-DAT1 SDIO-DAT1 1 3F43-1 8 FF42 13 14 FF46
15 16
47K 100R
1 3F42-1 8 SDIO-DAT2 SDIO-DAT2 3 3F44-3 6 FF43
47K SCDA7A0200
100R

1P09-2
3F42-2 FF44
2 7 SDIO-CDn SDIO-CDn 10
47K 11
12
3 3F42-3 6 SDIO-WP SDIO-WP FF50
SCDA7A0200
47K

3 2011-03-09

SPB SSB TV550 2 2010-12-23

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2K11 4DDR BR SD

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Circuit Diagrams and PWB Layouts Q552.2L LA 10. EN 77

PNX85500 Control

PNX85500 Control
B01E B01E

+3V3-STANDBY +3V3-STANDBY

+3V3-STANDBY
+3V3 +3V3 +3V3

RES
2F49

100p

100n
2F52

RES
10K
3F66

3F52

10K
8
7F52

3F67
M25P05-AVMN6

10K
BACKLIGHT-BOOST
VCC IF50
PNX-SPI-SDI IF51 2
Q Φ D
5 PNX-SPI-SDO 7F53 RES
PDTA114EU +5V
512K IF52
6 PNX-SPI-CLK
FLASH C
IF53

3F68 RES
1 PNX-SPI-CSBn
S
IF54
3 IF55

47K
W PNX-SPI-WPn BOOST-PWM
7F54-1 RES
7 BC847BPN(COL) 6
HOLD +3V3-STANDBY
FF29 IF61 7F54-2 RES IF56
VSS SPI-PROG BC847BPN(COL)
4 2
IF57
1
4

IF62 5
FF04
SDM
3

3F53 FF58
9CH0
10K

RES

RES
2F53

3F69

3F54

RES
1K0
1u0

10K
+3V3
MAIN NVM

DEBUG ONLY
RES
IF58 1F52
2F58 RES FF61 3F62 100R
SCL-SSB 1 SCL
FF62
100n 2
7F58 SDA-SSB 3 SDA
3F63
8

FF63 100R 4 5
Φ
10K

3F58 (8K × 8) 7
WC
EEPROM 3F59 FF55
IF59 1 6 SCL-UP-MIPS
0 SCL
2
1 ADR 100R 3F60 FF56
3 5 SDA-UP-MIPS
2 SDA
100R
4

FF57

DEBUG / RS232 INTERFACE LEVEL

RES SHIFTED
1F51
FF65 3F64
TXD-UP 1
100R
FF64
2
FOR
RXD-UP
FF66 3F65 UP
3
RESET-STBYn 100R
SPI-PROG
4 DEBUG
5
7 6
USE ONLY

3 2011-03-09

SPB SSB TV550 2 2010-12-23

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Circuit Diagrams and PWB Layouts Q552.2L LA 10. EN 78

Tuner

Tuner
B01F B01F
IF10
1T01
FF71
* IF11

15
TUNER 14

4MHZ_REF
PNX-IF-P

I2C_ADR

I2C_SDA

IF_OUT1

IF_OUT2
RF_AGC

I2C_SCL

B+_TUN
2F71
B+_LNA

9F00

9F01

9F02

9F03
16 13
RF_IO

+5V-TUN-PIN

TUN

NC
10n

2F72

2F73
7F75 * *

2F65 RES
1
UPC3221GV-E1
* *

10

11

12
1

VCC

15p
IF75 2F74 IF73 2F75 IF76 AF72

2F70 RES
IF74 3F79-1
1F75 2 INPUT1 OUTPUT1 7 1
1 5
I O1 10n 10n 220R IF16

RES
5F71

2F76

2F77

5F74

2F62
2 4

2p2

1p0
IF77
6p8

6p8

6p8

6p8

6p8

6p8

6p8
ISWI O2 2F78 IF78

3F82 RES
3 INPUT2 OUTPUT2 6 IF80
2F79 3F79-4
3 4 * * * *
GND IF81 10n

820R
RES 5F76

330n
GND1

GND2
10n 220R AF73
RES 2F9C

RES 2F9D
RES 2F9A

RES 2F9B
RES 2F97

RES 2F98

RES 2F99

X7251M 4 VAGC AGC CONTROL


36M17

2F80

2F82
8

5
* *
PNX-IF-N
PNX-IF-AGC IF82 3F77
AF71 TUN-IF-N
FF74 FF76
TUN-P1 AF70 TUN-IF-P 4K7 IF79
IF12 IF13
100n

FF00 FF01 2F63


4n7

4n7

3F80
* 9F04 IF-AGC IF-AGC IF72 +5V-TUN-PIN
220R 10n
IF-

100p

100p

9F05

9F06

5F66

2F66
680n
FF75

15p
BA591
RES 2F81

2F59

2F60

2F61

2F85

3F71

6F72

3F72

2F92
4K7

1K0
47n

10n
3F81 IF14 2F64 IF15
* * IF+

RES 2F95

RES 2F96
2F93

100n

* IF86 2F90
220R 10n

10n * For BR NIM Tuner only

3F78
FF81

3K3
TUN-P6
3 5F73 2

5F70

470n
+5V-TUN-PIN

TUN-P7 FF82 TUN-IF-N

TUN-IF-P 4 1
2F91 RES
ATB2012
10n
IF89
2F84 3F76 IF87 IF90
SCL-TUNER SELECT-SAW 7F70
PDTC114EU
15p 47R

RES
TUN-P6

10n
2F86 3F75 IF88 SDA-TUNER

2F94
15p 47R
TUN-P7
* For EU Hybrid Tuner Only
9F71
5F72 RES
+5V-TUN +5V-TUN-PIN

* Remarks Component
30R
2F88

Item No.
22u

Europe Brazil
1T01 TH26X3 FA23X7
2F61 4u7 RES
2F62 10p 5p6
9F02 RES Used
9F03 RES Used
9F04 RES Used
9F05 RES Used
9F06 RES Used
2F73 1p0 RES
2F82 1p0 RES
2F72 15p 12p
2F80 15p 12p
2F77 22p 18p
5F71 680n 560n
5F74 820n 680n

3 2011-03-09

SPB SSB TV550 2 2010-12-23

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Circuit Diagrams and PWB Layouts Q552.2L LA 10. EN 79

Toshiba Supply

Toshiba supply
B01G B01G

+3V3 +1V2-BRA-DR1

+1V2-BRA-VDDC

5FA3

5FA4
30R

30R
7FA3
LD1117DT12
FFAF
3 2
IN OUT
COM
2FA2

2FA3

2FA4
100n

100n

10u
1
FFA2

3 2011-03-09

SPB SSB TV550 2 2010-12-23

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Circuit Diagrams and PWB Layouts Q552.2L LA 10. EN 80

HDMI

HDMI
B01H B01H

HDMI CONNECTOR SIDE


1P05
1 DRX2+ DIN-5V
2
3 DRX2-
4 DRX1+
5
6 DRX1-
7 DRX0+
8
9 DRX0-

1 3FBF-1 8
10 DRXC+

47K
11
12 DRXC-
13 PCEC-HDMI
14
FFB1 DRX-DDC-SCL DRX-DDC-SCL
15
FFB2 DRX-DDC-SDA DRX-DDC-SDA 2 3FBF-2 7 DIN-5V
16
17 FFB3 47K
18 DIN-5V
19 FFB4 DRX-HOTPLUG
FFB5 21 20
23 22
FFB6

3 2011-03-09

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Circuit Diagrams and PWB Layouts Q552.2L LA 10. EN 81

VGA

VGA
B01I B01I
FFC1 3FC5
R-VGA

CDS4C12GTA
18R

RES 2FC1

1FC1

RES 6FC1
100p

12V
FFC2 3FC6
G-VGA

CDS4C12GTA
18R

RES 6FC2
RES 2FC2

1FC2
100p

12V
1E05
1
2
3 3FC7
B-VGA
4

CDS4C12GTA
FFC3 18R
5

RES 6FC3
RES 2FC3

1FC3
100p
6

12V
VGA 7
8
CONNECTOR 9 FFC4
10
11
FFC5
12 9FC5 H-SYNC-VGA
13
14

RES 6FC4

CDS4C12GTA
2FC4

1FC4

3FC3
15

12V

4K7
47p
17 16
FFC6
1216-02D-15L-2EC

FFC7
9FC6 V-SYNC-VGA

CDS4C12GTA
RES 6FC5
2FC5

1FC5

3FC4
12V
47p

4K7
9FC1 VGA-SDA-EDID-HDMI
RES
3FC1 FFC8
9FC2 VGA-SDA-EDID
RES

CDS4C12GTA
10K

RES 6FC6
2FC6

12V
47p
9FC3 VGA-SCL-EDID-HDMI
RES
3FC2 FFC9
9FC4 VGA-SCL-EDID

CDS4C12GTA
10K RES
2FC7

RES 6FC7

12V
47p

+5V-VGA

CDS4C12GTA
2FC8

1FC6

RES 6FC8

12V
47p

3 2011-03-09

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2011-Jul-15 back to
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Circuit Diagrams and PWB Layouts Q552.2L LA 10. EN 82

Temp sensor & headphone

Temp sensor & headphone


B01J B01J

+3V3

9FD1 RES

9FD2 RES
3FD1
RES

1K0

2FD1

3FD2
100n

1K0
LTST-C190KGKT
RES

8
7FD1
LM75BDP

6FD1

+VS
3 7 IFD1
OS A0
3FD3 IFD2
SDA-SSB 1 6 IFD3
SDA A1
3FD4 100R IFD4
SCL-SSB 2 5 IFD5
SCL A2

GND
100R

RES
3FD6

3FD7

9FD5
1K0

1K0
4
RES
1329
1
2
3
5 4

502382-0370

1328
2MSJ-035-69A-B-RF-PBT-BRF
FFDA
AMP1
3
AMP2

CDS4C12GTA

CDS4C12GTA
FFDB
7

1
3FDG-2

3FDG-1

2FDC

2FDD
1FD2

6FD2

1FD3

6FD3
1K0

1K0

12V

12V

22n

22n
FFDC

RES

RES
2

3 2011-03-09

SPB SSB TV550 2 2010-12-23

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Circuit Diagrams and PWB Layouts Q552.2L LA 10. EN 83

Tuner Brazil

Tuner Brazil
B01K B01K

5FE0 IF63 IF64


+2V5-BRA +1V2-BRA-VDDC
30R

2FE0

2FE3

2FE4

2FE5

2FF0

2FF1
100n

100n

100n

100n
1u0

1u0

+3V3-BRA-FLT
AGND
5FE3 IF65 IF66 5FE4
+3V3-BRA-FLT
+3V3-BRA
30R 30R

2FE6

2FF2

2FF3

2FF4

2FF5

2FF6
100n

100n

100n

100n
1u0

1u0
AGND
5FE5 IF67 IF68
+1V2-BRA-DR1
30R 5FE7 IF48
+3V3 +3V3-BRA
2FE8

2FF7

2FF8

2FF9
100n

100n
1u0

1u0
30R

IF69 5FE8
+2V5-BRA
30R 7FE3
1FE0 LD3985M25

2FG0

2FG1
100n
1 3

1u0
5FE9 FF03
1 5
25M4 +5V IN OUT +2V5-BRA
4 2 30R
2FG2

2FG3

3 4
18p

18p

INH BP
COM
7FE0
32

22

20

16
36
56
63

13
35
49
64

34
48

43

2FH2

2FH3

2FH4
TC90517FG

1u0

10n

1u0
2
AGND AGND AGND
AD_DVDD

AD_AVDD

PLLVDD

DR2VDD
VDDC Φ VDDS

DR1VDD
2FH5 * To be drawn near PNX85500
19 21
I FIL
AGND
X 1n5
18 58 3FG6-4 4 5 33R TS-BR-VALID 1 9F27-1 8 * TS-FE-VALID
O PBVAL
DFE6
3 53
0 RERR
2 XSEL
1 DFE7
54
RLOCK
IF+ 2FG4 10n IF17 30
P DFE8
IF- 2FG6 10n IF18 29 ADI_AI 55
N RSEORF
2FG7 100n 28 59 3FG6-3 3 6 33R TS-BR-SOP 2 9F27-2 7 * TS-FE-SOP
BFE2 P SBYTE
2FG8 100n 27 ADQ_AI
N DFE9
52
AGND BFE3 SLOCK 5FG0
2FG9 100n 24
P
2FH6 100n 25 AD_VREF 61 3FG7 33R TS-BR-CLOCK 9F28 * TS-FE-CLOCK
N SRCK 30R
AGND
2FH7 100n 26 60 3FG6-2 2 7 33R TS-BR-DATA 4 9F27-4 5 * TS-FE-DATA 5FG2
AD_VREF SRDT
DFF1
39 38
AGND DTCLK STSFLG1 30R
IF27 3FE5 IF28 AGND
40 9 IF-AGC
+3V3-BRA-FLT DTMB AGCCNTI
18K

2FH8
8 10

10n
S_INFO AGCCNTR
DFF2
3FE6 10K 1 51
0 STSFLG0
41 TSMD
1
42
SYRSTN
3FE7 10K IF29 7
AGCI
6 3FG2-1 RESET-SYSTEMn
0 3FG2-2
11 SLADRS 5 10K
CKI 1
10K
3FG4-2
AD_DVSS
AD_AVSS

SCL-SSB 3FE8 100R IF49 45 12


SCL SCL
PLLVSS

SDA-SSB 3FE9 100R 46 TN 14 4K7 3FG4-1


SDA SDA +3V3-BRA-FLT
4K7
VSS
23

31

17

4
15
33
37
44
47
50
57
62

AGND AGND

3 2011-03-09

SPB SSB TV550 2 2010-12-23

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10-2 B02 313912365213


NANDflash - conditional access

PNX85500: NANDflash - conditional access


B02A +3V3
B02A

3S1W

10K
7S00-5
PNX85500

FLASH D25 XIO-D00


00
D26 XIO-D01
01
C24 XIO-D02
02
D23 XIO-D03
03
NAND-ALE D22 C23 XIO-D04
ALE 04
NAND-CLE C21 NAND B23 XIO-D05
CLE 05
A22 XIO-D06
06
J25 E22 XIO-D07
00 07
J26 XIO_D F24
01 08
H21 F25
02 09
H22 F26 XIO-D10
03 10
H23 E23
04 11
H24 E24
05 12 IS26 3S15
H25 E25 INPACK INPACK
06 13
H26 E26
07 14 10K
G21 XIO_A D24
08 15
G22
09
G23 B22 XIO-OEn
10 OE_
G24 XIO C22 XIO-WEn
11 WE_
G25
12
G26 B21 +3V3
13 CLK_BURST
F22
IS25 14
F23 E21 NAND-CE1n
15 CE1_
D21
CE2_
A20
NAND RDY2

3S1V

RES
F21

10K
RDY1 NAND-RDY1n
A21 9S08 NAND-WPn
WP_
IS00

+3V3

3S1X

10K
7S00-11
PNX85500

P21 VIDEO_STREAM N26 CA-MDO0


0 0
P22 M21 CA-MDO1
1 1
P23 M22 CA-MDO2
2 2
P24 M23 CA-MDO3
3 3
P25 MDI MDO M24 CA-MDO4
4 4
P26 M25 CA-MDO5
5 5
N21 M26 CA-MDO6
6 6
N22 L21 CA-MDO7
7 7
J22
ADD_EN
K25 K23 CA-VS1n
DATA_DIR 1
VS K24 9S00 CA-MOCLK
2
K26
DATA_EN
K21 CA-CD1n
1
N23 CD K22 CA-CD2n
I 2
MCLK
CA-MOCLK L25
O CA
+3V3
N24
MISTRT
N25 TS-FE-DATA 3S1R
MIVAL
560R
CA-MOSTRT L22 TS-FE-CLOCK 3S1S
MOSTRT
560R
CA-MOVAL L23 TS-FE-VALID 3S1T
MOVAL
560R
J21 TS-FE-SOP 3S1U RES
OOB_EN
560R
RES
CA-RDY L24
RDY
L26 T21 TS-FE-DATA TS-FE-DATA 3S23
RST DATA
T23 TS-FE-ERR 470R
ERR
J23 T22 TS-FE-CLOCK TS-FE-CLOCK 3S24
VCCEN TNR_SER1 MICLK
R23 TS-FE-VALID 470R
MIVAL
J24 R22 TS-FE-SOP TS-FE-VALID 3S28
VPPEN SOP
470R
TS-FE-SOP 3S29 RES

RES 470R

3 2011-03-09

SPB SSB TV550 2 2010-12-23

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Circuit Diagrams and PWB Layouts Q552.2L LA 10. EN 85

SDRAM

PNX85500: SDRAM
B02B B02B

7S00-8
PNX85500
DDR2-BA0 H1 MEMORY J1 DDR2-A0
0 0
DDR2-BA1 H2 J3 DDR2-A1
1 BA 1
DDR2-BA2 G1 K1 DDR2-A2
2 2
G4 DDR2-A3
3
DDR2-DQM0 D1
0 M0 4
L3 DDR2-A4
DDR2-DQM1 D5 G3 DDR2-A5
1 5
DDR2-DQM2 R3 DM L2 DDR2-A6
2 6
DDR2-DQM3 T5 H5 DDR2-A7
3 7
L1 DDR2-A8
A 8
DDR2-D0 F3 J5 DDR2-A9
0 9
DDR2-D1 C2 J2 DDR2-A10
1 10
DDR2-D3 F2 M3 DDR2-A11
+1V8 2 11
DDR2-D2 C3 J4 DDR2-A12
3 12
DDR2-D6 B4 M2 DDR2-A13
4 13
DDR2-D5 F1 K5 DDR2-A14
5 14
DDR2-D4 C1
6
DDR2-D7 E1 N5 3S30 DDR2-CLK_N
7 N

100u 2.0V
F4 CLK N4 3S33 DDR2-CLK_P
180R 1%

180R 1%
DDR2-D8 8 P 10R
3S20

3S06

2S12
DDR2-D9 B2 10R
9
DDR2-D10 E5 E2 DDR2-DQS0_N
10 N
DDR2-D11 C5 DQS0 E3 DDR2-DQS0_P
FS02 11 P
DDR2-D12 A4
DDR2-VREF-CTRL3 FS01 12
DDR2-D13 G5 D3 DDR2-DQS1_N
DDR2-VREF-CTRL2 13 N
B3 DQS1 D4 DDR2-DQS1_P
180R 1%

DDR2-D14 14 P
3S22

DDR2-D15 F5
15
U3 DQ R1
180R 1%

DDR2-D16 DDR2-DQS2_N
16 N
3S07

DDR2-D17 P2 DQS2 R2 DDR2-DQS2_P


17 P
DDR2-D19 U2
18
DDR2-D18 P3 T3 DDR2-DQS3_N
19 N
DDR2-D22 N1 DQS3 T4 DDR2-DQS3_P
20 P
DDR2-D23 U1
21
DDR2-D20 P1 K3 DDR2-CAS
22 CASB 3S6Q
DDR2-D21 T1 K4 DDR2-CKE DDR2-CKE
23 CKE
DDR2-D24 V4 L5 DDR2-CS
24 CSB 10K
DDR2-D30 R5 M4 DDR2-ODT
25 ODT
DDR2-D26 U5 M1
26 PCAL 3S6P
DDR2-D25 P5 M5 DDR2-RAS DDR2-ODT
27 RASB
DDR2-D28 N3 H3 DDR2-WE
28 WEB 10K
DDR2-D31 V3 RES
29
DDR2-D27 R4 A2 DDR2-VREF-CTRL2
30 1
DDR2-D29 V5 VREF V1 DDR2-VREF-CTRL3
31 2

IS42

2S20

2S17

1%
2S24

2S25
100p

100n

100n

100p

3S0V

261R
3 2011-03-09

SPB SSB TV550 2 2010-12-23

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2K11 4DDR BR SD

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Circuit Diagrams and PWB Layouts Q552.2L LA 10. EN 86

Digital video in

PNX85500: Digital video in


B02C B02C

7S00-6
PNX85500

HDMIA-RX2+ T25 HDMI_DV


P
HDMIA-RX2- T26 RX0_A
N

HDMIA-RX1+ U25
P
HDMIA-RX1- U26 RX1_A Y26 DDCA-SCL
N SCL
DDC_A Y25 DDCA-SDA
SDA
HDMIA-RX0+ V25 IS10
P
HDMIA-RX0- V26 RX2_A T24
N HOT_PLUG_A

HDMIA-RXC+ W25
P
HDMIA-RXC- W26 RXC_A
N
+3V3 IS01
3S0W
W24
RREF
12K

2S2E
RES

10u

3 2011-03-09

SPB SSB TV550 2 2010-12-23

3139 123 6521


2K11 4DDR BR SD

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110415

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Circuit Diagrams and PWB Layouts Q552.2L LA 10. EN 87

Audio

PNX85500: Audio
B02D B02D
3S0Z
3S53-1 +2V5-AUDIO +24V-AUDIO-POWER
4R7 +24V-AUDIO-VDD
100R +3V3
3S53-2

2S3J

220n
7S08
LD3985M25
100R
1 IS1H 1 3S16-1 8
3S12-1 2S2W 3S53-3 FS08 FS03
AUDIO-IN1-L 8 10K 5 1
OUT IN
22K 1u0 100R IS12 IS13 4

10u RES
4 3 4S14 ADAC(1) 12 7S05-4
2 3S53-4 BP INH +2V5 3S38
LM324 14

2S2R

2S2S
3S16-2 7

10u
2 3S12-2 IS1J 2S2V +AUDIO-L
IS02

1u0 RES
AUDIO-IN1-R 7 10K COM 13
100R 100R

2S2T

100n
22K 1u0 11

2S34
2
3S16-3 3 6 2S2Z
IS1M
10K
1u0 3S36-2 10K
2 7
IS0V 8 1
3S16-4 5 2S2Y 10K 3S36-1

100u 4V
3S51

2S42

2S41
4R7
4

1u0
2S2G
10K
1u0
3S17-4 47p
IS0R 4 5 7S00-2
3S13-4 2S31
AUDIO-IN3-L 10K PNX85500 +24V-AUDIO-VDD
4 5 2S36
22K 1u0
AE10 AUDIO AC7 1 3S3G-1 8 ADAC(1)
3 L P
3S17-3 6 AF10 AIN1 ADACL AB7 IS1N
3S13-3 2S30 R N 1u0 33R 3S3G-3 IS03 4
AUDIO-IN3-R 3 6 10K 3 6 ADAC(2) ADAC(2) 10 7S05-3
LM324 8 3S39
AD10 AC6 -AUDIO-R
22K 1u0 L P 33R
AC10 AIN2 ADACR AB6 9
3S17-1 R N 100R
IS1P 1 8
3S13-1 2S33 11
AUDIO-IN4-L 10K AE9 AD7
L 1 3S3G-2
1 8 AF9 AIN3 AE7 2 7 ADAC(3)
22K 1u0 R 2
2 AF7 33R
3 3S3G-4
IS1Q 3S17-2 7 AD9 ADAC AD6 4 5 ADAC(4)
3S13-2 2S32 L 4 IS1S
AUDIO-IN4-R 2 10K AC9 AIN4 AE6 33R
7 R 5
AF6
22K 1u0 6
AF8
L 3S36-3 10K
AE8 AIN5 AD4 3 6
R OSCLK
3S10 AD1 5 4
I2S_OUT SCK 3S3H 10K 3S36-4
2S2L 100R AB9 AD2 ADAC(5)
POS WS 2S2H
IS1B AB8 VR_AADC 33R
1u0 NEG
IS19 AE1
1 3S3U 47p
AD8 AF2 ADAC(6)
VREF_AADC 2
AE3 +24V-AUDIO-VDD
IS1A I2S_OUT_SD 3 33R
AC8 AF3
VCOM_AADC 4
3S3F
AF5
SPDIF_OUT

2S3D

2S3C

2S3B

2S3A

2S39

2S38
1n0

1n0

1n0

1n0

1n0

1n0
56R DBS8 AE5 IS07 4
SPDIF_IN1
2S3G
2S3H
2S3E
2S3F

100n

100n

3 7S05-1
10u

10u

ADAC(5)
LM324
9S06
RES

1 AUDIO-OUT-L
2

11

3S37 3S6L

10K 22K
2S2K

+3V3 47p
+3V3-ARC

+24V-AUDIO-VDD
3S11 IS1L
1R0

4
2S3Q

100n

ADAC(6) 5 7S05-2
LM324 7
IS06 AUDIO-OUT-R
6
3S6N 11
7S09-1 SPDIF-OPT
14

74LVC00APW
IS1D RES 47R
SPDIF-OUT-PNX SPDIF-OUT-PNX 1 & 2S3K
3 IS1G 1 3S18-1 8 SPDIF-OUT
2
100n 220R 3S34 3S32

6
RES

3S18-2

3S18-3
+3V3

220R

220R
RES

RES
7

10K 22K
+3V3
2S2J

3
47p
+3V3-ARC
3S19

+3V3-ARC
10K

7S09-2
14

74LVC00APW 7S09-3
14

4 & 74LVC00APW
6 9 & 2S3L IS1K 2S3M IS44
IS1E 180R
SEL-HDMI-ARC 5 8 eHDMI+
10 3S6M
+3V3 100n 100n
7

3S25

68R
+3V3-ARC

7S09-4
14

74LVC00APW
12 &
11
13
+3V3
7

3 2011-03-09

SPB SSB TV550 2 2010-12-23

3139 123 6521


2K11 4DDR BR SD

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2011-Jul-15 back to
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Circuit Diagrams and PWB Layouts Q552.2L LA 10. EN 88

MIPS

PNX85500: MIPS
B02E B02E
+3V3
7S00-3
PNX85500
RES
CONTROL C25 1
3S56
2
3S69 1F10
IS05 SDA SDA-UP-MIPS SDA-UP-MIPS
3S45 2 3S57 FS44
BOOTMODE 1 C26 100R 1 SCL-UP-MIPS SCL-UP-MIPS 3S6A 4K7 4K7 EJTAG-TRSTn-PNX85500
+3V3 SCL 1
100R EJTAG-TMS-PNX85500 FS49
10K 3S58 2
BOOTMODE Y21 B26 1 2 SDA-SET SDA-SET 3S6B 4K7 EJTAG-TDO-PNX85500 FS50
3S40
3D-LR 3D-LR IS17 9S09 IS16 Y22 GPIO_0
2
SDA
A25 100R 1 2 3S5W SCL-SET SCL-SET 3S6C 4K7 EJTAG-TCK-PNX85500 FS51
3 FOR FACTORY
+3V3 GPIO_1 SCL 4
10K DS52 RXD1-MIPS Y23
GPIO_2
100R EJTAG-TDI-PNX85500 FS52
5 USE ONLY
TXD1-MIPS Y24 B25 1 3S5Y 2 SDA-SSB SDA-SSB 3S6D 2K2
3S82 GPIO_3 SDA 6
BOOST-PWM RXD2-MIPS W21 3 A24 100R 1 2 3S5Z SCL-SSB SCL-SSB 3S6E 2K2 EJTAG-DETECTn FS53
+3V3 GPIO_4 SCL 7
TXD2-MIPS W22 100R
10K GPIO_5 3S60 8
3S80 FS10 TXD2-MIPS GPIO6 W23 B24 1 2 SDA-TUNER SDA-TUNER 3S6F 2K2 10 9
+3V3 GPIO_6 SDA
3S81 10K FS11 RXD2-MIPS PNX-SPI-CS-BLn V22 4 A23 100R 1 2 3S61 SCL-TUNER SCL-TUNER 3S6G 2K2
+3V3 GPIO_7 SCL
10K BOOST-PWM V23 100R
RES 3S21 GPIO_10
+3V3 GPIO6 SELECT-SAW U23 AA25 EJTAG-TRSTn-PNX85500 EJTAG-TRSTn-PNX85500 3S6K
IS04 GPIO_11 TRSTN
AA24 EJTAG-TMS-PNX85500 EJTAG-TMS-PNX85500 1 8 3S6H-1 10K +3V3
10K TMS +3V3-STANDBY FS57 BM08B-SRSS-TBT
USB-DM R26 AA23 EJTAG-TCK-PNX85500 EJTAG-TCK-PNX85500 10K 3 6 3S6H-3
3S62 PNX-SPI-CS-BLn DN TCK
USB-DP R25 AB26 EJTAG-TDO-PNX85500 EJTAG-TDO-PNX85500 10K 2 7 3S6H-2
+3V3
IS4Z R24 DP USB TDO
AB25 EJTAG-TDI-PNX85500 EJTAG-TDI-PNX85500 10K 4 5 3S6H-4
10K RREF TDI
10K
3S00
AE4 RESET-SYSTEMn

5K6 1%
RESET_SYS

3S55
3S64 FS64 33R
SELECT-SAW AD5 BACKLIGHT-PWM
+3V3 BL_PWM
10K
AC5
CLK_54_OUT

3S26

3S27
3S6J

RES 10K

10K

10K
3S83
+3V3 RXD1-MIPS
10K
+3V3 +3V3
3S84
+3V3 TXD1-MIPS IS40
3S72
10K PXCLK54
47R

RES

+3V3

2S89

100n +3V3

3
7S01
PCA9540B
3S65
VDD SC0 5 SCL-DISP SCL-DISP 2 1
4K7
3S66
SC1 8 SCL-BL SCL-BL 2 1
4K7
3S67
SCL-SET 1 SCL SD0 4 SDA-DISP SDA-DISP 2 1
I2 C 4K7
INP 3S68
-BUS
SDA-SET 2 SDA FIL SD1 7 SDA-BL SDA-BL 2 1
CTRL
4K7
VSS

6
FS31

9S10 SCL-BL
IS08
SCL-SET 9S11 FS2W SCL-DISP

9S12 FS2Y SDA-DISP


IS09
SDA-SET 9S13 SDA-BL

7S00-4
PNX85500

ETH-RXCLK AA3
RXCLK ETHERNET
ETH-RXD(0) Y5
0
ETH-RXD(1) Y6 AA2 ETH-TXCLK
IS50 1 TXCLK
ETH-RXD(2) AB4 RXD ETH
2
ETH-RXD(3) AC1 AA1 ETH-TXD(0)
3 0
AA4 ETH-TXD(1)
1
ETH-RXDV AC2 TXD AB1 ETH-TXD(2)
RXDV 2
ETH-RXER Y4 AB2 ETH-TXD(3)
RXER 3
ETH AA5 ETH-TXEN
TXEN
SDIO-DAT3 W2 AB3 ETH-TXER
CC_DAT3 TXER
SDIO-CLK W1 AC3 ETH-COL
CLK COL
SDIO-CMD W6 Y2 ETH-CRS
CMD CRS
SDIO-DAT0 W5 Y3 ETH-MDC
0 MDC
SDIO-DAT1 W4 SDIO Y1 ETH-MDIO
1 DAT MDIO
SDIO-DAT2 W3
2
SDIO-CDn U6
SDCD
SDIO-WP V6
SDWP

3 2011-03-09

SPB SSB TV550 2 2010-12-23

3139 123 6521


2K11 4DDR BR SD

19110_025_110415.eps
110415

2011-Jul-15 back to
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Circuit Diagrams and PWB Layouts Q552.2L LA 10. EN 89

Video out - LVDS

PNX85500: Video out - LVDS


B02F B02F

7S00-7
PNX85500

PX1A- A7 LVDS D7 PX3A-


N N
PX1A+ B7 A A E7 PX3A+
P P

PX1B- C8 E8 PX3B-
N N
PX1B+ B8 B B D8 PX3B+
P P

PX1CLK- 9S90 C10 E10 9S94 PX3CLK-


N N
PX1CLK+ 9S91 B10 CLK CLK D10 9S95 PX3CLK+
P P

PX1C- A9 LOUT1 LOUT3 D9 PX3C-


N N
PX1C+ B9 C C E9 PX3C+
P P

PX1D- A11 D11 PX3D-


N N
PX1D+ B11 D D E11 PX3D+
P P

PX1E- C12 E12 PX3E-


N N
PX1E+ B12 E E D12 PX3E+
P P

PX2A- A14 D14 PX4A-


N N
PX2A+ B14 A A E14 PX4A+
P P

PX2B- C15 E15 PX4B-


N N
PX2B+ B15 B B D15 PX4B+
P P

PX2CLK- 9S92 C17 E17 9S96 PX4CLK-


N N
PX2CLK+ 9S93 B17 CLK CLK D17 9S97 PX4CLK+
P P
LOUT2 LOUT4
PX2C- A16 D16 PX4C-
N
PX2C+ B16 N C E16 PX4C+
C P
P
PX2D- A18 D18 PX4D-
N
PX2D+ B18 N D E18 PX4D+
D P
P
PX2E- C19 E19 PX4E-
N
PX2E+ B19 N E D19 PX4E+
E P
P

3 2011-03-09

SPB SSB TV550 2 2010-12-23

3139 123 6521


2K11 4DDR BR SD

19110_026_110415.eps
110415

2011-Jul-15 back to
div. table
Circuit Diagrams and PWB Layouts Q552.2L LA 10. EN 90

Standby controller

PNX85500: Standby controller


B02G B02G

+1V1

POL
IS3B

5S04
RES

30R

2S10

100n
1u0
2S13

2S37

1u0

9S24
RES
2S11

100n IS20 DS50 2S4G


3
1 10p

AC17
AA17

AF26
2

1S02

54M
7S00-9
PNX85500 4
2S4F
1

VDDA_1V1_DCS

VDDA_ADC2V5

VDD_XTAL
+3V3-STANDBY 2S4D AE17 +3V3-STANDBY
3S1B XTAL_IN 10p
1n0 RC RC AD19
0
3S1C RES 10K TACHO TACHO AE19 AF17
1 XTAL_OUT
10K 3S1D CEC-HDMI CEC-HDMI AF19
2 P1
3S1E RES 27K BACKLIGHT-PWM-ANA-DISP BACKLIGHT-PWM-ANA-DISP AA20 AA26 RESET-STBYn
3 RESET_IN
10K 3S1F SDM SDM AB20 IS3F
7 3S44
+3V3-STANDBY
3S3L 10K STANDBY EA
AB24 EA EA
RES LCD-PWR-ONn LCD-PWR-ONn AC20
0 ALE IS3E 10K 3S43
3S3M 10K EJTAG-DETECTn EJTAG-DETECTn AD20 AB23 ALE
3S3N RES 1 ALE
10K LAMP-ON LAMP-ON AE20 IS3D
2 10K
3S3P 10K STANDBY STANDBY AF20 AC26 PSEN PSEN 10K 3S42
3 PSEN
10K 3S3Q RES FAN-CTRL1 FAN-CTRL1 AA21 P2
4 RES 3S6V
RES 3S3S 10K FAN-CTRL2 FAN-CTRL2 AB21 AC23 3S2F 100R SDA-UP-MIPS SDA-UP-MIPS
3S3R 5 SDA 3S2G 100R
10K POWER-OK POWER-OK AC21 MC AC24 SCL-UP-MIPS SCL-UP-MIPS 4K7 3S6W
6 SCL
3S3T 10K RES ENABLE-3V3n ENABLE-3V3n AD21 RES
7 LED1 RES 3S1P 4K7
+3V3-STANDBY 10K AD26 3S2H 100R LED1
3S1G 0
RXD-UP RXD-UP AE21 PWM AC25 3S2K 100R LED2 LED2 10K 3S41
0 1
3S1H 10K TXD-UP TXD-UP AF21
1 10K
10K DETECT2 AA22 AE23 PNX-SPI-SDO
3S2A 2 SDO
DETECT2 AB22 P3 AF25 PNX-SPI-SDI
3 SDI
AC22 SPI AF24 PNX-SPI-CLK
10K 4 CLK
RES AD22 AF23 PNX-SPI-CSBn
5 CSB
3S1K
RESET-SYSTEMn RESET-SYSTEMn AD23 AB17 IS2V CTRL-DISP CTRL-DISP RES 3S2L
0 0
AV2-BLK AE26 AA18 IS2Z RESET-DVBS RESET-DVBS 10K RES 3S46
10K 1 1
RES AV1-BLK AE25 P5 AD18 RESET-USBn RESET-USBn RES 3S3Y 10K
3S1J KEYBOARD 2 2 +3V3-STANDBY
KEYBOARD AE24 AE18 RESET-ETHERNETn RESET-ETHERNETn 10K RES 3S47
3 3
LIGHT-SENSOR P0 AF18 SEL-HDMI-ARC SEL-HDMI-ARC 3S2S 10K
100K 2S4E 4
AV1-STATUS AF22 AA19 RESET-AVPIP RESET-AVPIP 10K RES 3S2M
RES 4 5

VSS_XTAL
AV2-STATUS AE22 P6 AB19 RESET-AUDIO RESET-AUDIO 3S3W 10K RES
100n 5 6
AC19 AUDIO-MUTE-UP AUDIO-MUTE-UP 4K7 3S49
7

AD17
3S1L
SPI-PROG SPI-PROG 4K7
10K PNX-SPI-WPn

+3V3-STANDBY +3V3-STANDBY

1 3S2V 2
1K0
9S0E
FS0Z
7S20 RESET-STBYn
NCP303LSN28
2
FS45 INP
1 IS2U 1
OUTP
5
CD
NC GND

3
9S0D

2S4K

100n
RES
4 2011-03-09

SPB SSB TV550 2 2010-12-23

3139 123 6521


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Circuit Diagrams and PWB Layouts Q552.2L LA 10. EN 91

Power

PNX85500: Power
B02H IS3Q 5S80

30R
+1V1 B02H

RES 10u
2S6A

2S5A
100n
1
5S81
+2V5

2
30R

RES 10u
2S6B

2S5B
100n
1
+1V8
IS3S 5S82

2S26

2S60

2S61

2S62

2S63

2S64

2S65

2S66

2S67

2S68
100u

100n

100n

100n

100n

100n

100n

100n

100n

100n
+3V3
30R

RES 10u
2S5C

2S5D
100n
SENSE+1V1 c001
5S93
7S00-10

G6

G7
R6
R7
U7

C6
D6
A5
A6
B5
B6

E6
F6

F7
L6
L7
PNX85500 30R +2V5

2S6E 2

220u 6.3V
VDD_1V8

2S4M
2S6D

100n

100n
+1V1 AF1 V20

7
AE2 HDMI_VDDA_1V1 V21

5
AD3

1
2S5G-1

2S5G-2

2S5G-3

2S5G-4

2S5H-1

2S5H-2

2S5H-3

2S5H-4
2S4Q

2S4R
2S43

2S28

2S27

2S23
100n

100n

100n

100n

100n

100n

100n

100n

100n

100n

100n

100u
AC4 VDD U20

22u

22u

1
AB5 HDMI_VDDA_2V5 U21
H20

4
F11 U22 +2V5-LVDS

2
HDMI_VDDA_3V3_TERM
G11
F13 N6

2S4N

2S4P
100n
G13 VDD_2V5 N7

10u
F15

8
8

5
G15 C7

2S5K-1

2S5K-2

2S5K-3

2S5K-4

2S5J-3

2S5J-1

2S5J-2

2S5J-4
100n

100n

100n

100n

100n

100n

100n

100n

220u 2.5V
F17 C9

2S29
G17 C11
5S85
F19 VDD_2V5_LVDS C14

4
+3V3

2
1 2S6G 2
G19 C16

1
30R

2S6N

2S6C

2S6P
2S6F

100n

100n

100n

100n
J9 C18

10u
J11
AA16
AA8
Y11
Y14

J13 W20
Y16
Y9

7S00-12

1
PNX85500 J15 P20
J17 M20
VSSA
A1 M7 L9 VDD_3V3 K20
+3V3-STANDBY
A10 N2 L11 V7

2S4U
2S4V

100n
A12 N20 L13 Y8

10u
A15 P10 L15
VDD_1V1
A17 P12 L17 Y19
A19 P14 N9 VDD_3V3_SBY Y18
A26 VSS P16 N11 IS3K 5S83
A3 P18 N13 B13
VDDA_1V1_LVDS_PLL +1V1
A8 P4 N15 30R
IS3L

2S4W
2S4Y

100n
B1 P6 N17 AA15

RES 1u0
B20 P7 R9 Y15
VDDA_1V2
C20 T10 R11 AA13
C4 T12 R13 5S95 +2V5
D2 VSS T14 R15 Y12
VSS VDDA_2V5 5S84
D20 T16 R17
30R

6.3V
E13 T18 U9 AA9 +1V2
VDDA_2V5_AADC 30R

2S4Z
2S51

2S52

2S50
100n

100n
E20 T2 U11

10u
E4 T6 U13 AA7 c000 SENSE+1V2

10u
VDDA_2V5_ADAC
F10 T7 U15
F12 U4 U17 Y17
VDDA_2V5_DCS
F14 V10 J6
F16 V12 AA6 D13
VDDA_2V5_LVDS_BG
F18 V14 Y7
F20 V16 W7 T20 POL

VSSA_1V1_LVDS_PLL

VSSA_2V5_LVDS_BG
VDDA_2V5_USB
F8 V18 F9
G10 V2 G9 Y13
VDDA_2V5_VADC +2V5-AUDIO
G12 Y20

V24 HDMI_AGND
5S94

2S46

100n
J7 Y10

VSSA_USB
VSS +1V1 VDD_1V1_DDR VDDA_2V5_VDAC
30R
2
G14
G16
G18
G2
G20
G8
H4
H6
H7
J20
K10
K12
K14
K16
K18
K2
K6
K7
L20
L4
M10
M12
M14
M16
M18
M6

R21
VDDA_3V3_USB
2S4S

2S5P
RES

2S21
100n
10u

1u0

U24

A13

C13

R20
1

+2V5-AUDIO

2S45

100n
5S87
+2V5
30R

2S55

2S56
100n

1u0
5S88
+2V5-LVDS
30R

2S5M

2S57
100n

10u
5S89
+2V5

2
30R

2S6H

2S6K
100n

100n
2S58

10u
1

1
5S90
+2V5
30R

2S4T

2S53
100n

10u
2SHW

100n
IS58 5S92
+3V3

2
30R

2S6M

2S6L

2S59
100n

100n

1u0
3 2011-03-09

1
2 2010-12-23
SPB SSB TV550
3139 123 6521
2K11 4DDR BR SD

19110_028_110415.eps
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2011-Jul-15 back to
div. table
Circuit Diagrams and PWB Layouts Q552.2L LA 10. EN 92

Analog video

PNX85500: Analog video


B02I B02I
AV1-CVBS 2S87

22n 2S8A Y-SVHS

3S59
47R
Connectivity 22n

3S5B
47R
AV1-R 2S7J

22n 2S22 C-SVHS

3S4J
56R
22n

3S05

56R
EU: SCART1 CVBS-MON-OUT1
AV1-B 2S7K
AP: -

3S5E

560R
22n

3S4L
56R
IS4V

560R
2S40

3S08
47p
2S7H
AV1-G
22n

3S4K
56R
IS4W

3S09

8K2
2S7M
YPBPR1-SYNCIN1
10n
2S7L
AV3-Y
22n

3S4P
56R
2S7N
AV3-PR
YPBPR1 22n

3S4R
EU:

56R
7S00-1
AP: YPBPR1 PNX85500
2S7P ANALOG_VIDEO
AV3-PB
AB15 AC12
22n CVBS_Y1 ATV_CVBS_Y3

2S19

2S18

2S16

2S15

2S14
3S4T
AC13 IS5C

56R
AF13

22n

22n

22n

22n

22n
R C3
AD13
B AV1
AE13 AD11
G CVBS_Y7
AC11
C7
AV2-CVBS 2S8G AF15
SYNCIN1 BS13
AE15 AF11
22n Y_G1 CVBS1_OUT
AC15 AE11
PR_R_C1 CVBS2_OUT

9S18
AD15
PB_B1
* RESREF
AB10
AB14 AA11 IS5E 3S5S
CVBS_Y2 CURREF
AF14 10K
SYNCIN2
AE14 AC16 IS5D
Y_G2 1
AC14 AB16 IS5F
PR_R_C2 2
AD14 AB13 IS5G
PB_B2 3
REF AB12 IS5H
4
AF16 AA12 IS5J
R 5 3S75
AD16 AA10 PNX-IF-AGC
G VGA 6
AE16
B 10K

2S75
2S7R AB18 AD12 BS15

10n
AV4-Y HSYNC_IN IF_AGC
AC18 AB11
22n IN RF_AGC
EU: SCART2 AF4
OUT
VSYNC
9S19

AD24 AE12
SCL VGA_EDID P
AP: YPBPR2 AD25
SDA TUNER N AF12 BS10 IS11
3S76
PNX-RF-AGC
+CVBS 47K

2S76
AGND

10n
AA14
AV4-PR 2S7U

22n
9S20

2S77
PNX-IF-P
10n

2S7E
AV4-PB
22n 2S78
9S21

PNX-IF-N
10n

2S84
R-VGA
22n
3S50
56R

2S85
G-VGA
22n
3S52
56R

2S86
B-VGA
22n
3S54
56R

EU: VGA

7
3S5V-4

3S5V-2
3S5T-4

3S5T-2
AP: VGA

100R

100R

100R

100R
3S5T-1
H-SYNC-VGA 1 8

2
100R

V-SYNC-VGA 3 3S5T-3 6
100R

RES 3S5V-3
* 319803104790 - RST SM0402 47R PMS Col R at 9S18 for BRZ
VGA-SCL-EDID 3 6
100R
RES 3S5V-1
VGA-SDA-EDID 1 8
100R
3 2011-03-09

SPB SSB TV550 2 2010-12-23

3139 123 6521


2K11 4DDR BR SD

19110_029_110415.eps
110415

2011-Jul-15 back to
div. table
Circuit Diagrams and PWB Layouts Q552.2L LA 10. EN 93

10-3 B03 313912365213


Audio

Audio
B03A B03A

+AVCC
7D03-1 +24V-AUDIO-POWER
3D09 BC847BS(COL) FD14

1
+24V-AUDIO-POWER
4R7

2D06

220n
2
3D16 ID12
ID11

5D07

220R
5D08

220R
22K

10u 35V
GND-AUDIO

2D05
ID27 ID28
FD01 2D28 ID14 2D24
-AUDIO-R

220u 35V

220u 35V
1u0 47n

8
2D20

2D07

2D19

2D08
220n

220n
6

3D02-4

3D14-4

3D14-3

3D14-2

3D14-1

2D22

2D26
220n

220n

RES
4K7

22K

22K

22K

22K
FD08
A-PLOP 7 3D02-2 2 2 7D15-1
BC847BS(COL)

1
4K7
1

GND-AUDIO GND-AUDIO

7D10-1
FD03 2D29 ID15 2D23 TPA3123D2PWP

19
20

10
12
1
3
+AUDIO-L
1u0 47n AVCC L R

1
3
PVCC ID32 2D10
Φ

3D02-1
16

4K7
3D02-3 ID19 BSR ID10 5D02 5D05 2D12 RIGHT-SPEAKER
6 3 5 7D15-2 6
BC847BS(COL) ID18
R CLASS-D 15
220n
ID06 ID08

8
4K7 IN R 22u 220R 35V 220u
4 5
L
AUDIO AMP OUT
22
L ID09 5D01 5D04 ID07 2D11
18 LEFT-SPEAKER
0 ID31 2D09
17 GAIN 21 22u ID05 220R
1 BSL 35V 220u
GND-AUDIO 2D16 ID29 220n
11
VCLAMP
2D17 1u0 7
BYPASS
ID30 4
1u0 MUTE
2
AUDIO-MUTE-UP ID37 SD
PGND
FD09 AGND L R
A-STBY GND_HS

8
9

23
24

13
14

25
+3V3-STANDBY
6

8
3D15

4K7
3D01-3

3D10-4

3D10-3

3D10-2

3D10-1

2D21

2D27
220n

220n
6

RES
47K

22K

22K

22K

22K
CD10 FD10
MAINS SWITCH DETECT
7D11-1 2
3

1
BC847BS(COL)
ID34 GND-AUDIO
1 3 +3V3-STANDBY
ID35
3D01-4
7D11-2 5 4 5 DETECT2
BC847BS(COL)
47K
4
GND-AUDIO GND-AUDIO

40
39
38
2D03
100p

GND-AUDIO 7D10-2
TPA3123D2PWP
VIA LEFT-SPEAKER
GND-AUDIO 26 37
GND-AUDIO
27 36
VIA

V_NOM
1D50

2D14
28 VIA VIA 35

10n
29 34
GND-AUDIO GND-AUDIO
VIA
1735 1D38
30
31
32
33
FD05
5D03 1 1
FD06
2 2
220R 3 3

2D01
GND-AUDIO FD02

10n
GND-AUDIO 4

2D13
3 7D03-2 2041145-3

10n
BC847BS(COL) 2041145-4
3D06-3 FD07 3D06-2 5
LEFT-SPEAKER
3 6 7 2
100K 100K
4
RIGHT-SPEAKER
8 3D06-1 1
ID33

V_NOM
100K

1D52
GND-AUDIO
2D02
3D06-4
RIGHT-SPEAKER 4 5
100K 10u
GND-AUDIO 3 2011-03-09

SPB SSB TV550 2 2010-12-23

3139 123 6521


2K11 4DDR BR SD

19110_030_110415.eps
110415

2011-Jul-15 back to
div. table
Circuit Diagrams and PWB Layouts Q552.2L LA 10. EN 94

DC/DC

DC/DC
B03B B03B

5U03 RES

30R
FU05 5U02 IU22
+12V
30R
7U02-1 * 0402 Jumper

2U24

2U23

2U25

2U19

2U20
10u

10u

10u

10u

1u0
SI4952DY
7 8
IU10
2
12V/1V8 CONVERSION

1
3U11

3R3
2U21 FU02 5U00 FU03
+1V8
IU11 220p 3u6

22u
3U23-4

3U23-3

3U23-2

3U23-1

2U15

2U16
47R

47R

47R

47R

47u
7U02-2
SI4952DY

1
5 6
IU09
4 IU23

2U17

1n0
IU15
7U01
SI4778DY

2U18

1n0
3U27 5 6 7 8
IU08 IU12
4
10R 1 2 3
2U00

3U14
10u

3R3
3R3

3U04
2U22
IU06 2U02 IU07
IU05 IU13 220p

3U28

10R
100n
2U01

100n

3R3

7U04
7U03 3U05 SI4778DY
TPS53126PW
5 6 78
IU16
2 23 4
1 1 1 2 3
IU24 11 VBST DRVL 14 IU14
2 2
3 1
12V/1V1 CONVERSION
1 1
ENABLE-1V8 10 EN DRVH 12
2 2
1n0 RES

5U01 FU01
FU06
2U03

+1V1 4 24 +1V1
1 1

STPS2L30A
+1V8 9 VO SW 13

RES 100u 2.0V


2 2 2u0

6U00

2U14
5 22

3U24-4

3U24-3

3U24-2
1 1

3U24-1

3U20

2U12

2U13
RES
8 VFB PGND 15

22u
47R

47R

47R

47R

10R

47u
RES GND-SIG 2 2
7U00 3U02 IU01
BC847BW 21 7
1 1
3 22K 3U03 16 TRIP TEST 17
IU03 2 2
1 IU02
GND-SIG 12K GND-SIG
20 18 FU04 IU17
GND-SIG VIN V5FILT
2 19 IU25
VREG5

2U11

1n0
+3V3-STANDBY 3U00 2U06
+1V1 GND
2U04

2U05
6

10u

1u0

10K 100n
IU18
10K

3U01 GND-SIG

2U09

2U10
1n0

1u0
GND-SIG
3U21 FU00
IU19 SENSE+1V1
100R 1%

3U17

1% 330R

2U29

100n
RES
IU20

100p RES

3U19
2U08

3U18
5K6

1% 1K0
3U08 3U22
IU04
+1V8 FU09 FU08
1K0 1% CU00
330R 1% IU21
RES 100p
1K0 1%
3U09

3U10

2U07

CU01
22K

CU02
GND-SIG GND-SIG GND-SIG
CU03
CU04
CU05
GND-SIG GND-SIG GND-SIG

GND-SIG

3 2011-03-09

SPB SSB TV550 2 2010-12-23

3139 123 65213


2K11 4DDR BR SD

19110_031_110415.eps
110415

2011-Jul-15 back to
div. table
Circuit Diagrams and PWB Layouts Q552.2L LA 10. EN 95

DC/DC

DC/DC
B03C +3V3 +3V3-STANDBY
B03C
LED-2

RES 10K

RES 10K
** Optional table for Ambilight

3U74

3U75
Optional table for Styling
+5V +3V3-STANDBY Items Emmy
( +24V AL)
Sundance / Infinity
( +12V AL)
BlockBuster
(For non-Amblight sets)
***
IU43 2U44 3U43 1M95
9U41 4U00 yes no no
4U01 yes no no
Dream Catcher 0R open

RES 10K
1M99 no yes no 13 POLE

3U68

3U69
10K
1M95 yes yes yes Core Range 100p 100R 14 POLE
IU44 3U41 3U59 2U56 no yes no
IU45 LED2 LED2
optionally 1M99 is a 9 pin connector
* LED-1 9U42
RES
10K RES 10K RES

7U42 RES +3V3


BC847BW
* 7U43
IU47 3U70 LED1 LED1 3U53
BC847BW
** 10K 10K
1M99
1 GND_AL 3U82 IU64
FU48
2
3 GND_AL 1K0 RES
FU49 +12V_AL +3V3 RES 3U56 10K
4 7U48-1
5 GND_AL 3U83-4 BC857BS(COL)
FU50 4 5 ENABLE-3V3-5V

6
6 FU07
FU54 RES 3U44 100R 3D-LR
7 100K
FU77 IU41
8

8
+12VIN

3U83-1
9
RES 3U66 100R

100K
FU56 BL-SPI-SDO

2
10

2U71

100n
FU57
11 100R
FU74 RES 3U67 BL-SPI-CSn

1
12
FU68
13
RES 3U84 100R BL-SPI-CLK
100p

100p

100p

100p

100p

1-2041145-3
RES 2U57

2U56

RES 3U76
1n0

1n0

MAINS-OK
+3V3-STANDBY
RES 2U48

RES 2U72

RES 2U51

100R
RES 2U52

RES 2U43
**

3
3U71 100R STANDBY 7U48-2
BC857BS(COL)

5
5
7U40-2 3U83-3 3U83-2
3 6 7 2

10K
2U68 BC847BPN(COL)
3U62-4 4
IU48 100K IU40 100K

4
1u0
5
2U47

3
3

3U62-3
3 3U60-3 6 FU73 ENABLE-1V8
***

10K
10n IU61
1M95

BZX384-C6V2
22K

RES 10K
7

3U61
FU58 +3V3-STANDBY

6
1 10n

6U40
FU59

10K
2 IU49 3U62-2
FU60
3 2U54 1U40 +12V 6

2
FU61 7U40-1

2
4 +12VIN IU51 FU72

22K
5 FU63 T 3.0A 32V BC847BPN(COL) DETECT2
FU75 2 3U60-2
6 FU66
3U72

1
1K0

+24V-AUDIO-POWER 7U41-2

7
7
2U50

1u0 RES
FU67 3 BC847BS(COL)
10n

8 IU63

5
2U55

9 3U60-1 IU57
ENABLE-3V3n
2U49

3U80
100n

5 8 1

4K7

22K
10 IU62 3U60-4
11 3U73 3U62-1 IU50 22K
IU56 4 IU52

4
12 3U81 +3V3-STANDBY
FU62 +3V3 8 1
10K 6
13 +24V GND-AUDIO 3K3

3U63

RES 10K
10K 7U41-1
14 FU76
BC847BS(COL) 2
3U45
2U58

100n

1-2041145-4 FU51 LAMP-ON 1


100R
FU52 3U42 BACKLIGHT-PWM_BL-VS

FU53
100R
3U43 *** BACKLIGHT-BOOST
100R
** 4U01 IU55
FU55 3U64 POWER-OK
** 4U00 1K0
100p

1n0

10n
2U53

3U65

100K
1n0

GND_AL
2U44

2U45

2U46
***

+12VIN +12VD 3 2011-03-09

SPB SSB TV550 2 2010-12-23

3139 123 6521


2K11 4DDR BR SD

19110_032_110415.eps
110415

2011-Jul-15 back to
div. table
Circuit Diagrams and PWB Layouts Q552.2L LA 10. EN 96

DC/DC

DC/DC
B03D B03D
+3V3
7UC0
LF25ABDT *
+12V 1 3
IN OUT
COM

2UA4

1u0
*

3UA0

2K2

2
FUA0
+2V5-REF
1
7UA0
TS2431 K

R 2
A

3 FUA4
+2V5

CUA0 +2V5-LVDS
IUB6
+5V5-TUN +5V-TUN

7UA6
BC817-25W

330R
1%
3UB6-3 3U12
+12V 3 6 IUB3

2
3UB6-2
1K0 IUB2
7 6
+1V8
* +3V3 * +3V3
3U15-1 3U16-1
1K0 +5V 1 8 +5V 1 8
3UB6-1
1 8 2 IU26 100R 100R
1K0 7UA3
3UB6-4 3U15-2 3U16-2

2UB0
4 5 IUB5 3 1 7UA7-1 PHD38N02LT 2 7 2 7

1u0
BC847BS(COL)
330R
1%

+2V5-REF 1K0
3UB7-4 3U13 100R 100R
5 4 5
3UB0 IUA5 3U15-3 3U16-3
1 2 3 6 3 6
470R
7UA7-2 4 IUB4
BC847BS(COL) 22R 100R 100R
3U15-4 3U16-4
470R

3UB7-1470R

4 5 4 5
FUA3
2

+1V2 100R 100R


3UB7-3
3UB7-2
2UB8

470R
22u

2UB1

2UB2
RES 1u0

1u0
7

NOT FOR 5000 SERIES


*
ENABLE-1V8
3U25-4
4 5
3UB1 SENSE+1V2
100K RES RESERVED
100K RES
7

IUA6 1K0 5UA0


3U25-3 3U25-2
3 6
30R
2

100K RES 3U29-1 RES


1 8 +12V 7UA5
LDS3985M50
470R
IU29 RES
100K RES

3U29-2
1

2 7 +5V5-TUN 1 5 +5V-TUN
IN OUT

4K7
470R 7UA4
3U25-1 3UB2 3 4
TS431AILT INH BP IUB1
3 6 +3V3 3 3U29-3 6 RES
8

RES RES IU30 5 3 COM


470R A K

2UB7

2UB5

2UB6
100n
7U06-2 5 7U06-1 2

1u0

1u0
3U29-4 RES
BC847BS(COL) BC847BS(COL) 4 5 2 1

2
NC NC
4 1

4K7
470R REF
3UB3
1 3U26-1 8 RES
4

470R
3U26-2 RES
2 7
3UB5 3UB4 IUB0 2UB3
470R +5V
3U26-3 RES 100K 1K0 1n0
+3V3 3 6
2UB4
470R
3U26-4 RES 330p
4 5
RES
470R 3 2011-03-09

SPB SSB TV550 2 2010-12-23

3139 123 6521


2K11 4DDR BR SD

19110_033_110415.eps
110415

2011-Jul-15 back to
div. table
Circuit Diagrams and PWB Layouts Q552.2L LA 10. EN 97

DC/DC

DC/DC
B03E B03E
5UD0 IUD0
+12V
30R +5V5-TUN
0402 Jumper
* 7UD0-1

2UD0

2UD1

2UD2
ST1S10PH

10u

10u

10u

6
A

SW
IUD3 5UD1 6UD0 FUD3
ENABLE-3V3-5V IUD7
2 7 +5V
INH VIN SW
3u6 SS36 +1V1

RES 2UE9
5 3

220u 16V
RES 1n0
SYNC VFB

2UD3

2UD4

2UD5

2UD6

RES 2U27

100n
GND

22u

22u

22u
A P HS

9
6

7U05-1 2
IU27
BC847BS(COL)
IUD6 2UD7
RES 1
7UD0-2 4n7

13

15
ST1S10PH

10K
3UD2

3UD0

3UD1
3U06

68K

33K
1%

1%
10 VIA 12
120K

RES
11

14
* * 5UD3 IUD1
+12V
30R
0402 Jumper
* 7UD1-1
2UD8

2UD9

2UE0

ST1S10PH
10u

10u

10u

6
A

SW
IUD4 5UD2 FUD2
ENABLE-3V3-5V 2 7 +3V3
INH VIN SW
3u6 +1V1
5 3

220u 16V
SYNC VFB

2UE1

2UE2

2UE3

2UE4

RES 2U28
1% 100K
3UD3

100n
GND

4n7

22u

22u
A P HS

9
3 BC847BS(COL)

7U05-2 5 IU28
RES
IUD2 4
7UD1-2

13

15
ST1S10PH

10K
3U07

3UD4

3UD5

33K
1M0

1%
10 VIA 12

RES
11
14

7UD2
* 6UD1
LD1117DT25
IUD5
+5V 3 2 +2V5
IN OUT
S1D COM
(*) FOR 5000 SERIES ONLY

22u 16V
2UE5

2UE6
100n

(**) NOT FOR 5000 SERIES


7UD3
LD1117DT33

3 2 +3V3
IN OUT
COM
22u 16V
2UE7

2UE8
100n

3 2011-03-09

SPB SSB TV550 2 2010-12-23

3139 123 6521


2K11 4DDR BR SD

19110_034_110415.eps
110415

2011-Jul-15 back to
div. table
Circuit Diagrams and PWB Layouts Q552.2L LA 10. EN 98

Temperature sensor & AmbiLight

Temperature sensor & AmbiLight


B03F B03F

5UM1 IUM0 1UM0 FUM0


+3V3 V-AMBI
30R T 1.0A 63V

3 2011-03-09
2 2010-12-23
SPB SSB TV550
3139 123 65213
2K11 4DDR BR SD

19110_035_110415.eps
110415

2011-Jul-15 back to
div. table
Circuit Diagrams and PWB Layouts Q552.2L LA 10. EN 99

Fan control

Fan control
B03G B03G

+12V +12V

+3V3

1 3US4-1 8
10K

10K 7
+12V

3US5-2

2US3

100n
10K
3US2 7US1-1
3US7 3
9 LM339P

2
IUS3 3US5-1 IUS6
1K0 14 8 1
FAN-CTRL1 8
10K
7US2
IUT1 12 BC807-25W
+12V IUS7
+3V3

3US9

22R
6
3US5-3
+12V

10K
10K
3US3 3 7US1-2

3
11 LM339P
IUS4 3US5-4
IUT2 13 5 4 BC807-25W
FAN-CTRL2 10 7US3
10K IUS8
12
IUS9

3US6

47R
FAN-DRV

+3V3

+12V

5
IUS5

3US4-4
+12V

10K
6
3US4-3

10K
7US1-3

4
3
5 LM339P
2
TACH01 3 4

12
+12V
RES
9US0

+12V
7
3US4-2

10K

7US1-4
3
7 LM339P
1
2

FUS0
TACH02 6
12

TACHO

3 2011-03-09

SPB SSB TV550 2 2010-12-23

3139 123 6521


2K11 4DDR BR SD

19110_035_110415.eps
110415

2011-Jul-15 back to
div. table
Circuit Diagrams and PWB Layouts Q552.2L LA 10. EN 100

Vdisp switch

Vdisp switch
B03H B03H

1 9UU0-1 8
RES
2 9UU0-2 7
RES
3 9UU0-3 6
RES
4 9UU0-4 5
RES
1 9UU1-1 8
RES
2 9UU1-2 7
RES
3 9UU1-3 6
RES FUU0
4 9UU1-4 5
RES

RES
7UU0
SI4835DDY RES
7UU1 +VDISP-INT
+12VD SI3441BDV
RES

RES 2UU2

22n
7UU2-2
PUMD12
3UU3-1
8 1
4
47K RES
RES 3UU1 RES 2UU1 3UU3-2 IUU3
5 2 7
47R 1u0 IUU2 47K RES
3 IUU1
IUU0 RES 3UU0-1 RES
8 1 7UU3
BC847BW
47K

2
6 3 IUU4 3UU3-3 IUU5 3UU3-4

RES 3UU0-2
1 6 3 4 5

47K
RES 3UU0-4 RES +3V3
2 7UU2-1
+3V3-STANDBY 47K RES 47K RES
5 4 PUMD12 2

7
47K

2UU0

RES 100n
1

FUU1
VDISP-SWITCH
3UU2
+3V3
4K7 RES

LCD-PWR-ONn

3 2011-03-09

SPB SSB TV550 2 2010-12-23

3139 123 6521


2K11 4DDR BR SD

19110_037_110415.eps
110415

2011-Jul-15 back to
div. table
Circuit Diagrams and PWB Layouts Q552.2L LA 10. EN 101

10-4 B04 313912365213


Analogue externals A

Analogue externals A
B04A B04A

IE22 3E07-1 FE71


AUDIO-IN1-R
1 1K0 8

CDS4C12GTA
2E06

RES 6E03

1E31

2E88
100p

12V

1n0
FE23 3E07-4
AUDIO-IN1-L
4 1K0 5

CDS4C12GTA
2E04

6E09

1E54

2E91
100p

12V

1n0
1E02-1 IE18
MSP-8032SH-01-NI-FE-RF-PBT-BRF AV1-STATUS
**
RED

RES
1
** 4E01

3E32

4K7
RES
2

1E02-2
MSP-8032SH-01-NI-FE-RF-PBT-BRF
WHITE
3
YPBPR1-PB ** 4E02 AV2-STATUS
FE73 RES
EU 3E74 18R 4 IE05

3E17

4K7
IE53 5E73 BEC3 3E75
AV1-B
1u8
CDS4C12GTA

18R
2E79

2E80

RES 6E23

1E12

2E15
150p

150p

100p
12V

+3V3
RES 1E01-2
MSP-8033SH-02-NI-FE-RF-PBT-BRF
BLUE
** 4E04 3

3E44

4K7
FE74 RES
4

IE48
AV1-BLK
YPBPR1-SYNCIN1 1E01-3
MSP-8033SH-02-NI-FE-RF-PBT-BRF
EU 3E76 18R
GREEN +3V3
5
** 4E05
FE86 RES
5E74 3E77 FE80 6
AV1-G
CDS4C12GTA

1u8 18R
2E83

2E84

3E73
150p

150p

4K7
RES 6E26

1E18

2E14

100p
12V

IE51
RES AV2-BLK

1E01-1
YPBPR1-PR MSP-8033SH-02-NI-FE-RF-PBT-BRF
RED
4E03 1
EU 3E78 18R **
IE55 BEC5 3E79 FE81 RES
5E76
AV1-R 2 CVBS-MON-OUT1
CDS4C12GTA

1u8 18R
2E85

2E86
150p

150p

RES 6E28

1E19

2E12

2E98
100p
12V

18p
FE85

RES
GND_A

3E07-2

2 1K0 7
3E07-3
3 1K0 6

3 2011-03-09
2 2010-12-23
SPB SSB TV550
3139 123 6521
2K11 4DDR BR SD

19110_038_110415.eps
110415

2011-Jul-15 back to
div. table
Circuit Diagrams and PWB Layouts Q552.2L LA 10. EN 102

Analogue externals B

Analogue externals B
B04B B04B
YPBPR SPDIF out
RES
1E07
2 FE54 EU IE71 3E87 FE72 RES
9E29 AV3-Y IE15 MTJ-032-68B-46-NI-FE
5E06 FE59 1
1E08-1 18R SPDIF-OUT
* 1

CDS4C12GTA
MSP-8033SH-05-NI-FE-RF-PBT-BRF YPBPR1-SYNCIN1

CDS4C12GTA
30R 2

2E27

1E43

RES 6E40
100p

12V
YELLOW

RES 2E22

RES 1E44

6E46
RES

12V
10p
4E20
AP 9E04 3E88 IE73
** AV2-CVBS FE41
RES 27R

GND_A
MTJ-032-21B-45 NI FE (PBT) FE51 EU IE74 3E89 IE75
9E57 AV3-PB
2

CDS4C12GTA
1E03 18R
YPBPR1-PB

2E67

RES 6E51
100p

1E28
** 4E21 1

12V
RES

GND_A
FE48 EU 9E58 IE76 3E90 IE77
MTJ-032-21B-42 NI FE AV3-PR
2
1E04 18R

CDS4C12GTA
YPBPR1-PR
2E68

RES 6E52
100p

1E39

12V
** 4E22
RES FE42

GND_A
Provision for
YPBPR AUDIO Dreamcatcher
+3V3
MSP-8033SH-05-NI-FE-RF-PBT-BRF
6 3E97 RES
AUDIO-IN3-R
1E32
CDS4C12GTA

1E08-3 5 FE50 1K0 IE31


* AV3-Y 9E15 RES 1
2E39

1E29

RES 6E06

2E72
100p

AV1-CVBS 9E16 RES 2


12V
1n0

RED
** 4E23 3
RES FE43 4
AV3-PR 9E19 RES 5
RXD1-MIPS 9E12 RES 6
GND_A FE49 IE29 7
4 3E96
AUDIO-IN3-L 8
AV3-PB 9E17 RES 9
CDS4C12GTA

1E08-2 1K0
*
MSP-8033SH-05-NI-FE-RF-PBT-BRF 3 TXD1-MIPS 9E14 RES 10
2E40

1E42

2E71
100p
RES 6E38

11
12V
1n0

RES
4E24 WHITE 12
**
AUDIO-IN3-R 9E11 RES 13
AV1-B 9E18 RES 14
GND_A 15
16
AUDIO-IN3-L 9E13 RES 17
AV1-G 9E20 RES 18
19
VGA ( OR DVI ) AUDIO 20
21
AV1-R 9E22 RES 22
1E09 23
MSJ-035-69A-B-RF-PBT-BRF IE09 24
FE02 3E21
2 AUDIO-IN4-L 25
3 AV1-STATUS 9E24 RES 26
CDS4C12GTA

1K0
1 AUDIO-IN1-R 9E25 RES 27
V_NOM
2E36

1E37

RES 6E19

2E35

100p

AV1-BLK 9E26 RES 28


12V
1n0

29
AUDIO-IN1-L 9E28 RES 30
32 31

DF50-30DP
FE01

FE03 3E20 IE10


AUDIO-IN4-R
CDS4C12GTA

1K0
V_NOM
2E37

1E38

RES 6E20

2E38

100p
12V
1n0

+3V3
3E9C

1R0

1E10
3150-831-030-H1
2
VCC
FE44
1 SPDIF-OPT
VIN
3
GND
CDS4C12GTA

MT
V_NOM

7 6 5 4
2E73

RES 2E77

1E80

RES 6E53
100n

100p

12V

* SOC Cinch V 3P 1L3 YEWHRDY at 1E08 for Brazil

** Provision for ESD 3 2011-03-09

SPB SSB TV550 2 2010-12-23

3139 123 6521


2K11 4DDR BR SD

19110_039_110415.eps
110415

2011-Jul-15 back to
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Circuit Diagrams and PWB Layouts Q552.2L LA 10. EN 103

Ethernet & Service

Ethernet & Service


B04C TXD1-MIPS 7
3E53-2

47R
3E53-3
2

IE50
IE49
1
3E53-1

47R
3E53-4
8

FE57
FE56

2
1E06
UART
B04C
RXD1-MIPS 6 3 4 5 3
1 SERVICE

BZX384-C5V1
5E08 IE07 47R 47R
+3V3 CONNECTOR

BZX384-C5V1
+3V3-ET-ANA

6E43

6E44

1E85

1E86
MSJ-035-69A-B-RF-PBT-BRF
30R
FE58

2E62

2E63

2E66
100n

100n
10u
+3V3-ET-ANA +3V3
+3V3
PROVISION FOR iTV
IE32 IE38 IE06

3E30 IE33
10K
10K
10K
10K

10K

2E52

2E53

2E48
100n

100n

2E49

10u
4n7
1M0
1E70 RES
NX3225GA 1E71
1
TXD 2
3E81
3E82
3E66
3E67

3E33

25M RXD 3

2E54
10p 5 4

10p
7E10-1
+3V3

27

12
LAN8710A-EZK
RES
RES
RES
RES

1
2E55 CR 1A 2A IO 502382-0370
VDD
CLKIN
5
1
4 XTAL 31 ETH-RXP

BAS316
2 P

6E48
RES
RES 2E70 10p RX 30 ETH-RXN provision for iTV
IE26 N
RESET-ETHERNETn 19
RST
29 ETH-TXP
P
ETH-RXD(0) 11 TX 28 ETH-TXN
0 N
ETH-RXD(1) 10 MODE
1
ETH-RXD(2) 9 20 ETH-TXCLK
RMIISEL TXCLK
ETH-RXD(3) 8
PHYAD2

2E69

100n
RES
3E69 10K 26 ETH-RXDV
RXD<0:3> RXDV
3E70 RES
IE63
ETH-COL RES 10K 15 13 ETH-RXER
COL RXER
RES 3E71 10K 3E64 10K RES
CRS_DV RXD4 +3V3
RES 3E80 10K +3V3 7E11-1
MODE2 0 IE64 RES

14

3E9D

3E9E
RES
RES
PHYAD 7 74HC4066PW

10K

10K
1 ETH-RXCLK
ETH-TXEN 21 3E65 10K 1
TXEN RXCLK +3V3 1
RXD-UP 2
RES 1
ETH-TXD(0) 22 3 ETH-REGOFF 13
0 REGOFF X1
ETH-TXD(1) 23 10K 3E34 3E68 10K
1 1 +3V3
LED 2

7
ETH-TXD(2) 24 RES ETH-INTSEL RES RES
2 TXD 2
ETH-TXD(3) 25 10K 3E72 3E35 10K +3V3 7E12 7E13
3 INTSEL
ETH-TXER 18 RES RES PDTC144EU PDTC144EU
4
14 9E42 ETH-CRS 7E11-2
INT CRS

14
74HC4066PW AV2-BLK
TXER
32 4
RBIAS 1
ETH-MDC 17 IE39 RXD1-MIPS 3 1

1%
MDC

3E40

12K1
ETH-MDIO 16 5
MDIO X1

7
3E51 1K5 +3V3 VSS
33

7E10-2 RES
LAN8710A-EZK 7E11-3

14
74HC4066PW
34 40 8
1
35 41 TXD-UP 9
VIA VIA 1
36 42 6
X1
VIA

7
37
38
39

RES
7E11-4

14
74HC4066PW
11
1
TXD1-MIPS 10
1
12
X1

7
+3V3-ET-ANA +3V3-ET-ANA

CONFIGURATION RESISTOR SETTINGS


1%

1%

1%

1%
49R9

49R9

49R9

49R9
3E22

3E25

3E95

3E99

3E26

3E98
22R

22R

Resistor POP EMPTY

ETHERNET CONNECTOR
1E87 1N00
FE27 3 ACM2012 2
ETH-TXP 1 3E64 (RES) PHYADD(0) = 1 PHYADD(0) = 0
FE60
4 1 2
ETH-TXN FE28
3
FE30
1E88 4 3E65 (RES) PHYADD(1) = 1 PHYADD(1) = 0
3 ACM2012 2 5
ETH-RXP FE29 FE61
6
4 1 7 3E66 (RES) PHYADD(2) = 1 PHYADD(2) = 0
ETH-RXN FE31
8
9 11
CDA5C16GTH

CDA5C16GTH

CDA5C16GTH

CDA5C16GTH
8

10 12 3E67 (RES) RMII mode selected MII mode selected


6E47-1

6E47-2

6E47-3

6E47-4
5E01

5E02

5E03

5E04

RES

2E60
RES
RES

RES
16V

16V

16V

16V
RES 27n

RES 27n

RES 27n

RES 27n

22n

FE34 5450-323-183-H3
3E68 (RES) Internal 1.2V reg. disabled Internal 1.2V reg. enabled
1

4
2E05

2E07

2E08

2E09
RES 15p

RES 15p

RES 15p

RES 15p

3E69 (RES) MODE(0) = 0 MODE(0) = 1

3E70 (RES) MODE(1) = 0 MODE(1) = 1


2E56

2E57

2E58

2E59
15p

15p

15p

15p
0 ohm

0 ohm

0 ohm

0 ohm
3E27

3E28

3E29

3E39

3E71 (RES) MODE(2) = 0 MODE(2) = 1


RES

RES

RES
RES
RES
RES

RES

RES

FE32

3E72 INTERRUPT FUNCTION INTERRUPT FUNCTION


ETH-INTSEL
DISABLED ON ENABLED ON
ETH-REGOFF
FE33 nINT/TXER/TXD4 SIGNAL nINT/TXER/TXD4 SIGNAL

3 2011-03-09

SPB SSB TV550 2 2010-12-23

3139 123 6521


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Circuit Diagrams and PWB Layouts Q552.2L LA 10. EN 104

HDMI

HDMI
B04D I2C Address B04D
5EC0 FEC0 FEC3 MICOM-VCC33

30R
SII9187B = 0xB2
HDMI CONNECTOR 3 +3V3

2ECV
2EC0

2EC2
RES 2EC1

100n

10K
10u

1u0
220u 16V
1P04 3ECH

1 ARX2+
2 FECB
3 ARX2-
4 ARX1+
5 RES
ARX1- AIN-5V FEC7 5EC3 +3V3
6
7 ARX0+ +3V3-HDMI
8 30R

RES 2ECW
2EC6

2EC7

2EC8

2EC3
100n

100n

100n

100n
10u
9 ARX0-
10 ARXC+

6
3EC1-3
11
ARXC-

47K
12
13 PCEC-HDMI
7EC1

3
14

27
64

37

38
FEC1 SII9187B

9
15 ARX-DDC-SCL ARX-DDC-SCL

MICOM_VCC33

SBVCC33
FEC2 ARX-DDC-SDA ARX-DDC-SDA VCC33
16
17 ARX-HOTPLUG +5V-EDID
FEC4

1
1 8 31

3EC1-1
18 AIN-5V 3ECM-4 IE42 (CBUS) HPD0

6
19 FEC5 ARX-HOTPLUG 4 5 3ECN-1 100K 32

47K

3ECP-1

3ECP-3
AIN-5V R0PWR5V
FEC6 21

10K

10K
20 10R
23 22 ARX-DDC-SDA 1u0 2ECM 29

8
DSDA0
ARX-DDC-SCL 30 49

3
DSCL0 R4PWR5V

ARXC- 65 48
N DSCL4 VGA-SCL-EDID-HDMI
ARXC+ 66 R0XC 47 VGA-SDA-EDID-HDMI
AIN-5V P DSDA4
HDMI CONNECTOR 2
1P03 ARX0- 67 51 9EC2 CEC-HDMI
N CEC_D
BRX2+ ARX0+ 68 R0X0 RES
1 P
2
BRX2- ARX1- 69
3 N
BRX1+ ARX1+ 70 R0X1
4 P
5
BRX1- ARX2- 71
6 BIN-5V N
BRX0+ ARX2+ 72 R0X2
7 P
BRX-HOTPLUG 57 HDMIA-RX2-
8 N
BRX0- 2 7 35 TX2 56 HDMIA-RX2+
9 3ECM-3 IE43 (CBUS) HPD1 P
BRXC+ 3 6 3ECN-2 100K 36
10 BIN-5V R1PWR5V
2

59 HDMIA-RX1-
3ECA-2

11 10R N
BRXC- BRX-DDC-SDA 1u0 2ECN 33 TX1 58 HDMIA-RX1+
12 DSDA1 P
47K

PCEC-HDMI BRX-DDC-SCL 34
13 DSCL1
61 HDMIA-RX0-
7

14 N
FECC BRX-DDC-SCL BRX-DDC-SCL BRXC- 1 TX0 60 HDMIA-RX0+
15 N P
FECD BRX-DDC-SDA BRX-DDC-SDA BRXC+ 2 R1XC
16 P
63 HDMIA-RXC-
17 N
8

FECE BRX0- 3 TXC 62 HDMIA-RXC+


3ECA-1

18 BIN-5V N P
19 FECF BRX-HOTPLUG BRX0+ 4 R1X0
P
47K

FECG 21 3ECJ RES RES


20 MICOM-VCC33
3ECK
23 22 BRX1- 5 55 4K7
1

N TPWR_CI2CA
BRX1+ 6 R1X1 IE12
P 4K7
FECR
BRX2- 7 50 9EC3 PCEC-HDMI
N CEC_A
BRX2+ 8 R1X2 RES
BIN-5V P
CRX-HOTPLUG FECY 3ECL RES
3 6 41 52 +3V3
3ECM-2 IE44 (CBUS) HPD2 INT
HDMI CONNECTOR 1 CIN-5V
2 7 3ECN-3 100K 42
R2PWR5V 4K7
1P02
10R
CRX2+ CRX-DDC-SDA 1u0 2ECP 39
1 DSDA2
CRX-DDC-SCL 40
2 DSCL2
3 CRX2-
CRX1+ CRXC- 11
4 N
CRXC+ 12 R2XC 54 SCL-SSB
5 P CSCL
CRX1- 53 3EC3 100R SDA-SSB
6 CIN-5V CSDA
CRX0+ CRX0- 13 3EC5 100R
7 N
CRX0+ 14 R2X0
8 P
CRX0- 10
9

RES 2ECX

RES 2ECY
15 RSVDL 28

10p

10p
10 CRXC+ CRX1- N
4

CRX1+ 16 R2X1
3ECA-4

11 P
12 CRXC-
47K

FECJ PCEC-HDMI CRX2- 17


13 N
FECA ARC-eHDMI+ CRX2+ 18 R2X2
5

14 P
FECK CRX-DDC-SCL CRX-DDC-SCL DRX-HOTPLUG
15
FECL CRX-DDC-SDA CRX-DDC-SDA 4 5 45
16 3ECM-1 IE45 (CBUS) HPD3
1 8 3ECN-4 100K 46 74
17 DIN-5V R3PWR5V
6

FECM CIN-5V 75
3ECA-3

18 10R
FECN CRX-HOTPLUG DRX-DDC-SDA 1u0 2ECQ 43 76
19 DSDA3
47K

21 20 DRX-DDC-SCL 44 77
FECP DSCL3
23 22 78
3

3E23 +3V3-STANDBY 5EC2


eHDMI+ DRXC- 19 79
N
DRXC+ 20 R3XC 80
RES 22K 30R P
7E02 81
RES
BC847BW ARC-eHDMI+ DRX0- 21 VIA 82
CIN-5V N
DRX0+ 22 R3X0 83
P
84
2ECC

23 85
10p
DRX1- N
7EC0 DRX1+ 24 R3X1 86
P
BC847BW IEC6 87
3ECD
PCEC-HDMI 9EC0 CEC-HDMI DRX2- 25 88
N
IEC4 DRX2+ 26 R3X2 89
100R IEC5 P

EPAD

73
IEC7

FECW
22K

3ECE +3V3-STANDBY

6EC1
7EC1 3ECN 3ECF
+5V +5V-VGA

BAT54 NON-INSTAPORT 9187B 4X 100K 100K BLOCKBUSTER


IE11
INSTAPORT 9287B 4X 100K 100K SUNDANCE
IE65 3ECU-2 +3V3
2 7
4R7

DDCA-SDA
3ECG
10K
IE66 4 3ECU-4 5
3ECF 2ECU DDCA-SCL
FECZ
10K
100K 1u0
3 2011-03-09

SPB SSB TV550 2 2010-12-23

3139 123 6521


+5V-EDID 2K11 4DDR BR SD

19110_041_110415.eps
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2011-Jul-15 back to
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Circuit Diagrams and PWB Layouts Q552.2L LA 10. EN 105

Headphone

Headphone
B04E B04E

+3V3-STANDBY

4
PUMD12
5 7EE0-2
A-PLOP
3

6 A-STBY
FEE0
RESET-AUDIO 2 7EE0-1
PUMD12
1

2EE0

47p
3EE1-1
1 8

6
3EE1-2
22K

3EE1-3
22K

22K
3EE1-4
4 5

3
22K
2EE5

47p +3V3

2EE1

100n
7EE1
TPA6111A2DGN
3EE2-3
3 6

8
IEE0 IEE3
Φ VDD
2EE6
33R
FE36
ADAC(3)
2EE3 IEE1
8
3EE0-1
1 2 AMPLIFIER 1
IEE7
4
3EE2-4
5 AMP1
1 1
IEE2 1u0 2EE4 10K 3EE0-4 IN- 4V 100u 33R
ADAC(4) 5 4 6
2 VO
1u0 10K IEE4 2EE7 IEE8 3EE2-2 FE35
5 7 2 7 AMP2
SHUTDOWN 2
2EE2 IEE6
IEE5 4V 100u 33R
3 10
BYPASS 3EE2-1
VIA 11 1 8
1u0
GND GND_HS
33R
4

A-PLOP 3 3EE0-3 6
10K
3EE3
RES

22K

3 2011-03-09

SPB SSB TV550 2 2010-12-23

3139 123 6521


2K11 4DDR BR SD

19110_042_110415.eps
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Circuit Diagrams and PWB Layouts Q552.2L LA 10. EN 106

10-5 B05 313912365213


DDR

DDR
B05A +1V8 DDR2-VREF-DDR +1V8 DDR2-VREF-DDR
B05A

2B08
100p

100n
2B36
2B40

2B00

2B01

2B02

2B03

2B04

2B05

2B06

2B07
100n

100n

100n

100n

100n

100n

100n

100n
47u

2B17

2B37
100n

100p
2B41

2B09

2B10

2B11

2B12

2B13

2B14

2B15

2B16
100n

100n

100n

100n

100n

100n

100n

100n
47u
7B02

H9

C1
C3
C7
C9
A1
E9

E1

A9

E2
L1
EDE1108AGBG-1J-F 7B03

H9

C1
C3
C7
C9
A1
E9

E1

A9

E2
L1
VDDL VREF EDE1108AGBG-1J-F
VDD VDDQ
DDR2-A0 H8 VDDL VREF
AT T-POINT DDR2-A1 H3
0
Φ DDR2-A0 H8
VDD VDDQ

3B22
DDR2-A2 H7
1
2 SDRAM 0
C8 2
3B00-2
7 DDR2-D16 DDR2-A1 H3
0
1 Φ 3B04-2
J2 C2 3 6 3B02-3 33R H7 C8 2 7
DDR2-CLK_P DDR2-A3 3 1 DDR2-D17 DDR2-A2 2 SDRAM 0 DDR2-D24
240R DDR2-A4 J8 D7 33R 3 6 3B00-3 DDR2-D18 DDR2-A3 J2 3B05-3
C2 3 6 33R DDR2-D25
4 2 3 1
DDR2-CLK_N DDR2-A5 J3 D3 1 8 3B02-1 33R DDR2-D19 DDR2-A4 J8 D7
3B04-3 3 6 33R DDR2-D26
5 3 4 2
DDR2-A6 J7 DQ D1 33R 2
3B02-2 7 DDR2-D20 DDR2-A5 J3 D3 33R 33R 2 7 3B05-2 DDR2-D27
3B27 6 A 4 5 3
DDR2-CLK_P DDR2-A7 K2 D93B00-4 4 5 33R DDR2-D21 DDR2-A6 J7 DQ D1 1 8 3B05-1 DDR2-D28
7 5 6 A 4
DDR2-A8 K8 B1 33R
3B02-4 4 5 DDR2-D22 DDR2-A7 K2 D93B04-4 4 5 33R DDR2-D29
240R 8 6 7 5
DDR2-CLK_N DDR2-A9 K3 B9 3B00-11 8 33R DDR2-D23 DDR2-A8 K8 B1 33R 4 5 3B05-4 DDR2-D30
9 7 8 6
DDR2-A10 H2 33R DDR2-A9 K3 B93B04-1 1 8 33R DDR2-D31
3B28 10 9 7
DDR2-CLK_P DDR2-A11 K7 DDR2-A10 H2 33R
11 10
DDR2-A12 L2 B7 3B12 DDR2-DQS2_P DDR2-A11 K7
240R 12 11
DDR2-CLK_N DDR2-A13 L8 DQS A8 3B13 33R DDR2-DQS2_N DDR2-A12 L2 B7 3B14 DDR2-DQS3_P
13 12
2B44 DDR2-A13 L8 DQS A8 3B15 33R DDR2-DQS3_N
33R 13
DDR2-BA0 G2 RES 2p2 2B45 RES
0 33R
DDR2-BA1 G3 A2 DDR2-BA0 G2 2p2
1 BA NU|RDQS 0
DDR2-BA2 G1 DDR2-BA1 G3 A2
2 1 BA NU|RDQS
DDR2-ODT DDR2-BA2 G1
2
3B01 RES F9 DDR2-ODT
ODT
DDR2-CLK_P 240R E8 3B03 RES F9
ODT
DDR2-CLK_N F8 CK DDR2-CLK_P 240R E8
DDR2-CKE F2 DDR2-CLK_N F8 CK
CKE
DDR2-CS G8 DDR2-CKE F2
CS CKE
DDR2-RAS F7 L3 DDR2-A14 DDR2-CS G8
RAS CS
DDR2-CAS G7 NC L7 DDR2-RAS F7 L3 DDR2-A14
CAS RAS
DDR2-WE F3 DDR2-CAS G7 NC L7
WE CAS
DDR2-DQM2 3B23 B3 DDR2-WE F3
DM|RDQS WE
DDR2-DQM3 3B24 B3
33R VSS VSSQ DM|RDQS
VSSDL 33R VSS VSSQ

A3
E3
J1
K9

E7

A7
B2
B8
D2
D8
VSSDL

A3
E3
J1
K9

E7

A7
B2
B8
D2
D8
+1V8
+1V8

DDR2-VREF-DDR
DDR2-VREF-DDR

2B26

2B38
100n

100p
2B42

2B18

2B19

2B20

2B21

2B22

2B23

2B24

2B25
100n

100n

100n

100n

100n

100n

100n

100n

2B39
47u

2B35

100p
100n
2B43

2B27

2B28

2B29

2B30

2B31

2B32

2B33

2B34
100n

100n

100n

100n

100n

100n

100n

100n
47u
7B00
H9

C1
C3
C7
C9
A1
E9

E1

A9

E2
L1

EDE1108AGBG-1J-F 7B01

H9

C1
C3
C7
C9
A1
E9

E1

A9

E2
L1
VDDL VREF EDE1108AGBG-1J-F
VDD VDDQ
DDR2-A0 H8 VDDL VREF
Φ
0 VDD VDDQ
DDR2-A1 H3 DDR2-A0 H8
DDR2-A2 H7
J2
1
2 SDRAM 0
C8
C23B08-4 4 5
2
3B07-2
7
33R
DDR2-D0 DDR2-A1 H3
H7
0
1 Φ C8 2 3B10-2 7
DDR2-A3
3 1
33R
DDR2-D1 DDR2-A2
2 SDRAM 0
DDR2-D8
DDR2-A4 J8 D7 3 6 3B07-3 DDR2-D3 DDR2-A3 J2 C2
3B11-3 3 6 33R DDR2-D14
4 2 3 1
DDR2-A5 J3 D3 3B08-2 2 7 33R DDR2-D2 DDR2-A4 J8 3B10-3 33R 3
D7 6 33R DDR2-D10
5 3 4 2
DDR2-A6 J7 DQ D1 33R 1 8 3B08-1 DDR2-D4 DDR2-A5 J3 D3 2 7 3B11-2 DDR2-D11
6 A 4 5 3
DDR2-A7 K2 D9 3B07-4 4 5 33R DDR2-D5 DDR2-A6 J7 DQ D1 1 8 33R DDR2-D12
7 5 6 A 4
DDR2-A8 K8 B1 33R 3 6 3B08-3 DDR2-D6 DDR2-A7 K2 D93B10-4 4 5 3B11-1 33R DDR2-D13
8 6 7 5
DDR2-A9 K3 B9 3B07-1 1 8 33R DDR2-D7 DDR2-A8 K8 B1 33R 4 5 3B11-4 DDR2-D9
9 7 8 6
DDR2-A10 H2 33R DDR2-A9 K3 B9 3B10-1 1 8 33R DDR2-D15
10 9 7
DDR2-A11 K7 DDR2-A10 H2 33R
11 10
DDR2-A12 L2 B7 3B16 DDR2-DQS0_P DDR2-A11 K7
12 11
DDR2-A13 L8 DQS A8 3B17 33R DDR2-DQS0_N DDR2-A12 L2 B7 3B18 DDR2-DQS1_P
13 12
2B46 RES DDR2-A13 L8 DQS A8 3B19 33R DDR2-DQS1_N
33R 13
DDR2-BA0 G2 2p2 2B47 RES 33R
0
DDR2-BA1 G3 A2 DDR2-BA0 G2 2p2
1 BA NU|RDQS 0
DDR2-BA2 G1 DDR2-BA1 G3 A2
2 1 BA NU|RDQS
DDR2-ODT DDR2-BA2 G1
+1V8 2
3B06 RES F9 DDR2-ODT
ODT
DDR2-CLK_P 240R E8 3B09 RES F9
ODT
DDR2-CLK_N F8 CK DDR2-CLK_P 240R E8
DDR2-CKE F2 DDR2-CLK_N F8 CK
CKE
DDR2-CS G8 DDR2-CKE F2
CS CKE
180R 1%

DDR2-RAS F7 L3 DDR2-A14 DDR2-CS G8


RAS CS
DDR2-CAS G7 NC L7 DDR2-RAS F7 L3 DDR2-A14
3B20

CAS RAS
DDR2-WE F3 DDR2-CAS G7 NC L7
WE CAS
DDR2-DQM0 3B25 B3 DDR2-WE F3
DM|RDQS WE
DDR2-DQM1 3B26 B3
FB00 33R VSS VSSQ DM|RDQS
VSSDL
DDR2-VREF-DDR 33R VSS VSSQ
A3
E3
J1
K9

E7

A7
B2
B8
D2
D8

VSSDL

A3
E3
J1
K9

E7

A7
B2
B8
D2
D8
180R 1%
3B21

1X20 1X21 1X22 1X23 1X24


HOOK1 HOOK1 HOOK1 HOOK1 HOOK1

3 2011-03-09

SPB SSB TV550 2 2010-12-23

3139 123 6521


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Circuit Diagrams and PWB Layouts Q552.2L LA 10. EN 107

10-6 B06 313912365213


Display interfacing-Vdisp

Display interfacing-Vdisp
B06A B06A

1G03

T 3.0A 32V

5G01 1G00 FG0H


+VDISP-INT +VDISP
30R T 3.0A 32V

2G43

100n
RES RES
5G02

30R
RES

2G44

RES
22u
RES IG11 RES
3G28 6G00
2K2 LTST-C190KGKT
For Development use only

3 2010-03-09
2 2010-12-23
SPB SSB TV550
3139 123 6521
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Circuit Diagrams and PWB Layouts Q552.2L LA 10. EN 108

Video out - LVDS

Video out - LVDS


B06B B06B

+3V3

10K

10K

10K
+VDISP

47p

47p

47p

47p

47p

47p

47p

47p

47p

47p
RES

2G7A
2G77

2G75

2G76

2G78

2G79

2G24

2G25

2G26

2G27
RES 3G33

RES 3G34

RES 3G35
FI-RE51S-HF

5
6
7
8
9G0K-4
9G0K-3
9G0K-2
9G0K-1
60 61
58 59
56 57
54 55
4
3
2
1 CTRL-DISP RES 3G32 100R FG34 52 53
2G92 100n SDA-DISP 3G2W 51
FI-RE41S-HF 100R FG2H
50
50 51 SCL-DISP 3G2Y 100R FG2G
100n 49
2G93 48 49
48
46 47 CTRL-DISP RES 3G38 100R FG35
100n FG2J 47
2G94 44 45 BACKLIGHT-BOOST RES 3G37 100R FG2R
46
42 43
100n FG2K 45
2G95 FG30 3D-LR RES 3G2Z 100R
41 44
FG31 CTRL-DISP FG04 RES 3G30 100R FG2L
40 43
FG32 CTRL-DISP RES 3G31 100R FG2M
39 42
FG33 3D-VS-DISP RES 3G36 100R
47p 38 41
2G96 PX1A- FG2E
47p 37 40
2G99 PX1A+ FG2F
47p 36 FG1Y 39
2G97 PX1B-
47p 35 38
2G98 PX1B+ FG1Z
34 FG20 37
33 PX1C- 36
PX3A- FG1C PX1C+ FG21
32 35
PX3A+ FG1D
FG1E 31 34
PX3B- PX1CLK- FG22
30 33
PX3B+ FG1F PX1CLK+ FG23
29 32
PX3C- FG1G
28 31
PX3C+ FG1H PX1D- FG24
27 30
PX1D+ FG25
FG11 26 29
PX3CLK- 25 PX1E- FG26 28
PX3CLK+ FG1J PX1E+ FG27
24 10p 27
2G28
FG1K 23 2G29 10p 26
PX3D- 22 25
PX3D+ FG1L PX2A- FG28
21 24
PX3E- FG1M PX2A+ FG29
20 23
PX3E+ FG1N PX2B- FG2A
19 22
PX2B+ FG2B
18 21
PX2C- FG2C
17 20
PX4A- FG12 PX2C+ FG2D
16 19
PX4A+ FG13 15 18
PX4B- FG14 PX2CLK- FG1R
14 17
PX4B+ FG15 13 PX2CLK+ FG1S 16
PX4C- FG16 12 15
PX4C+ FG17 PX2D- FG1T
11 14
PX2D+ FG1U
FG18 10 13
PX4CLK- PX2E- FG1W
9 12
PX4CLK+ FG19 PX2E+ FG1V
8 11
7 10
PX4D- FG1A
6 FG2P 9
PX4D+ FG1B
5 8
PX4E- FG1Q
4 7

2G91

100n
PX4E+ FG1P
3 6
+VDISP RES 9G0G FG2N
2 5
1 4
3
1G50
2
1

TO DISPLAY 1G51

TO DISPLAY

1X05
REF EMC HOLE

3 2011-03-09

SPB SSB TV550 2 2010-12-23

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AmbiLight CPLD

AmbiLight CPLD
B06C B06C
5GA0 FGA0
+3V3 VINT
30R

2GA0

2GA1

2GA2
100n

100n
1u0
DEBUG ONLY

5GA1 FGA1
+3V3 VIO
+3V3
30R
2GA3

2GA5

100n
1u0

RES
1G37

3GA4

RES
10K
+3V3 1
2
GCK3 3GA5-4 4 5 100R RES 3
GTS1 3GA5-3 3 6 100R RES 4
GTS2 3GA5-2 2 7 100R RES 5
GSR 3GA5-1 1 8 100R RES 6

2GA6

RES
10p
VINT VIO SD51022

7GA0

15
35

26
XC9572XL-10VQG44C0100
VCCINT Φ
VCCIO AMBI-SPI-CLK-OUT-R IGA1
PXCLK54 43 AMBI-SPI-SDI-OUT_G1-R CPLED2
IXO1_43|GCK1
GCK2 44 AMBI-SPI-SDO-OUT-R
IXO1_44|GCK2
GCK3 1 IGA2
IXO1_1|GCK3
CPLED3
2 5 PNX-SPI-CSBn
IXO1_2 IXO3_5
PNX-SPI-CS-BLn 3 6 9GA1 RES BACKLIGHT-PWM IGA3
IXO1_3 IXO3_6
PNX-SPI-SDO 39 7 3D-LR GCK2
IXO1_39 IXO3_7
PNX-SPI-SDI 3GA3 33R 40 8 3D-VS-DISP +3V3
IXO1_40 IXO3_8
PNX-SPI-CLK 41 IXO3_12 12 BL-SPI-SDO
IXO1_41
42 13 BL-SPI-SDI 3
IXO1_42 IXO3_13
14 BL-SPI-CSn RES
IXO3_14
GTS1 36 16 3GA1 RES BACKLIGHT-PWM_BL-VS GCK3 5 7GA1-2
IXO2_36|GTS1 IXO3_16
GTS2 34 18 47R BL-SPI-CLK BC847BS(COL)
IXO2_34|GTS2 IXO3_18
GSR 33 4
IXO2_33|GSR
AMBI-SPI-CS-OUTn_R2-R 19 4 5 AMBI-PROG_B1 +3V3
IXO4_19
AMBI-PWM-CLK_B2 29 20 3G10-4 33R 3 6 AMBI-BLANK_R1
IXO2_29 IXO4_20
AMBI-SPI-CS-OUTn_R2 8 1 3G14 33R 30 21 2 7 3G10-3 33R AMBI-SPI-CS-EXTLAMPSn 6
IXO2_30 IXO4_21
AMBI-LATCH1_G2 3G11-1 33R 6 3 31 22 3G10-2 33R AMBI-SPI-CLK-OUT RES
IXO2_31 IXO4_22
AMBI-TEMP 3G11-3 33R 32 23 3G13 33R AMBI-SPI-SDI-OUT_G1 GTS1 2 7GA1-1
IXO2_32 IXO4_23 BC847BS(COL)
CPLED3 37 27 3G12 10R 1 8 AMBI-SPI-SDO-OUT
IXO2_37 IXO4_27
CPLED2 38 28 4 5 3G10-1 33R AMBI-LATCH2_DIS 1
IXO2_38 IXO4_28
3G11-4 33R +3V3
11
TCK
9 3
TDI
2G10

2G11

2G12

2G13

2G14

2G15

2G16

2G17

2G18

2G19
24
10K

10p

10p

10p

10p

10p

10p

10p

10p

10p

10p
TDO RES
3G15 10 GTS2 5 7GA2-2
TMS
BC847BS(COL)
GND 4
+3V3
4
17
25

+3V3

6
RES
GSR 2 7GA2-1
BC847BS(COL)
1

7 330R 2

8 330R 1

5 330R 4

6 330R 3
DEBUG ONLY

3GA6-2

3GA6-1

3GA6-4

3GA6-3
RES

RES

RES

RES
RES RES
1G35 1G36
1 RES 3GA2-1 1 8 100R 1 FGA6
2 RES 3GA2-2 2 7 100R 2 FGA4

LTST-C190KGKT

LTST-C190KGKT

LTST-C190KGKT

LTST-C190KGKT
3 RES 3GA2-3 3 6 100R 3 FGA5
4 RES 3GA2-4 4 5 100R 4 FGA3
5 5 FGA2
6 6

6GA0

6GA1

6GA2

6GA3
RES

RES

RES

RES
+3V3
7 8
100n RES

SD51022
2GA4

BACKLIGHT-PWM 9GA0 BACKLIGHT-PWM_BL-VS

3 2011-03-09

SPB SSB TV550 2 2010-12-23

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SPI buffer

SPI buffer
B06D B06D

RES
+3V3
+3V3

RES

3GE2
7GE1

RES

10K
2GE0

100n
RES
PDTC114EU

RES
7GE0 PNX-SPI-CSBn

20
74LVC245A
1
3EN1
3EN2 IGE0
19
G3
3GE0-3
PNX-SPI-CLK 18 2 3 6 RES BL-SPI-CLK
1
2 47R 3GE0-1
17 3 1 8 RES BL-SPI-SDO
PNX-SPI-SDO 16 4 3GE1-3 6 3 RES 47R AMBI-SPI-CLK-OUT-R
15 5 47R 5 4 3GE1-4 AMBI-SPI-SDO-OUT-R
AMBI-SPI-SDI-OUT_G1-R 14 6 3GE3 47R RES PNX-SPI-SDI
BL-SPI-SDI 13 7 3GE4 47R RES
12 8 RES
47R
11 9

10
RES
PNX-SPI-CLK 8 9GE0-1 1 BL-SPI-CLK

RES
PNX-SPI-SDO 7 9GE0-2 2 BL-SPI-SDO

BL-SPI-SDI RES 9GE1 PNX-SPI-SDI

RES 9GE2
RES *
5 9GE0-4
PNX-SPI-CS-BLn IGE1
** 4 BL-SPI-CSn

Buffer
*
Direct
**

3 2011-03-09

SPB SSB TV550 2 2010-12-23

3139 123 6521


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10-7 B09 313912365213


Connectors comp

Connectors comp
B09A B09A
5C55 FC67 +3V3

30R
1M59
FC70
AMBI-SPI-CLK-OUT 1

3C74

100K
RES
2
AMBI-SPI-SDO-OUT FC71 3
AMBI-SPI-SDI-OUT_G1 FC72 4
2C76
V-AMBI 5
AMBI-PWM-CLK_B2 FC73 6 FC87 3C75 100p
7 LIGHT-SENSOR
AMBI-SPI-CS-OUTn_R2 FC74 8
2C93 100R 2C77
AMBI-LATCH1_G2 FC75 9
10
TO
V-AMBI 47n RES 3C76 100p
AMBI-BLANK_R1 FC77 11 RC LED PANEL**
AMBI-PROG_B1 FC76

BZX384-C5V6
12 IC73 100R 2C78

6C02
AMBI-LATCH2_DIS FC78 13 1M19

RES
FC88
AMBI-TEMP 3C70 100R FC79 14 IC74 3C77 100p 1
15 LED-2 FC89
2
16 FC90
FC81 100R 3
17 FC91
4
2C70

100n
18 +3V3-STANDBY FC92
5
19 2C79 FC93
GND_AL 6
20 FC94
7
* FC82
21
22 LED-1
IC75 3C78 100p +5V 8
FC83 1C86
AMBI-POWER 23
+24V 100R 2C80

2C81

100n
24
T 2.0A 63V
25
100p
26 FC95 3C79
* 1C87

2C94

2C95

RES
100n

100n
27 28 KEYBOARD

RES
FC84 10R

6C03 RES
100p

BZX384-C5V6

BZX384-C5V6
+12V_AL 2C96
T 2.0A 63V FH34SRJ-26S-0.5SH(50)
2C82

6C05
100n
RES

GND_AL GND_AL

RES 3C96 **
+3V3-STANDBY
Option table for Ambilight
* +T 0R3
1
1M20

ITEMS BLOCKBUSTER EMMY SUNDANCE 1 9C02-1 8 2


/ INFINITY 2 9C02-2 7 3
3 9C02-3 6 4
4 9C02-4 5 5
1C86 N Y N 6
3C97
+5V 7
1C87 N N Y 8
+T 0R3
SCL-SET 9C00 3C94 47R FC65 9
RES 10
RES
SDA-SET 9C01 3C95 47R FC66 11
+3V3 * RES 3C90
10K * iTV
RES
RES
12

FC61
FAN-CTRL1 * RES 3C91
100R
FH52-11S-0.5SH

FC62

2C87 RES
RES 3C80

2C86 RES
TACH01
100R RES

2C90

2C91
1M71

10p

10p

1u0

1u0
FC85 RES3C81 100R FC96
SCL-BL 1

**
**
FC63 RES 3C82 FC97 2
TACH02 FC98
3
100R 4
FC86 RES 3C83
RES 2C83

RES 2C84
100p

100p

SDA-BL 2041145-4
100R
FC64 TEMPERATURE
FAN-CTRL2 * RES 3C92 SENSOR
100R Option table for Leading Edge
+3V3 * RES 3C93 **
10K Items BlockBuster / Emmy Sundance / Infinity
FAN-DRV FC99
1M19 Yes No
RES 5C54
RES 2C85

1u0

+3V3
30R
1M20 No Yes
T 1.0A 63V
RES
1C85

RES 5C53
+12V IC78 RESERVED 3 2011-03-09
30R
SPB SSB TV550 2 2010-12-23

3139 123 6521


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10-8 313912365213 SSB Layout


Overview top side

1M95 1M99 1F24 1M71 1M59

2C84

3C83
1C85

1C86
1C87
3U81
4U01

4U00

2U58

2U53

3U64

3U65

2U44

3U43

2U45

2U46

2U49

3U45

3U76

2U48

2U72

3U84

2U51

3U67

2U52

3U66

2U50

2U43

3U44

3U56

2U56
3U71 2U54 2U68 2U47

2C85

3G13

2G16

3G12

3G14
3C82

3C92

3C81

5C55
3US6
3US9
3G11

2C95

2C94
5C54

3C70

2C96
3U42
3G10

3C93

2C83

3C91

3C80
5C53

2C70
1UM0
3C90
3GA1 9GA0

5U02

5U03
2U24
2U23
2U25
2U20
IUT1

2U19

6GA1

6GA0

6GA3

6GA2
IU15
5UM1

7US2
7US3
IUS9 3US2

2U17

2U18
IUS5 3US7

IUT2

7US1
3US3
3GA6
1G37

3US4
9US0
7U01 7U04 7U02
IU23

2US3
IUS4
3US5 IUS6

IUS3
3U23
7GA0

7GA2
3GA5
7GA1
IU18

5U00
2U11 3U24

6U00
1G36

2U09

2U15
2U16
IU17 2UB2

2UB1 IGA3

5U01
3GA2

7UA3

1G50
IGA2

3B11
1G35

2UE8
IGA1

3UB0

3UB3

3UB2

2UE6
3B26

7B01

2UB3

2UB4
2UB0
3B18
7UA4 2GA4

2B47
3B19
3UB4
2UE3
3UB5 3UB1

2G98
2UE2
2G97

2S4P
2G99

7F20

3B10
2UE4
2G96

2D19

2UD6
9S90

9S91

9S92

9S93
3B08
2UE0 IUD1

7B00
3B25

5D08
IUD4

7UD1
3UD4
3B16

2B46
5UD2
3UD5
3B17

2D05
2UE1 IUD2

3B07
3UD3

2U28

3U07
2UD8

7U05
2UD9

3F11

3F08
9S00
5UD3

2UE9
3S3Y
3U06

6UD0

2D20
2U27

3F10

3F09
7S00 2UD0 IUD0

3S28

3S29

3S24
3S23
3S62

3S3Q
3B02
3S21
2UD3

7UD0
7B02 5UD1
3S3S

2UD5
2UD4
3UD2
3S1K
2S4E
2UD7
3B23
3S1J 3S1B

3S3R

3S2A
3UD1
3B12 3S3T

2B44

2S4D

3S1L

9F28
3S3N 3UD0
3B13
9F27 2UD1
3S1C

3B00
5D07
3S3L
2UD2
5UD0

3S6K
3B05
1D50

IF62
1735 1D38

2D17

2D23
2D24

3S81
2D08

3S80

3S6N
3B24
2D07

2S4F 3S52

7B03

3S3F
BS15 DS50
3B15 3S54

2B45
2S4G

3B14 3S50

1S02
3S3M
3S43

DBS8

7S00
3S44
1D52

7D10

3S3H

3S3U
9S06
3S3G

3B04

3S2M
3S00

2S2W
2S2Z
3S6H

2S33
2S30

3S42
3E17 3S3W
2S2R

1P09
3S27
IS13
2D09

2S2V
2S2Y
2S2T
2S34

2S32
2S31
3S26

7S08
2D10

2S7M

2F40

4S14
3S6J

2S7K

2S7H

2S7R
2S7E
BS10

2D06 2S77

3S4J 2S7J

2S8G
2S7U

2S7N
2S7P

2S7L

2S87
2S78

3S4L

3S4K

9S21

9S19
2S2S

3S4R
3S4P
3S4T

9S20

9S18

3S59
3S53 3S84
3S13
3S83

2S41
3S12 BS13

1F10
2D12 2D11

2S4M
5D02 5D01

IF61

2F58
3F59
7F58 3F60
9FLH 9FLC

9FLJ 9FLD

3F58
9E20

5D04 3E32 9E18

1F75

1E06 1E71
9E24

4E03

4E02
9E22
6F72 3F78
7F70 3FLE
1FL5

2F92 2F94
2F90 3F71
2FL6 2FL7

2F91
3F72
1E31
IF89
5F70
1P08
1E19

1E86
1E54
1E18
1G51

1E12

7FL5
2F9D

2G29

2G28
5D05
1E02 1E01
1E85

IF86

9F00 9F01
9F05 9F06
5F73

9FLG

9FLF
9FLL
3FL7

9FLK
3FLC
3F34

9FL3
9F04
9FLE
2F9C
2E48

2F93
3E69

3E70

3E67

3E66

3E65
3E71

9E43

9E42

3E64

2E49

3FL4

1E32

2F88
2G7A
4E04

4E05

4E01
3E87

1F51
3E88
2G79

2F9B
2E53 3E97 9E29
9E04

2G24
2E52
6E40

5F72
IE09

9F71
9E11

2E72

6E06

2G25

4E23
3E51
4E22
3E96

6E38

3F65
3F64
2E27
1E70

1P07
2G26
2E39

3G38 2E55

3FL2
2E36
2E40

3E33
9E13

2E71

7E10
2G78
3E30

3F75
2G27
6E19 IE10

2F86
2E35

2E38
2E54
2G76 3E21

1328
1E09
2F9A
2G75

3E20
1E37

2E37
2G77 IE07 3E34 3E68 2F99
3E35
1E29 1E42

1E08
1E43

1E03 1E04
2C76

6E20
3E72

3E25 3E22

2FDD
3E40

3C75 3C74 2E63


2E66

6FD3

1FD3
1E38
7EE0

2E57 2E56
6C02

3FDG
1T01
2E07
5E02 5E01 IE11
1E39

2C77 3C76 2C93


1E28

3E28
2E62

6FD2

1FD2
1M20

2E05
1M19

2FDC
2C80 3C78 IC75
1E88

1E87

3ECG

2F98
2C78 3C77
6EC1
3E27

6E47
9E15
5E08

3E98

3E26

2E60

6C03 2ECU
3ECF
6E51

3EC3
2EE6

2C82 3C79 IC74 3ECP


1F52
2E67

3EC5
4E24

6C05
4E21

1329
4E20

9E17 3E89
9E57

3ECN IE42

1P05
2C91 2C90
3EE3

3F623F63
IEE6

2C86 3C94 2EE3 IEE4


2EE4

IEE5

2ECN

7EC1
2ECP

2EE7
2F60

2EC1
2C87 2EE2
3EE0

3C95
2ECM 6FC7
2F97
6FC5

7EE1

2F81
2EE0

3ECM
3EE1

6FC3
2EE5

3FC4
2E77
2E22

2E73
5E06

2C81
6E46 6FC4
3EE2 2EE1
IEE3

3FC3
6E53 3E9C
3U68

1E44 6FC2
7U43
3U70

1E80

6FC1

3FC5
3FC7

3FC6
9FC5
9EC3 5EC2 2ECC
3U69 9U42 3U53 9FC3 9FC6
6FC6

1N00

2FC3

2FC4

2FC2

2FC1

2FC6

3FC1
2FC5
1E10
3U75 9U41 3U59 2FC7 6FC8
3FC2 9FC4
3U41

3U74

2FC8

7U42
1FC6 1FC3 1FC4 1FC2

1FC1
1E07

1P04 1P03 1P02

1FC5
1E05
2 2011-03-07

SSB Layout Top


3139 123 6521

19110_001_110307.eps
110309

2011-Jul-15 back to
div. table
Circuit Diagrams and PWB Layouts Q552.2L LA 10. EN 113

Overview bottom side

CXXX

FC81 FC96

FC67

FL38
FC78

FC82
FC71
9FL1 9FL2
FC79

FC75 FC99
FC76 FC77

2G13

2G14
FC98
FC97 IC78

2G11

2G10

2G17

2G18
FC73 FC70

2G19

2G15

2G12

3U01

3U00

CU00
FU48 FU50 FU49 FU54 FU77 FU63 FU75 FU56 FU57 FU74 FU68 FU09 FU08 FU58 FU59 FU60 FU61 IU56 FU66 FU67 FU51 FU52 FU53 FU55 FU62 FU76
FC84
FC72
3UU0

FC74
FC83 3U72 2U57

3U08

3U22

2U07

3U10

7UU2
2U03

3U09

3U18

2U08

3U19
FU07 2U06 IU03 IU55

FC64
1U40

FS2W

FS2Y
IU20
FC62 FC61 FU01 3U17
FUM0 FC63
6U40 IU04
IUU3
FUU1

IU51 7U00 IU06


3UU2

7U40
IU08

3U27
IU22 IU05
2GA2 3GE1 3GE0 IUM0
IU49
IU24 IU13 2U02 IUU0
7UU3 IUU4
IUS7 3U04 2U01
FGA5 3U14 IU07

2U22

3U05
7U03
3UU1
IU16

3GA4

2GA6
2U21 IU11 FG2J
IU12 IUU1 3UU3

IUS8
2U55 2UU0
2UU1
3U62 IU48

3U11

3U28
IU63

FU05
7GE0
2GA5

2GA3

IUU5
FUS0 3U73
IU10

7UU1
2UA4 FU72
9GE0 FGA1
FU73 FU02
IU50 IU62

5GA1
FU06

3U80
IUU2

7U41
FUD2
9GA1 3U60 IU09
FU04
IU14

2GE0
IU25 FG1P FG1Q

3U26
7UC0
FU00
9GE2 IU61 2U05

3U02
2U00
3U20 3U21

IU02
2U04

IU19
IGE1 3U63

IU01
IU52

5GA0
FG1B

3G15
FG1A

7UU0

IS17

CU03
2U10 2U29

3U29

CU02
IU57
3U82

CU04
CU01
3U03 IU21

2GA0
FGA0 IU64 FG19 FG18
3U61 CU05
FUA3
FG17 FG16

7U48
9GE1 3GE2 2GA1
7GE1 FUA4
3U83
2U13 2U12

6UD1
IUA5

3GE3
3GE4

3GA3
FG15 FG14

2B43
CUA0 IUD5

9UU1 9UU0
IU41
2UU2 FUU0

FG13

FG12
2B39
IGE0

7UD3
FGA4

FGA6
IU40

FU03
FGA2 FGA3 IS40 2U71
2B32

2U14
2UE5

2G44

2B27
FB00 2B34
FG1N

2B33

2B35
FG1M

9S95

9S94
5G01 FG1K FG1L

7UD2
5G02
FG11 FG1J
IUA6

1G00
1G03
6G00

2B29
FG1H FG1G

3S66

3S68
IF04

2B28
FC86
IUB0 IG11
IF08 FS31 3B09

FC85
2B30
3F24 FG1E FG1F

2G43

3G28
7S01
IS08 2B31

2S12
9S11
3F23

3F21

9S10
FG33
3S65 FG1C FG1D
IF21 IF23
FG0H 2G92
2F20

9S97

9S96
9S13
3S67

9G0K
2UE7 3F12

3F22
FF08 2G93
9S12
2F21
2B42

2G94
FG32
IS09 3B27
3U16 3U15

FG30
IF22

3F20
3F19 2B22

2G95
9C01 3S6B 2S89 3S58
FG31

2B23

2B38
9C00 3S6C 3S5W

2B25

3B21
FL31 2B24

3S06
IS00 9S08
IF87
FS01
2S4N

2B26
3S61
2S66

3S07

2S17
3S6G

2S25
3S1V 2B20

3B20
2S61

2B19
3B06

3S15
3S60

2B21
2B18

2S26
IF88 3S6E
3S6F
FUD3
IU30

2S67
3S5Z
3S6D IS26
IU29

2S63
IU28 3S5Y

5S88
7U06 3U25
FF07
3S57 IS25 2S5M
IS3K
2S62

2S6P

2S4S
5S85

2S5H
3S2G 3S2F 3S56 5S94
IUB3
3S1W
2S57

2S5P
2S4W

2S64
FF06 2D03 ID35
3S6A 3S6W 3S6V 3S69
3F07
7UA0

2S5J

3S6Q
2S4Y
IU27
2S21

2S60
3S1X

2S6F
5S83
7D11

3D01
IS3Q
FF05
FF09 5S80
3S1E 3B22

3S6P
FUA0 3UA0
2S5G

5S93
IS58

5S89
5S92
3S30

2S5A
2S27 ID34

5S87
3UB7 3UB6 3S33

5S81
2S6E

2S23
IS3S
3D15

2S5D
2S5K

2S6M

2S59
3S1R

3S1U
3S1S

3S1T
2B10

5S82
3S82

2S58
2S28
IUD3

2S6L 2S6D
2UB8

IUB4 3S0V

2B16

2B14
IS42 ID12

2S5C
IUB2 2S43

2S6K
IS04 2S65

2S6H

7D03
7UA7 5S95
2B15
2B37

3D09

3D16
2S68
IUB5 IS10

5S90
FD07

5S04

2S53
2S55

2S56

3S20
IU26 2B17

2S24
2S2E

2S52
IUD6 2S5B 2S20

3D06
3U12

3U13
7UA6

3S0W

2S6A
FS02
ID11

FS64

3S64

2S4V
2S6N

2S37
IS01 2S6B 2B13
3S22 2D02

2S11
2SHW

2B12
2UB7

IF55
ID14 ID33

2B11
2S6C 2S51

9FD2

3FD7

9FD5

3FD2
2S6G
2S4T
3F67 3B01 2B09

3S45
IS05
FF58 9S09 2S4U 2S46 2D28
3F66

2S50
3F53
IUD7

2S4Z
2S15

2S4R
IS3L

3D02
FC95

3S40
IFD3 IFD5 IS16 DS52
3F54 3S2K

2B40 FD01 FD08

2S45
7F53 7D15
5UA0

3S41

7UA5
7FD1

2S4Q
2FD1

7F54
3S55
2D29

7S20
IF57 3S1P IS4Z IS5F

2S4K
3FD1

2F53
3F69

3S1F

9S0D

2S29
3FD6

9FD1

IF51 IS5E

2S13

2S3G
3S2H ID15

9CH0

5S84
FD03
2S76 IS1A
IUB1 2UB5 2UB6 IUB6 FF04 IS2U 2S10 IS3B 3S5S IS4W

3S2V

9S0E
6FD1

FS0Z

2S3H
FS45 2S75 2S36
IFD1 IF56 3S76

3S09
FS51 IS50

C001
3B28 ID30

3S5V
IS19 2B01 ID18
3F68

2B03
3S75
2S3L

2B02

2D16
2S2L
2S14

2B04

2B08

2B36
FS10 3S1G IS5D ID37

3S10
FS11

2S3E
IS1B

2S18
7S09
ID19

ID29
IFD2 IFD4
3FD3

3FD4

2S85 3S1H 3S2L

IS3D

2S3F
FD09
IS5H
2S86 IS1N ID27

2S40

3S08
IS1L 3S46 IS2Z

2S19

CD10
2S84 IS5J ID28

3S2S
FS08

2S3K
IS1M

3S5T
2S3Q IS1S

2S16
IS4V

2B07
3S19 IS1G

2B05
IS5G

3S6M

2B06
3S11
IS1E 3B03 2B00

2S3D

2S3C
2S3B

2S3A

2S38

2S39
IS3F

2S8A
3S18 FS49 9S24 IS5C

3S5B
FF43 FF50

3S72
IS2V
IS1K

2S3M
3S25
IS06

2B41
IS3E IS20
3F44

3F42

FF44 FS44
FS50

2S2J
IS03

3S05

2S22

2S2K

3S6L

3S37

3S34

3S32
FF47 IS07 FD10
IE05
IS44 FD05

3S51
3F45 ID09 ID32

2S3J
FF49
2D01 2D14

FE86
7S05
IS12
3S16 3S17
3F40
ID31
FF45 FD14 5D03 FD06

3S47
IF47

IS0V IS1J ID10 2D13

FS03
FF48
3F43

3F41

2S42
IS1Q FD02

2S2G

2S2H

3S39
FF46
IF16
5F76 6E48 3S5E
IS02
3S36 3S0Z

C000
IS1H

7E13 7E12
IS0R

2F62
2F70
2F65 IS1P 3S38

3S3P

3S49

3S1D
FF41 3F82

3E9E
FS53
IS11 2F95 IS1D

FS57
FF42
FF56
AF72
5F74

3E9D
IF53 FS52
2F73 2F80
FF55
2F72 2F82
FF29

2F77
7F52

FL39
IFLF 2F76 AF73

7E11
FL32
IF58
5F71

2E69
FL30
3F52 3F79
IF50 IF54
IE15

2D27
2D21
IF80

9E14

9E12
IF79
FL37 IFL2
2F49
IE50
3D10
BEC5
6E43

9F25
2F52

IF59

ID07
IF52
FF57
2F96 BEC3 2E86
IE18
FE23 ID05

2E83
9F26 5E74 5E73 5E76
IF72

IFL1 9E25
3E77 2E84 2E80 3E75 3E74 IE53 2E79 9E28
IE55 3E78 3E79 IE22
FL36 IU43 3E07
3E53 6E44 3E76 2E14 FE80 6E26 2E98 2E15 FE74 6E23 2E85 2E12 FE81 6E28
2E04 2E06

FE57
6E09 FE73 2E91 2E88 FE71 6E03
IF90 IE49 IU45
IFLG FE56
2G91
IF75
IFL4
IF81

9G0G
FG1V FG1W
2F78
2F74

FG2N
IFLC FF75
IF77

FF71 FE58
2FLA IF73

FG1T
2F71

FG2P FG1U
2F85
2FLD

3FLA

2FL9

7F75

2FL5
2FLB FF01

FG2C FG1S FG1R

2D26
2D22
2FL4 IF10 9F03

FG2D
IF76
9F02 3D14 FG2A
IF11
2FL8 AF71 2F75 FG2B
IF12 ID08
IF78

IF74

IF13 ID06
2FL1
5F66

2F63 3F80 2F79


2F66

FG27 FG28
FG29
2FL3 2F64 IF14 3F81 3F77 IF82
3FLF

2FLC IFLE
IFLA IF15
FG26 FG25 FG24
2FL2 2FH8 IF28 3FE5 IF27
2FE5

3FE7

3FE6
2FF3

3FLH
3FLD

3FG4 3FG2 FG23 FG22


3FLB
5FG2

5FG0

AF70 FG2M
IF29

IFLD IF64
IFL3 3FLG
IFLB 3G31 FG21 FG20
IF66
2FF6
1FE0
3F32

3G33
2FG2

9E16
5FE4
FL43 2FF5 FG1Y FG1Z
3G34
FF00 IE26
2FG3

IF63 FE50 IE64


2FF0
FL33

3G30

FE72
FF64 IE73
IE63 FG2E FG2F
3FG7 IE38 3G36 FG2L
IF48 FE85 FE49

FE43
IE48 9E26

3E44
IE71
FE42 IE29
3FG6

3G2Z
2FE0 IE31

3E73
5FE0 FE54

7FE0
FFDC FF66 FF65 FG2R 3G37
FF82 IE51
FG2K
5FE3 2FH5
IE06 FG2G 3G2Y
IF65 DFE8 FG35
FL41 2FE4 IE32
2FE6
BFE3

2FG9 3G2W

FG04

FG34
2FH6 DFE7
FL40

3G32 FG2H

2FH7
5FE7

IE33 IE39 3G35


BFE2
DFE6

2FG8
FE31
FC89
2FG7 2FG6
DFE9

FE33
IF17 IF18 FE29
FE34
2F84 3F76

2FG4

DFF2 FC87

2FE8
FF81 5FE5 IF67
DFF1
IF49
FE32 3E95 3E99
2FF4

FF03
2FF7

2FF2

2FE3

2FG0

3FE8

3FE9

2FF8
FF62 2E58 2E59
3E29 3E39
7FE3

FC88
IF68

2E08

2E09
2FH4
2FH2

FE27 FE28
5E03 5E04
2FF9
2FG1

IF69
2FA4
5FE8

FF61
2FF1 FE01
5FA4

IC73

IEE8
IEE7 FC90
FF63
5FE9 2FH3 FFAF
5FA3 2FA3
FE30

FL42
IEE0 FE59 FC91

2C79
2E68

6E52

FFDB FE02
FFB5 FE61
FECZ FC92

IE77
FE48 FE60
FE03 FECB FC93
2F59

IE44
FFA2 IE74
FF76 3E90 9E19 FE51 IE75
2ECY

2ECX

7FA3
IE45
2F61

9E58

FFDA
FFB6
2ECQ
2ECW

FC65
2FA2

IE76
2EC2

FEC7 2EC3
FECY FEE0
2EC7

3ECJ

FECR 3ECK
3ECH

FC94
3ECL

5EC3
FF74 IE43 FEC3
IE12
3FBF

IEE1
FFC9 FE41
9EC2
FFB1
FC66 IU47

IEE2
FE44
FFB2

FFC4

FFB3 FFC3
2ECV

5EC0
2EC6

2EC0

IU44
FFC5 FFC7 IE65
FFB4 2EC8 IE66
3ECU
9FC2

FEC0
9FC1

FFC2
FE36
FFC1

IEC7

FFC6 FECA 3ECE


FFC8 FECW FECJ

FE35
IEC6 IEC5

9EC0
7EC0 7E02 3E23

FEC2

FEC4
3ECD

IEC4 FECE

FEC5
FEC1
FECM
3ECA 3EC1
FECF FECD
FEC6
FECK
FECG

FECP FECL FECC


FECN

2 2011-03-07

SSB Layout Bottom


3139 123 6521

19110_002_110307.eps
110307

2011-Jul-15 back to
div. table
Circuit Diagrams and PWB Layouts Q552.2L LA 10. EN 114

10-9 B01 313912365214

2011-Jul-15 back to
div. table
Circuit Diagrams and PWB Layouts Q552.2L LA 10. EN 115

Common Interface

Common Interface
B01A B01A

FF05 3F07-3
CA-CD1n 3 6
+3V3
FF06 10K
3F07-4
CA-CD2n 4 5
10K
3F07-1
1 8
10K
3F07-2
2 7
10K
3F08-1
1 8
10K
3F08-4
CA-MOCLK 4 5
+3V3
FF07 10K
3F08-3
CA-MOVAL 3 6
10K
3F08-2
CA-MOSTRT 2 7
10K
RES 1 3F09-1 8
CA-MDO0
10K
RES 2 3F09-2 7
CA-MDO1
10K
RES 3 3F09-3 6
CA-MDO2
10K
RES 4 3F09-4 5 IF04
CA-MDO3
10K
RES 4 3F10-4 5
CA-MDO4
10K
RES 3 3F10-3 6
CA-MDO5
10K
RES 2 3F10-2 7
CA-MDO6
10K
RES 1 3F10-1 8
CA-MDO7
10K

FF08 3F12
CA-RDY +3V3
10K
2 3F11-2 7
10K
3 3F11-3 6 IF08
10K
4 3F11-4 5
FF09 10K
CA-VS1n 8 3F11-1 1
+3V3
10K

1X07 1X04 1X08 1X01


REF EMC HOLE EMC HOLE REF EMC HOLE REF EMC HOLE

4 2011-05-10

SPB SSB TV550 3 2011-03-09

3139 123 6521 2 2010-12-23


2K11 4DDR BR SD

19112_002_110628.eps
110628

2011-Jul-15 back to
div. table
Circuit Diagrams and PWB Layouts Q552.2L LA 10. EN 116

Flash

Flash
B01B B01B

+3V3

2F20

2F21
100n

100n
7F20

12

37
NAND04GW3B2DN6F
Φ VCC
1
2
[FLASH] 3
4G × 16 4
5
XIO-D00 3F20-1 1 8 100R 29 6
0
XIO-D01 3F20-2 2 7 100R 30 10
1
XIO-D02 3F20-3 3 6 100R 31 11
2
XIO-D03 3F20-4 4 5 100R 32 14
3
XIO-D04 3F21-1 1 8 100R 41 IO 15
4
XIO-D05 3F21-2 2 7 100R 42 20
5
XIO-D06 3F21-3 3 6 100R 43 21
6
XIO-D07 3F21-4 4 5 100R 44 22
7
NC 23
24
IF21 25
NAND-CE1n
26
NAND-CLE 3F22-2 2 7 100R 16 27
CLE
NAND-ALE 3F22-3 3 6 100R 17 28
ALE
+3V3 3F23 10K 9 33
CE
XIO-OEn 3F22-1 1 8 100R 8 34
RE
XIO-WEn 3F22-4 4 5 100R 18 35
IF22 WE
NAND-WPn 19 38
WP
+3V3 3F24 7 39
R
40
2K2 B
NAND-RDY1n 45
IF23 46
47
48
10K
3F19 VSS

13

36
+3V3

4 2011-05-11

SPB SSB TV550 3 2011-03-09

3139 123 6521 2 2010-12-23


2K11 4DDR BR SD

19112_003_110628.eps
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2011-Jul-15 back to
div. table
Circuit Diagrams and PWB Layouts Q552.2L LA 10. EN 117

USB Hub

USB Hub
B01C B01C
+3V3

USB-OVR1
3FL2
+5V
+T 0R3

100n
100n

100n

100n
1u0

10n

10n

10n

2FLA 1n0

2FLB 1n0

2FLC 1n0
4 3FL4-4 5 FL33
+5V-USB2

2FL2

2FLD
2FL5

2FL3
USB1

2FL1
100K

2FL4
2FL9
2FL8
1FL5 3FL4-3
1 3 3 6 1P08
+5V-USB1 FL43 1
24M 100K
USB1-DM FL36 2
4
2

1 3FL4-1 8
2FL6

2FL7

7FL5 FL37 3
12p

12p

USB1-DP

+3V3
11
15
19
23
27
33
39
55
CY7C65621-56LTXCT 4

3
7
100K
FL32 5 6 IFLF
IFL4 VCC 3FL4-2
21 35 2 7
XIN GREEN1
36
IFLG AMBER1 100K
22
XOUT USB-16-PBT-B-30-CU1-BRF
37
GREEN2

3FL7

9FL3
3FLD 10K 45 38

10K
+3V3 SELFPWR AMBER2 3F32
3FLE-1 +5V USB2
1 8 26 29 +T 0R3
+5V VBUSPOWER PWR1 IFLB 3F34-4
100K IFLA 30 9FLE 4 +5V-USB1 1P07
OVR1
46 +5V-USB2 1
3FLE-2 RESET 100K
2 7 31 USB2-DM FL40 2
IFL1 PWR2 3F34-3
9F26 17 32 3 6 USB2-DP FL41 3
100K D- OVR2
9F25 IFL2 18 4
D+ 100K
4 3FLE-4 5

FL42
25 IFLC 3FLA 10K 5 6
9FLC SPI_CS +3V3 3F34-2
100K 13 48 IFLD 3FLB 15K +3V3 2 7
9FLD DD1- SPI_SCK
14 49 IFLE 3FLC 10K
3FLE-3 DD1+ SPI_SD 100K
3 6
9 58 1 3F34-1 8 USB-16-PBT-B-30-CU1-BRF
100K DD2-
10 59 100K
3FLF DD2+
+3V3 60
10K 61 +3V3 RES 1 9FL1-1 8
9FLG

9FLH
9FLF

9FLJ

RESET-USBn 62 RES 2 9FL1-2 7


USB1-DM 63 RES 3 9FL1-3 6
USB1-DP 64 RES 4 9FL1-4 5
USB-DM 65
USB-DP 66 +5V 1 9FL2-1 8
USB2-DM 67 2 9FL2-2 7
USB2-DP 68 3 9FL2-3 6
USB-WIFI-DDn 69 4 9FL2-4 5
IFL3 53 70 (WIFI)
USB-WIFI-DDp VIA RES 3FLJ
51 RES 71 RES
72 +T 0R3 1F24
USB2-DM 9FLK 5 73 FL38 1
USB2-DP 9FLL 6 74 USB-WIFI-DDn FL39 2
42 75 USB-WIFI-DDp FL30 3
3FLG
+3V3 41 76 4

FL31
54 77 5
10K
USB-OVR1 1 NC 78 6 7
2 79
3FLH
+3V3 44 80 502386-0570
43 81
10K
52 82
GND
GND
HS
4
8
12
16
20
24
28
34
40
47
50
56

57

SCENARIO 1P07 1P08 1F24 3FLG 3FL2 3FL4 3FL7 3F32 3F34 7FL5 9FLE 9FLC/D 9F25/6 9FL2 9FL3 9FLF/G 9FLH/J 9FLK/L
1x USB N Y N N N N N Y N - N N Y N N N N N
1x USB + WIFI N Y Y Y N N Y Y Y CY7C65621 N N N Y N N Y N
2x USB Y Y N Y Y Y N Y Y CY7C65621 Y Y N N N Y N N
2x USB + WIFI Y Y Y N Y Y Y Y Y CY7C65631 N N N Y Y N Y Y

4 2011-05-10

SPB SSB TV550 3 2011-03-09

3139 123 6521 2 2010-12-23


2K11 4DDR BR SD

19112_004_110628.eps
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2011-Jul-15 back to
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Circuit Diagrams and PWB Layouts Q552.2L LA 10. EN 118

SD Card

SD-Card
B01D B01D

3F40 FF45
+3V3 +3V3-SD
+T 0R3

22u 16V
2F40
+3V3

3F41-4 IF47 3F44-2


4 5 SDIO-DAT3 SDIO-DAT3 2 7 FF47
1P09-1
47K 3F41-3 100R 3F43-3
3 6 SDIO-CMD SDIO-CMD 3 6 FF48
1
47K 100R 2
+3V3-SD 3
3F45 RES 3F44-1 4
SDIO-CLK SDIO-CLK 1 8
5
FF49
10K 100R 6
7
2 3F41-2 7 SDIO-DAT0 SDIO-DAT0 2 3F43-2 7 FF41
8
47K 100R 9
1 3F41-1 8 SDIO-DAT1 SDIO-DAT1 1 3F43-1 8 FF42 13 14 FF46
15 16
47K 100R
1 3F42-1 8 SDIO-DAT2 SDIO-DAT2 3 3F44-3 6 FF43
47K SCDA7A0200
100R

1P09-2
3F42-2 FF44
2 7 SDIO-CDn SDIO-CDn 10
47K 11
12
3 3F42-3 6 SDIO-WP SDIO-WP FF50
SCDA7A0200
47K

4 2011-05-10

3 2011-03-09
SPB SSB TV550
3139 123 6521 2 2010-12-23
2K11 4DDR BR SD

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Circuit Diagrams and PWB Layouts Q552.2L LA 10. EN 119

PNX85500 Control

PNX85500 Control
B01E B01E

+3V3-STANDBY +3V3-STANDBY

+3V3-STANDBY
+3V3 +3V3 +3V3

RES
2F49

100p

100n
2F52

RES
10K
3F66

3F52

10K
8
7F52

3F67
M25P05-AVMN6

10K
BACKLIGHT-BOOST
VCC IF50
PNX-SPI-SDI IF51 2
Q Φ D
5 PNX-SPI-SDO 7F53 RES
PDTA114EU +5V
512K IF52
6 PNX-SPI-CLK
FLASH C
IF53

3F68 RES
1 PNX-SPI-CSBn
S
IF54
3 IF55

47K
W PNX-SPI-WPn BOOST-PWM
7F54-1 RES
7 BC847BPN(COL) 6
HOLD +3V3-STANDBY
FF29 IF61 7F54-2 RES IF56
VSS SPI-PROG BC847BPN(COL)
4 2
IF57
1
4

IF62 5
FF04
SDM
3

3F53 FF58
9CH0
10K

RES

RES
2F53

3F69

3F54

RES
1K0
1u0

10K
+3V3
MAIN NVM

DEBUG ONLY
RES
IF58 1F52
2F58 RES FF61 3F62 100R
SCL-SSB 1 SCL
FF62
100n 2
7F58 SDA-SSB 3 SDA
3F63
8

FF63 100R 4 5
Φ
10K

3F58 (8K × 8) 7
WC
EEPROM 3F59 FF55
IF59 1 6 SCL-UP-MIPS
0 SCL
2
1 ADR 100R 3F60 FF56
3 5 SDA-UP-MIPS
2 SDA
100R
4

FF57

DEBUG / RS232 INTERFACE LEVEL

RES SHIFTED
1F51
FF65 3F64
TXD-UP 1
100R
FF64
2
FOR
RXD-UP
FF66 3F65 UP
3
RESET-STBYn 100R
SPI-PROG
4 DEBUG
5
7 6
USE ONLY

4 2011-05-10

SPB SSB TV550 3 2011-03-09

3139 123 6521 2 2010-12-23


2K11 4DDR BR SD

19112_006_110628.eps
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Circuit Diagrams and PWB Layouts Q552.2L LA 10. EN 120

Tuner

Tuner
B01F B01F
IF10
1T01
FF71
* IF11

15
TUNER 14

4MHZ_REF
PNX-IF-P

I2C_ADR

I2C_SDA

IF_OUT1

IF_OUT2
RF_AGC

I2C_SCL

B+_TUN
2F71
B+_LNA

9F00

9F01

9F02

9F03
16 13
RF_IO

+5V-TUN-PIN

TUN

NC
10n

2F72

2F73
7F75 * *

2F65 RES
1
UPC3221GV-E1
* *

10

11

12
1

VCC

15p
IF75 2F74 IF73 2F75 IF76 AF72

2F70 RES
IF74 3F79-1
1F75 2 INPUT1 OUTPUT1 7 1
1 5
I O1 10n 10n 220R IF16

RES
5F71

2F76

2F77

5F74

2F62
2 4

2p2

1p0
IF77
6p8

6p8

6p8

6p8

6p8

6p8

6p8
ISWI O2 2F78 IF78

3F82 RES
3 INPUT2 OUTPUT2 6 IF80
2F79 3F79-4
3 4 * * * *
GND IF81 10n

820R
RES 5F76

330n
GND1

GND2
10n 220R AF73
RES 2F9C

RES 2F9D
RES 2F9A

RES 2F9B
RES 2F97

RES 2F98

RES 2F99

X7251M 4 VAGC AGC CONTROL


36M17

2F80

2F82
8

5
* *
PNX-IF-N
PNX-IF-AGC IF82 3F77
AF71 TUN-IF-N
FF74 FF76
TUN-P1 AF70 TUN-IF-P 4K7 IF79
IF12 IF13
100n

FF00 FF01 2F63


4n7

4n7

3F80
* 9F04 IF-AGC IF-AGC IF72 +5V-TUN-PIN
220R 10n
IF-

100p

100p

9F05

9F06

5F66

2F66
680n
FF75

15p
BA591
RES 2F81

2F59

2F60

2F61

2F85

3F71

6F72

3F72

2F92
4K7

1K0
47n

10n
3F81 IF14 2F64 IF15
* * IF+

RES 2F95

RES 2F96
2F93

100n

* IF86 2F90
220R 10n

10n * For BR NIM Tuner only

3F78
FF81

3K3
TUN-P6
3 5F73 2

5F70

470n
+5V-TUN-PIN

TUN-P7 FF82 TUN-IF-N

TUN-IF-P 4 1
2F91 RES
ATB2012
10n
IF89
2F84 3F76 IF87 IF90
SCL-TUNER SELECT-SAW 7F70
PDTC114EU
15p 47R

RES
TUN-P6

10n
2F86 3F75 IF88 SDA-TUNER

2F94
15p 47R
TUN-P7
* For EU Hybrid Tuner Only
9F71
5F72 RES
+5V-TUN +5V-TUN-PIN

* Remarks Component
30R
2F88

Item No.
22u

Europe Brazil
1T01 TH26X3 FA23X7
2F61 4u7 RES
2F62 10p 5p6
9F02 RES Used
9F03 RES Used
9F04 RES Used
9F05 RES Used
9F06 RES Used
2F73 1p0 RES
2F82 1p0 RES
2F72 15p 12p
2F80 15p 12p
2F77 22p 18p
5F71 680n 560n
5F74 820n 680n

4 2011-05-10

SPB SSB TV550 3 2011-03-09

3139 123 6521 2 2010-12-23


2K11 4DDR BR SD

19112_007_110628.eps
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Circuit Diagrams and PWB Layouts Q552.2L LA 10. EN 121

Toshiba Supply

Toshiba supply
B01G B01G

+3V3 +1V2-BRA-DR1

+1V2-BRA-VDDC

5FA3

5FA4
30R

30R
7FA3
LD1117DT12
FFAF
3 2
IN OUT
COM
2FA2

2FA3

2FA4
100n

100n

10u
1
FFA2

4 2011-05-10

SPB SSB TV550 3 2010-03-09

3139 123 6521 2 2010-12-23


2K11 4DDR BR SD

19112_008_110628.eps
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Circuit Diagrams and PWB Layouts Q552.2L LA 10. EN 122

HDMI

HDMI
B01H B01H

HDMI CONNECTOR SIDE


1P05
1 DRX2+ DIN-5V
2
3 DRX2-
4 DRX1+
5
6 DRX1-
7 DRX0+
8
9 DRX0-

1 3FBF-1 8
10 DRXC+

47K
11
12 DRXC-
13 PCEC-HDMI
14
FFB1 DRX-DDC-SCL DRX-DDC-SCL
15
FFB2 DRX-DDC-SDA DRX-DDC-SDA 2 3FBF-2 7 DIN-5V
16
17 FFB3 47K
18 DIN-5V
19 FFB4 DRX-HOTPLUG
FFB5 21 20
23 22
FFB6

4 2011-05-10

SPB SSB TV550 3 2011-03-09

3139 123 6521 2 2010-12-23


2K11 4DDR BR SD

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Circuit Diagrams and PWB Layouts Q552.2L LA 10. EN 123

VGA

VGA
B01I B01I
FFC1 3FC5
R-VGA

CDS4C12GTA
18R

RES 2FC1

1FC1

RES 6FC1
100p

12V
FFC2 3FC6
G-VGA

CDS4C12GTA
18R

RES 6FC2
RES 2FC2

1FC2
100p

12V
1E05
1
2
3 3FC7
B-VGA
4

CDS4C12GTA
FFC3 18R
5

RES 6FC3
RES 2FC3

1FC3
100p
6

12V
VGA 7
8
CONNECTOR 9 FFC4
10
11
FFC5
12 9FC5 H-SYNC-VGA
13
14

RES 6FC4

CDS4C12GTA
2FC4

1FC4

3FC3
15

12V

4K7
47p
17 16
FFC6
1216-02D-15L-2EC

FFC7
9FC6 V-SYNC-VGA

CDS4C12GTA
RES 6FC5
2FC5

1FC5

3FC4
12V
47p

4K7
9FC1 VGA-SDA-EDID-HDMI
RES
3FC1 FFC8
9FC2 VGA-SDA-EDID
RES

CDS4C12GTA
10K

RES 6FC6
2FC6

12V
47p
9FC3 VGA-SCL-EDID-HDMI
RES
3FC2 FFC9
9FC4 VGA-SCL-EDID

CDS4C12GTA
10K RES
2FC7

RES 6FC7

12V
47p

+5V-VGA

CDS4C12GTA
2FC8

1FC6

RES 6FC8

12V
47p

4 2011-05-10

SPB SSB TV550 3 2011-03-09

3139 123 6521 2 2010-12-23


2K11 4DDR BR SD

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Circuit Diagrams and PWB Layouts Q552.2L LA 10. EN 124

Temp sensor & headphone

Temp sensor & headphone


B01J B01J

+3V3

9FD1 RES

9FD2 RES
3FD1
RES

1K0

2FD1

3FD2
100n

1K0
LTST-C190KGKT
RES

8
7FD1
LM75BDP

6FD1

+VS
3 7 IFD1
OS A0
3FD3 IFD2
SDA-SSB 1 6 IFD3
SDA A1
3FD4 100R IFD4
SCL-SSB 2 5 IFD5
SCL A2

GND
100R

RES
3FD6

3FD7

9FD5
1K0

1K0
4
RES
1329
1
2
3
5 4

502382-0370

1328
2MSJ-035-69A-B-RF-PBT-BRF
FFDA
AMP1
3
AMP2

CDS4C12GTA

CDS4C12GTA
FFDB
7

1
3FDG-2

3FDG-1

2FDC

2FDD
1FD2

6FD2

1FD3

6FD3
1K0

1K0

12V

12V

22n

22n
FFDC

RES

RES
2

4 2011-05-10

SPB SSB TV550 3 2011-03-09

3139 123 6521 2 2010-12-23


2K11 4DDR BR SD

19112_011_110628.eps
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Circuit Diagrams and PWB Layouts Q552.2L LA 10. EN 125

Tuner Brazil

Tuner Brazil
B01K B01K

5FE0 IF63 IF64


+2V5-BRA +1V2-BRA-VDDC
30R

2FE0

2FE3

2FE4

2FE5

2FF0

2FF1
100n

100n

100n

100n
1u0

1u0

+3V3-BRA-FLT
AGND
5FE3 IF65 IF66 5FE4
+3V3-BRA-FLT
+3V3-BRA
30R 30R

2FE6

2FF2

2FF3

2FF4

2FF5

2FF6
100n

100n

100n

100n
1u0

1u0
AGND
5FE5 IF67 IF68
+1V2-BRA-DR1
30R 5FE7 IF48
+3V3 +3V3-BRA
2FE8

2FF7

2FF8

2FF9
100n

100n
1u0

1u0
30R

IF69 5FE8
+2V5-BRA
30R 7FE3
1FE0 LD3985M25

2FG0

2FG1
100n
1 3

1u0
5FE9 FF03
1 5
25M4 +5V IN OUT +2V5-BRA
4 2 30R
2FG2

2FG3

3 4
18p

18p

INH BP
COM
7FE0
32

22

20

16
36
56
63

13
35
49
64

34
48

43

2FH2

2FH3

2FH4
TC90517FG

1u0

10n

1u0
2
AGND AGND AGND
AD_DVDD

AD_AVDD

PLLVDD

DR2VDD
VDDC Φ VDDS

DR1VDD
2FH5 * To be drawn near PNX85500
19 21
I FIL
AGND
X 1n5
18 58 3FG6-4 4 5 33R TS-BR-VALID 1 9F27-1 8 * TS-FE-VALID
O PBVAL
DFE6
3 53
0 RERR
2 XSEL
1 DFE7
54
RLOCK
IF+ 2FG4 10n IF17 30
P DFE8
IF- 2FG6 10n IF18 29 ADI_AI 55
N RSEORF
2FG7 100n 28 59 3FG6-3 3 6 33R TS-BR-SOP 2 9F27-2 7 * TS-FE-SOP
BFE2 P SBYTE
2FG8 100n 27 ADQ_AI
N DFE9
52
AGND BFE3 SLOCK 5FG0
2FG9 100n 24
P
2FH6 100n 25 AD_VREF 61 3FG7 33R TS-BR-CLOCK 9F28 * TS-FE-CLOCK
N SRCK 30R
AGND
2FH7 100n 26 60 3FG6-2 2 7 33R TS-BR-DATA 4 9F27-4 5 * TS-FE-DATA 5FG2
AD_VREF SRDT
DFF1
39 38
AGND DTCLK STSFLG1 30R
IF27 3FE5 IF28 AGND
40 9 IF-AGC
+3V3-BRA-FLT DTMB AGCCNTI
18K

2FH8
8 10

10n
S_INFO AGCCNTR
DFF2
3FE6 10K 1 51
0 STSFLG0
41 TSMD
1
42
SYRSTN
3FE7 10K IF29 7
AGCI
6 3FG2-1 RESET-SYSTEMn
0 3FG2-2
11 SLADRS 5 10K
CKI 1
10K
3FG4-2
AD_DVSS
AD_AVSS

SCL-SSB 3FE8 100R IF49 45 12


SCL SCL
PLLVSS

SDA-SSB 3FE9 100R 46 TN 14 4K7 3FG4-1


SDA SDA +3V3-BRA-FLT
4K7
VSS
23

31

17

4
15
33
37
44
47
50
57
62

AGND AGND

4 2011-05-10

SPB SSB TV550 3 2011-03-09

3139 123 6521 2 2010-12-23


2K11 4DDR BR SD

19112_012_110628.eps
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2011-Jul-15 back to
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Circuit Diagrams and PWB Layouts Q552.2L LA 10. EN 126

10-10 B02 313912365214


NANDflash - conditional access

PNX85500: NANDflash - conditional access


B02A +3V3
B02A

3S1W

10K
7S00-5
PNX85500

FLASH D25 XIO-D00


00
D26 XIO-D01
01
C24 XIO-D02
02
D23 XIO-D03
03
NAND-ALE D22 C23 XIO-D04
ALE 04
NAND-CLE C21 NAND B23 XIO-D05
CLE 05
A22 XIO-D06
06
J25 E22 XIO-D07
00 07
J26 XIO_D F24
01 08
H21 F25
02 09
H22 F26 XIO-D10
03 10
H23 E23
04 11
H24 E24
05 12 IS26 3S15
H25 E25 INPACK INPACK
06 13
H26 E26
07 14 10K
G21 XIO_A D24
08 15
G22
09
G23 B22 XIO-OEn
10 OE_
G24 XIO C22 XIO-WEn
11 WE_
G25
12
G26 B21 +3V3
13 CLK_BURST
F22
IS25 14
F23 E21 NAND-CE1n
15 CE1_
D21
CE2_
A20
NAND RDY2

3S1V

RES
F21

10K
RDY1 NAND-RDY1n
A21 9S08 NAND-WPn
WP_
IS00

+3V3

3S1X

10K
7S00-11
PNX85500

P21 VIDEO_STREAM N26 CA-MDO0


0 0
P22 M21 CA-MDO1
1 1
P23 M22 CA-MDO2
2 2
P24 M23 CA-MDO3
3 3
P25 MDI MDO M24 CA-MDO4
4 4
P26 M25 CA-MDO5
5 5
N21 M26 CA-MDO6
6 6
N22 L21 CA-MDO7
7 7
J22
ADD_EN
K25 K23 CA-VS1n
DATA_DIR 1
VS K24 9S00 CA-MOCLK
2
K26
DATA_EN
K21 CA-CD1n
1
N23 CD K22 CA-CD2n
I 2
MCLK
CA-MOCLK L25
O CA
+3V3
N24
MISTRT
N25 TS-FE-DATA 3S1R
MIVAL
560R
CA-MOSTRT L22 TS-FE-CLOCK 3S1S
MOSTRT
560R
CA-MOVAL L23 TS-FE-VALID 3S1T
MOVAL
560R
J21 TS-FE-SOP 3S1U RES
OOB_EN
560R
RES
CA-RDY L24
RDY
L26 T21 TS-FE-DATA TS-FE-DATA 3S23
RST DATA
T23 TS-FE-ERR 470R
ERR
J23 T22 TS-FE-CLOCK TS-FE-CLOCK 3S24
VCCEN TNR_SER1 MICLK
R23 TS-FE-VALID 470R
MIVAL
J24 R22 TS-FE-SOP TS-FE-VALID 3S28
VPPEN SOP
470R
TS-FE-SOP 3S29 RES

RES 470R

4 2011-05-10

SPB SSB TV550 3 2011-03-09

3139 123 6521 2 2010-12-23


2K11 4DDR BR SD

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Circuit Diagrams and PWB Layouts Q552.2L LA 10. EN 127

SDRAM

PNX85500: SDRAM
B02B B02B

7S00-8
PNX85500
DDR2-BA0 H1 MEMORY J1 DDR2-A0
0 0
DDR2-BA1 H2 J3 DDR2-A1
1 BA 1
DDR2-BA2 G1 K1 DDR2-A2
2 2
G4 DDR2-A3
3
DDR2-DQM0 D1
0 M0 4
L3 DDR2-A4
DDR2-DQM1 D5 G3 DDR2-A5
1 5
DDR2-DQM2 R3 DM L2 DDR2-A6
2 6
DDR2-DQM3 T5 H5 DDR2-A7
3 7
L1 DDR2-A8
A 8
DDR2-D0 F3 J5 DDR2-A9
0 9
DDR2-D1 C2 J2 DDR2-A10
1 10
DDR2-D3 F2 M3 DDR2-A11
+1V8 2 11
DDR2-D2 C3 J4 DDR2-A12
3 12
DDR2-D6 B4 M2 DDR2-A13
4 13
DDR2-D5 F1 K5 DDR2-A14
5 14
DDR2-D4 C1
6
DDR2-D7 E1 N5 3S30 DDR2-CLK_N
7 N

100u 2.0V
F4 CLK N4 10R 3S33 DDR2-CLK_P
180R 1%

180R 1%
DDR2-D8 8 P
3S20

3S06

2S12
DDR2-D9 B2 10R
9
DDR2-D10 E5 E2 DDR2-DQS0_N
10 N
DDR2-D11 C5 DQS0 E3 DDR2-DQS0_P
FS02 11 P
DDR2-D12 A4
DDR2-VREF-CTRL3 FS01 12
DDR2-D13 G5 D3 DDR2-DQS1_N
DDR2-VREF-CTRL2 13 N
B3 DQS1 D4 DDR2-DQS1_P
180R 1%

DDR2-D14 14 P
3S22

DDR2-D15 F5
15
U3 DQ R1 DDR2-DQS2_N
180R 1%

DDR2-D16 16 N
3S07

DDR2-D17 P2 DQS2 R2 DDR2-DQS2_P


17 P
DDR2-D19 U2
18
DDR2-D18 P3 T3 DDR2-DQS3_N
19 N
DDR2-D22 N1 DQS3 T4 DDR2-DQS3_P
20 P
DDR2-D23 U1
21
DDR2-D20 P1 K3 DDR2-CAS
22 CASB 3S6Q
DDR2-D21 T1 K4 DDR2-CKE DDR2-CKE
23 CKE
DDR2-D24 V4 L5 DDR2-CS
24 CSB 10K
DDR2-D30 R5 M4 DDR2-ODT
25 ODT
DDR2-D26 U5 M1
26 PCAL 3S6P
DDR2-D25 P5 M5 DDR2-RAS DDR2-ODT
27 RASB
DDR2-D28 N3 H3 DDR2-WE
28 WEB 10K
DDR2-D31 V3 RES
29
DDR2-D27 R4 A2 DDR2-VREF-CTRL2
30 1
DDR2-D29 V5 VREF V1 DDR2-VREF-CTRL3
31 2

IS42

2S20

2S17

1%
2S24

2S25
100p

100n

100n

100p

3S0V

261R
4 2011-05-10

SPB SSB TV550 3 2011-03-09

3139 123 6521 2 2010-12-23


2K11 4DDR BR SD

19112_014_110628.eps
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Circuit Diagrams and PWB Layouts Q552.2L LA 10. EN 128

Digital video in

PNX85500: Digital video in


B02C B02C

7S00-6
PNX85500

HDMIA-RX2+ T25 HDMI_DV


P
HDMIA-RX2- T26 RX0_A
N

HDMIA-RX1+ U25
P
HDMIA-RX1- U26 RX1_A Y26 DDCA-SCL
N SCL
DDC_A Y25 DDCA-SDA
SDA
HDMIA-RX0+ V25 IS10
P
HDMIA-RX0- V26 RX2_A T24
N HOT_PLUG_A

HDMIA-RXC+ W25
P
HDMIA-RXC- W26 RXC_A
N
+3V3 IS01
3S0W
W24
RREF
12K

2S2E
RES

10u

4 2011-05-10

SPB SSB TV550 3 2011-03-09

3139 123 6521 2 2010-12-23


2K11 4DDR BR SD

19112_015_110628.eps
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Circuit Diagrams and PWB Layouts Q552.2L LA 10. EN 129

Audio

PNX85500: Audio
B02D B02D
3S0Z
3S53-1 +2V5-AUDIO +24V-AUDIO-POWER
4R7 +24V-AUDIO-VDD
100R +3V3
3S53-2

2S3J

220n
7S08
LD3985M25
100R
1 IS1H 1 3S16-1 8
3S12-1 2S2W 3S53-3 FS08 FS03
AUDIO-IN1-L 8 10K 5 1
OUT IN
22K 1u0 100R IS12 IS13 4

10u RES
4 3 4S14 ADAC(1) 12 7S05-4
2 3S53-4 BP INH +2V5 3S38
LM324 14

2S2R

2S2S
3S16-2 7

10u
2 3S12-2 IS1J 2S2V +AUDIO-L
IS02

1u0 RES
AUDIO-IN1-R 7 10K COM 13
100R 100R

2S2T

100n
22K 1u0 11

2S34
2
3S16-3 3 6 2S2Z
IS1M
10K
1u0 3S36-2 10K
2 7
IS0V 8 1
3S16-4 5 2S2Y 10K 3S36-1

100u 4V
3S51

2S42

2S41
4R7
4

1u0
2S2G
10K
1u0
3S17-4 47p
IS0R 4 5 7S00-2
3S13-4 2S31
AUDIO-IN3-L 10K PNX85500 +24V-AUDIO-VDD
4 5 2S36
22K 1u0
AE10 AUDIO AC7 1 3S3G-1 8 ADAC(1)
3 L P
3S17-3 6 AF10 AIN1 ADACL AB7 IS1N
3S13-3 2S30 R N 1u0 33R 3S3G-3 IS03 4
AUDIO-IN3-R 3 6 10K 3 6 ADAC(2) ADAC(2) 10 7S05-3
LM324 8 3S39
AD10 AC6 -AUDIO-R
22K 1u0 L P 33R
AC10 AIN2 ADACR AB6 9
3S17-1 R N 100R
IS1P 1 8
3S13-1 2S33 11
AUDIO-IN4-L 10K AE9 AD7
L 1 3S3G-2
1 8 AF9 AIN3 AE7 2 7 ADAC(3)
22K 1u0 R 2
2 AF7 33R
3 3S3G-4
IS1Q 3S17-2 7 AD9 ADAC AD6 4 5 ADAC(4)
3S13-2 2S32 L 4 IS1S
AUDIO-IN4-R 2 10K AC9 AIN4 AE6 33R
7 R 5
AF6
22K 1u0 6
AF8
L 3S36-3 10K
AE8 AIN5 AD4 3 6
R OSCLK
3S10 AD1 5 4
I2S_OUT SCK 3S3H 10K 3S36-4
2S2L 100R AB9 AD2 ADAC(5)
POS WS 2S2H
IS1B AB8 VR_AADC 33R
1u0 NEG
IS19 AE1
1 3S3U 47p
AD8 AF2 ADAC(6)
VREF_AADC 2
AE3 +24V-AUDIO-VDD
IS1A I2S_OUT_SD 3 33R
AC8 AF3
VCOM_AADC 4
3S3F
AF5
SPDIF_OUT

2S3D

2S3C

2S3B

2S3A

2S39

2S38
1n0

1n0

1n0

1n0

1n0

1n0
56R DBS8 AE5 IS07 4
SPDIF_IN1
2S3G
2S3H
2S3E
2S3F

100n

100n

3 7S05-1
10u

10u

ADAC(5)
LM324
9S06
RES

1 AUDIO-OUT-L
2

11

3S37 3S6L

10K 22K
2S2K

+3V3 47p
+3V3-ARC

+24V-AUDIO-VDD
3S11 IS1L
1R0

4
2S3Q

100n

ADAC(6) 5 7S05-2
LM324 7
IS06 AUDIO-OUT-R
6
3S6N 11
7S09-1 SPDIF-OPT
14

74LVC00APW
IS1D RES 47R
SPDIF-OUT-PNX SPDIF-OUT-PNX 1 & 2S3K
3 IS1G 1 3S18-1 8 SPDIF-OUT
2
100n 220R 3S34 3S32

6
RES

3S18-2

3S18-3
+3V3

220R

220R
RES

RES
7

10K 22K
+3V3
2S2J

3
47p
+3V3-ARC
3S19

+3V3-ARC
10K

7S09-2
14

74LVC00APW 7S09-3
14

4 & 74LVC00APW
6 9 & 2S3L IS1K 2S3M IS44
IS1E 180R
SEL-HDMI-ARC 5 8 eHDMI+
10 3S6M
+3V3 100n 100n
7

3S25

68R
+3V3-ARC

7S09-4
14

74LVC00APW
12 &
11
13
+3V3
7

4 2011-05-10

SPB SSB TV550 3 2011-03-09

3139 123 6521 2 2010-12-23


2K11 4DDR BR SD

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MIPS

PNX85500: MIPS
B02E B02E
+3V3
7S00-3
PNX85500
RES
CONTROL C25 1
3S56
2
3S69 1F10
IS05 SDA SDA-UP-MIPS SDA-UP-MIPS
3S45 2 3S57 FS44
BOOTMODE 1 C26 100R 1 SCL-UP-MIPS SCL-UP-MIPS 3S6A 4K7 4K7 EJTAG-TRSTn-PNX85500
+3V3 SCL 1
100R EJTAG-TMS-PNX85500 FS49
10K 3S58 2
BOOTMODE Y21 B26 1 2 SDA-SET SDA-SET 3S6B 4K7 EJTAG-TDO-PNX85500 FS50
3S40
3D-LR 3D-LR IS17 9S09 IS16 Y22 GPIO_0
2
SDA
A25 100R 1 2 3S5W SCL-SET SCL-SET 3S6C 4K7 EJTAG-TCK-PNX85500 FS51
3 FOR FACTORY
+3V3 GPIO_1 SCL 4
10K DS52 RXD1-MIPS Y23
GPIO_2
100R EJTAG-TDI-PNX85500 FS52
5 USE ONLY
TXD1-MIPS Y24 B25 1 3S5Y 2 SDA-SSB SDA-SSB 3S6D 2K2
3S82 GPIO_3 SDA 6
BOOST-PWM RXD2-MIPS W21 3 A24 100R 1 2 3S5Z SCL-SSB SCL-SSB 3S6E 2K2 EJTAG-DETECTn FS53
+3V3 GPIO_4 SCL 7
TXD2-MIPS W22 100R
10K GPIO_5 3S60 8
3S80 FS10 TXD2-MIPS GPIO6 W23 B24 1 2 SDA-TUNER SDA-TUNER 3S6F 2K2 10 9
+3V3 GPIO_6 SDA
3S81 10K FS11 RXD2-MIPS PNX-SPI-CS-BLn V22 4 A23 100R 1 2 3S61 SCL-TUNER SCL-TUNER 3S6G 2K2
+3V3 GPIO_7 SCL
10K BOOST-PWM V23 100R
RES 3S21 GPIO_10
+3V3 GPIO6 SELECT-SAW U23 AA25 EJTAG-TRSTn-PNX85500 EJTAG-TRSTn-PNX85500 3S6K
IS04 GPIO_11 TRSTN
AA24 EJTAG-TMS-PNX85500 EJTAG-TMS-PNX85500 1 8 3S6H-1 10K +3V3
10K TMS +3V3-STANDBY FS57 BM08B-SRSS-TBT
USB-DM R26 AA23 EJTAG-TCK-PNX85500 EJTAG-TCK-PNX85500 10K 3 6 3S6H-3
3S62 PNX-SPI-CS-BLn DN TCK
USB-DP R25 AB26 EJTAG-TDO-PNX85500 EJTAG-TDO-PNX85500 10K 2 7 3S6H-2
+3V3
IS4Z R24 DP USB TDO
AB25 EJTAG-TDI-PNX85500 EJTAG-TDI-PNX85500 10K 4 5 3S6H-4
10K RREF TDI
10K
3S00
AE4 RESET-SYSTEMn

5K6 1%
RESET_SYS

3S55
3S64 FS64 33R
SELECT-SAW AD5 BACKLIGHT-PWM
+3V3 BL_PWM
10K
AC5
CLK_54_OUT

3S26

3S27
3S6J

RES 10K

10K

10K
3S83
+3V3 RXD1-MIPS
10K
+3V3 +3V3
3S84
+3V3 TXD1-MIPS IS40
3S72
10K PXCLK54
47R

RES

+3V3

2S89

100n +3V3

3
7S01
PCA9540B
3S65
VDD SC0 5 SCL-DISP SCL-DISP 2 1
4K7
3S66
SC1 8 SCL-BL SCL-BL 2 1
4K7
3S67
SCL-SET 1 SCL SD0 4 SDA-DISP SDA-DISP 2 1
I2 C 4K7
INP 3S68
-BUS
SDA-SET 2 SDA FIL SD1 7 SDA-BL SDA-BL 2 1
CTRL
4K7
VSS

6
FS31

9S10 SCL-BL
IS08
SCL-SET 9S11 FS2W SCL-DISP

9S12 FS2Y SDA-DISP


IS09
SDA-SET 9S13 SDA-BL

7S00-4
PNX85500

ETH-RXCLK AA3
RXCLK ETHERNET
ETH-RXD(0) Y5
0
ETH-RXD(1) Y6 AA2 ETH-TXCLK
IS50 1 TXCLK
ETH-RXD(2) AB4 RXD ETH
2
ETH-RXD(3) AC1 AA1 ETH-TXD(0)
3 0
AA4 ETH-TXD(1)
1
ETH-RXDV AC2 TXD AB1 ETH-TXD(2)
RXDV 2
ETH-RXER Y4 AB2 ETH-TXD(3)
RXER 3
ETH AA5 ETH-TXEN
TXEN
SDIO-DAT3 W2 AB3 ETH-TXER
CC_DAT3 TXER
SDIO-CLK W1 AC3 ETH-COL
CLK COL
SDIO-CMD W6 Y2 ETH-CRS
CMD CRS
SDIO-DAT0 W5 Y3 ETH-MDC
0 MDC
SDIO-DAT1 W4 SDIO Y1 ETH-MDIO
1 DAT MDIO
SDIO-DAT2 W3
2
SDIO-CDn U6
SDCD
SDIO-WP V6
SDWP

4 2011-05-10

SPB SSB TV550 3 2011-03-09

3139 123 6521 2 2010-12-23


2K11 4DDR BR SD

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Video out - LVDS

PNX85500: Video out - LVDS


B02F B02F

7S00-7
PNX85500

PX1A- A7 LVDS D7 PX3A-


N N
PX1A+ B7 A A E7 PX3A+
P P

PX1B- C8 E8 PX3B-
N N
PX1B+ B8 B B D8 PX3B+
P P

PX1CLK- 9S90 C10 E10 9S94 PX3CLK-


N N
PX1CLK+ 9S91 B10 CLK CLK D10 9S95 PX3CLK+
P P

PX1C- A9 LOUT1 LOUT3 D9 PX3C-


N N
PX1C+ B9 C C E9 PX3C+
P P

PX1D- A11 D11 PX3D-


N N
PX1D+ B11 D D E11 PX3D+
P P

PX1E- C12 E12 PX3E-


N N
PX1E+ B12 E E D12 PX3E+
P P

PX2A- A14 D14 PX4A-


N N
PX2A+ B14 A A E14 PX4A+
P P

PX2B- C15 E15 PX4B-


N N
PX2B+ B15 B B D15 PX4B+
P P

PX2CLK- 9S92 C17 E17 9S96 PX4CLK-


N N
PX2CLK+ 9S93 B17 CLK CLK D17 9S97 PX4CLK+
P P
LOUT2 LOUT4
PX2C- A16 D16 PX4C-
N
PX2C+ B16 N C E16 PX4C+
C P
P
PX2D- A18 D18 PX4D-
N
PX2D+ B18 N D E18 PX4D+
D P
P
PX2E- C19 E19 PX4E-
N
PX2E+ B19 N E D19 PX4E+
E P
P

4 2011-05-10

SPB SSB TV550 3 2011-03-09

3139 123 6521 2 2010-12-23

2K11 4DDR BR SD

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Standby controller

PNX85500: Standby controller


B02G B02G

+1V1

POL
IS3B

5S04
RES

30R

2S10

100n
1u0
2S13

2S37

1u0

9S24
RES
2S11

100n IS20 DS50 2S4G


3
1 10p

AC17
AA17

AF26
2

1S02

54M
7S00-9
PNX85500 4
2S4F
1

VDDA_1V1_DCS

VDDA_ADC2V5

VDD_XTAL
+3V3-STANDBY 2S4D AE17 +3V3-STANDBY
3S1B XTAL_IN 10p
1n0 RC RC AD19
0
3S1C RES 10K TACHO TACHO AE19 AF17
1 XTAL_OUT
10K 3S1D CEC-HDMI CEC-HDMI AF19
2 P1
3S1E RES 27K BACKLIGHT-PWM-ANA-DISP BACKLIGHT-PWM-ANA-DISP AA20 AA26 RESET-STBYn
3 RESET_IN
10K 3S1F SDM SDM AB20 IS3F
7 3S44
+3V3-STANDBY
3S3L 10K STANDBY EA
AB24 EA EA
RES LCD-PWR-ONn LCD-PWR-ONn AC20
0 ALE IS3E 10K 3S43
3S3M 10K EJTAG-DETECTn EJTAG-DETECTn AD20 AB23 ALE
3S3N RES 1 ALE
10K LAMP-ON LAMP-ON AE20 IS3D
2 10K
3S3P 10K STANDBY STANDBY AF20 AC26 PSEN PSEN 10K 3S42
3 PSEN
10K 3S3Q RES FAN-CTRL1 FAN-CTRL1 AA21 P2
4 RES 3S6V
RES 3S3S 10K FAN-CTRL2 FAN-CTRL2 AB21 AC23 3S2F 100R SDA-UP-MIPS SDA-UP-MIPS
3S3R 5 SDA 3S2G 100R
10K POWER-OK POWER-OK AC21 MC AC24 SCL-UP-MIPS SCL-UP-MIPS 4K7 3S6W
6 SCL
3S3T 10K RES ENABLE-3V3n ENABLE-3V3n AD21 RES
7 LED1 RES 3S1P 4K7
+3V3-STANDBY 10K AD26 3S2H 100R LED1
3S1G 0
RXD-UP RXD-UP AE21 PWM AC25 3S2K 100R LED2 LED2 10K 3S41
0 1
3S1H 10K TXD-UP TXD-UP AF21
1 10K
10K DETECT2 AA22 AE23 PNX-SPI-SDO
3S2A 2 SDO
DETECT2 AB22 P3 AF25 PNX-SPI-SDI
3 SDI
AC22 SPI AF24 PNX-SPI-CLK
10K 4 CLK
RES AD22 AF23 PNX-SPI-CSBn
5 CSB
3S1K
RESET-SYSTEMn RESET-SYSTEMn AD23 AB17 IS2V CTRL-DISP CTRL-DISP RES 3S2L
0 0
AV2-BLK AE26 AA18 IS2Z RESET-DVBS RESET-DVBS 10K RES 3S46
10K 1 1
RES AV1-BLK AE25 P5 AD18 RESET-USBn RESET-USBn RES 3S3Y 10K
3S1J KEYBOARD 2 2 +3V3-STANDBY
KEYBOARD AE24 AE18 RESET-ETHERNETn RESET-ETHERNETn 10K RES 3S47
3 3
LIGHT-SENSOR P0 AF18 SEL-HDMI-ARC SEL-HDMI-ARC 3S2S 10K
100K 2S4E 4
AV1-STATUS AF22 AA19 RESET-AVPIP RESET-AVPIP 10K RES 3S2M
RES 4 5

VSS_XTAL
AV2-STATUS AE22 P6 AB19 RESET-AUDIO RESET-AUDIO 3S3W 10K RES
100n 5 6
AC19 AUDIO-MUTE-UP AUDIO-MUTE-UP 4K7 3S49
7

AD17
3S1L
SPI-PROG SPI-PROG 4K7
10K PNX-SPI-WPn

+3V3-STANDBY +3V3-STANDBY

1 3S2V 2
1K0
9S0E
FS0Z
7S20 RESET-STBYn
NCP303LSN28
2
FS45 INP
1 IS2U 1
OUTP
5
CD
NC GND

3
9S0D

2S4K

100n
RES
4 2011-05-10

SPB SSB TV550 3 2010-03-09

3139 123 6521 2 2010-12-23


2K11 4DDR BR SD

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Power

PNX85500: Power
B02H IS3Q 5S80

30R
+1V1 B02H

RES 10u
2S6A

2S5A
100n
1
5S81
+2V5

2
30R

RES 10u
2S6B

2S5B
100n
1
+1V8
IS3S 5S82

2S26

2S60

2S61

2S62

2S63

2S64

2S65

2S66

2S67

2S68
100u

100n

100n

100n

100n

100n

100n

100n

100n

100n
+3V3
30R

RES 10u
2S5C

2S5D
100n
SENSE+1V1 c001
5S93
7S00-10

G6

G7
R6
R7
U7

C6
D6
A5
A6
B5
B6

E6
F6

F7
L6
L7
PNX85500 30R +2V5

2S6E 2

220u 6.3V
VDD_1V8

2S4M
2S6D

100n

100n
+1V1 AF1 V20

7
AE2 HDMI_VDDA_1V1 V21

5
AD3

1
2S5G-1

2S5G-2

2S5G-3

2S5G-4

2S5H-1

2S5H-2

2S5H-3

2S5H-4
2S4Q

2S4R
2S43

2S28

2S27

2S23
100n

100n

100n

100n

100n

100n

100n

100n

100n

100n

100n

100u
AC4 VDD U20

22u

22u

1
AB5 HDMI_VDDA_2V5 U21
H20

4
F11 U22 +2V5-LVDS

2
HDMI_VDDA_3V3_TERM
G11
F13 N6

2S4N

2S4P
100n
G13 VDD_2V5 N7

10u
F15

8
8

5
G15 C7

2S5K-1

2S5K-2

2S5K-3

2S5K-4

2S5J-3

2S5J-1

2S5J-2

2S5J-4
100n

100n

100n

100n

100n

100n

100n

100n

220u 2.5V
F17 C9

2S29
G17 C11
5S85
F19 VDD_2V5_LVDS C14

4
+3V3

2
1 2S6G 2
G19 C16

1
30R

2S6N

2S6C

2S6P
2S6F

100n

100n

100n

100n
J9 C18

10u
J11
AA16
AA8
Y11
Y14

J13 W20
Y16
Y9

7S00-12

1
PNX85500 J15 P20
J17 M20
VSSA
A1 M7 L9 VDD_3V3 K20
+3V3-STANDBY
A10 N2 L11 V7

2S4U
2S4V

100n
A12 N20 L13 Y8

10u
A15 P10 L15
VDD_1V1
A17 P12 L17 Y19
A19 P14 N9 VDD_3V3_SBY Y18
A26 VSS P16 N11 IS3K 5S83
A3 P18 N13 B13
VDDA_1V1_LVDS_PLL +1V1
A8 P4 N15 30R
IS3L

2S4W
2S4Y

100n
B1 P6 N17 AA15

RES 1u0
B20 P7 R9 Y15
VDDA_1V2
C20 T10 R11 AA13
C4 T12 R13 5S95 +2V5
D2 VSS T14 R15 Y12
VSS VDDA_2V5 5S84
D20 T16 R17
30R

6.3V
E13 T18 U9 AA9 +1V2
VDDA_2V5_AADC 30R

2S4Z
2S51

2S52

2S50
100n

100n
E20 T2 U11

10u
E4 T6 U13 AA7 c000 SENSE+1V2

10u
VDDA_2V5_ADAC
F10 T7 U15
F12 U4 U17 Y17
VDDA_2V5_DCS
F14 V10 J6
F16 V12 AA6 D13
VDDA_2V5_LVDS_BG
F18 V14 Y7
F20 V16 W7 T20 POL

VSSA_1V1_LVDS_PLL

VSSA_2V5_LVDS_BG
VDDA_2V5_USB
F8 V18 F9
G10 V2 G9 Y13
VDDA_2V5_VADC +2V5-AUDIO
G12 Y20

V24 HDMI_AGND
5S94

2S46

100n
J7 Y10

VSSA_USB
VSS +1V1 VDD_1V1_DDR VDDA_2V5_VDAC
30R
2
G14
G16
G18
G2
G20
G8
H4
H6
H7
J20
K10
K12
K14
K16
K18
K2
K6
K7
L20
L4
M10
M12
M14
M16
M18
M6

R21
VDDA_3V3_USB
2S4S

2S5P
RES

2S21
100n
10u

1u0

U24

A13

C13

R20
1

+2V5-AUDIO

2S45

100n
5S87
+2V5
30R

2S55

2S56
100n

1u0
5S88
+2V5-LVDS
30R

2S5M

2S57
100n

10u
5S89
+2V5

2
30R

2S6H

2S6K
100n

100n
2S58

10u
1

1
5S90
+2V5
30R

2S4T

2S53
100n

10u
2SHW

100n
IS58 5S92
+3V3

2
30R

2S6M

2S6L

2S59
100n

100n

1u0
4 2011-05-10

1
SPB SSB TV550 3 2011-03-09

3139 123 6521 2 2010-12-23

2K11 4DDR BR SD

19112_020_110628.eps
110628

2011-Jul-15 back to
div. table
Circuit Diagrams and PWB Layouts Q552.2L LA 10. EN 134

Analog video

PNX85500: Analog video


B02I B02I
AV1-CVBS 2S87

22n 2S8A Y-SVHS

3S59
47R
Connectivity 22n

3S5B
47R
AV1-R 2S7J

22n 2S22 C-SVHS

3S4J
56R
22n

3S05

56R
EU: SCART1 CVBS-MON-OUT1
AV1-B 2S7K
AP: -

3S5E

560R
22n

3S4L
56R
IS4V

560R
2S40

3S08
47p
2S7H
AV1-G
22n

3S4K
56R
IS4W

3S09

8K2
2S7M
YPBPR1-SYNCIN1
10n
2S7L
AV3-Y
22n

3S4P
56R
2S7N
AV3-PR
YPBPR1 22n

3S4R
EU:

56R
7S00-1
AP: YPBPR1 PNX85500
2S7P ANALOG_VIDEO
AV3-PB
AB15 AC12
22n CVBS_Y1 ATV_CVBS_Y3

2S19

2S18

2S16

2S15

2S14
3S4T
AC13 IS5C

56R
AF13

22n

22n

22n

22n

22n
R C3
AD13
B AV1
AE13 AD11
G CVBS_Y7
AC11
C7
AV2-CVBS 2S8G AF15
SYNCIN1 BS13
AE15 AF11
22n Y_G1 CVBS1_OUT
AC15 AE11
PR_R_C1 CVBS2_OUT

9S18
AD15
PB_B1
* RESREF
AB10
AB14 AA11 IS5E 3S5S
CVBS_Y2 CURREF
AF14 10K
SYNCIN2
AE14 AC16 IS5D
Y_G2 1
AC14 AB16 IS5F
PR_R_C2 2
AD14 AB13 IS5G
PB_B2 3
REF AB12 IS5H
4
AF16 AA12 IS5J
R 5 3S75
AD16 AA10 PNX-IF-AGC
G VGA 6
AE16
B 10K

2S75
2S7R AB18 AD12 BS15

10n
AV4-Y HSYNC_IN IF_AGC
AC18 AB11
22n IN RF_AGC
EU: SCART2 AF4
OUT
VSYNC
9S19

AD24 AE12
SCL VGA_EDID P
AP: YPBPR2 AD25
SDA TUNER N AF12 BS10 IS11
3S76
PNX-RF-AGC
+CVBS 47K

2S76
AGND

10n
AA14
AV4-PR 2S7U

22n
9S20

2S77
PNX-IF-P
10n

2S7E
AV4-PB
22n 2S78
9S21

PNX-IF-N
10n

2S84
R-VGA
22n
3S50
56R

2S85
G-VGA
22n
3S52
56R

2S86
B-VGA
22n
3S54
56R

EU: VGA

7
3S5V-4

3S5V-2
3S5T-4

3S5T-2
AP: VGA

100R

100R

100R

100R
3S5T-1
H-SYNC-VGA 1 8

2
100R

V-SYNC-VGA 3 3S5T-3 6
100R

RES 3S5V-3
* 319803104790 - RST SM0402 47R PMS Col R at 9S18 for BRZ
VGA-SCL-EDID 3 6
100R
RES 3S5V-1
VGA-SDA-EDID 1 8
100R
4 2011-05-10

SPB SSB TV550 3 2011-03-09

3139 123 6521 2 2010-12-23


2K11 4DDR BR SD

19112_021_110628.eps
110628

2011-Jul-15 back to
div. table
Circuit Diagrams and PWB Layouts Q552.2L LA 10. EN 135

10-11 B03 313912365214


Audio

Audio
B03A B03A

+AVCC
7D03-1 +24V-AUDIO-POWER
3D09 BC847BS(COL) FD14

1
+24V-AUDIO-POWER
4R7

2D06

220n
2
3D16 ID12
ID11

5D07

220R
5D08

220R
22K

10u 35V
GND-AUDIO

2D05
ID27 ID28
FD01 2D28 ID14 2D24
-AUDIO-R

220u 35V

220u 35V
1u0 47n

8
2D20

2D07

2D19

2D08
220n

220n
6

3D02-4

3D14-4

3D14-3

3D14-2

3D14-1

2D22

2D26
220n

220n

RES
4K7

22K

22K

22K

22K
FD08
A-PLOP 7 3D02-2 2 2 7D15-1
BC847BS(COL)

1
4K7
1

GND-AUDIO GND-AUDIO

7D10-1
FD03 2D29 ID15 2D23 TPA3123D2PWP

19
20

10
12
1
3
+AUDIO-L
1u0 47n AVCC L R

1
3
PVCC ID32 2D10
Φ

3D02-1
16

4K7
3D02-3 ID19 BSR ID10 5D02 5D05 2D12 RIGHT-SPEAKER
6 3 5 7D15-2 6
BC847BS(COL) ID18
R CLASS-D 15
220n
ID06 ID08

8
4K7 IN R 22u 220R 35V 220u
4 5
L
AUDIO AMP OUT
22
L ID09 5D01 5D04 ID07 2D11
18 LEFT-SPEAKER
0 ID31 2D09
17 GAIN 21 22u ID05 220R
1 BSL 35V 220u
GND-AUDIO 2D16 ID29 220n
11
VCLAMP
2D17 1u0 7
BYPASS
ID30 4
1u0 MUTE
2
AUDIO-MUTE-UP ID37 SD
PGND
FD09 AGND L R
A-STBY GND_HS

8
9

23
24

13
14

25
+3V3-STANDBY
6

8
3D15

4K7
3D01-3

3D10-4

3D10-3

3D10-2

3D10-1

2D21

2D27
220n

220n
6

RES
47K

22K

22K

22K

22K
CD10 FD10
MAINS SWITCH DETECT
7D11-1 2
3

1
BC847BS(COL)
ID34 GND-AUDIO
1 3 +3V3-STANDBY
ID35
3D01-4
7D11-2 5 4 5 DETECT2
BC847BS(COL)
47K
4
GND-AUDIO GND-AUDIO

40
39
38
2D03
100p

GND-AUDIO 7D10-2
TPA3123D2PWP
VIA LEFT-SPEAKER
GND-AUDIO 26 37
GND-AUDIO
27 36
VIA

V_NOM
1D50

2D14
28 VIA VIA 35

10n
29 34
GND-AUDIO GND-AUDIO
VIA
1735 1D38
30
31
32
33
FD05
5D03 1 1
FD06
2 2
220R 3 3

2D01
GND-AUDIO FD02

10n
GND-AUDIO 4

2D13
3 7D03-2 2041145-3

10n
BC847BS(COL) 2041145-4
3D06-3 FD07 3D06-2 5
LEFT-SPEAKER
3 6 7 2
100K 100K
4
RIGHT-SPEAKER
8 3D06-1 1
ID33

V_NOM
100K

1D52
GND-AUDIO
2D02
3D06-4
RIGHT-SPEAKER 4 5
100K 10u
GND-AUDIO 4 2011-05-10

SPB SSB TV550 3 2011-03-09

3139 123 6521 2 2010-12-23


2K11 4DDR BR SD

19112_022_110628.eps
110628

2011-Jul-15 back to
div. table
Circuit Diagrams and PWB Layouts Q552.2L LA 10. EN 136

DC/DC

DC/DC
B03B B03B

5U03 RES

30R
FU05 5U02 IU22
+12V
30R
7U02-1 * 0402 Jumper

2U24

2U23

2U25

2U19

2U20
10u

10u

10u

10u

1u0
SI4952DY
7 8
IU10
2
12V/1V8 CONVERSION

1
3U11

3R3
2U21 FU02 5U00 FU03
+1V8
IU11 220p 3u6

22u
3U23-4

3U23-3

3U23-2

3U23-1

2U15

2U16
47R

47R

47R

47R

47u
7U02-2
SI4952DY

1
5 6
IU09
4 IU23

2U17

1n0
IU15
7U01
SI4778DY

2U18

1n0
3U27 5 6 7 8
IU08 IU12
4
10R 1 2 3
2U00

3U14
10u

3R3
3R3

3U04
2U22
IU06 2U02 IU07
IU05 IU13 220p

3U28

10R
100n
2U01

100n

3R3

7U04
7U03 3U05 SI4778DY
TPS53126PW
5 6 78
IU16
2 23 4
1 1 1 2 3
IU24 11 VBST DRVL 14 IU14
2 2
3 1
12V/1V1 CONVERSION
1 1
ENABLE-1V8 10 EN DRVH 12
2 2
1n0 RES

5U01 FU01
FU06
2U03

+1V1 4 24 +1V1
1 1

STPS2L30A
+1V8 9 VO SW 13

RES 100u 2.0V


2 2 2u0

6U00

2U14
5 22

3U24-4

3U24-3

3U24-2
1 1

3U24-1

3U20

2U12

2U13
RES
8 VFB PGND 15

22u
47R

47R

47R

47R

10R

47u
RES GND-SIG 2 2
7U00 3U02 IU01
BC847BW 21 7
1 1
3 22K 3U03 16 TRIP TEST 17
IU03 2 2
1 IU02
GND-SIG 12K GND-SIG
20 18 FU04 IU17
GND-SIG VIN V5FILT
2 19 IU25
VREG5

2U11

1n0
+3V3-STANDBY 3U00 2U06
+1V1 GND
2U04

2U05
6

10u

1u0

10K 100n
IU18
10K

3U01 GND-SIG

2U09

2U10
1n0

1u0
GND-SIG
3U21 FU00
IU19 SENSE+1V1
100R 1%

3U17

1% 330R

2U29

100n
RES
IU20

100p RES

3U19
2U08

3U18
5K6

1% 1K0
3U08 3U22
IU04
+1V8 FU09 FU08
1K0 1% CU00
330R 1% IU21
RES 100p
1K0 1%
3U09

3U10

2U07

CU01
22K

CU02
GND-SIG GND-SIG GND-SIG
CU03
CU04
CU05
GND-SIG GND-SIG GND-SIG

GND-SIG

4 2011-05-10

SPB SSB TV550 3 2011-03-09

3139 123 65213 2 2010-12-23


2K11 4DDR BR SD

19112_023_110628.eps
110628

2011-Jul-15 back to
div. table
Circuit Diagrams and PWB Layouts Q552.2L LA 10. EN 137

DC/DC

DC/DC
B03C +3V3 +3V3-STANDBY
B03C
LED-2

RES 10K

RES 10K
** Optional table for Ambilight

3U74

3U75
Optional table for Styling
+5V +3V3-STANDBY Items Emmy
( +24V AL)
Sundance / Infinity
( +12V AL)
BlockBuster
(For non-Amblight sets)
***
IU43 2U44 3U43 1M95
9U41 4U00 yes no no
4U01 yes no no
Dream Catcher 0R open

RES 10K
1M99 no yes no 13 POLE

3U68

3U69
10K
1M95 yes yes yes Core Range 100p 100R 14 POLE
IU44 3U41 3U59 2U56 no yes no
IU45 LED2 LED2
optionally 1M99 is a 9 pin connector
* LED-1 9U42
RES
10K RES 10K RES

7U42 RES +3V3


BC847BW
* 7U43
IU47 3U70 LED1 LED1 3U53
BC847BW
** 10K 10K
1M99
1 GND_AL 3U82 IU64
FU48
2
3 GND_AL 1K0 RES
FU49 +12V_AL +3V3 RES 3U56 10K
4 7U48-1
5 GND_AL 3U83-4 BC857BS(COL)
FU50 4 5 ENABLE-3V3-5V

6
6 FU07
FU54 RES 3U44 100R 3D-LR
7 100K
FU77 IU41
8

8
+12VIN

3U83-1
9
RES 3U66 100R

100K
FU56 BL-SPI-SDO

2
10

2U71

100n
FU57
11 100R
FU74 RES 3U67 BL-SPI-CSn

1
12
FU68
13
RES 3U84 100R BL-SPI-CLK
100p

100p

100p

100p

100p

1-2041145-3
RES 2U57

2U56

RES 3U76
1n0

1n0

MAINS-OK
+3V3-STANDBY
RES 2U48

RES 2U72

RES 2U51

100R
RES 2U52

RES 2U43
**

3
3U71 100R STANDBY 7U48-2
BC857BS(COL)

5
5
7U40-2 3U83-3 3U83-2
3 6 7 2

10K
2U68 BC847BPN(COL)
3U62-4 4
IU48 100K IU40 100K

4
1u0
5
2U47

3
3

3U62-3
3 3U60-3 6 FU73 ENABLE-1V8
***

10K
10n IU61
1M95

BZX384-C6V2
22K

RES 10K
7

3U61
FU58 +3V3-STANDBY

6
1 10n

6U40
FU59

10K
2 IU49 3U62-2
FU60
3 2U54 1U40 +12V 6

2
FU61 7U40-1

2
4 +12VIN IU51 FU72

22K
5 FU63 T 3.0A 32V BC847BPN(COL) DETECT2
FU75 2 3U60-2
6 FU66
3U72

1
1K0

+24V-AUDIO-POWER 7U41-2

7
7
2U50

1u0 RES
FU67 3 BC847BS(COL)
10n

8 IU63

5
2U55

9 3U60-1 IU57
ENABLE-3V3n
2U49

3U80
100n

5 8 1

4K7

22K
10 IU62 3U60-4
11 3U73 3U62-1 IU50 22K
IU56 4 IU52

4
12 3U81 +3V3-STANDBY
FU62 +3V3 8 1
10K 6
13 +24V GND-AUDIO 3K3

3U63

RES 10K
10K 7U41-1
14 FU76
BC847BS(COL) 2
3U45
2U58

100n

1-2041145-4 FU51 LAMP-ON 1


100R
FU52 3U42 BACKLIGHT-PWM_BL-VS

FU53
100R
3U43 *** BACKLIGHT-BOOST
100R
** 4U01 IU55
FU55 3U64 POWER-OK
** 4U00 1K0
100p

1n0

10n
2U53

3U65

100K
1n0

GND_AL
2U44

2U45

2U46
***

+12VIN +12VD 4 2011-05-10

SPB SSB TV550 3 2011-03-09

3139 123 6521 2 2010-12-23


2K11 4DDR BR SD

19112_024_110628.eps
110628

2011-Jul-15 back to
div. table
Circuit Diagrams and PWB Layouts Q552.2L LA 10. EN 138

DC/DC

DC/DC
B03D B03D
+3V3
7UC0
LF25ABDT *
+12V 1 3
IN OUT
COM

2UA4

1u0
*

3UA0

2K2

2
FUA0
+2V5-REF
1
7UA0
TS2431 K

R 2
A

3 FUA4
+2V5

CUA0 +2V5-LVDS
IUB6
+5V5-TUN +5V-TUN

7UA6
BC817-25W

330R
1%
3UB6-3 3U12
+12V 3 6 IUB3

2
3UB6-2
1K0 IUB2
7 6
+1V8
* +3V3 * +3V3
3U15-1 3U16-1
1K0 +5V 1 8 +5V 1 8
3UB6-1
1 8 2 IU26 100R 100R
1K0 7UA3
3UB6-4 3U15-2 3U16-2

2UB0
4 5 IUB5 3 1 7UA7-1 PHD38N02LT 2 7 2 7

1u0
BC847BS(COL)
330R
1%

+2V5-REF 1K0
3UB7-4 3U13 100R 100R
5 4 5
3UB0 IUA5 3U15-3 3U16-3
1 2 3 6 3 6
470R
7UA7-2 4 IUB4
BC847BS(COL) 22R 100R 100R
3U15-4 3U16-4
470R

3UB7-1470R

4 5 4 5
FUA3
2

+1V2 100R 100R


3UB7-3
3UB7-2
2UB8

470R
22u

2UB1

2UB2
RES 1u0

1u0
7

NOT FOR 5000 SERIES


*
ENABLE-1V8
3U25-4
4 5
3UB1 SENSE+1V2
100K RES RESERVED
100K RES
7

IUA6 1K0 5UA0


3U25-3 3U25-2
3 6
30R
2

100K RES 3U29-1 RES


1 8 +12V 7UA5
LDS3985M50
470R
IU29 RES
100K RES

3U29-2
1

2 7 +5V5-TUN 1 5 +5V-TUN
IN OUT

4K7
470R 7UA4
3U25-1 3UB2 3 4
TS431AILT INH BP IUB1
3 6 +3V3 3 3U29-3 6 RES
8

RES RES IU30 5 3 COM


470R A K

2UB7

2UB5

2UB6
100n
7U06-2 5 7U06-1 2

1u0

1u0
3U29-4 RES
BC847BS(COL) BC847BS(COL) 4 5 2 1

2
NC NC
4 1

4K7
470R REF
3UB3
1 3U26-1 8 RES
4

470R
3U26-2 RES
2 7
3UB5 3UB4 IUB0 2UB3
470R +5V
3U26-3 RES 100K 1K0 1n0
+3V3 3 6
2UB4
470R
3U26-4 RES 330p
4 5
RES
470R 4 2011-05-10

SPB SSB TV550 3 2011-03-09

3139 123 6521 2 2010-12-23


2K11 4DDR BR SD

19112_025_110628.eps
110628

2011-Jul-15 back to
div. table
Circuit Diagrams and PWB Layouts Q552.2L LA 10. EN 139

DC/DC

DC/DC
B03E B03E
5UD0 IUD0
+12V
30R +5V5-TUN
0402 Jumper
* 7UD0-1

2UD0

2UD1

2UD2
ST1S10PH

10u

10u

10u

6
A

SW
IUD3 5UD1 6UD0 FUD3
ENABLE-3V3-5V IUD7
2 7 +5V
INH VIN SW
3u6 SS36 +1V1

RES 2UE9
5 3

220u 16V
RES 1n0
SYNC VFB

2UD3

2UD4

2UD5

2UD6

RES 2U27

100n
GND

22u

22u

22u
A P HS

9
6

7U05-1 2
IU27
BC847BS(COL)
IUD6 2UD7
RES 1
7UD0-2 4n7

13

15
ST1S10PH

10K
3UD2

3UD0

3UD1
3U06

68K

33K
1%

1%
10 VIA 12
120K

RES
11

14
* * 5UD3 IUD1
+12V
30R
0402 Jumper
* 7UD1-1
2UD8

2UD9

2UE0

ST1S10PH
10u

10u

10u

6
A

SW
IUD4 5UD2 FUD2
ENABLE-3V3-5V 2 7 +3V3
INH VIN SW
3u6 +1V1
5 3

220u 16V
SYNC VFB

2UE1

2UE2

2UE3

2UE4

RES 2U28
1% 100K
3UD3

100n
GND

4n7

22u

22u
A P HS

9
3 BC847BS(COL)

7U05-2 5 IU28
RES
IUD2 4
7UD1-2

13

15
ST1S10PH

10K
3U07

3UD4

3UD5

33K
1M0

1%
10 VIA 12

RES
11
14

7UD2
* 6UD1
LD1117DT25
IUD5
+5V 3 2 +2V5
IN OUT
S1D COM
(*) FOR 5000 SERIES ONLY

22u 16V
2UE5

2UE6
100n

(**) NOT FOR 5000 SERIES


7UD3
LD1117DT33

3 2 +3V3
IN OUT
COM
22u 16V
2UE7

2UE8
100n

4 2011-05-10

SPB SSB TV550 3 2011-03-09

3139 123 6521 2 2010-12-23


2K11 4DDR BR SD

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2011-Jul-15 back to
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Circuit Diagrams and PWB Layouts Q552.2L LA 10. EN 140

Temperature sensor & AmbiLight

Temperature sensor & AmbiLight


B03F B03F

5UM1 IUM0 1UM0 FUM0


+3V3 V-AMBI
30R T 1.0A 63V

4 2011-05-10
3 2011-03-09
SPB SSB TV550
3139 123 65213 2 2010-12-23

2K11 4DDR BR SD

19112_027_110628.eps
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2011-Jul-15 back to
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Circuit Diagrams and PWB Layouts Q552.2L LA 10. EN 141

Fan control

Fan control
B03G B03G

+12V +12V

+3V3

1 3US4-1 8
10K

10K 7
+12V

3US5-2

2US3

100n
10K
3US2 7US1-1
3US7 3
9 LM339P

2
IUS3 3US5-1 IUS6
1K0 14 8 1
FAN-CTRL1 8
10K
7US2
IUT1 12 BC807-25W
+12V IUS7
+3V3

3US9

22R
6
3US5-3
+12V

10K
10K
3US3 3 7US1-2

3
11 LM339P
IUS4 3US5-4
IUT2 13 5 4 BC807-25W
FAN-CTRL2 10 7US3
10K IUS8
12
IUS9

3US6

47R
FAN-DRV

+3V3

+12V

5
IUS5

3US4-4
+12V

10K
6
3US4-3

10K
7US1-3

4
3
5 LM339P
2
TACH01 3 4

12
+12V
RES
9US0

+12V
7
3US4-2

10K

7US1-4
3
7 LM339P
1
2

FUS0
TACH02 6
12

TACHO

4 2011-05-10

SPB SSB TV550 3 2011-03-09

3139 123 6521 2 2010-12-23


2K11 4DDR BR SD

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2011-Jul-15 back to
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Circuit Diagrams and PWB Layouts Q552.2L LA 10. EN 142

Vdisp switch

Vdisp switch
B03H B03H

1 9UU0-1 8
RES
2 9UU0-2 7
RES
3 9UU0-3 6
RES
4 9UU0-4 5
RES
1 9UU1-1 8
RES
2 9UU1-2 7
RES
3 9UU1-3 6
RES FUU0
4 9UU1-4 5
RES

RES
7UU0
SI4835DDY RES
7UU1 +VDISP-INT
+12VD SI3441BDV
RES

RES 2UU2

22n
7UU2-2
PUMD12
3UU3-1
8 1
4
47K RES
RES 3UU1 RES 2UU1 3UU3-2 IUU3
5 2 7
47R 1u0 IUU2 47K RES
3 IUU1
IUU0 RES 3UU0-1 RES
8 1 7UU3
BC847BW
47K

2
6 3 IUU4 3UU3-3 IUU5 3UU3-4

RES 3UU0-2
1 6 3 4 5

47K
RES 3UU0-4 RES +3V3
2 7UU2-1
+3V3-STANDBY 47K RES 47K RES
5 4 PUMD12 2

7
47K

2UU0

RES 100n
1

FUU1
VDISP-SWITCH
3UU2
+3V3
4K7 RES

LCD-PWR-ONn

4 2011-05-10

SPB SSB TV550 3 2011-03-09

3139 123 6521 2 2010-12-23


2K11 4DDR BR SD

19112_029_110628.eps
110628

2011-Jul-15 back to
div. table
Circuit Diagrams and PWB Layouts Q552.2L LA 10. EN 143

10-12 B04 313912365214


Analogue externals A

Analogue externals A
B04A B04A

IE22 3E07-1 FE71


AUDIO-IN1-R
1 1K0 8

CDS4C12GTA
2E06

RES 6E03

1E31

2E88
100p

12V

1n0
FE23 3E07-4
AUDIO-IN1-L
4 1K0 5

CDS4C12GTA
2E04

6E09

1E54

2E91
100p

12V

1n0
1E02-1 IE18
MSP-8032SH-01-NI-FE-RF-PBT-BRF AV1-STATUS
**
RED

RES
1
** 4E01

3E32

4K7
RES
2

1E02-2
MSP-8032SH-01-NI-FE-RF-PBT-BRF
WHITE
3
YPBPR1-PB ** 4E02 AV2-STATUS
FE73 RES
EU 3E74 18R 4 IE05

3E17

4K7
IE53 5E73 BEC3 3E75
AV1-B
1u8
CDS4C12GTA

18R
2E79

2E80

RES 6E23

1E12

2E15
150p

150p

100p
12V

+3V3
RES 1E01-2
MSP-8033SH-02-NI-FE-RF-PBT-BRF
BLUE
** 4E04 3

3E44

4K7
FE74 RES
4

IE48
AV1-BLK
YPBPR1-SYNCIN1 1E01-3
MSP-8033SH-02-NI-FE-RF-PBT-BRF
EU 3E76 18R
GREEN +3V3
5
** 4E05
FE86 RES
5E74 3E77 FE80 6
AV1-G
CDS4C12GTA

1u8 18R
2E83

2E84

3E73
150p

150p

4K7
RES 6E26

1E18

2E14

100p
12V

IE51
RES AV2-BLK

1E01-1
YPBPR1-PR MSP-8033SH-02-NI-FE-RF-PBT-BRF
RED
4E03 1
EU 3E78 18R **
IE55 BEC5 3E79 FE81 RES
5E76
AV1-R 2 CVBS-MON-OUT1
CDS4C12GTA

1u8 18R
2E85

2E86
150p

150p

RES 6E28

1E19

2E12

2E98
100p
12V

18p
FE85

RES
GND_A

3E07-2

2 1K0 7
3E07-3
3 1K0 6

4 2011-05-10

SPB SSB TV550 3 2011-03-09

3139 123 6521 2 2010-12-23

2K11 4DDR BR SD

19112_030_110628.eps
110628

2011-Jul-15 back to
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Circuit Diagrams and PWB Layouts Q552.2L LA 10. EN 144

Analogue externals B

Analogue externals B
B04B B04B
YPBPR SPDIF out
RES
1E07
2 FE54 EU IE71 3E87 FE72 RES
9E29 AV3-Y IE15 MTJ-032-68B-46-NI-FE
5E06 FE59 1
1E08-1 18R SPDIF-OUT
* 1

CDS4C12GTA
MSP-8033SH-05-NI-FE-RF-PBT-BRF YPBPR1-SYNCIN1

CDS4C12GTA
30R 2

2E27

1E43

RES 6E40
100p

12V
YELLOW

RES 2E22

RES 1E44

6E46
RES

12V
10p
4E20
AP 9E04 3E88 IE73
** AV2-CVBS FE41
RES 27R

GND_A
MTJ-032-21B-45 NI FE (PBT) FE51 EU IE74 3E89 IE75
9E57 AV3-PB
2

CDS4C12GTA
1E03 18R
YPBPR1-PB

2E67

RES 6E51
100p

1E28
** 4E21 1

12V
RES

GND_A
FE48 EU 9E58 IE76 3E90 IE77
MTJ-032-21B-42 NI FE AV3-PR
2
1E04 18R

CDS4C12GTA
YPBPR1-PR
2E68

RES 6E52
100p

1E39

12V
** 4E22
RES FE42

GND_A
Provision for
YPBPR AUDIO Dreamcatcher
+3V3
MSP-8033SH-05-NI-FE-RF-PBT-BRF
6 3E97 RES
AUDIO-IN3-R
1E32
CDS4C12GTA

1E08-3 5 FE50 1K0 IE31


* AV3-Y 9E15 RES 1
2E39

1E29

RES 6E06

2E72
100p

AV1-CVBS 9E16 RES 2


12V
1n0

RED
** 4E23 3
RES FE43 4
AV3-PR 9E19 RES 5
RXD1-MIPS 9E12 RES 6
GND_A FE49 IE29 7
4 3E96
AUDIO-IN3-L 8
AV3-PB 9E17 RES 9
CDS4C12GTA

1E08-2 1K0
*
MSP-8033SH-05-NI-FE-RF-PBT-BRF 3 TXD1-MIPS 9E14 RES 10
2E40

1E42

2E71
100p
RES 6E38

11
12V
1n0

RES
4E24 WHITE 12
**
AUDIO-IN3-R 9E11 RES 13
AV1-B 9E18 RES 14
GND_A 15
16
AUDIO-IN3-L 9E13 RES 17
AV1-G 9E20 RES 18
19
VGA ( OR DVI ) AUDIO 20
21
AV1-R 9E22 RES 22
1E09 23
MSJ-035-69A-B-RF-PBT-BRF IE09 24
FE02 3E21
2 AUDIO-IN4-L 25
3 AV1-STATUS 9E24 RES 26
CDS4C12GTA

1K0
1 AUDIO-IN1-R 9E25 RES 27
V_NOM
2E36

1E37

RES 6E19

2E35

100p

AV1-BLK 9E26 RES 28


12V
1n0

29
AUDIO-IN1-L 9E28 RES 30
32 31

DF50-30DP
FE01

FE03 3E20 IE10


AUDIO-IN4-R
CDS4C12GTA

1K0
V_NOM
2E37

1E38

RES 6E20

2E38

100p
12V
1n0

+3V3
3E9C

1R0

1E10
3150-831-030-H1
2
VCC
FE44
1 SPDIF-OPT
VIN
3
GND
CDS4C12GTA

MT
V_NOM

7 6 5 4
2E73

RES 2E77

1E80

RES 6E53
100n

100p

12V

* SOC Cinch V 3P 1L3 YEWHRDY at 1E08 for Brazil

** Provision for ESD 4 2011-05-10

SPB SSB TV550 3 2011-03-09

3139 123 6521 2 2010-12-23

2K11 4DDR BR SD

19112_031_110628.eps
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Circuit Diagrams and PWB Layouts Q552.2L LA 10. EN 145

Ethernet & Service

Ethernet & Service


B04C TXD1-MIPS 7
3E53-2

47R
3E53-3
2

IE50
IE49
1
3E53-1

47R
3E53-4
8

FE57
FE56

2
1E06
UART
B04C
RXD1-MIPS 6 3 4 5 3
1 SERVICE

BZX384-C5V1
5E08 IE07 47R 47R
+3V3 CONNECTOR

BZX384-C5V1
+3V3-ET-ANA

6E43

6E44

1E85

1E86
MSJ-035-69A-B-RF-PBT-BRF
30R
FE58

2E62

2E63

2E66
100n

100n
10u
+3V3-ET-ANA +3V3
+3V3
PROVISION FOR iTV
IE32 IE38 IE06

3E30 IE33
10K
10K
10K
10K

10K

2E52

2E53

2E48
100n

100n

2E49

10u
4n7
1M0
1E70 RES
NX3225GA 1E71
1
TXD 2
3E81
3E82
3E66
3E67

3E33

25M RXD 3

2E54
10p 5 4

10p
7E10-1
+3V3

27

12
LAN8710A-EZK
RES
RES
RES
RES

1
2E55 CR 1A 2A IO 502382-0370
VDD
CLKIN
5
1
4 XTAL 31 ETH-RXP

BAS316
2 P

6E48
RES
RES 2E70 10p RX 30 ETH-RXN provision for iTV
IE26 N
RESET-ETHERNETn 19
RST
29 ETH-TXP
P
ETH-RXD(0) 11 TX 28 ETH-TXN
0 N
ETH-RXD(1) 10 MODE
1
ETH-RXD(2) 9 20 ETH-TXCLK
RMIISEL TXCLK
ETH-RXD(3) 8
PHYAD2

2E69

100n
RES
3E69 10K 26 ETH-RXDV
RXD<0:3> RXDV
3E70 RES
IE63
ETH-COL RES 10K 15 13 ETH-RXER
COL RXER
RES 3E71 10K 3E64 10K RES
CRS_DV RXD4 +3V3
RES 3E80 10K +3V3 7E11-1
MODE2 0 IE64 RES

14

3E9D

3E9E
RES
RES
PHYAD 7 74HC4066PW

10K

10K
1 ETH-RXCLK
ETH-TXEN 21 3E65 10K 1
TXEN RXCLK +3V3 1
RXD-UP 2
RES 1
ETH-TXD(0) 22 3 ETH-REGOFF 13
0 REGOFF X1
ETH-TXD(1) 23 10K 3E34 3E68 10K
1 1 +3V3
24 LED 2 RES

7
ETH-TXD(2) 2 TXD 2 ETH-INTSEL RES RES
ETH-TXD(3) 25 10K 3E72 3E35 10K +3V3 7E12 7E13
3 INTSEL
ETH-TXER 18 RES RES PDTC144EU PDTC144EU
4
14 9E42 ETH-CRS 7E11-2
INT CRS

14
74HC4066PW AV2-BLK
TXER
32 4
RBIAS 1
ETH-MDC 17 IE39 RXD1-MIPS 3 1

1%
MDC

3E40

12K1
ETH-MDIO 16 5
MDIO X1

7
3E51 1K5 +3V3 VSS
33

7E10-2 RES
LAN8710A-EZK 7E11-3

14
74HC4066PW
34 40 8
1
35 41 TXD-UP 9
VIA VIA 1
36 42 6
X1
VIA

7
37
38
39

RES
7E11-4

14
74HC4066PW
11
1
TXD1-MIPS 10
1
12
X1

7
+3V3-ET-ANA +3V3-ET-ANA

CONFIGURATION RESISTOR SETTINGS


1%

1%

1%

1%
49R9

49R9

49R9

49R9
3E22

3E25

3E95

3E99

3E26

3E98
22R

22R

Resistor POP EMPTY

ETHERNET CONNECTOR
1E87 1N00
FE27 3 ACM2012 2
ETH-TXP 1 3E64 (RES) PHYADD(0) = 1 PHYADD(0) = 0
FE60
4 1 2
ETH-TXN FE28
3
FE30
1E88 4 3E65 (RES) PHYADD(1) = 1 PHYADD(1) = 0
3 ACM2012 2 5
ETH-RXP FE29 FE61
6
4 1 7 3E66 (RES) PHYADD(2) = 1 PHYADD(2) = 0
ETH-RXN FE31
8
9 11
CDA5C16GTH

CDA5C16GTH

CDA5C16GTH

CDA5C16GTH
8

10 12 3E67 (RES) RMII mode selected MII mode selected


6E47-1

6E47-2

6E47-3

6E47-4
5E01

5E02

5E03

5E04

RES

2E60
RES
RES

RES
16V

16V

16V

16V
RES 27n

RES 27n

RES 27n

RES 27n

22n

FE34 5450-323-183-H3
3E68 (RES) Internal 1.2V reg. disabled Internal 1.2V reg. enabled
1

4
2E05

2E07

2E08

2E09
RES 15p

RES 15p

RES 15p

RES 15p

3E69 (RES) MODE(0) = 0 MODE(0) = 1

3E70 (RES) MODE(1) = 0 MODE(1) = 1


2E56

2E57

2E58

2E59
15p

15p

15p

15p
0 ohm

0 ohm

0 ohm

0 ohm
3E27

3E28

3E29

3E39

3E71 (RES) MODE(2) = 0 MODE(2) = 1


RES

RES

RES
RES
RES
RES

RES

RES

FE32

3E72 INTERRUPT FUNCTION INTERRUPT FUNCTION


ETH-INTSEL
DISABLED ON ENABLED ON
ETH-REGOFF
FE33 nINT/TXER/TXD4 SIGNAL nINT/TXER/TXD4 SIGNAL

4 2011-05-10

SPB SSB TV550 3 2011-03-09

3139 123 6521 2 2010-12-23


2K11 4DDR BR SD

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Circuit Diagrams and PWB Layouts Q552.2L LA 10. EN 146

HDMI

HDMI
B04D I2C Address B04D
5EC0 FEC0 FEC3 MICOM-VCC33

30R
SII9187B = 0xB2
HDMI CONNECTOR 3 +3V3

2ECV
2EC0

2EC2
RES 2EC1

100n

10K
10u

1u0
220u 16V
1P04 3ECH

1 ARX2+
2 FECB
3 ARX2-
4 ARX1+
5 RES
ARX1- AIN-5V FEC7 5EC3 +3V3
6
7 ARX0+ +3V3-HDMI
8 30R

RES 2ECW
2EC6

2EC7

2EC8

2EC3
100n

100n

100n

100n
10u
9 ARX0-
10 ARXC+

6
3EC1-3
11
ARXC-

47K
12
13 PCEC-HDMI
7EC1

3
14

27
64

37

38
FEC1 SII9187B

9
15 ARX-DDC-SCL ARX-DDC-SCL

MICOM_VCC33

SBVCC33
FEC2 ARX-DDC-SDA ARX-DDC-SDA VCC33
16
17 ARX-HOTPLUG +5V-EDID
FEC4

1
1 8 31

3EC1-1
18 AIN-5V 3ECM-4 IE42 (CBUS) HPD0

6
19 FEC5 ARX-HOTPLUG 4 5 3ECN-1 100K 32

47K

3ECP-1

3ECP-3
AIN-5V R0PWR5V
FEC6 21

10K

10K
20 10R
23 22 ARX-DDC-SDA 1u0 2ECM 29

8
DSDA0
ARX-DDC-SCL 30 49

3
DSCL0 R4PWR5V

ARXC- 65 48
N DSCL4 VGA-SCL-EDID-HDMI
ARXC+ 66 R0XC 47 VGA-SDA-EDID-HDMI
AIN-5V P DSDA4
HDMI CONNECTOR 2
1P03 ARX0- 67 51 9EC2 CEC-HDMI
N CEC_D
BRX2+ ARX0+ 68 R0X0 RES
1 P
2
BRX2- ARX1- 69
3 N
BRX1+ ARX1+ 70 R0X1
4 P
5
BRX1- ARX2- 71
6 BIN-5V N
BRX0+ ARX2+ 72 R0X2
7 P
BRX-HOTPLUG 57 HDMIA-RX2-
8 N
BRX0- 2 7 35 TX2 56 HDMIA-RX2+
9 3ECM-3 IE43 (CBUS) HPD1 P
BRXC+ 3 6 3ECN-2 100K 36
10 BIN-5V R1PWR5V
2

59 HDMIA-RX1-
3ECA-2

11 10R N
BRXC- BRX-DDC-SDA 1u0 2ECN 33 TX1 58 HDMIA-RX1+
12 DSDA1 P
47K

PCEC-HDMI BRX-DDC-SCL 34
13 DSCL1
61 HDMIA-RX0-
7

14 N
FECC BRX-DDC-SCL BRX-DDC-SCL BRXC- 1 TX0 60 HDMIA-RX0+
15 N P
FECD BRX-DDC-SDA BRX-DDC-SDA BRXC+ 2 R1XC
16 P
63 HDMIA-RXC-
17 N
8

FECE BRX0- 3 TXC 62 HDMIA-RXC+


3ECA-1

18 BIN-5V N P
19 FECF BRX-HOTPLUG BRX0+ 4 R1X0
P
47K

FECG 21 3ECJ RES RES


20 MICOM-VCC33
3ECK
23 22 BRX1- 5 55 4K7
1

N TPWR_CI2CA
BRX1+ 6 R1X1 IE12
P 4K7
FECR
BRX2- 7 50 9EC3 PCEC-HDMI
N CEC_A
BRX2+ 8 R1X2 RES
BIN-5V P
CRX-HOTPLUG FECY 3ECL RES
3 6 41 52 +3V3
3ECM-2 IE44 (CBUS) HPD2 INT
HDMI CONNECTOR 1 CIN-5V
2 7 3ECN-3 100K 42
R2PWR5V 4K7
1P02
10R
CRX2+ CRX-DDC-SDA 1u0 2ECP 39
1 DSDA2
CRX-DDC-SCL 40
2 DSCL2
3 CRX2-
CRX1+ CRXC- 11
4 N
CRXC+ 12 R2XC 54 SCL-SSB
5 P CSCL
CRX1- 53 3EC3 100R SDA-SSB
6 CIN-5V CSDA
CRX0+ CRX0- 13 3EC5 100R
7 N
CRX0+ 14 R2X0
8 P
CRX0- 10
9

RES 2ECX

RES 2ECY
15 RSVDL 28

10p

10p
10 CRXC+ CRX1- N
4

CRX1+ 16 R2X1
3ECA-4

11 P
12 CRXC-
47K

FECJ PCEC-HDMI CRX2- 17


13 N
FECA ARC-eHDMI+ CRX2+ 18 R2X2
5

14 P
FECK CRX-DDC-SCL CRX-DDC-SCL DRX-HOTPLUG
15
FECL CRX-DDC-SDA CRX-DDC-SDA 4 5 45
16 3ECM-1 IE45 (CBUS) HPD3
1 8 3ECN-4 100K 46 74
17 DIN-5V R3PWR5V
6

FECM CIN-5V 75
3ECA-3

18 10R
FECN CRX-HOTPLUG DRX-DDC-SDA 1u0 2ECQ 43 76
19 DSDA3
47K

21 20 DRX-DDC-SCL 44 77
FECP DSCL3
23 22 78
3

3E23 +3V3-STANDBY 5EC2


eHDMI+ DRXC- 19 79
N
DRXC+ 20 R3XC 80
RES 22K 30R P
7E02 81
RES
BC847BW ARC-eHDMI+ DRX0- 21 VIA 82
CIN-5V N
DRX0+ 22 R3X0 83
P
84
2ECC

23 85
10p
DRX1- N
7EC0 DRX1+ 24 R3X1 86
P
BC847BW IEC6 87
3ECD
PCEC-HDMI 9EC0 CEC-HDMI DRX2- 25 88
N
IEC4 DRX2+ 26 R3X2 89
100R IEC5 P

EPAD

73
IEC7

FECW
22K

3ECE +3V3-STANDBY

6EC1
7EC1 3ECN 3ECF
+5V +5V-VGA

BAT54 NON-INSTAPORT 9187B 4X 100K 100K BLOCKBUSTER


IE11
INSTAPORT 9287B 4X 100K 100K SUNDANCE
IE65 3ECU-2 +3V3
2 7
4R7

DDCA-SDA
3ECG
10K
IE66 4 3ECU-4 5
3ECF 2ECU DDCA-SCL
FECZ
10K
100K 1u0
4 2011-05-10

SPB SSB TV550 3 2011-03-09

3139 123 6521 2 2010-12-23


+5V-EDID 2K11 4DDR BR SD

19112_033_110628.eps
110628

2011-Jul-15 back to
div. table
Circuit Diagrams and PWB Layouts Q552.2L LA 10. EN 147

Headphone

Headphone
B04E B04E

+3V3-STANDBY

4
PUMD12
5 7EE0-2
A-PLOP
3

6 A-STBY
FEE0
RESET-AUDIO 2 7EE0-1
PUMD12
1

2EE0

47p
3EE1-1
1 8

6
3EE1-2
22K

3EE1-3
22K

22K
3EE1-4
4 5

3
22K
2EE5

47p +3V3

2EE1

100n
7EE1
TPA6111A2DGN
3EE2-3
3 6

8
IEE0 IEE3
Φ VDD
2EE6
33R
FE36
ADAC(3)
2EE3 IEE1
8
3EE0-1
1 2 AMPLIFIER 1
IEE7
4
3EE2-4
5 AMP1
1 1
IEE2 1u0 2EE4 10K 3EE0-4 IN- 4V 100u 33R
ADAC(4) 5 4 6
2 VO
1u0 10K IEE4 2EE7 IEE8 3EE2-2 FE35
5 7 2 7 AMP2
SHUTDOWN 2
2EE2 IEE6
IEE5 4V 100u 33R
3 10
BYPASS 3EE2-1
VIA 11 1 8
1u0
GND GND_HS
33R
4

A-PLOP 3 3EE0-3 6
10K
3EE3
RES

22K

4 2011-05-10

SPB SSB TV550 3 2011-03-09

3139 123 6521 2 2010-12-23

2K11 4DDR BR SD

19112_034_110628.eps
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Circuit Diagrams and PWB Layouts Q552.2L LA 10. EN 148

10-13 B05 313912365214


DDR

DDR
B05A +1V8 DDR2-VREF-DDR +1V8 DDR2-VREF-DDR
B05A

2B08
100p

100n
2B36
2B40

2B00

2B01

2B02

2B03

2B04

2B05

2B06

2B07
100n

100n

100n

100n

100n

100n

100n

100n
47u

2B17

2B37
100n

100p
2B41

2B09

2B10

2B11

2B12

2B13

2B14

2B15

2B16
100n

100n

100n

100n

100n

100n

100n

100n
47u
7B02

H9

C1
C3
C7
C9
A1
E9

E1

A9

E2
L1
EDE1108AGBG-1J-F 7B03

H9

C1
C3
C7
C9
A1
E9

E1

A9

E2
L1
VDDL VREF EDE1108AGBG-1J-F
VDD VDDQ
DDR2-A0 H8 VDDL VREF
AT T-POINT DDR2-A1 H3
0
Φ DDR2-A0 H8
VDD VDDQ

3B22
DDR2-A2 H7
1
2 SDRAM 0
C8 2
3B00-2
7 DDR2-D16 DDR2-A1 H3
0
1 Φ 3B04-2
J2 C2 3 6 3B02-3 33R H7 C8 2 7
DDR2-CLK_P DDR2-A3 3 1 DDR2-D17 DDR2-A2 2 SDRAM 0 DDR2-D24
240R DDR2-A4 J8 D7 33R 3 6 3B00-3 DDR2-D18 DDR2-A3 J2 3B05-3
C2 3 6 33R DDR2-D25
4 2 3 1
DDR2-CLK_N DDR2-A5 J3 D3 1 8 3B02-1 33R DDR2-D19 DDR2-A4 J8 D7
3B04-3 3 6 33R DDR2-D26
5 3 4 2
DDR2-A6 J7 DQ D1 33R 2
3B02-2 7 DDR2-D20 DDR2-A5 J3 D3 33R 33R 2 7 3B05-2 DDR2-D27
3B27 6 A 4 5 3
DDR2-CLK_P DDR2-A7 K2 D93B00-4 4 5 33R DDR2-D21 DDR2-A6 J7 DQ D1 1 8 3B05-1 DDR2-D28
7 5 6 A 4
DDR2-A8 K8 B1 3B02-4
33R 4 5 DDR2-D22 DDR2-A7 K2 D93B04-4 4 5 33R DDR2-D29
240R 8 6 7 5
DDR2-CLK_N DDR2-A9 K3 B9 3B00-11 8 33R DDR2-D23 DDR2-A8 K8 B1 33R 4 5 3B05-4 DDR2-D30
9 7 8 6
DDR2-A10 H2 33R DDR2-A9 K3 B93B04-1 1 8 33R DDR2-D31
3B28 10 9 7
DDR2-CLK_P DDR2-A11 K7 DDR2-A10 H2 33R
11 10
DDR2-A12 L2 B7 3B12 DDR2-DQS2_P DDR2-A11 K7
240R 12 11
DDR2-CLK_N DDR2-A13 L8 DQS A8 3B13 33R DDR2-DQS2_N DDR2-A12 L2 B7 3B14 DDR2-DQS3_P
13 12
2B44 DDR2-A13 L8 DQS A8 3B15 33R DDR2-DQS3_N
33R 13
DDR2-BA0 G2 RES 2p2 2B45 RES
0 33R
DDR2-BA1 G3 A2 DDR2-BA0 G2 2p2
1 BA NU|RDQS 0
DDR2-BA2 G1 DDR2-BA1 G3 A2
2 1 BA NU|RDQS
DDR2-ODT DDR2-BA2 G1
2
3B01 RES F9 DDR2-ODT
ODT
DDR2-CLK_P 240R E8 3B03 RES F9
ODT
DDR2-CLK_N F8 CK DDR2-CLK_P 240R E8
DDR2-CKE F2 DDR2-CLK_N F8 CK
CKE
DDR2-CS G8 DDR2-CKE F2
CS CKE
DDR2-RAS F7 L3 DDR2-A14 DDR2-CS G8
RAS CS
DDR2-CAS G7 NC L7 DDR2-RAS F7 L3 DDR2-A14
CAS RAS
DDR2-WE F3 DDR2-CAS G7 NC L7
WE CAS
DDR2-DQM2 3B23 B3 DDR2-WE F3
DM|RDQS WE
DDR2-DQM3 3B24 B3
33R VSS VSSQ DM|RDQS
VSSDL 33R VSS VSSQ

A3
E3
J1
K9

E7

A7
B2
B8
D2
D8
VSSDL

A3
E3
J1
K9

E7

A7
B2
B8
D2
D8
+1V8
+1V8

DDR2-VREF-DDR
DDR2-VREF-DDR

2B26

2B38
100n

100p
2B42

2B18

2B19

2B20

2B21

2B22

2B23

2B24

2B25
100n

100n

100n

100n

100n

100n

100n

100n

2B39
47u

2B35

100p
100n
2B43

2B27

2B28

2B29

2B30

2B31

2B32

2B33

2B34
100n

100n

100n

100n

100n

100n

100n

100n
47u
7B00
H9

C1
C3
C7
C9
A1
E9

E1

A9

E2
L1

EDE1108AGBG-1J-F 7B01

H9

C1
C3
C7
C9
A1
E9

E1

A9

E2
L1
VDDL VREF EDE1108AGBG-1J-F
VDD VDDQ
DDR2-A0 H8 VDDL VREF
Φ
0 VDD VDDQ
DDR2-A1 H3 DDR2-A0 H8
DDR2-A2 H7
J2
1
2 SDRAM 0
C8
C23B08-4 4 5
2
3B07-2
7
33R
DDR2-D0 DDR2-A1 H3
H7
0
1 Φ C8 2 3B10-2 7
DDR2-A3
3 1
33R
DDR2-D1 DDR2-A2
2 SDRAM 0
DDR2-D8
DDR2-A4 J8 D7 3 6 3B07-3 DDR2-D3 DDR2-A3 J2 C2
3B11-3 3 6 33R DDR2-D14
4 2 3 1
DDR2-A5 J3 D3 3B08-2 2 7 33R DDR2-D2 DDR2-A4 J8 3B10-3 33R 3
D7 6 33R DDR2-D10
5 3 4 2
DDR2-A6 J7 DQ D1 33R 1 8 3B08-1 DDR2-D4 DDR2-A5 J3 D3 2 7 3B11-2 DDR2-D11
6 A 4 5 3
DDR2-A7 K2 D9 3B07-4 4 5 33R DDR2-D5 DDR2-A6 J7 DQ D1 1 8 33R DDR2-D12
7 5 6 A 4
DDR2-A8 K8 B1 33R 3 6 3B08-3 DDR2-D6 DDR2-A7 K2 D93B10-4 4 5 3B11-1 33R DDR2-D13
8 6 7 5
DDR2-A9 K3 B9 3B07-1 1 8 33R DDR2-D7 DDR2-A8 K8 B1 33R 4 5 3B11-4 DDR2-D9
9 7 8 6
DDR2-A10 H2 33R DDR2-A9 K3 B9 3B10-1 1 8 33R DDR2-D15
10 9 7
DDR2-A11 K7 DDR2-A10 H2 33R
11 10
DDR2-A12 L2 B7 3B16 DDR2-DQS0_P DDR2-A11 K7
12 11
DDR2-A13 L8 DQS A8 3B17 33R DDR2-DQS0_N DDR2-A12 L2 B7 3B18 DDR2-DQS1_P
13 12
2B46 RES DDR2-A13 L8 DQS A8 3B19 33R DDR2-DQS1_N
33R 13
DDR2-BA0 G2 2p2 2B47 RES 33R
0
DDR2-BA1 G3 A2 DDR2-BA0 G2 2p2
1 BA NU|RDQS 0
DDR2-BA2 G1 DDR2-BA1 G3 A2
2 1 BA NU|RDQS
DDR2-ODT DDR2-BA2 G1
+1V8 2
3B06 RES F9 DDR2-ODT
ODT
DDR2-CLK_P 240R E8 3B09 RES F9
ODT
DDR2-CLK_N F8 CK DDR2-CLK_P 240R E8
DDR2-CKE F2 DDR2-CLK_N F8 CK
CKE
DDR2-CS G8 DDR2-CKE F2
CS CKE
180R 1%

DDR2-RAS F7 L3 DDR2-A14 DDR2-CS G8


RAS CS
DDR2-CAS G7 NC L7 DDR2-RAS F7 L3 DDR2-A14
3B20

CAS RAS
DDR2-WE F3 DDR2-CAS G7 NC L7
WE CAS
DDR2-DQM0 3B25 B3 DDR2-WE F3
DM|RDQS WE
DDR2-DQM1 3B26 B3
FB00 33R VSS VSSQ DM|RDQS
VSSDL
DDR2-VREF-DDR 33R VSS VSSQ
A3
E3
J1
K9

E7

A7
B2
B8
D2
D8

VSSDL

A3
E3
J1
K9

E7

A7
B2
B8
D2
D8
180R 1%
3B21

1X20 1X21 1X22 1X23 1X24


HOOK1 HOOK1 HOOK1 HOOK1 HOOK1

4 2011-05-10

SPB SSB TV550 3 2011-03-09

3139 123 6521 2 2010-12-23

2K11 4DDR BR SD

19112_035_110628.eps
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Circuit Diagrams and PWB Layouts Q552.2L LA 10. EN 149

10-14 B06 313912365214


Display interfacing-Vdisp

Display interfacing-Vdisp
B06A B06A

1G03

T 3.0A 32V

5G01 1G00 FG0H


+VDISP-INT +VDISP
30R T 3.0A 32V

2G43

100n
RES RES
5G02

30R
RES

2G44

RES
22u
RES IG11 RES
3G28 6G00
2K2 LTST-C190KGKT
For Development use only

4 2011-05-10

SPB SSB TV550 3 2011-03-09

3139 123 6521 2 2010-12-23

2K11 4DDR BR SD

19112_036_110628.eps
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2011-Jul-15 back to
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Circuit Diagrams and PWB Layouts Q552.2L LA 10. EN 150

Video out - LVDS

Video out - LVDS


B06B B06B

+3V3

10K

10K

10K
+VDISP

47p

47p

47p

47p

47p

47p

47p

47p

47p

47p
RES

2G7A
2G77

2G75

2G76

2G78

2G79

2G24

2G25

2G26

2G27
RES 3G33

RES 3G34

RES 3G35
FI-RE51S-HF

5
6
7
8
9G0K-4
9G0K-3
9G0K-2
9G0K-1
60 61
58 59
56 57
54 55
4
3
2
1 CTRL-DISP RES 3G32 100R FG34 52 53
2G92 100n SDA-DISP 3G2W 51
FI-RE41S-HF 100R FG2H
50
50 51 SCL-DISP 3G2Y 100R FG2G
100n 49
2G93 48 49
48
46 47 CTRL-DISP RES 3G38 100R FG35
100n FG2J 47
2G94 44 45 BACKLIGHT-BOOST RES 3G37 100R FG2R
46
42 43
100n FG2K 45
2G95 FG30 3D-LR RES 3G2Z 100R
41 44
FG31 CTRL-DISP FG04 RES 3G30 100R FG2L
40 43
FG32 CTRL-DISP RES 3G31 100R FG2M
39 42
FG33 3D-VS-DISP RES 3G36 100R
47p 38 41
2G96 PX1A- FG2E
47p 37 40
2G99 PX1A+ FG2F
47p 36 FG1Y 39
2G97 PX1B-
47p 35 38
2G98 PX1B+ FG1Z
34 FG20 37
33 PX1C- 36
PX3A- FG1C PX1C+ FG21
32 35
PX3A+ FG1D
FG1E 31 34
PX3B- PX1CLK- FG22
30 33
PX3B+ FG1F PX1CLK+ FG23
29 32
PX3C- FG1G
28 31
PX3C+ FG1H PX1D- FG24
27 30
PX1D+ FG25
FG11 26 29
PX3CLK- 25 PX1E- FG26 28
PX3CLK+ FG1J PX1E+ FG27
24 10p 27
2G28
FG1K 23 2G29 10p 26
PX3D- 22 25
PX3D+ FG1L PX2A- FG28
21 24
PX3E- FG1M PX2A+ FG29
20 23
PX3E+ FG1N PX2B- FG2A
19 22
PX2B+ FG2B
18 21
PX2C- FG2C
17 20
PX4A- FG12 PX2C+ FG2D
16 19
PX4A+ FG13 15 18
PX4B- FG14 PX2CLK- FG1R
14 17
PX4B+ FG15 13 PX2CLK+ FG1S 16
PX4C- FG16 12 15
PX4C+ FG17 PX2D- FG1T
11 14
PX2D+ FG1U
FG18 10 13
PX4CLK- PX2E- FG1W
9 12
PX4CLK+ FG19 PX2E+ FG1V
8 11
7 10
PX4D- FG1A
6 FG2P 9
PX4D+ FG1B
5 8
PX4E- FG1Q
4 7

2G91

100n
PX4E+ FG1P
3 6
+VDISP RES 9G0G FG2N
2 5
1 4
3
1G50
2
1

TO DISPLAY 1G51

TO DISPLAY

1X05
REF EMC HOLE

4 2011-05-10

SPB SSB TV550 3 2011-03-09

3139 123 6521 2 2010-12-23


2K11 4DDR BR SD

19112_037_110628.eps
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Circuit Diagrams and PWB Layouts Q552.2L LA 10. EN 151

AmbiLight CPLD

AmbiLight CPLD
B06C B06C
5GA0 FGA0
+3V3 VINT
30R

2GA0

2GA1

2GA2
100n

100n
1u0
DEBUG ONLY

5GA1 FGA1
+3V3 VIO
+3V3
30R
2GA3

2GA5

100n
1u0

RES
1G37

3GA4

RES
10K
+3V3 1
2
GCK3 3GA5-4 4 5 100R RES 3
GTS1 3GA5-3 3 6 100R RES 4
GTS2 3GA5-2 2 7 100R RES 5
GSR 3GA5-1 1 8 100R RES 6

2GA6

RES
10p
VINT VIO SD51022

7GA0

15
35

26
XC9572XL-10VQG44C0100
VCCINT Φ
VCCIO AMBI-SPI-CLK-OUT-R IGA1
PXCLK54 43 AMBI-SPI-SDI-OUT_G1-R CPLED2
IXO1_43|GCK1
GCK2 44 AMBI-SPI-SDO-OUT-R
IXO1_44|GCK2
GCK3 1 IGA2
IXO1_1|GCK3
CPLED3
2 5 PNX-SPI-CSBn
IXO1_2 IXO3_5
PNX-SPI-CS-BLn 3 6 9GA1 RES BACKLIGHT-PWM IGA3
IXO1_3 IXO3_6
PNX-SPI-SDO 39 7 3D-LR GCK2
IXO1_39 IXO3_7
PNX-SPI-SDI 3GA3 33R 40 8 3D-VS-DISP +3V3
IXO1_40 IXO3_8
PNX-SPI-CLK 41 IXO3_12 12 BL-SPI-SDO
IXO1_41
42 13 BL-SPI-SDI 3
IXO1_42 IXO3_13
14 BL-SPI-CSn RES
IXO3_14
GTS1 36 16 3GA1 RES BACKLIGHT-PWM_BL-VS GCK3 5 7GA1-2
IXO2_36|GTS1 IXO3_16
GTS2 34 18 47R BL-SPI-CLK BC847BS(COL)
IXO2_34|GTS2 IXO3_18
GSR 33 4
IXO2_33|GSR
AMBI-SPI-CS-OUTn_R2-R 19 4 5 AMBI-PROG_B1 +3V3
IXO4_19
AMBI-PWM-CLK_B2 29 20 3G10-4 33R 3 6 AMBI-BLANK_R1
IXO2_29 IXO4_20
AMBI-SPI-CS-OUTn_R2 8 1 3G14 33R 30 21 2 7 3G10-3 33R AMBI-SPI-CS-EXTLAMPSn 6
IXO2_30 IXO4_21
AMBI-LATCH1_G2 3G11-1 33R 6 3 31 22 3G10-2 33R AMBI-SPI-CLK-OUT RES
IXO2_31 IXO4_22
AMBI-TEMP 3G11-3 33R 32 23 3G13 33R AMBI-SPI-SDI-OUT_G1 GTS1 2 7GA1-1
IXO2_32 IXO4_23 BC847BS(COL)
CPLED3 37 27 3G12 10R 1 8 AMBI-SPI-SDO-OUT
IXO2_37 IXO4_27
CPLED2 38 28 4 5 3G10-1 33R AMBI-LATCH2_DIS 1
IXO2_38 IXO4_28
3G11-4 33R +3V3
11
TCK
9 3
TDI
2G10

2G11

2G12

2G13

2G14

2G15

2G16

2G17

2G18

2G19
24
10K

10p

10p

10p

10p

10p

10p

10p

10p

10p

10p
TDO RES
3G15 10 GTS2 5 7GA2-2
TMS
BC847BS(COL)
GND 4
+3V3
4
17
25

+3V3

6
RES
GSR 2 7GA2-1
BC847BS(COL)
1

7 330R 2

8 330R 1

5 330R 4

6 330R 3
DEBUG ONLY

3GA6-2

3GA6-1

3GA6-4

3GA6-3
RES

RES

RES

RES
RES RES
1G35 1G36
1 RES 3GA2-1 1 8 100R 1 FGA6
2 RES 3GA2-2 2 7 100R 2 FGA4

LTST-C190KGKT

LTST-C190KGKT

LTST-C190KGKT

LTST-C190KGKT
3 RES 3GA2-3 3 6 100R 3 FGA5
4 RES 3GA2-4 4 5 100R 4 FGA3
5 5 FGA2
6 6

6GA0

6GA1

6GA2

6GA3
RES

RES

RES

RES
+3V3
7 8
100n RES

SD51022
2GA4

BACKLIGHT-PWM 9GA0 BACKLIGHT-PWM_BL-VS

4 2011-05-10

SPB SSB TV550 3 2011-03-09

3139 123 6521 2 2010-12-23


2K11 4DDR BR SD

19112_038_110628.eps
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2011-Jul-15 back to
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Circuit Diagrams and PWB Layouts Q552.2L LA 10. EN 152

SPI buffer

SPI buffer
B06D B06D

RES
+3V3
+3V3

RES

3GE2
7GE1

RES

10K
2GE0

100n
RES
PDTC114EU

RES
7GE0 PNX-SPI-CSBn

20
74LVC245A
1
3EN1
3EN2 IGE0
19
G3
3GE0-3
PNX-SPI-CLK 18 2 3 6 RES BL-SPI-CLK
1
2 47R 3GE0-1
17 3 1 8 RES BL-SPI-SDO
PNX-SPI-SDO 16 4 3GE1-3 6 3 RES 47R AMBI-SPI-CLK-OUT-R
15 5 47R 5 4 3GE1-4 AMBI-SPI-SDO-OUT-R
AMBI-SPI-SDI-OUT_G1-R 14 6 3GE3 47R RES PNX-SPI-SDI
BL-SPI-SDI 13 7 3GE4 47R RES
12 8 RES
47R
11 9

10
RES
PNX-SPI-CLK 8 9GE0-1 1 BL-SPI-CLK

RES
PNX-SPI-SDO 7 9GE0-2 2 BL-SPI-SDO

BL-SPI-SDI RES 9GE1 PNX-SPI-SDI

RES 9GE2
RES *
5 9GE0-4
PNX-SPI-CS-BLn IGE1
** 4 BL-SPI-CSn

Buffer
*
Direct
**

4 2011-05-10

SPB SSB TV550 3 2011-03-09

3139 123 6521 2 2010-12-23


2K11 4DDR BR SD

19112_039_110628.eps
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2011-Jul-15 back to
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Circuit Diagrams and PWB Layouts Q552.2L LA 10. EN 153

10-15 B09 313912365214


Connectors comp

Connectors comp
B09A B09A
5C55 FC67 +3V3

30R
1M59
FC70
AMBI-SPI-CLK-OUT 1

3C74

100K
RES
2
AMBI-SPI-SDO-OUT FC71 3
AMBI-SPI-SDI-OUT_G1 FC72 4
2C76
V-AMBI 5
AMBI-PWM-CLK_B2 FC73 6 FC87 3C75 100p
7 LIGHT-SENSOR
AMBI-SPI-CS-OUTn_R2 FC74 8
2C93 100R 2C77
AMBI-LATCH1_G2 FC75 9
10
TO
V-AMBI 47n RES 3C76 100p
AMBI-BLANK_R1 FC77 11 RC LED PANEL**
AMBI-PROG_B1 FC76

BZX384-C5V6
12 IC73 100R 2C78

6C02
AMBI-LATCH2_DIS FC78 13 1M19

RES
FC88
AMBI-TEMP 3C70 100R FC79 14 IC74 3C77 100p 1
15 LED-2 FC89
2
16 FC90
FC81 100R 3
17 FC91
4
2C70

100n
18 +3V3-STANDBY FC92
5
19 2C79 FC93
GND_AL 6
20 FC94
7
* FC82
21
22 LED-1
IC75 3C78 100p +5V 8
FC83 1C86
AMBI-POWER 23
+24V 100R 2C80

2C81

100n
24
T 2.0A 63V
25
100p
26 FC95 3C79
* 1C87

2C94

2C95

RES
100n

100n
27 28 KEYBOARD

RES
FC84 10R

6C03 RES
100p

BZX384-C5V6

BZX384-C5V6
+12V_AL 2C96
T 2.0A 63V FH34SRJ-26S-0.5SH(50)
2C82

6C05
100n
RES

GND_AL GND_AL

RES 3C96 **
+3V3-STANDBY
Option table for Ambilight
* +T 0R3
1
1M20

ITEMS BLOCKBUSTER EMMY SUNDANCE 1 9C02-1 8 2


/ INFINITY 2 9C02-2 7 3
3 9C02-3 6 4
4 9C02-4 5 5
1C86 N Y N 6
3C97
+5V 7
1C87 N N Y 8
+T 0R3
SCL-SET 9C00 3C94 47R FC65 9
RES 10
RES
SDA-SET 9C01 3C95 47R FC66 11
+3V3 * RES 3C90
10K * iTV
RES
RES
12

FC61
FAN-CTRL1 * RES 3C91
100R
FH52-11S-0.5SH

FC62

2C87 RES
RES 3C80

2C86 RES
TACH01
100R RES

2C90

2C91
1M71

10p

10p

1u0

1u0
FC85 RES3C81 100R FC96
SCL-BL 1

**
**
FC63 RES 3C82 FC97 2
TACH02 FC98
3
100R 4
FC86 RES 3C83
RES 2C83

RES 2C84
100p

100p

SDA-BL 2041145-4
100R
FC64 TEMPERATURE
FAN-CTRL2 * RES 3C92 SENSOR
100R Option table for Leading Edge
+3V3 * RES 3C93 **
10K Items BlockBuster / Emmy Sundance / Infinity
FAN-DRV FC99
1M19 Yes No
RES 5C54
RES 2C85

1u0

+3V3
30R
1M20 No Yes
T 1.0A 63V
RES
1C85

RES 5C53
+12V IC78 RESERVED 4 2011-05-10
30R 3 2011-03-09
SPB SSB TV550
3139 123 6521 2 2010-12-23

2K11 4DDR BR SD

19112_040_110628.eps
110628

2011-Jul-15 back to
div. table
Circuit Diagrams and PWB Layouts Q552.2L LA 10. EN 154

10-16 313912365214 SSB Layout


Overview top side

1M95 1M99 1F24 1M71 1M59

2C84

3C83
1C85

1C86
1C87
4U01

4U00

2U58

2U53

3U64

3U65

2U44

3U43

2U45

2U46

2U49

3U45

3U81

3U76

2U48

2U72

3U84

2U51

3U67

2U52

3U66

2U50

2U43

3U44

3U56

2U56
3U71 2U54 2U68 2U47

3G13

2G16

3G12

3G14
3C82

3C92

3C81

5C55
3US6
3US9
3G11

2C95

2C94
5C54

2C85

3C70

2C96
3U42
3G10

3C93

2C83

3C91

3C80
5C53

2C70
1UM0
3C90
3GA1 9GA0

5U02

5U03
2U24
2U23
2U25
2U20
IUT1

2U19

6GA1

6GA0

6GA3

6GA2
IU15
5UM1

7US2
7US3
IUS9 3US2

2U17

2U18
IUS5 3US7

IUT2

7US1
3US3
3GA6
1G37

3US4
9US0
7U01 7U04 7U02
IU23

2US3
3US5 IUS6
IUS4

3U23
IUS3

7GA0

7GA2
3GA5
7GA1
IU18

5U00
2U11 3U24

6U00
1G36

2U09

2U15
2U16
IU17
2UB2

2UB1 IGA3

5U01
3GA2

7UA3
1G50
IGA2

3B11
1G35

2UE8
IGA1

3UB0

3UB3

3UB2

2UE6
3B26

7B01

2UB3

2UB4
2UB0
3B18
7UA4 2GA4

2B47
3B19
3UB4
2UE3
3UB5 3UB1

2G98
2UE2
2G97

2S4P
2G99

7F20

3B10
2UE4
2G96

2D19

2UD6
9S90

9S91

9S92

9S93
3B08
2UE0 IUD1

7B00
3B25

5D08
IUD4

7UD1
3UD4
3B16

2B46
5UD2
3UD5
3B17

2D05
2UE1 IUD2

3B07
3UD3

2U28

3U07
2UD8

7U05
2UD9

3F11

3F08
9S00
5UD3

2UE9
3S3Y
3U06

6UD0
2D20
2U27

3F10

3F09
2UD0 IUD0

3S28

3S29

3S24
3S23
3S62

3S3Q
3B02
3S21
2UD3

7UD0
7B02 5UD1
3S3S

2UD5
2UD4
3UD2
3S1K
2S4E
2UD7
3B23
3S1J 3S1B

3S3R

3S2A
3UD1
3B12 3S3T

2B44

2S4D

3S1L

9F28
3S3N 3UD0
3B13
9F27 2UD1
3S1C

3B00
5D07
3S3L
2UD2
5UD0

3S6K
3B05
1D50

IF62
1735 1D38

2D17

2D23
2D24

3S81
2D08

3S80

3S6N
3B24
2D07

2S4F 3S52

7B03

3S3F
BS15 DS50
3B15 3S54

2B45
2S4G

3B14 3S50

1S02
3S3M
3S43

DBS8

7S00
3S44
1D52

7D10

3S3H

3S3U
9S06
3S3G

3B04

3S2M
3S00

2S2W
2S2Z
3S6H

2S33
2S30

3S42
3E17 3S3W
2S2R

1P09
3S27
IS13
2D09

2S2V
2S2Y
2S2T
2S34

2S32
2S31
3S26

7S08
2D10

2S7M

2F40

4S14
3S6J

2S7K

2S7H

2S7R
2S7E
BS10

2D06 2S77

3S4J 2S7J

2S8G
2S7U

2S7N
2S7P

2S7L

2S87
2S78

3S4L

3S4K

9S21

9S19
2S2S

3S4R
3S4P
3S4T

9S20

9S18

3S59
3S53 3S84
3S13
3S83

2S41
3S12 BS13

1F10
2D12 2D11

2S4M
5D02 5D01

IF61

2F58
3F59
7F58 3F60
9FLH 9FLC

9FLJ 9FLD

3F58
9E20

5D04 3E32 9E18

1F75

1E06 1E71
9E24

4E03

4E02
9E22
6F72 3F78
7F70 3FLE
1FL5

2F92 2F94
2F90 3F71
2FL6 2FL7

2F91
3F72
1E31
IF89
5F70
1P08
1E19

1E86
1E54
1E18
1G51

1E12

7FL5
2F9D

2G29

2G28
5D05
1E02 1E01
1E85

IF86

9F00 9F01
9F05 9F06
5F73

9FLG

9FLF
9FLL
3FL7

9FLK
3FLC
3F34

9FL3
9F04
9FLE
2F9C
2E48

2F93
3E69

3E70

3E67

3E66

3E65
3E71

3E80

9E42

3E64

2E49

3FL4

1E32

2F88
2G7A
4E04

4E05

4E01
3E87

1F51
3E88
2G79

2F9B
2E53 3E97 9E29
9E04

2G24
2E52
6E40

5F72
IE09

9F71
9E11

2E72

6E06

2G25

4E23
3E51
4E22
3E96

6E38

3F65
3F64
2E27
1E70

1P07
2G26
2E39

3G38 2E55

3FL2
2E36
2E40

3E33
9E13

2E71

7E10
2G78
3E30

3F75
2G27
6E19 IE10

2F86
2E35

2E38
2E54
2G76 3E21

1328
1E09
2F9A
2G75

3E20
1E37

2E37
2G77 IE07 3E34 3E68 2F99
3E35
1E29 1E42

1E08
1E43

1E03 1E04
2C76

6E20
3E72

3E25 3E22

2FDD
3E40

3C75 3C74 2E63


2E66

6FD3

1FD3
1E38
7EE0

2E57 2E56
6C02

3FDG
1T01
1M19

2E07
5E02 5E01 IE11
1E39

2C77 3C76 2C93


1E28

3E28
2E62

6FD2

1FD2
1M20

2E05

2FDC
2C80 3C78 IC75
1E88

1E87

3ECG

2F98
2C78 3C77
6EC1
3E27

6E47
3C96

9E15
5E08

3E98

3E26

2E60

6C03 2ECU
3ECF
6E51

3EC3
2EE6

2C82 3C79 IC74 3ECP


1F52
2E67

3EC5
4E24

6C05
4E21

1329
4E20

9E17 3E89
9E57

9C02 3ECN IE42

1P05
2C91 2C90
3EE3

3F623F63
IEE4 IEE6
3C97

3C94 2EE3
2EE4

IEE5

2ECN

7EC1
2C86
2ECP

2EE7
2F60

2EC1
2EE2
3EE0

2C87 3C95
2ECM 6FC7
2F97
6FC5

7EE1

2F81
2EE0

3ECM
3EE1

6FC3
2EE5

3FC4
2E77
2E22

2E73
5E06

2C81
6E46 6FC4
3EE2 2EE1
IEE3

3FC3
6E53 3E9C
3U68

6FC2
1E44
7U43
3U70

1E80

6FC1

3FC5
3FC7

3FC6
9FC5
9EC3 5EC2 2ECC
3U69 9U42 3U53 9FC3 9FC6
6FC6

1N00

2FC3

2FC4

2FC2

2FC1

2FC6

3FC1
2FC5
1E10
3U75 9U41 3U59 2FC7 6FC8
3FC2 9FC4
3U41

3U74

2FC8

7U42
1FC6 1FC3 1FC4 1FC2

1FC1
1E07

1P04 1P03 1P02

1FC5
1E05
4 2011-05-10

SSB Layout Top


3139 123 6521

19112_041_110628.eps
110628

2011-Jul-15 back to
div. table
Circuit Diagrams and PWB Layouts Q552.2L LA 10. EN 155

Overview bottom side

CXXX

FC81

FC67
FC96 3FLJ
FL38

FC78
FC71
FC82

FC79
9FL1 9FL2

FC75 FC99
FC76 FC77

2G13

2G14
FC98
FC97 IC78

2G11

2G10

2G17

2G18

IU56
FC73 FC70

2G19

2G15

2G12

3U01

3U00
FU48 FU50 FU49 FU54 FU77 FU63 FU75 FU56 FU57 FU74 FU68 FU09 FU08

CU00
FU58 FU59 FU60 FU61 FU66 FU67 FU51 FU52 FU53 FU55 FU62 FU76
FC84
FC72
3UU0
FC83 3U72 2U57

3U08

3U22

2U07

3U10

IU55
FC74

FU07

7UU2
2U03

3U09

3U18

2U08

3U19
2U06 IU03

FUM0
FC62 FC61
FC63
FC64

6U40 1U40 FU01


IU04
IU20
3U17 FS2W FS2Y
IUU3
FUU1

7U00 IU06

IU51
3UU2

7U40
IU08

3U27

IU13
IU22 IU05
7UU3

IUU0
2GA2 3GE1 3GE0 IU24 2U02
IUM0 IUU4
IU49
IUS7 3U04 2U01
FGA5 3U14 IU07

2U22

3U05
7U03
3UU1
IU16

3GA4

2GA6
2U21 IU11
2U55
IU12 IUU1 3UU3 2UU0
FG2J
2UU1
IUS8
3U62 IU48

3U11

3U28
IU63

7GE0
2GA5

2GA3
FUS0 FU05
3U73 IUU5
IU10

7UU1
2UA4 FU72
9GE0 FGA1

FU02
IU50 FU73
IU62

5GA1
FU06

3U80
IUU2

7U41
FUD2
9GA1 3U60 IU09
FU04
IU14

2GE0
IU25

3U26
FG1P FG1Q

7UC0
FU00
9GE2 IU61 2U05

3U02
2U00
3U20 3U21
IGE1 3U63 IU52 IU02 2U04 IU19

5GA0
FG1B

3G15
IU01 FG1A

7UU0

CU03
IS17 2U10 2U29

3U29
IU57

CU02
3U82

CU04
CU01
3U03 IU21

2GA0

FGA0

IU64
3U61

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