rn Book 1 Module 5 DIGITAL TECHNIQUES Cae ad Licence By Post | a 9 ISSUE 2.50 Licence By Post © copyright eae neeneened> AUTHORITY It is IMPORTANT to note that the information in this book is for study /training purposes only. When carrying out a procedure/work on aircraft/aircraft equipment you MUST always refer to the relevant aircraft maintenance manual or equipment manufacturer’s handbook. You should also follow the requirements of your national regulatory authority (the CAA in the UK) and laid down company policy as regards local procedures, recording, report writing, documentation etc. For health and safety in the workplace you should follow the regulations/guidelines as specified by the equipment manufacturer, your company, national safety authorities and national governments.AUTHORITY It is IMPORTANT to note that the information in this book is for study/training purposes only. When carrying out a procedure/work on aircraft/aircraft equipment you MUST always refer to the relevant aircraft maintenance manual or equipment manufacturer's handbook. You should also follow the requirements of your national regulatory authority (the CAA in the UK) and laid down company policy as regards local procedures, recording, report writing, documentation etc. For health and safety in the workplace you should follow the regulations/ guidelines as specified by the equipment manufacturer, your company, national safety authorities and national governments. NOTE It is policy to review our study material in the light of changing technology and syllabus requirements. This means that books are re-written and/or updated on a regular basis. LBP. 140 Narbeth Drive Aylesbury Bucks HP20 19a UK Tel: (+ 44) 01296 433871 Fax: (+ 44) 01296 330697 Email: infe@licencebypost.com Website: licencebypost.comoO CONTENTS Numbering systems Decimal Binary Octal Hexadecimal Binary coded decimal Digital circuits Logic gates Electronic gates De Morgan's rules Take-off warning Landing gear lever disagree Sequential /combinational logic Flip-flops SR Clocks D type SR JK Counters Shift register Encoders/decoders Encoders Analogue to digital converter Decoders Digital to analogue converter R-2R type D to A converter Multiplexers Demultiplexers Passenger entertainment system Assignments Solutions to activitiesHOW TO TACKLE THIS BOOK Basically, very slowly! Make sure you understand each part before going onto the next. It is important you can recognise logic gates, be able to draw relevant truth tables and be able to interpret aircraft schematic diagrams in relation to logic circuits. It is important that you have a full appreciation of the involvement of logic circuitry in aircraft computer and related systems. This book is written mainly for the B1 and B2 technician with the A line mechanic needing to study only a small section and all to level 1 standard. The B2 technician needs to study this book in its entirety with all subjects to level 2 and Electronic Instrument Systems to level 3. ‘The B1 technician needs to study most of the book with most subjects at level 2 — check JAR66. All students should refer to JAR66 for the subjects to be studied and the level of knowledge required.NUMBERING SYSTEMS: Most digital transmission in today’s modern aircraft uses various types of number systems. Typically these would be decimal, binary, octal and hexadecimal, or various forms of these systems Decimal System ‘This is the system in everyday use, there are 10 digits (0 to 9 inclusive), so it has a ‘base’ or ‘Tadix’ (number of digits used in the system) of 10. Taking the number 72306 can be written as: (7 x 10,000) + (2 x 1000) + (3 x 100) + (0x 10)+6x1 (7 x 104) + (2 x 103) + (3 x 102) + (0 x 10!) + (6 x 109) 72306 Each digit is effectively multiplied by a power of 10. Note that to write 19-526 in powers of 10 then: 1x 10!+9x 10°+5x101+2x 102+6x 109 = (10) + (9) + (5x _1=-5)+(2_= 02)+(6_ = -006) 10 100 1000 10+9+-5+-02+- 006 4" 19-526 Note that 10° = 1, in fact any number to the power of nought = Proof, using the number 3 ie 3° = 1 (9 = 325 32x32 = 32-2) = 30 9 3 3 was used because it is an easy number to show you that any number to the power of nought is equal to 1. It can be seen that the decimal system is based on successive powers of 10, the number with the smallest value (10°) is known as the least significant digit (LSD) and the number with the highest value (10¢ in my example) is known as the most significant digit (MSD).‘The disadvantage of the decimal system for use in a digital computer is that the circuits which would be used, eg transistors, would have to have 10 ~~ discrete levels at collector current. For example OmA (milliamps) = 0, 1mA = 1, 2mA = 2, 3mA = 3etc. Such a system would be extremely difficult to operate because: (a) Any variation of power supply would cause errors. (b) Component tolerance would have to be virtually zero, and be unaffected by temperature variations. () Component values will change with age. Any errors from the above may cause an error increment of one or two, giving an incorrect output (eg instead of 8 [correct reading] it might be 7 or 9). Precision is important, and to expect a circuit to be infallible in distinguishing between 10 different magnitudes of current is a bit much. Where accuracy and speed are important it would be better to use a system which has just two states. Reliance is high because the circuit is either HIGH (voltage level) or LOW (voltage level) or ON and OFF and component characteristics variations are unimportant. ‘The system that is the basis of today’s digital processing is the “two states” BINARY SYSTEM. The Binary System ‘This has a base or radix of 2. As in the decimal system, we can represent any number in successive powers of 2. For example: 27 = 24+ 23+ 21+ 20 = 16+8+2+1 further expanded = Lx24+1x230x2?+1x2!=1x2° + bo Lv + 1 1 oO 1 1 means the binary number for 27 = 110112r To avoid confusion between systems with different radix this would be written as 110112 to identify it as a binary number. What about the fraction expressed as powers of 2? 00012 = 24 = 1 = 0.0625 24 Example Change 17-75 decimal to binary. T= 2442421422 expanded gives 1x29+0x23+0x22+0x2+1x 2041x2141 "22 + + + + + + 4 i 0 0 0 a. ou 1 17-75 = 10001-112 Note a binary digit is termed a bit. The table below shows the relationship between Binary and Decimal numbers up to Decimal 21, but it could obviously be continued for larger numbers.Decimal | 5-bit Binary No (word) | Decimal | 5-bit Binary No (word) Number Number ~ | : 24 | 23) 22] 21} 20 24 | 23 | 22 | a1 | 20 0 ° oj o}oj|o un ° 1 ° 1 1 1 ° ofojoji 12 ° L 1 o jo ° 2 0 o}o}ilo 13 0 1 1 0 1 3 0 ofoj;ifr 14 0 1 1 L 0 4 o of ijojo 15 ° 1 1 a af 5 0 o}iajfofa 16 1 0 0 o Jo 6 0 o/1i}ijo 7 1 ° ° ° 1 ) a ° ofajaqa 18 1 ° 0 a 0 8 ° 1} oo] o]0 19 1 ° ° 1 1 9 0 a1}o}ofa 20 1 ° 1 o jo 10 |o 1] o}ijo 21 1 0 1 ° 1 BINARY /DECIMAL EQUIVALENTS From the table it can be seen that the binary number is longer than the decimal number but because of the very fast switching speeds of modern circuits this does not present a problem. Also because of the reliability of the two-state system, the practical advantages gained by using binary numbers are considerable. ACTIVITY: Write the successive powers of 2 for the following decimal numbers and then expand to finally give the binary number. (a) 19 {c) 15-125 (b) 29 (4) 22.0625 This method is OK but when you get larger numbers it becomes much more difficult, to convert from decimal to binary, the successive division by two may be employed, the ‘remainder’ of any division (which must be either 0 or 1) is then recorded successively in a separate column. The following examples show the method used. ae ~Example a Example b Convert 796 to binary Write 217 in binary form 2 | 796 2 217 2 | 398 remainder 0 2 108 remainder 1 2|199 ” 0 2 54 2 o 2] 9 ” 1 2 a” ° 2 490” 1 2 oaaan 1 2 2400” 1 2 6. ” i 2 2” 0 2 3°” 0 2 6 ” 0 2 eeeee 1 2 Stee 0 2 o ” 1 2 ee 1 | READ UP READ UP to obtain to obtain o ” 1 | binary binary equivalent form 1100011100 11011001 CONVERSION OF DECIMAL TO BINARY ACTIVITY: Convert the following decimal numbers to binary (a) 846 (b) 317 () 147 You should practice converting the smaller numbers using powers of 2 and perhaps speed it up a bit.Example Convert 4510 to binary Write down the successive powers of 2 (25) (24) (23) (24) (21) (29) 3216 8 4 2 1 Then make up the number, ie (1x 32)+(1x8)+(1x4)+(1x1) = 45 So 32168421 101101 The binary number is 1011012 4 ACTIVITY: So the idea is to write down the powers of 2 and put 1’s in the powers you need to make up the number. Try these: (a) 47 (b) 32 © 21 ‘The following example shows you how to convert decimal fractions to binary. You use successive multiplication by two, recording the carries and then reading DOWN the carries column. Convert 0-615 to binary form 0+ 615 x2 READ DOWN And write from left to right to give binary fraction: Q-1001112 ~ until required accuracy is obtainedConversion of a decimal fraction to a binary fraction ‘The next example shows how to convert a mixed decimal number to binary. Note that it must be treated in two parts as shown, Example Convert 14 - 625 to binary Separate into whole and fraction parts ~ ie: 14-625 = 14-000 + 0-625 (WHOLE) (FRACTION) WHOLE FRACTION 2 14 0-625 x 2 2 7 ~~ remainder 0 READ 2 3 ” 1] UP READ DOWN 2 1 ” 1 oO ” 1 1410 = 11102 0-62510 = 0-1012 Recombine the whole fraction parts to give: 14-62510 = 1110-1022 CONVERSION OF A MIXED DECIMAL TO BINARY Conversion of Binary to Decimal Assume we have a binary number eg, 1011012 The easy way to convert this is to write the powers of 2 above each bit position starting from left and working towards the right eg: 32168421 « the powers added ee So it can be seen that the number is: 32+8+4+1=45i0 (there are no 16s and no 2s but one of each of the other values - 32, 8, 4 & 1)Examples: 1. Convert 1101101 binary to decimal 7 Again write the powers of 2 above each bit position. 64 32 168 421 lel peal erliae JO} 1 So 64+32+8+4+1= 1090 2. Convert 1101-1 binary to decimal Again write down the powers of 2 above each bit position 842155 i) 11014 = 13-510 3. Convert 1001110-112 to decimal 64 32 16 8421-5 25 10 0111011 =644+844+24.5+.25 = 78-7510 ACTIVITY: Try these yourself - convert to decimal (a) 110011 () 1011-1 (b) 1110011 = (@)_: 1100-001 The Octal System In the binary system the number of bits in a word can be quite lengthy and problems can occur such as the high possibility of an error in manipulating so many digits. The octal system helps lessen these difficulties, being more compact and easily converted back to decimal or binary. -8- LUThe system uses the base or radix 8, this means of course, to convert from decimal to octal we divide by 8 then record the remainders as before and read upwards to get the octal number. To convert this number to binary split each octal number into it’s three figure binary number and join together. Example 1 Convert 796 to octal and then convert octal to binary a. Conversion of decimal to octal b. Conversion of octal to binary 8 | 796 (to convert 1434s to binary) 8 | 99 remainder 4 The binary number is obtained by taking each octal digit and converting 8 | 12 remainder 3 | READ it to a three figure binary number 8 | 1. remainder4 | UP 14 3 4 0 remainder 1 001 100 011 100 2 79510= 14348 +. 1434s = 0011000111002 - 11000111002 +. 79610 = 14343 = 11000111002 To convert from binary to octal, start from the right and group into threes, if the final group does not have three bits then add noughts to make up to the three. Example 2 Convert 10101002 to octal Ho1oi100 add 2 noughts 001 o10 100 | Convert to octal digit 1 2 4 read left to right 10101002 = 1248 -9-Example 3 0100000; to octal O11 00!000 it \ 000 100 = 000 0 4 0 01000002 = 403 To convert from octal to binary (just a recap) the reverse procedure is used, Example - convert 1263s to binary eA 1263s = 10101100112 ‘ Oo 110 1 Put into groups J Of three oo. 0 11 ACTIVITY: Convert the following binary numbers to octal: (a) 101010100 (b) 1110100000 (c) 111010001 Convert the following octal numbers to binary: (a) 426 (b) 5625 (c) 65217 Fractions in decimal to octal are dealt with in a similar manner to decimal to binary except multiplication by 8 is used. Example Convert -90625i0 to binary then octal. 0:90625 x2 = 1.81250 08125 x2 = 1.6250 0625 x2 = 1.250 0-25x2 = 0.5 O5x2 = 1.0 read down pote. 09062510 = 0:111012 -10-to convert to octal 0-90625 x 8 25x8 7-25 7 if read 2.00 2 ¥ down 0-9062510 = 0-728 or we could have used the binary number split into threes 0-11101 starting after the decimal point going left to right oi ia ion | i add nought 111i 010 7 2 = -728 ‘The reverse procedure is used to obtain a binary fraction from an octal fraction. ACTIVITY: Convert the following binary numbers to octal. r (a) lanai (b) 101-1 () 110-0111 Convert the following octal numbers to binary. fa) 64 (bo) -77 () 43 Hexadecimal System ‘This system has a base or radix of 16 and is used again where large binary numbers are handled to cut down possible errors. Since we have only ten different digit symbols (0 to 9 inclusive) six other symbols have to be used these are the letters A to F inclusive. The table below shows the three numbering systems already considered and the hexadecimal system. -l-Decimal i Octal Binary Hexadecimal ° | 0 0000 0 1 1 0001 1 2 2 0010 2 3 3 0011 3 4 4 0100 4 5 | 5 0101 5 6 6 0110 6 7 7 oll 7 8 10 1000 8 9 il 1001 9 10 12 1010 A 11 13 1011 B 12 14 1100 ic 13 15 1101 D 14 16 1110 E 15 17 111 F Ib __ to 10600 yo COMPARISON OF NUMBERING SYSTEMS Conversion from Decimal to Hexadecimal Convert 76219 to Hexadecimal 16 | 762 16 | 47 remainder A 16 | 2 remainder F read up 0 remainder 2 ». 76210 = 2FAi6s Conversion from Hexadecimal to Binary group into} 4 digits } 2 + 0010 “ 2BCi6 Convert 2BCis to Binary B c 1011 1100 1010111002 -12-ACTIVITY: Convert the following Binary numbers to Hexadecimal (a) 11100010 (by 1111111 () 111001 Convert the following Hexadecimal codes to Decimal (a) 2D (o) AF () 21a Convert the following Decimal numbers to Hexadecimal (a) 1632 (b) 494 (co) 5174 Convert 17816 to Decimal, Binary and Octal Convert EF\s to Decimal, Binary and Octal Fractions in Hexadecimal Convert 0-9062510 to Hexadecimal 0.90625x 16=145 E Read O5x16= 80 8 Down 0-9062510 = O-E8 to convert to Binary 0-E8 Group into four digits 0-1110 1000 = 01110110002 ACTIVITY: Convert the following decimal fractions to Hexadecimal (a) 06250 (bj 0-81250 Convert the following Hexadecimal numbers to Binary (a) O-A8 (b) O-F6 Just comparing the length of a binary number to Octal or Hexadecimal 111100001111101100011.00010011012 741754304645 1E1F63-13416 -13-Binary Coded Decimal BCD There are several forms of this system but we shall concentrate on the 8421 code. It is used in display read-out systems, decoders and counters. DECIMAL, BCD 23 22 21 20 HHOOOCCOOO OOreHEH OOOO COHHOOFHOS HOHOHOHOnS 0 1 2 3 4 5 6 7 8 9 It is called an 8421 code as each digit is weighted from left to right 8421 in powers of 2. You might be thinking that this is the same as the binary code, however, with numbers from 10 upwards each number is represented by the 4 bit code. Example 1110 to BCD is 0001 0001 _ leaving a space between each group of four digits. Another example 42910 to BCD ¥+\ Is 0100 0010 1001 Converting from BCD to Decimal is again quite easy 10000101 Split into groups of four 1000 0101 8 5 = 8510 -14-ACTIVITY: Convert the following decimal numbers to BCD (a) 94 (b) 529 () 2947 Convert the following BCD numbers to decimal (a) 011100001001 (b) 001101100100 By way of a summary and to enable a comparison to be made between a number representation in the various systems and codes, consider the decimal number 347. DECIMAL 347 BINARY 101011011 8421 BCD 0011 0100 O111 OCTAL 533 HEXADECIMAL — 159 When a number such as decimal 347 is converted into any binary form the corresponding group of binary digits is known as a WORD. Each word is formed of a number of BITS (BINARY DIGITS) and this represents the word length. Principle of Adding, Subtracting, Dividing and Multiplying binary numbers. Adding The rules are similar to those when adding decimal numbers, eg 5+5 = 0 and carry 1 to the next higher ‘power’ column, and 1+1 in binary results in 0 carry 1. Rules 0 +0=0 ol 1 1 +0 1 1 + 1 = Owith 1 to carry Example: add 1011 and 1110 1011 1110 11001 Note 1+1+1= 1 carry 1 V1 Carry = 11001 -15-Subtraction ~ Again similar to rules for decimal subtraction except 0 - 1 = 1 borrow 1 Rules Example: subtract 10101 from 11011 11011 10101 00110 4 Multiplication Rules 0x0=0 Ox1=0 1x0=0 1xl=l Example: multiply 1100 x 11 1100 u 1100 1100_ ADD 3 100100 Multiplication in a computer is achieved by repeated addition (eg in decimal 2x4 is computed as 2+2+2+2~=8). Division Rules 1 o yi yo Example: divide 111100 by 110 = -16-1010 110) TTTI00_ 110 00110 110 00000 Check this by converting binary 1010 to see if the answer is correct Computers cannot divide, they carry out division by repeated subtraction, which is in itself done by an addition process. Positive and Negative Numbers ‘The computer needs to distinguish between positive and negative numbers. For storage purposes only there is usually an additional bit added which identifies whether the number is positive or negative, eg: ‘0’ for positive numbers ‘1’ for negative numbers Example - using an 8 bit binary word the sign bit is added on the front. Decimal binary -25 100100-100 A sign bit -ve + 10.25 001010-010 sign bit +ve As mentioned, this is a convenient method for storing numbers but does not allow direct subtraction of one number from another. By inverting the number and adding 1 we get the negative of the number. This process is called TWO’s COMPLEMENT. ‘The Twos Complement process involves inverting each bit in a word and adding 1 ShsExample. Find the negative binary number of +5 decimal +5 as a 4 bit word 0101 invert (change ‘0’s to ‘1’s and ‘1’s to ‘0’s) 1010 Add 1 1 1011 Note negative numbers have a 1 in the most significant bit position whilst the positive number has a 0. When numbers are represented as negative, subtraction is achieved by addition (adding a negative number being the same as subtracting a positive number) eg. 5-7=5+(-7) +7 = 0111 Invert = 1000 Add 1 = 1001 v = 0101 + 1001 =0101 1001 1110 1110 =-2 +2 0010 Invert 1101 Add 1 1 1110 ‘This means that both addition and subtraction can be done by the same circuits in a computer which considerably reduces the hardware involved. DIGITAL CIRCUITS w Logic gates Devices used in logic networks control the flow of information through the system and are therefore known as logic gates since the ‘gates’ are opened and closed by the binary inputs in order to perform a logical function. Logic gates are the basic building blocks from which many different kinds of logical outputs can be obtained. The gates we shall consider are the AND, NOT, OR, NAND, NOR and XOR gates. They are made up of electronic components and the output can be represented by Boolean algebra (named after George Boole (1815 -1864). -18-Logic gates have binary inputs of 1 or 0 and they may represent (in a circuit) ON, CLOSED (logic 1) or OFF, OPEN (logic 0). We shall be using the American symbols for the gates (there are British Standard symbols but are not in common use in the aircraft industry). AND Gate This gate can have two or more inputs and only one output. It will give an output if all inputs are on. If any one input is not available the output will be zero. The symbol for a 2 input AND gate is shown below. A 8 INPUTS = A&B ourpur=s ‘AND’ GATE SYMBOL ~~ SWITCH A SWITCH B EARTH ELECTRICAL ‘AND’ GATE CIRCUIT The AND gate can be made up electrically by two switches in series. The lamp will only light when switches A AND B are both made. If any one switch is open the lamp will not light. The operation of the logic gate can be described by means of a TRUTH TABLE. When switch A is open (logic 0) and switch B is open (logic 0) there is no output the lamp (logic 0). When switch A is made (logic 1) and switch B is open (logic 0) there is still no output to lamp (logic 0), oatsWhen switch A is open (logic 0) and switch B is made (logic 1) - still no output to lamp (logic 0). When switch A is made (logic 1) and switch B is made (logic 1) there is an output to the lamp (logic 1). So when A AND B are logic 1 then there is an output. This is summarised in the truth table. HoHoD> HHooWw HoOoOn Where A and B are the inputs and S$ is the output. Only 2 inputs are shown but there may be more A, B, C, D etc. You must remember the symbols and the truth table. ACTIVITY: Sketch a circuit for a three input AND gate and draw it’s symbol and derive it’s truth table. The Boolean expression for this gate is written A.B = S, The dot means AND, and the expression is read as “A AND B equals S” (in some books the output is called z). OR Gate This can have two or more inputs and will give an output if any one input is. logic 1 ‘OR’ GATE SYMBOL -20-SWITCH A —_— =— -—e- +VE - LAMP EARTH SWITCH B ELECTRICAL ‘OR’ GATE CIRCUIT ‘An OR gate circuit can be made up by two switches in parallel. The lamp will light if switch A OR B is closed So the truth table will be: Both switches open Switch A closed Switch B closed Switches A and B closed Honom HHoow HHH OD The Boolean expression is: eee ‘The + means OR and the expression is read as “A OR B equals S”. NOT Gate ‘This gate has one input and one output. SYMBOL FOR A ‘NOT’ GATE ‘This gate produces an inversion of the input signal, so when the input is A the output is NOT A, which is symbolised by a bar on top of the A = A, So the output of this gate is the opposite to it’s input. opyheSo input logic 1, output logic 0. Input logic 0, output logic 1. The truth table: A Ss 1 Oo of}. The Boolean expression is: NAND Gate This is short for NOT AND and works similar to a NOT gate except that it has more than one input. SYMBOL FOR A ‘NAND’ GATE The bubble on the end of what is an AND gate has the same function as in the NOT gate - it inverts the signal, except that in this case more than one input is involved. In this gate when A is 0 AND B is 0 then the output is 1. In the AND gate this would be 0. So the NAND gate is an inverted AND gate, ‘The truth table is: HOoHoD HHoow Oren The Boolean expression is: S The bar over A.B gives NOT AND and is read as “NOT (A AND B) EQUALS S”. -22-NOR GATE This is short for NOT OR and is simply a negated OR gate. SYMBOL FOR A ‘NOR’ GATE Again an input A = 0 and B = 0 would, for a OR gate, give 0 as an output, but for the NOR gate it would give a 1 as an output. ‘The truth table is: HH ooD Horow coone ‘The Boolean expression is: A¥B=S The bar over A + B gives NOT OR and is read as “NOT (A OR B) equals S’. XOR Gate You may have noticed that the OR gate gives an output when A OR B = 1 and when A AND B = 1. The XOR gate only gives an output when A OR B are 1 not when A and B are 1, so it is exclusively an OR gate and will not work under the AND function, It is read as a two syllable word x then or. SYMBOL FOR XOR GATE -23-The truth table is: A B s 0 0 0 1 0 1 0 1 1 1 1 0 ‘The Boolean expression is AB+AB=S which is read as “NOT A AND B OR A AND NOT B EQUALS 8”. It should be appreciated that for all the gates so far discussed we have assumed logic 1 is positive (+5 volts) and logic 0 is zero (0 volts). This is called POSITIVE LOGIC and is the notation most frequently used. However, NEGATIVE LOGIC may be used, and this means that logic 0 is positive (+5 volts) and logic 1 is zero (0 volts). We shall use positive logic throughout this book. To consolidate your knowledge of logic gates we shall put a few together to make up some simple logic circuits. Note. Bubbles on inputs to gates negates or inverts the signal, Oe: LOGIC CIRCUIT 1 With reference to logic circuit 1, what is the output logic level $ if A = logic 1 B = logic 0 and C = logic 1? With A = 1 and B = 0 (remember this 0 is changed to 1 by the bubble) the output of the first gate = 1. The input to the second gate is 0 (the 1 from gate 1 inverted, and input C = 0) so the output is 0. What would be the Boolean expression for this circuit? ‘The output of gate 1 is A.B (read as “A AND NOT B”). The output of gate 2 is A.B.C (read as “NOT [A AND NOT B] AND C”) -24-ACTIVITY: Study the following circuits and determine the logic level of the output from each. tbe LOGIC CIRCUIT 2 LOGIC CIRCUIT 3 Electronic Gates The earliest examples of logic mechanisms were those using mechanical levers (the key in a lock for example - AND logic), gear wheels etc. Other systems used low-pressure highly filtered air in accurately engineered logic gates to control machines. These devices were slow, heavy and prone to failure due to their moving parts. Electrics have played a part in logic circuits as shown in the drawings above on AND and OR circuits. Micro switches, suitably wired are still used on many aircraft to perform logic functions. With the introduction of electronics, solid state circuitry can perform the most complex logic functions with the advantages of minimal size and weight; very low power consumption, and extremely fast operation. We shall, of course, be concentrating on electronic systems in this book. -25-The simplest logic using discrete components was the diode-resistor logic, the diagram below shows an AND gate. +ve —K}-— B. KI > S=AB ov AND GATE CIRCUIT When A or B = 0 then current will flow through the resistor and the diodes. ‘This means that all the voltage is dropped across the resistor and no voltage is on the output line, so the output is OV (logic state 0). When A and B are logic 1 (+5 volts), no current flows, voltage is the same both sides of resistor R and output is +5v (logic state 1). ‘The diagram below shows an OR gate. A B == S=A+B ov OR LOGIC CIRCUIT When A or B are logic 1 current will flow and S will be high logic 1. ‘The next advance was resistor transistor logic and diode transistor logic. The diagrams below show some typical circuits. -26-R| +E RL R2 ‘e RTL NOR GATE +E« RL R2 TT DTL NAND GATE Today since the integrated circuit (IC) became possible the logic gates work by transistor-transistor logic (TTL), metal oxide semiconductors (MOS) and complementary metal oxide semiconductor (CMOS) group of families. ‘The integrated circuit is a complete electronic circuit, transistors, diodes, resistors, capacitors, all made from and on one ‘chip’ of silicon, typically 5mm square and 0-5mm thick, The following diagram shows a typical IC with it’s plastic case partly cut- away to show the ‘chip’. OTeCONNECTIONS FROM CHIP TO PINS PLasTic BODY AN IC PACKAGE Note the metal pins - for inserting into a suitable IC socket or to be soldered into a PCB (Printed Circuit Board). Note also the metal connections from the chip to the pins. The reason for this form of construction is so as to allow the chip to be connected to other circuits. It is too small, in it’s original form, to be handled and/or to be connected to anything. The scales of integration refer to the number of gates contained in a single IC package: * Small scale integration (SSI) - containing not more than 11 gates. * Medium scale integration (MSI) - containing up to 100 gates. * Large scale integration (LSI) - containing between 100 to 1000 gates. * Very large scale integration (VLSI) - containing over 1000 gates. ‘The diagrams below show the some TTL and CMOS gates. TTL AND GATE moeD1 TTL NAND GATE +5V D2 CMOS NOR GATE CMOS NAND GATE -29-Properties of TTL and CMOS TTL uses bi-polar transistors along with diodes and transistors formed to microscopic dimensions on a slice of silicon (chip). TTL must have a steady Sv de supply, while CMOS will work on de voltages between 3 and 15v and usually requires much less power. CMOS uses unipolar Field Effect Transistors (FET) with metal-oxide-silicon technology, this lends itself to VLSI as they take up less room on a chip, compared to the TTL. CMOS has a much higher input impedance. One important point with CMOS is that if static electric charges are allowed to build up on it’s input pins, these voltages can break down the thin layer of silicon oxide insulation between the gate and the other electrodes of MOSFET’S and this will destroy the IC. So anti-static protection is important. Gate operating parameters include: (a) Speed of operation (b) Fan in () Fan out (@) Noise margin (e) Power dissipation Speed of operation - the time that elapses between the application of a signal to an input terminal and the resulting change in the logical state at the output terminals. Fan in - number of inputs coming from similar circuits that can be connected to the gate without adversely affecting it’s performance. Fan out - the maximum number of similar circuits that can be connected to it’s output terminals without the output falling outside the limits at which logic levels 1 and 0 are specified. Noise margin - this is maximum noise voltage (unwanted voltage) that can appear at it’s input terminals without producing a change in output state. Power dissipation - as in any circuit, supply voltage multiplied by the current (Power = V x I) gives the power in the circuit and this heat must be dissipated. Typical figures for TTL and CMOS are shown below. Speedof Fan Fan Noise Power Operation in out margin dissipation Standard TTL OnS 8 10 (Oa 40mW CMOS 30nS 8 50 15v -001mW -30- @If you look back at the diagrams for the TTL AND gate and the TTL NAND gate you will see that the NAND gate uses fewer components and is therefore cheaper to produce. This also applies to the NOR gate, ie it is cheaper to produce than the OR gate. NAND gates can be connected together to form any of the other basic gates — thus reducing production costs by manufacturing one gate only. The following drawings show how these gates can be formed. ae = — > NOT GATE (INVERTING) _ +> eH > pe AND GATE OR GATE -31-p> - pera NOR GATE Eo oo Det NAND GATE : ‘The following drawings show the pin connections of ICs for different gate configurations. There is no need to remember them but it does give a good idea of how the chip (with the gates in) is connected - although the chip itself is so small that it looks like a piece of silver metal 4 or 5 mm square. RAAA a fa ta . To Wo PIN CONNECTIONS TTL NOR GATE a ves RAAnRAo St a To Wow PIN CONNECTIONS CMOS NOR GATE nat -32-vee ARAnAAA —_I — i J WoUUEUWo PIN CONNECTIONS TTL AND GATE AAA — g Lp Ss) — VOU Woo PIN CONNECTIONS CMOS AND GATE It is sometimes useful to know other logic gate representations. The drawings below show some alternative logic gate symbols. >" A —— K¥E=A-8 8 AND GATE A a Ase __ FaBeave a 8 OR GATE -33-NAND GATE : = 1) 8 an) NOR GATE NOT OR INVERTING GATE At first sight it might appear that they are not equivalent by looking at the Boolean expressions. However using De Morgans rules we can prove they are the same. De Morgans rules state: A+B =A.B AB -A+B ‘Taking rule 1. NOT A OR B= NOT A AND NOTB. To apply the rule ~ split the bar and change the sign. A+B splitthebar © A+Band the change the sign A.B -34- vvTaking the first AND gate output A.B output of equivalent circuit A. B= split the bar A +B change the sign A. B, Double bar over a letter removes the bar, ie second bar negates the single bar so the output is A.B, same as the AND gate. This procedure can be used with all the equivalent circuits. However, much more importantly, to convert the AND gate into it’s OR gate equivalent, remove bubbles where there are any, add bubbles where there are none. No bubbles on AND gate so add bubbles on all three connections. Ifyou look at the NAND gate you will see that the OR gate has two bubbles on the input (none on the NAND) and none on the output,(one on the NAND). So WHERE THERE ARE BUBBLES REMOVE THEM, WHERE THER ARE NO BUBBLES PUT SOME IN, this will then give you the equivalent circuit. ACTIVITY: Draw the equivalent circuit of these gates. 1 —-d We now need to look at how these gates are used in aircraft circuits. You will need to be able to interpret these diagrams and explain how an output is arrived at. You should be able to describe the operation of a logic circuit if an unexpected logic input is present. Logic gate circuitry is extensively used in aircraft schematic diagrams for all aircraft systems including airframe systems, engine systems, and all avionic systems. The following schematic diagram shows a take-off warning circuit -35-cr crore pee Sar Nae TeOTTLe Sutra assy Ted iene PooaTy Gute stage, Sar Se "ee nace eel ht ere} ‘Motion ‘Sensom Be vores suman 5 CENTRAL, AURAL, WARRING 3-5 1 1) nore: a Crognos ane TO WARNING CIRCUITS TAKE-OFF WARNING SYSTEM It can be seen that it consists of two OR gates and an AND gate, with logic states sent from 7 parameters. When either throttle lever is pushed forward, the switch at that position is made (advance) and there is a logic state 1 to OR gate 1. -36- YFive other parameters are sensed and logic states sent to OR gate 2. If all the other parameters are in the take-off position, ie 1) Slats not fully extended. 2) Flaps in take-off position ie less than 25°, 3) Spoiler handle in retract position. 4) Horizontal stabiliser in the green band (correct angle of incidence for take-off). then the inputs to OR gate 2 are all logic 0 and it’s output to the AND gate is logic state 0. ‘The aircraft on the ground (weight switch) gives another logic 1 to the AND gate, which has at this time 2 logic 1’s and a logic 0, If either of the four inputs go out of the take-off position eg flaps greater than 25°, then the flap input signal to logic gate 2 is logic 1 which makes the input to the AND gate logic 1. The AND gate now has three logic 1’s which now gives an output to the warning circuits (CONFIG light and aural warning). fare ite ee ams nr ew al Bw: ‘Amber GEAR light EICAS: “GEAR DISAGREE" (8) Tews SyStem 1 AND system 2, any gear ne roone disagreement with lever position LANDING GEAR LEVER “DISAGREE” CIRCUIT -37-‘The previous diagram is of an undercarriage “gear disagree” indication circuit. Systems 1 and 2 sense any disagreement between the landing gear position and the landing gear selector lever position. So if a disagreement is detected then the ‘gear’ light illuminates. ACTIVITY: Explain the operation of the circuit. (If in doubt about anything contact your tutor). ACTIVITY: To further enhance your ability to interpret logic diagrams, study the next drawing. It is a take-off warning circuit to warn the pilot if the aircraft is in the incorrect configuration for take- off. Draw the logic circuit for the diagram. (Contact your tutor if you have any problems). reeeee | — oe oe Oo =f} pe fe FI [ ce tone | aby aoe i arn Lepper? ‘TAKE-OFF WARNING CIRCUIT It is important that you look at the logic schematic diagrams for your aircraft and work out how the gates are used. Sequential/Combinational Logic Before we tackle actual devices we need to look at some memory type circuits which use sequential logic ie, their outputs depend not only on their present inputs but on past ones as well. -38-So far we have only been looking at combination logic circuits whose outputs are always the same for the same combination of inputs. FLIP-FLOPS Memory type circuits use ‘lip-flops’ as their main components. There are many types but we shall look at three, the SR or RS, D and JK flip-flops. These are so called because on the application of a suitable pulse at the input it causes it to ‘lip’ into one of it’s two stable states and stay in that state until a second input will ‘flop’ it into its previous state. SR Flip-flop The SR flip-flop has two output terminals Q and Q. The diagram shows the SR flip-flop using NAND gates. SR FLIP-FLOP When S=1 R=0 Q=1 Q=0 the flip flop is SET When $=0 R=1 Q=0 Q=1 the flip flop is RESET When S = 0 R= 0 then no change occurs Q and Q will be what they were before. When S = 1 and R= 1 then Q = 1 and Q equals 1. The circuit is stable while S = R= 1, but if they are changed simultaneously from 1 to 0 then due to different switching times of the gates we cannot predict whether Q or Q will be 1. 1 should not be The output state is said to be indeterminate so S allowed to occur. The truth table is shown below. BIsors|R/Q|@ 1 oO 1 0 0 1 0 1 0 | 0 | Depends on state before inputs applied 1 1 Indeterminate So basically the flip-flop can exist in two stable states: Q=1(Q=0) or Q=0Q=1). Clocks In sequential logic circuits where there may be a large number of flip-flops, it is important they all act at the same time, so no circuit operates out of sequence. This is achieved by a CLOCK pulse which is derived from a pulse generator with a high frequency. The circuits may be triggered when the clock pulse changes from 1 to 0 or when it changes from 0 to 1 (edge triggered) or when the level is 1 or 0. ‘The diagrams below shows a clocked SR flip-flop and it’s truth table. eK (eLock) melee DRAWING SYMBOL LOCKED SR FLIP FLOP -40-OUTPUTS OUTPUTS INPUTS feces peoke Aree PULSE CLOCK CLOCK COMMENTS PULSE PULSE s;TR]aATB/|OQ|[Q/o To 0 0 1 1 1 0 1 0 NO CHANGE IN 0 0 1 iy 1 0 1 0 OUTPUTS: Tam [Os [ea Ones anon | me ON eM oe er Witt 1 0 0 I 0 I 1 0 | ge1a geo 0 1 1 0 1 0 0 1 FLIP-FLOP RES 0 T T 0 | 0 T 0 lea focormtaen 1 1 oO 9 1 0 1 1 THIS INPUT IS I T 0 0 fo T T 1 _| NOTALLOwED D Type SR Flip-flop This is a modified SR flip-flop. ‘TRUTH TABLE CLOCKED SR FLIP-FLOP The D stands for delay. If you look at the truth table, when the clock pulse changes (rises), whatever is at D is transferred to Q, when clock pulse falls Q stays at that level. NO MATTER WHAT IS APPLIED TO D, Q will only change state at the next clock pulse. The truth table shows that the output equals the input one clock pulse earlier ie, the data is held back until the clock pulse = 1. CLOCKED D TYPE FLIP-FLOP -41- — abe «x 8 DRAWING SYMBOLourPuts INPUT BEFORE CLock | OUTPUTS AFTER RE CL CLOCK PULSE D s R Q Q Q Q 0 0 1 1 0 0 1 0 0 1 0 1 0 1 1 i 0 L 0 1 oO 1 1 0 0 1 1 0 TRUTH TABLE CLOCKED D TYPE FLIP-FLOP JK Flip-flop ‘The next diagrams show the NAND gates. layout and truth table of the JK flip-flop using ie ; 7a mu ' “ be ok ‘ DRAWING SYMBOL JK FLIP-FLOP ‘ouTeuTs DURING cLock | OUTPUTS AFTER wuts | Berore ciock | PUBS SO°K | Oreo use| comments J K Q Q A B Q Q o | 0 1 0 1 1 1 0] No cuance in o |.0 | 0 1 1 1 0 1 OUTPUTS i i 7 i rl i T 0] STAYS ATOR I 0 0 1 0 T 1 Ol Laantiron STAYS AT OR 0 Hl 1 0 T 0 0 I STAYS AT OF Q T 0 T I I 0 T_| g-0%Q-1 1 1 az 0 1 0 o z TOGGLES 1 1 0 i 0 i a 0 TRUTH TABLE JK FLIP-FLOP -42-‘The two inputs are called J and K, the operation is fully described in the truth table and J = K = 1 is allowed (unlike S = 1 in a SR flip flop) and toggles (changes state) when this input is applied. These flip-flops are used in counters and shift registers and a wide variety of logic circuits Counters There are many types of counters and the flip-flop counter is the one discussed here. The next diagram shows the basic principles of counting using flip-flops. It is a 4 bit binary counter using JK flip-flops. The J & K inputs are at logic 1 so any pulse 1 to 0 will trigger the output to change from it's previous state. The output of one flip-flop is the input to the next - they are said to be connected in ‘cascade’ : is LAL web fo oa f | \/ 1 ?—_——_, j Fl i a / 1 : 1 i Cy \/ eB . 2 BACK 76. START FOUR BIT BINARY COUNTER -43-As can be seen from the diagram, every time the input pulse falls from 1 to 0 the counter increases the 4 bit binary number by 1, eg: Qa is least significant bit Qo is most significant bit After the first pulse Qa = 1 Qu = 0 Qc= 0 Qn = 0 which is 0001 ie, decimal 1. After the second pulse Qa flips back to 0, Qa = 1, Qc = 0, Qo = 0 which is 0010 ie, decimal 2. You should now be able to follow the sequence through yourself. Remember every time the outputs go from 1 to 0 the next flip-flop triggers. When the count reaches 1111 (15) all four flip-flops are reset. Studying the diagram further you will see it takes two input pulses to make flip-flop A go from 0 to 1 and back to 0, two pulses from Qa to force Qe from 0 to 1 and back again, and so on down the chain. In fact each flip-flop acts as a divide by two circuit and four flip-flops in a chain like this make a divide by 16 circuit, because the pulse frequency at Qo output is one sixteenth of the frequency of the input. So this chain of flip-flops can be referred to as either a divide by 16 counter or modulo 16 counter (modulo means the maximum number a counter can count to, which is of course the same number it divides by). QUESTION: If there are two flip-flops connected in cascade what would the division be? (5 mins). If you are not sure of the answer check with your tutor (Full Students). Shift registers A register is a number of flip-flops arranged in a circuit (typically D or JK) used for storing data. A shift register is one that is designed to move the data along the register. The next diagram shows a 4 bit register using JK flip- flops. Assume the register is cleared and therefore reads 0000 and an externally generated word 1011 is to be stored in the register. At the end of the first clock pulse Qa= 1 Js = 1. After the second clock pulse flip-flop B is set Qa = 1 Qs=1. The state of the register when the third clock pulse arrives is Ja= 0 Ka = 1 Ja= Je = 1 Ke = Ke = 0 and at the trailing edge of the clock pulse flip-flop A resets and flip-flop C sets. Now Qa = Ja = 0, Qa = Qe =Jc = Up = 1. -44-The last bit to be stored is 1 and at the end of the fourth clock pulse flip- flops A, C and D are set and flip-flop B is reset ie 1011 is stored. The effect of each clock pulse is to shift the content of the register one place to the right. 0 0 0 0 SERIAL INPUT 1011 1 | 7 @ J Q J a v a SERIAL TA TB Te Tt oD |ourpur kK oT Ko KT ko RESET CLOCK OR SHIFT PULSE FOUR BIT SHIFT REGISTER The shift register shown is SERIAL IN and SERIAL OUT but a register can also be: Serial in - parallel out Parallel in ~ serial out Parallel in ~ parallel out OUT IN Qa Qa Qe Qo REGISTER - SERIAL IN PARALLEL OUT IN oo Berea REGISTER - PARALLEL IN SERIAL OUT -45-IN OUT REGISTER - PARALLEL IN PARALLEL OUT ENCODERS AND DECODERS Encoders ‘These are generally at the input end of a system to convert the input signal) © into a binary code necessary for the operation of the system. Encoding circuits may take many forms eg: convert an analogue signal to BCD or 4 bit binary code; take in a binary signal and convert it into another code to suit the system eg, OCTAL to BCD. SWITCHES 0; —e~o- 1}-oo abie“o yo Bonnecrion 3 is es ecm ‘toc Put : ~~“ _ACONNECTION *} e~. | * e“o Tal suery == ‘| at ae er ssnanY CODED DECMAL OUTPUT DECIMAL TO BCD ENCODER -46- ~The drawing shows a keyboard layout (decimal input) to give a BCD output. By pressing any one key or switch (suitably decimal numbered) the appropriate BCD code is given at the output. Assume “4” is pressed then diode Ds will conduct through Re making the output (C) go high, all the other inputs stay low (DBA), so the output is 0100 (decimal 4). ‘This principle will be employed in INS (Inertial Navigation Systems), IRS. (Inertial Reference Systems) and FMS (Flight Management Systems) as all these have keyboards. So some form of encoding will convert the input signals into the correct code for the system. In Flight Data recording some of the inputs into the system are in analogue form, such as de, ac or syncro signals. This mans that they have to be encoded into digital for use by the Central Processing Unit (CPU). This is done by an Analogue to Digital Converter. Analogue to Digital Converter ‘The diagram below shows the basic layout of a digital ramp converter. When the start pulse is applied, it becomes logic 1, the counter is reset, no pulses are fed through the AND gate as it is ‘closed’. ~~ Wel. ANALOGUE TO DIGITAL CONVERTER, A comparator is a device with two inputs which compare the voltages at each input to determine which is greater, the output is logic 1 if A is larger than B and logic 0 if input B is larger than A. On start B is 0, A is the larger output, from the comparator is logic statel and when the START pulse goes low the AND gate ‘opens’ and the clock pulses go to the counter. Each pulse causes the counter to advance, -47-As the counter counts up, its value is converted into it's analogue equivalent by the digital to analogue convertor (DAC or D to A or D/A) and applied to the comparator at B. The DAC output therefore increases in steps until it reaches just above the analogue input level ie, B input >A. The comparator output goes low, AND gate closes, the count stops, the digital read-out is then taken from the counter. The best approximation we can obtain, depends on how much input B has to be greater than A ie, the step size, this is known as the quantization error. ‘This type of Analogue to Digital (ADC or A to D or A/D) converter is slow in operation and is unsuitable for high speed operation, and of course the larger the voltage the longer (more steps) time it takes. The comparator would be an operational amplier (see JAR Module 4). This problem can be partly overcome by using an up/down counter. It counts up when the comparator is logic 1 and down when the comparator output is logic 0. As the analogue input varies it simply counts up or down from the previous count rather than re-setting to zero as did the digital ramp convertor. This type is called the continuous digital-ramp convertor and is a considerable improvement on the previous one. Co However, the fastest type of ADC of the ones considered is the successive approximation type. ANALOGUE INPUT VOLTAGE_B. COMPARATOR REGISTER CONTROL LoGic DIGITAL OUTPUT Dac SUCCESSIVE APPROXIMATION TYPE OF D TO A CONVERTER This is similar to the previous circuit but the register is used instead of a counter and a control logic block is included between the comparator and register, which controls the output of the register. Initially a reset signal puts all bits in the register to 0. The control logic sets the MSB in the register to 1 and the rest to logic 0. The output of the DAC is then compared to the analogue input if B > A then this number is too large and the MSB remains at 1. -48-At the next clock pulse the control changes the next bit in the register B>A it is set to 0 if B coumion 7 2 z 800 B/S LINE 2 3 3 >| | 3 3 ‘ > eral ;— * TIME DIVISION MULTIPLEXER The duration of each bit is 1/200s or 5ms (5 milli seconds) so an 8 bit word occupies 40ms. The common line is operated at input channel speed times the number of channels ie, 4 x 200 = 800 bits/sec. So each bit will have a time slot of 1-25ms. Data from the systems connected to Channels 1, 2, 3 and 4 are fed into a Buffer Store, until each store is signalled by the clock pulse to output its data onto the common line in sequence. Boatve As you can see from the diagram there must be some way of converting these signals to the appropriate receiving channel, ie channel 1 input signal data to be picked up by channel 1 receiving channel. This will be by a de-multiplexer, a device with a single input but with multiple outputs. ‘There obviously has to be synchronisation between the input and output channels to ensure each data goes to the correct channel. Thus all the system works on the command of the clock (electronic). De-multipexer These are similar to a multiplexer but work “the other way round”. They take sequential input data from a common data line and output each piece of data to it’s appropriate channel. The drawing below shows the mechanical equivalent of the electronic device. COMMON LINE SERIAL DATA INPUT SEPARATE DATA LINE OUTPUTS SIMPLE REPRESENTATION OF A DE-MULTIPLEXER The next diagram shows a 1 line to 8 line de-multiplexer. It has 8 AND gates, three NOT gates, and input line and 8 output lines. As the name implies it has 1 input line and 8 output lines, with the single data input line is connected to all eight gates. Each gate will be enabled by the signals on the select lines S2 S: So. Assuming 000 input on the select lines only GATE 0 will open and the data will appear at its output. The truth table shows the logic states of the de- multiplexer . ooncos ote c= os os = = ore 2 DATAINPUT st so ONE LINE TO 8 MULTIPLEXER 0% oy or 03 eoonccce ourpurs % ecconcce 05 o eccccone Ss TRUTH TABLE FOR THE ONE LINE TO 8 MULTIPLEXER SELECT CODE -56-The next diagram shows the basic principles of a passenger entertainment system The multiplexer selects all the inputs in turn, (12 channels of recorded music, passenger address messages and tape signals) digitises them (analogue to digital converter) into one serial data signal stream. This stream of data is fed to the seats via the sidewall disconnects. The data is received by the electronic boxes. Depending on the selection made by the passenger, the signal is de-multiplexed and decoded (digital to analogue) to output the required signal. rassencen conteou ce {Gn INSIDE oF ann RESTD eee eee 42 cues (Ot DNSIE OF Am aes1) [~~ seconoen mite rate sear rovrinicxeo— Bstomecr SE soates Kee Gaetan moses rot ro nex ‘ioe wun 8 ate rf A PASSENGER ENTERTAINMENT SYSTEM - GENERAL ARRANGEMENT BSTASSIGNMENT Complete all activity sections in this book. Give examples of where the following occur in aircraft systems: () Encoding (i) Decoding (ii) A to D conversion (iv) to A conversion (*) Multiplexing and de-multiplexing Sketch an aircraft system using logic gates and explain its operation -58-~ SOLUTIONS TO ACTIVITIES Page 4 (a) 1x24+0x29+0x22+1x21+1x20= 100112 (ob) 1x24 41x 23+1x22+0x214+1%20= 111012 () | -1x23+1x22+1x21+1x20+0x21+0x224+1x29= 11110012 (4) 1x 2440x2341 x22+1x2140K 2041x2141 2240x2941 x24 = 10110.00012 Page 5 846 423r0 Qlirl 105r1 52rl 26r0 13rd 6rl 3r0 irl Or1= 11010011102 fa) VYONYYNNYNYNYNHN (b) 317 158rl 7910 39rl 18r1 orl 4r1 2r0 1rd Orl = 1001111012 VY NYYNYNYNYYVYN -59-147 73r1 36r1 18r0 9r0 4r1 2r0 1rd Orl {c) WONNNNYNN 100100112 Page 6 (2) 32168421 1 01111 (b) 32168421 1 0000 02 =3210 32168421 1 010 12 =2li0 Page 8 (a) 32168421 1 1001 12=S5ho (be) 64 32168421 1 1 1001 12=115: () 8421 8 1011.12 =11.510 (deste aeopleee se o5pel 25 1100.0 0 02 ~=12.12510 Page 10 (@) 1oio1010 101 of0 100 5 2 4e (b) ATT oo ao 100 oe 4 03 -60-) ponjeton, itt i(Ge9010) 2a 00) 7 2 Is (a) 426 ¥ SN 100 010 110 1000101102 (b) 5 6 2 Se “ 101 110 010 110 1011100101102 ) 65217 110 101 010 001 111 1101010100011112 Page 11 ' (a) wpe 7. 78 (&) — 103/.100 vy 5.48 (co) no ousngo 6.3 4s (a) 64 110 1002 (b) Te -111 11a () 438 100 O112 -61-