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Block Diagram Function Management Patent

This patent describes management of functions for block diagrams. It allows pattern-matching portions of a block diagram model as equivalent, and creating common instructions to replace the occurrences to enhance efficiency. Diagnostics provide information on the execution structure and guidance to modify the block diagram to reduce image size. Automatically generated hierarchical structures, control over function signatures, and user control over file packaging provide flexible control over generated code for block diagrams.

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Hafid Hamzah
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0% found this document useful (0 votes)
59 views61 pages

Block Diagram Function Management Patent

This patent describes management of functions for block diagrams. It allows pattern-matching portions of a block diagram model as equivalent, and creating common instructions to replace the occurrences to enhance efficiency. Diagnostics provide information on the execution structure and guidance to modify the block diagram to reduce image size. Automatically generated hierarchical structures, control over function signatures, and user control over file packaging provide flexible control over generated code for block diagrams.

Uploaded by

Hafid Hamzah
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd

(12) United States Patent (10) Patent N0.

: US 7,178,112 B1
Ciol? et a1. (45) Date of Patent: Feb. 13, 2007

(54) MANAGEMENT OF FUNCTIONS FOR OTHER PUBLICATIONS


BLOCK DIAGRAMS
dSpace News. National Instruments. “More than just a code gen
(75) Inventors; John Edward ciol?s wellesleys MA erator: TargetLink 2.0.” Retrieved from the Internetziwwwfengco.
(Us); Michael David Tocci’ se/nl-02-02.pdf. Retrieved on Apr. 26, 2006, pp. 13-16.
Shrewsbury, MA (US); Moj deh National Instruments. “MatriXXiSystem design and control devel
shakeri’ southborougha MA (Us); opment software.” Retrieved from the Internet: WWW.ni.com/pdf/
Murali Yeddanapudis Watenown, MA pgo7ducts/us/matrixxi04pdf. Retrieved on Apr. 26, 2005, pp. 124
(US); Kai Tuschner, Sudbury, MA '
(US); Ramamurthy Mani, Needham, * Cited b y examlner
-
MA (US)
Primary ExamineriThuan Do
(73) Assigneer The Mathwol‘ksa Inc's Natick, MA (74) Attorney, Agent, or FirmiLahive & Cock?eld LLP
(Us)
(57) ABSTRACT
(*) Notice: Subject to any disclaimer, the term of this
patent is extended or adjusted under 35
U-S~C~ 154(b) by 425 days- A method is provided that includes pattem-matching por
tions of a block diagram model as being equivalent, and
(21) Appl' N05 10/418,002 creation of a common set of instructions in place of the
_ _ occurrences of the pattern-matched portions to enhance the
(22) Flled' Apr‘ 16’ 2003 ef?ciency of simulation or generated code for the block
(51) Int Cl diagram model, such as by a reduced image siZe. Diagnos
Got'sF 27/50 (2006 01) ties are also available to provide information on the execu
52 U 5 Cl ' 716/1_ 716/18 tion structure of the block diagram and guidance on hoW to
( ) I. . . ....... ...... ..; ......................... .. , modify block Ofthe block diagram to Obtain reduced image
(58) Field of Classi?cation Search ................ .. 716/21, Size by increasing the amount of matching patterns Also,
I I 716(1’ 2’ 5’ 18 automatically generated hierarchical structures, a tool to
See apphcanon ?le for Complete Search hlstory' control the function signature and the ability for a user to
(56) References Cited control ?le packaging Which all provide ?exible control over
the generated code for block diagrams, are provided.
U.S. PATENT DOCUMENTS
2004/0019872 A1 * l/2004 Lippincott et al. .......... .. 716/21 35 Claims, 40 Drawing Sheets

Sorted list Sample time


F(output/update) 0. l
E(0utput/update) 0.1
D(0utput/update) 1
A(output) 0.1
B(output) l
Single-tasking execution in a non real-time system C(ompm) 1

output: FDEQDOAOBOCO
K-262 FOEOAD FOEDAO FDEODOAOBOCO FOEOAO 260

update: FuEuDu I
FuEul FuEu I
FuEuDul FuEu >
I l l l V

264 Real-world time


Execution time: 0.0 0.2 1.0 1.1

Single-tasking execution in a real-time system

/262
output: FOEODOAOBOCO FOEOAO FQEOAO FDEODOAOBUCD FOEOAO 270

update: FuEuD\| I FHE‘l I FuEu I FUEUDu FuEu


l | l | | >
0.0 0.1 0.2 1.0 1.1 Real-world time
wait L264 wait wait =Execution Time)
U.S. Patent Feb. 13, 2007 Sheet 1 0140 US 7,178,112 B1

/—2
In ut, u t —>
Dynamic System —> Output, y(t)
p () State: x(t), Parameters: P

Output: y(t,) = 1(1, x(t), u(t), P)f 4


Derivative: (FL) = g0, x0), u(t). P>f 6
dt

Fig. 1A
/8
Input, u(tk —> Dynamic System ——> Output, y(tk)
State: X(Ik), Parameters: P

Output: y(t,) = 1(7, x(tk), u(tk), P) f1‘)


Update: wk”) = g(tk, wk), u(tk), P)/12

Fig. 1B
/14
Input, u(t) —> Dynamic System —> Output, y(t)
Parameters: P

Algebraic Eq : 101(1), y(t), P) = of 16

Fig. 1C
U.S. Patent Feb. 13, 2007 Sheet 2 0f 40 US 7,178,112 B1

Fig. 2

Fig. 3
U.S. Patent Feb. 13, 2007 Sheet 3 0f 40 US 7,178,112 B1

Start with
Block-Diagram Model

/46
Link Linearize

Generate
code for model
sections?
48 N v
Generate Code

Continue with
simulation?

[Target“ 7 External mode


52d 54J / 50
Simulate / Execute Model
through Simulation Loop

Fig. 4
U.S. Patent Feb. 13, 2007 Sheet 4 0f 40 US 7,178,112 B1

62
K60 / K66
1 sineWave ' +
result
Constant + accum
To Workspace
delay
/ 64
l 4__
2

Initial condition = 0
Sample time = .2 seconds

K68 / 66
Synthesized block
representing > result
accumulator pattern
To Workspace

Fig. 5
U.S. Patent Feb. 13, 2007 Sheet 5 0f 40 US 7,178,112 B1

v2

w
wolf
59 5
mmmm

71/;. _8sS.§ F:5+K


281

=
E5
an
8 é § £
N2N2.
v:v6.MNRN
C
W
9l
6+:82>>E_2,
Y N5
26
35>
E6 1
2.. c
d

K
//Em ugowmhcmo //£2 326
Q:EF
26m >m§
U.S. Patent Feb. 13, 2007 Sheet 6 0f 40 US 7,178,112 B1

128
Sorted List: /—
0:0 Sine Wave 1
0:1 Sine Wave 2
0:2 Function-Call Generator
0:3 Function-Call Subsystem
0:4 Integrator
0:5 Gain (algebraic id 0#l)
0:6 Sum (algebraic variable for id 0#1)
0:7 Outl

Fig. 6B
U.S. Patent Feb. 13, 2007 Sheet 7 0f 40 US 7,178,112 B1

140 W 142 \ 144 \ 146 \ 148W 150\


' Block Block Block Block Block Block
A —>df B —> df C —> D —> E —> F
7
Qm/
Fig. 7A
160
g Block A Block B Block 0 Block D Block E Block F
Method1 Method1 Method1 Method1 Method1 Method1
Method3 Method3 Method3 Method2 Method2 Method2
Method4 Method4 Meth0d3
/ Meth0d5 7
\164 K166 K162 K168

Sorted list

Fig. 7C
U.S. Patent Feb. 13, 2007 Sheet 9 0f 40 US 7,178,112 B1

X
on“
928x5

N2
(2 % qME
5329:301
J
0“_x85mx86<a
w3;

2:.
U.S. Patent Feb. 13, 2007 Sheet 10 of 40 US 7,178,112 B1

Initialize

/ 202
Time < Stop Time? Simulation Complete

Execute Root Output


Method Execution List

Execute Root Update


Method Execution List

Integrate
7

Time = Time + Step Size

Fig. 10
U.S. Patent Feb. 13, 2007 Sheet 11 0140 US 7,178,112 B1

a.82 85

282%5: 589:05328 cu2om:s2u0:xam ‘ E2"S.8E58 52$8.58


896.285
@62.858 $2.858 568.58
mnw 22ME
E
V826520 @20358: 9E AH
a:8 %
"285 E85 585 $285 @305 Q80 5
U.S. Patent Feb. 13, 2007 Sheet 12 0f 40 US 7,178,112 B1
U.S. Patent Feb. 13, 2007 Sheet 15 of 40 US 7,178,112 B1

Initialize
l
Execute Output Method List /_222
for Sample Time
l
Execute Update Method List
for Fastest Sample Time

/ 226
Simulation
Complete

Integ rate r228


V

Increment TID $230

236\ Execute Output Method J


List of Given TID
Increment TID t
234
Execute Update Method J
List of Given TID
_____________l

Increment Simulation /238


Time / Reset TID
l
Fig. 13
U.S. Patent Feb. 13, 2007 Sheet 16 of 40 US 7,178,112 B1

l 240
Execute Derivative Method /
Execution List

v 242
Execute Output Method J
Execution List

244
Execute Derivative Method J
Execution List

l 246
Execute Output Method 2
Execution List

248
Execute Zero Crossing J
Method Execution List

i
Fig. 14
U.S. Patent Feb. 13, 2007 Sheet 17 0f 40 US 7,178,112 B1

300
\4
Search the block diagram for f 310
repeated patterns of blocks

Process the block d' am f320


to produce instru ' s

Fig. 15

* |n1 Out1 ln1 Out1 ‘

A1 A2
354 J \356
/\
\/
350i SineWave

Fig. 16A
U.S. Patent Feb. 13, 2007 Sheet 19 0f 40 US 7,178,112 B1

@ l
|n1 2'1 Out1
Di rete-Time
l grator

Fig. ]6C

f( ) 360
function f

<I>—~
|n1
l1
Z‘
—@
Out1
Discrete-Time
Integrator

Fig. 16D

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