Synthesis Tutorial using

Cadence RTL Compiler

1. Copy FreePDK directory and place it in your home directory. This is
the directory that has all the libraries you need for synthesis and
place & route

cd
rsync -avz /raid/home/jzhang41/FreePDK45 .

2. make a directory called my_syn in your home directory. This will

contain all the files for your synthesis.

cd
mkdir my_syn

3. go into my_syn, and copy the RC compiler start up script

cd
cd my_syn
rsync -avz /raid/home/jzhang41/my_syn/rc_start .

3. go into my_syn, and copy the counter VHDL file, an example

synthesis script, and also an example standard delay contrain file to
this directory

cd
cd my_syn
rsync -avz /raid/home/jzhang41/my_syn/src .
rsync -avz /raid/home/jzhang41/my_syn/rc_counter_top.tcl .
rsync -avz /raid/home/jzhang41/my_syn/counter.sdc .

Now, the counter VHDL file is placed in the sub-directory ./src of

my_syn. rc_counter_top.tcl is an example synthesis script. You can run
this script directly in rc compiler to generate the final verilog
netlist. But in this lab, I will ask you to copy the script line by
line and run it in RC compiler so you can learn the flow.

4. start RC compiler to begin synthesis by running the rc_start script

in the my_syn directory

sh ./rc_start

5. Now, you should see the RC compiler GUI startup, together with a
command line window. Now open up the example synthesis script
"rc_counter_top.tcl", copy and paste each line of the command into the
command line window of RC compiler to run each step of synthesis! let
me know if you have questions!

6. After you finish running the synthesis script, you should see the
RTL schematic of the counter displayed in the GUI. Please check the
timing report to make sure you have enough slack in your setup and
hold time.

7. At the end, the synthesis tool will generate a verilog net

(rc_counter_gates.v). This is what you will need to do the place and
route.