BF998 PDF

DISCRETE SEMICONDUCTORS
DATA SHEET
BF998; BF998R
Silicon N-channel dual-gate
MOS-FETs
Product specification 1996 Aug 01
Supersedes data of April 1991
NXP Semiconductors Product specification
Silicon N-channel dual-gate MOS-FETs BF998; BF998R
FEATURES
 Short channel transistor with high forward transfer handbook, halfpage d
admittance to input capacitance ratio 4 3
 Low noise gain controlled amplifier up to 1 GHz. g

2
g1
APPLICATIONS
 VHF and UHF applications with 12 V supply voltage,
such as television tuners and professional 1 2
communications equipment. s,b
Top view MAM039
DESCRIPTION Marking code: MOp.
Depletion type field effect transistor in a plastic

Fig.1 Simplified outline (SOT143B)
microminiature SOT143B or SOT143R package with
and symbol; BF998.
source and substrate interconnected. The transistors are
protected against excessive input voltage surges by
integrated back-to-back diodes between gates and
source.
handbook, halfpage
d
CAUTION 3 4
The device is supplied in an antistatic package. The g2
gate-source input must be protected against static
g1
discharge during transport or handling.
PINNING
2 1
PIN SYMBOL DESCRIPTION s,b
Top view MAM040
1 s, b source
Marking code: MOp.
2 d drain
3 g2 gate 2 Fig.2 Simplified outline (SOT143R)
4 g1 gate 1 and symbol; BF998R.
QUICK REFERENCE DATA
SYMBOL PARAMETER CONDITIONS TYP. MAX. UNIT

VDS drain-source voltage  12 V
ID drain current  30 mA
Ptot total power dissipation  200 mW
yfs forward transfer admittance 24  mS
Cig1-s input capacitance at gate 1 2.1  pF
Crs reverse transfer capacitance f = 1 MHz 25  fF
F noise figure f = 800 MHz 1  dB
Tj operating junction temperature  150 C
1996 Aug 01 2
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
VDS drain-source voltage  12 V
ID drain current  30 mA
IG1 gate 1 current  10 mA
IG2 gate 2 current  10 mA
Ptot total power dissipation; BF998 up to Tamb = 60 C; see Fig.3; note 1  200 mW
up to Tamb = 50 C; see Fig.3; note 2  200 mW
Ptot total power dissipation; BF998R up to Tamb = 50 C; see Fig.4; note 1  200 mW
Tstg storage temperature 65 +150 C
Tj operating junction temperature  150 C
Notes
1. Device mounted on a ceramic substrate, 8 mm  10 mm  0.7 mm.
2. Device mounted on a printed-circuit board.
MLA198 MGA002
handbook, halfpage handbook, halfpage
200 200
Ptot max (2) (1) Ptot max

(mW) (mW)
100 100
0
0 0 100 200
0 100 200
Tamb (o C) Tamb (°C)
(1) Ceramic substrate.

(2) Printed-circuit board.
Fig.3 Power derating curves; BF998. Fig.4 Power derating curve; BF998R.
1996 Aug 01 3
THERMAL CHARACTERISTICS
SYMBOL PARAMETER CONDITIONS VALUE UNIT

Rth j-a thermal resistance from junction to ambient in free air; BF998 note 1 460 K/W
note 2 500 K/W
Rth j-a thermal resistance from junction to ambient in free air; BF998R note 1 500 K/W
Notes
1. Device mounted on a ceramic substrate, 8 mm  10 mm  0.7 mm.
2. Device mounted on a printed-circuit board.
STATIC CHARACTERISTICS
Tj = 25 C; unless otherwise specified.
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V(BR)G1-SS gate 1-source breakdown voltage VG2-S = VDS = 0; IG1-SS = 10 mA 6 20 V
V(BR)G2-SS gate 2-source breakdown voltage VG1-S = VDS = 0; IG2-SS = 10 mA 6 20 V
V(P)G1-S gate 1-source cut-off voltage VG2-S = 4 V; VDS = 8 V; ID = 20 A  2.0 V
V(P)G2-S gate 2-source cut-off voltage VG1-S = 0; VDS = 8 V; ID = 20 A  1.5 V
IDSS drain-source current VG2-S = 4 V; VDS = 8 V; VG1-S = 0; note 1 2 18 mA
IG1-SS gate 1 cut-off current VG2-S = VDS = 0; VG1-S = 5 V  50 nA
IG2-SS gate 2 cut-off current VG1-S = VDS = 0; VG2-S = 5 V  50 nA
Note
1. Measured under pulse condition.
DYNAMIC CHARACTERISTICS
Common source; Tamb = 25 C; VDS = 8 V; VG2-S = 4 V; ID = 10 mA.
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

yfs forward transfer admittance f = 1 kHz 21 24  mS
Cig1-s input capacitance at gate 1 f = 1 MHz  2.1 2.5 pF
Cig2-s input capacitance at gate 2 f = 1 MHz  1.2  pF
Cos output capacitance f = 1 MHz  1.05  pF
Crs reverse transfer capacitance f = 1 MHz  25  fF
F noise figure f = 200 MHz; GS = 2 mS; BS = BSopt  0.6  dB
f = 800 MHz; GS = 3.3 mS; BS = BSopt  1.0  dB
1996 Aug 01 4
MGE813 MGE815
24 24
handbook,
I halfpage handbook,
I halfpage
D D 3V
VG1-S =
(mA) (mA) VG2-S = 4 V 2V
20 0.4 V 20
1V
0.3 V
16 16
0.2 V
12 0.1 V 12
0V
8 −0.1 V 8
−0.2 V
4 0V
4 −0.3 V
−0.4 V
−0.5 V
0 0
0 2 4 6 8 10 −1 0 1
VG1 (V)
VDS (V)
VG2-S = 4 V; Tamb = 25 C. VDS = 8 V; Tamb = 25 C.
Fig.5 Output characteristics; typical values. Fig.6 Transfer characteristics; typical values.
MGE814 MGE811
24 30
handbook,
I halfpage handbook, halfpage
D 4V
|yfs|
(mA) 3V
max typ (mS)
20 2V
24
1V
16
18
12
min
12
8
6
4
VG2-S = 0 V 0.5 V
0 0
−1600 −1200 −800 −400 0 400 0 4 8 12 16 20
VG1 (mV) ID (mA)
VDS = 8 V; VG2-S = 4 V; Tamb = 25 C. VDS = 8 V; Tamb = 25 C.
Fig.7 Drain current as a function of gate 1 Fig.8 Forward transfer admittance as a function of
voltage; typical values. drain current; typical values.
1996 Aug 01 5
MGE812 MGE810
30 1.5
|yfs| VG2-S = 4 V Cos
(mS) (pF)
24 1.4
3V
18 1.3
2V
12 1.2
12 mA
6 1V 1.1 10 mA
8 mA
0V
0 1.0
−1 0 1 4 6 8 10 12 14
VG1 (V)
VDS (V)
VDS = 8 V; Tamb = 25 C. VG2-S = 4 V; f = 1 MHz; Tamb = 25 C.
Fig.9 Forward transfer admittance as a function of Fig.10 Output capacitance as a function of

gate 1 voltage; typical values. drain-source voltage; typical values.
MGE809 MBH479
2.3 2.4
Cis Cis
(pF) (pF)
2.1
2.3
1.9
2.2
1.7
2.1
1.5
1.3 2.0
−2.4 −1.6 −0.8 0 0.8 6 4 2 0 −2
VG1-S (V) VG2−S (V)
VDS = 8 V; VG2-S = 4 V; f = 1 MHz; Tamb = 25 C. VDS = 8 V; VG1-S = 0 V; f = 1 MHz; Tamb = 25 C.
Fig.11 Gate 1 input capacitance as a function of Fig.12 Gate 1 input capacitance as a function of
gate 1-source voltage; typical values. gate 2-source voltage; typical values.
1996 Aug 01 6
MGC466 MGC467
10 10 3 10 3
y is y rs ϕrs
(mS) (μS) (deg)
b is ϕ rs
1 10 2 10 2
y rs
10 1 10 10
g is
10 2 1 1
10 102 f (MHz) 10 3 10 102 f (MHz) 10 3
VDS = 8 V; VG2-S = 4 V; ID = 10 mA; Tamb = 25 C. VDS = 8 V; VG2-S = 4 V; ID = 10 mA; Tamb = 25 C.
Fig.13 Input admittance as a function of the Fig.14 Reverse transfer admittance and phase as a
frequency; typical values. function of frequency; typical values.
MGC468 MGC469
10 2 10 2 10
yos
y fs ϕ fs (mS) bos
(mS) y fs (deg)
1
10 ϕ 10
fs
gos
10 1
1 1 10 2
10 102 f (MHz) 10 3 10 102 f (MHz) 10 3
VDS = 8 V; VG2-S = 4 V; ID = 10 mA; Tamb = 25 C. VDS = 8 V; VG2-S = 4 V; ID = 10 mA; Tamb = 25 C.
Fig.15 Forward transfer admittance and phase as a Fig.16 Output admittance as a function of the
function of frequency; typical values. frequency; typical values.
1996 Aug 01 7
handbook, full pagewidth VDD

47 μF
Vagc 1 nF
1 nF
20 μH
1 nF
1 nF
1.8 kΩ 50 Ω
47 kΩ output
L2
1 nF
C1
5.5 pF
50 Ω 1 nF
input
15 pF 360 Ω 10 pF
L1
140 kΩ
VDD 1 nF D1 D2
BB405 330 kΩ BB405 330 kΩ
100 kΩ 1 nF 1 nF
Vtun Vtun
input output MGE802
VDD = 12 V; GS = 2 mS; GL = 0.5 mS.

L1 = 45 nH; 4 turns 0.8 mm copper wire, internal diameter 4 mm.
L2 = 160 nH; 3 turns 0.8 mm copper wire, internal diameter 8 mm.
Tapped at approximately half a turn from the cold side, to adjust GL = 0.5 mS. C1 adjusted for GS = 2 mS.
Fig.17 Gain control test circuit at f = 200 MHz.
1996 Aug 01 8
handbook, full pagewidth VDD Vagc VDD
1 nF 1 nF
140 kΩ
100 kΩ
1 nF
L4
270 kΩ
L3 1 nF
L1 1 nF 50 Ω
output
1 nF L2
50 Ω 1 nF C3 C4
input 0.5 to 4 to 40 pF
3.5 pF
C1 C2
2 to 18 pF 0.5 to 3.5 pF MGE801
1.8 kΩ 360 Ω
VDD
VDD = 12 V; GS = 3.3 mS; GL = 1 mS.

L1 = L4 = 200 nH; 11 turns 0.5 mm copper wire, without spacing, internal diameter 3 mm.
L2 = 2 cm, silvered 0.8 mm copper wire, 4 mm above ground plane.
L3 = 2 cm, silvered 0.5 mm copper wire, 4 mm above ground plane.
Fig.18 Gain control test circuit at f = 800 MHz.
1996 Aug 01 9
MGE808 MGE807
0 0
ΔGtr ΔGtr
(dB) (dB) IDSS =
−10 −10 max
typ
min
−20 −20
−30 −30
IDSS =
−40 −40
max
typ
min
−50 −50
0 2 4 6 8 10 0 2 4 6 8 10
Vagc (V) Vagc (V)
VDD = 12 V; f = 200 MHz; Tamb = 25 C. VDD = 12 V; f = 800 MHz; Tamb = 25 C.
Fig.19 Automatic gain control characteristics Fig.20 Automatic gain control characteristics
measured in circuit of Fig.17. measured in circuit of Fig.18.
1996 Aug 01 10
PACKAGE OUTLINES
Plastic surface-mounted package; 4 leads SOT143B
D B E A X
y
v M A HE
e
bp w M B
4 3
A1
c
1 2
Lp
b1
e1 detail X
0 1 2 mm
scale
DIMENSIONS (mm are the original dimensions)

A1
UNIT A bp b1 c D E e e1 HE Lp Q v w y
max
1.1 0.1 0.48 0.88 0.15 3.0 1.4 2.5 0.45 0.55
mm 1.9 1.7 0.2 0.1 0.1
0.9 0.38 0.78 0.09 2.8 1.2 2.1 0.15 0.45
OUTLINE REFERENCES EUROPEAN

ISSUE DATE
VERSION IEC JEDEC JEITA PROJECTION
04-11-16
SOT143B
06-03-16
1996 Aug 01 11
Plastic surface-mounted package; reverse pinning; 4 leads SOT143R
D B E A X
y
v M A HE
e
bp w M B
3 4
Q
A1
c
2 1
Lp
b1
e1 detail X
0 1 2 mm
scale
DIMENSIONS (mm are the original dimensions)

A1
UNIT A bp b1 c D E e e1 HE Lp Q v w y
max
1.1 0.1 0.48 0.88 0.15 3.0 1.4 2.5 0.55 0.45
mm 1.9 1.7 0.2 0.1 0.1
0.9 0.38 0.78 0.09 2.8 1.2 2.1 0.25 0.25
OUTLINE REFERENCES EUROPEAN

ISSUE DATE
VERSION IEC JEDEC JEITA PROJECTION
04-11-16
SOT143R SC-61AA
06-03-16
1996 Aug 01 12
DATA SHEET STATUS
DOCUMENT PRODUCT
DEFINITION
STATUS(1) STATUS(2)
Objective data sheet Development This document contains data from the objective specification for product
development.
Preliminary data sheet Qualification This document contains data from the preliminary specification.
Product data sheet Production This document contains the product specification.
Notes
1. Please consult the most recently issued document before initiating or completing a design.
2. The product status of device(s) described in this document may have changed since this document was published
and may differ in case of multiple devices. The latest product status information is available on the Internet at
URL http://www.nxp.com.
DEFINITIONS Right to make changes  NXP Semiconductors

reserves the right to make changes to information
Product specification  The information and data
published in this document, including without limitation
provided in a Product data sheet shall define the
specifications and product descriptions, at any time and
specification of the product as agreed between NXP
without notice. This document supersedes and replaces all
Semiconductors and its customer, unless NXP
information supplied prior to the publication hereof.
Semiconductors and customer have explicitly agreed
otherwise in writing. In no event however, shall an Suitability for use  NXP Semiconductors products are
agreement be valid in which the NXP Semiconductors not designed, authorized or warranted to be suitable for
product is deemed to offer functions and qualities beyond use in life support, life-critical or safety-critical systems or
those described in the Product data sheet. equipment, nor in applications where failure or malfunction
of an NXP Semiconductors product can reasonably be
expected to result in personal injury, death or severe
DISCLAIMERS
property or environmental damage. NXP Semiconductors
Limited warranty and liability  Information in this accepts no liability for inclusion and/or use of NXP
document is believed to be accurate and reliable. Semiconductors products in such equipment or
However, NXP Semiconductors does not give any applications and therefore such inclusion and/or use is at
representations or warranties, expressed or implied, as to the customer’s own risk.
the accuracy or completeness of such information and
Applications  Applications that are described herein for
shall have no liability for the consequences of use of such
any of these products are for illustrative purposes only.
information.
NXP Semiconductors makes no representation or
In no event shall NXP Semiconductors be liable for any warranty that such applications will be suitable for the
indirect, incidental, punitive, special or consequential specified use without further testing or modification.
damages (including - without limitation - lost profits, lost
Customers are responsible for the design and operation of
savings, business interruption, costs related to the
their applications and products using NXP
removal or replacement of any products or rework
Semiconductors products, and NXP Semiconductors
charges) whether or not such damages are based on tort
accepts no liability for any assistance with applications or
(including negligence), warranty, breach of contract or any
customer product design. It is customer’s sole
other legal theory.
responsibility to determine whether the NXP
Notwithstanding any damages that customer might incur Semiconductors product is suitable and fit for the
for any reason whatsoever, NXP Semiconductors’ customer’s applications and products planned, as well as
aggregate and cumulative liability towards customer for for the planned application and use of customer’s third
the products described herein shall be limited in party customer(s). Customers should provide appropriate
accordance with the Terms and conditions of commercial design and operating safeguards to minimize the risks
sale of NXP Semiconductors. associated with their applications and products.
1996 Aug 01 13
NXP Semiconductors does not accept any liability related Export control  This document as well as the item(s)
to any default, damage, costs or problem which is based described herein may be subject to export control
on any weakness or default in the customer’s applications regulations. Export might require a prior authorization from
or products, or the application or use by customer’s third national authorities.
party customer(s). Customer is responsible for doing all
Quick reference data  The Quick reference data is an
necessary testing for the customer’s applications and
extract of the product data given in the Limiting values and
products using NXP Semiconductors products in order to
Characteristics sections of this document, and as such is
avoid a default of the applications and the products or of
not complete, exhaustive or legally binding.
the application or use by customer’s third party
customer(s). NXP does not accept any liability in this Non-automotive qualified products  Unless this data
respect. sheet expressly states that this specific NXP
Semiconductors product is automotive qualified, the
Limiting values  Stress above one or more limiting
product is not suitable for automotive use. It is neither
values (as defined in the Absolute Maximum Ratings
qualified nor tested in accordance with automotive testing
System of IEC 60134) will cause permanent damage to
or application requirements. NXP Semiconductors accepts
the device. Limiting values are stress ratings only and
no liability for inclusion and/or use of non-automotive
(proper) operation of the device at these or any other
qualified products in automotive equipment or
conditions above those given in the Recommended
applications.
operating conditions section (if present) or the
Characteristics sections of this document is not warranted. In the event that customer uses the product for design-in
Constant or repeated exposure to limiting values will and use in automotive applications to automotive
permanently and irreversibly affect the quality and specifications and standards, customer (a) shall use the
reliability of the device. product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and
Terms and conditions of commercial sale  NXP
specifications, and (b) whenever customer uses the
Semiconductors products are sold subject to the general
product for automotive applications beyond NXP
terms and conditions of commercial sale, as published at
Semiconductors’ specifications such use shall be solely at
http://www.nxp.com/profile/terms, unless otherwise
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NXP Semiconductors for any liability, damages or failed
individual agreement is concluded only the terms and
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the product for automotive applications beyond NXP
Semiconductors hereby expressly objects to applying the
Semiconductors’ standard warranty and NXP
customer’s general terms and conditions with regard to the
Semiconductors’ product specifications.
purchase of NXP Semiconductors products by customer.
No offer to sell or license  Nothing in this document
may be interpreted or construed as an offer to sell products
that is open for acceptance or the grant, conveyance or
implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
1996 Aug 01 14
NXP Semiconductors
provides High Performance Mixed Signal and Standard Product
solutions that leverage its leading RF, Analog, Power Management,
Interface, Security and Digital Processing expertise
Customer notification
This data sheet was changed to reflect the new company name NXP Semiconductors, including new legal
definitions and disclaimers. No changes were made to the technical content, except for package outline
drawings which were updated to the latest version.
Contact information
For additional information please visit: http://www.nxp.com

For sales offices addresses send e-mail to: salesaddresses@nxp.com
© NXP B.V. 2010
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands R77/02/pp15 Date of release:1996 Aug 01

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DISCRETE SEMICONDUCTORS

Silicon N-channel dual-gate MOS-FETs BF998; BF998R

 Low noise gain controlled amplifier up to 1 GHz. g

DESCRIPTION Marking code: MOp.

Depletion type field effect transistor in a plastic

QUICK REFERENCE DATA

SYMBOL PARAMETER CONDITIONS TYP. MAX. UNIT

Silicon N-channel dual-gate MOS-FETs BF998; BF998R

Ptot max (2) (1) Ptot max

(1) Ceramic substrate.

Silicon N-channel dual-gate MOS-FETs BF998; BF998R

SYMBOL PARAMETER CONDITIONS VALUE UNIT

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Silicon N-channel dual-gate MOS-FETs BF998; BF998R

VG2-S = 4 V; Tamb = 25 C. VDS = 8 V; Tamb = 25 C.

VDS = 8 V; VG2-S = 4 V; Tamb = 25 C. VDS = 8 V; Tamb = 25 C.

Silicon N-channel dual-gate MOS-FETs BF998; BF998R

VDS = 8 V; Tamb = 25 C. VG2-S = 4 V; f = 1 MHz; Tamb = 25 C.

Fig.9 Forward transfer admittance as a function of Fig.10 Output capacitance as a function of

Silicon N-channel dual-gate MOS-FETs BF998; BF998R

Silicon N-channel dual-gate MOS-FETs BF998; BF998R

handbook, full pagewidth VDD

VDD = 12 V; GS = 2 mS; GL = 0.5 mS.

Fig.17 Gain control test circuit at f = 200 MHz.

Silicon N-channel dual-gate MOS-FETs BF998; BF998R

handbook, full pagewidth VDD Vagc VDD

VDD = 12 V; GS = 3.3 mS; GL = 1 mS.

Fig.18 Gain control test circuit at f = 800 MHz.

Silicon N-channel dual-gate MOS-FETs BF998; BF998R

Silicon N-channel dual-gate MOS-FETs BF998; BF998R

DIMENSIONS (mm are the original dimensions)

OUTLINE REFERENCES EUROPEAN

Silicon N-channel dual-gate MOS-FETs BF998; BF998R

Plastic surface-mounted package; reverse pinning; 4 leads SOT143R

DIMENSIONS (mm are the original dimensions)

OUTLINE REFERENCES EUROPEAN

Silicon N-channel dual-gate MOS-FETs BF998; BF998R

DATA SHEET STATUS

DEFINITIONS Right to make changes  NXP Semiconductors

Silicon N-channel dual-gate MOS-FETs BF998; BF998R

For additional information please visit: http://www.nxp.com

© NXP B.V. 2010

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