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Class D Amplifier Introduction - Gate Driver - Mosfet - Package - Design Example
Class D Amplifier Introduction - Gate Driver - Mosfet - Package - Design Example
• Gate Driver
How to drive the gate, key parameters in gate
drive stage
• MOSFET
How to choose, tradeoff relationships, loss calculation
• Package
Importance of layout and package, new packaging
technology
• Design Example
200W+200W stereo Class D amplifier
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Prepared Oct.8 2003 by Jun Honda and Jorge Cerezo
Trend in Class D Amplifiers
• Make it smaller!
- higher efficiency
- smaller package
- Half Bridge
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System Î Gate Drive Î MOSFET Î Design Example
Traditional Linear Amplifier
Feed back
• Vcc
• •
Error amp Bias
•
• Vcc
Feed back
Triangle +V C C
Nch
Level Shift
Class D
COMP LPF
switching stage
Efficiency
Output Output
Good PSRR 0 dB
Both way
Always from Direction of Creates Vbus pumping
supply to load phenomena
energy flow
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System Î Gate Drive Î MOSFET Î Design Example
Analogy to Buck DC-DC Converter
Buck Converter Class D Amplifier
Fc of LPF is above
Gate Driver
Gate Driver
20KHz
Q1
MOSFET
Q1
MOSFET
U1A
8
U1A L1
3
8
+
L1 1
3 2
+
1 - INDUCTOR
2 ERROR AMP
- INDUCTOR
4
R1
ERROR AMP C1 LOAD
4
R1 CAPACITOR
C1 LOAD Q2
Vref
CAPACITOR
MOSFET
Q2
MOSFET
ÎLow RDS(ON) for longer duty, low Qg ÎSame RDS(ON) required for both sides
for shorter duty www.irf.com
System Î Gate Drive Î MOSFET Î Design Example
Loss in Power Device Loss
2
VCC
Pc = 0.2 ⋅
8 ⋅ RL
Loss in class AB
π
Vcc
PC =
1
⋅∫ (1 − K sin ω ⋅ t ) Vcc K sin ω ⋅ t • dω ⋅ t
2 ⋅π 0 2 2 ⋅ RL
Vcc 2 2K K 2
= ⋅ − Regardless of output
8π ⋅ RL π 2 device parameters. K=2/π K=1
Loss
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System Î Gate Drive Î MOSFET Î Design Example
Major Cause of Imperfection
Perturbation
Zo
Pulse width error Bus Pumping +V C C Non linear inductance /
Quantization error Capacitance
DCR
-V C C
Dead time
Delay time Finite RDS(on)
Vth and Qg
Body diode recovery
R DS(ON)
Finite dV/dt
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System Î Gate Drive Î MOSFET Î Design Example
THD and Dead Time
High Side Dead Time
Low Side Dead Time
ON
High Side
OFF
ON
Low Side
OFF
30
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System Î Gate Drive Î MOSFET Î Design Example
Shoot Through and Dead Time
Q s t a s a f u n c t io n o f O v e r la p T im e & R g
V b u s = 6 0 V , Id = 2 A , V g s = 1 2 V
High side Vgs ( O v e r la p t im e m e a s u r e d f r o m 5 0 % V g s h ig h s id e f a ll t o 1 0 % V g s lo w s id e r is e )
80
R g=1O hm s
60 R g=5O hm s
rg=10O hm s
40
0
-10 -5 0 5 10 15 20
O v e r la p tim e (n s )
Vo
-Vcc
Commutation VBUS
current ∆VBUS max =
8 ⋅ π ⋅ f PWM ⋅ RLOAD ⋅ C BUS
1• 2 3•
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System Î Gate Drive Î MOSFET Î Design Example
Functional Block Diagram Inside Gate Driver
International Rectifier's family of MOS gate drivers integrate most of the
functions required to drive one high side and one low side power
MOSFET in a compact package.
With the addition of few components, they provide very fast switching
speeds and low power dissipation.
Input Logic
High side well
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System Î Gate Drive Î MOSFET Î Design Example
Boot Strap High Side Power Supply
Charge Discharge
ON
ON
When Vs is pulled down to ground through the low side FET, the bootstrap capacitor (CBOOT)
charges through the bootstrap diode (Dbs) from the Vcc supply, thus providing a supply to
Vbs.
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System Î Gate Drive Î MOSFET Î Design Example
Boot Strap High Side Power Supply (Cont’d)
• Boot Strap Capacitor Selection
To minimize the risk of overcharging and further reduce ripple on the Vbs voltage the
Cbs value obtained from the above equation should be should be multiplied by a factor
of 15 (rule of thumb).
PG = V ⋅ f SW ⋅ QG
For two IRF540 HEXFET® MOSFETs operated at 400kHz with Vgs = 12V, we
have:
PG = 2 • 12 • 37 • 10-9 • 400 • 103 = 0.36W
R3 R3
High Side High Side
SW1
SW1
R2 C1 R2 C1
Low Side Ciss Low Side Ciss
50.00
•These losses are not
25.00
temperature dependent.
0.00
1.E +03 1.E +04 1.E +05 1.E +06
Frequency (H z)
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System Î Gate Drive Î MOSFET Î Design Example
Layout Considerations
IR2011
Key Specs
IR2011(S)
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System Î Gate Drive Î MOSFET Î Design Example
How MOSFETs Work
• A MOSFET is a voltage-controlled power switch.
A voltage must be applied between Gate and
Source terminals to produce a flow of current in
the Drain.
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System Î Gate Drive Î MOSFET Î Design Example
MOSFET Technologies (1)
• IR is striving to continuously improve the power MOSFET
to enhance the performance, quality and reliability.
• Trench Technology
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System Î Gate Drive Î MOSFET Î Design Example
MOSFET Technologies (2)
• Power MOSFET FOMs (R*Qg) have significantly improved
between the released IR MOSFET technologies
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System Î Gate Drive Î MOSFET Î Design Example
Key Parameters of MOSFETs (1)
• Voltage Rating, BVDSS
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System Î Gate Drive Î MOSFET Î Design Example
Key Parameters of MOSFETs (2)
• Gate Charge, Qg
This parameter is directly
related to the MOSFET speed
and is temperature-
independent. Lower Qg results
in faster switching speeds and
consequently lower switching
losses.
The total gate charge has two
main components: the gate- Basic Gate Charge Waveform
source charge, Qgs and, the
gate-drain charge, Qgd (often
called the Miller charge). www.irf.com
System Î Gate Drive Î MOSFET Î Design Example
Key Parameters of MOSFETs (3)
• Static Drain-to-Source On-Resistance, RDS(ON)
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System Î Gate Drive Î MOSFET Î Design Example
Key Parameters of MOSFETs (4)
• Body Diode Reverse Recovery Characteristics, Qrr, trr, Irr
and S factor.
Power MOSFETs inherently have an
integral reverse body-drain diode. This
body diode exhibits reverse recovery
characteristics. Reverse Recovery
Charge Qrr, Reverse Recovery Time trr,
Reverse Recovery Current Irr and
Softness factor (S = tb/ta), are typically
specified on data sheets at 25°C and
di/dt = 100A/us.
Reverse recovery characteristics are
temperature-dependent and lower trr, Irr
and Qrr improves THD, EMI and
Efficiency η. Typical Voltage –Current Waveforms
for a MOSFET Body Diode
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System Î Gate Drive Î MOSFET Î Design Example
Key Parameters of MOSFETs (5)
• Package
MOSFET devices are available in several
packages as SO-8,TO-220, D-Pak, I-Pak, TO-
262, DirectFET™, etc.
The selection of a MOSFET package for a
specific application depends on the package
characteristics such as dimensions, power
dissipation capability, current capability, internal
inductance, internal resistance, electrical
isolation and mounting process.
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System Î Gate Drive Î MOSFET Î Design Example
Choosing the MOSFET Voltage Rating for Class D applications (1)
2 * POUT * RLOAD
VBDSS min = * 1.5
M
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Note 1. Modulation Factor M = 85%
System Î Gate Drive Î MOSFET Î Design Example
Calculation of Switching Loss (1)
• Switching Losses are the result of turn-on and
turn-off switching times
↑ Rg ⇒ ↓ Ig ⇒ ↑ tSWITCHING ⇒ ↑ PSWITCHING
RG
↑ Qg ⇒ ↑ tSWITCHING ⇒ ↑ PSWITCHING
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System Î Gate Drive Î MOSFET Î Design Example
Estimation of Switching Losses (1)
• Switching losses can be obtained by calculating
the switching energy dissipated in the MOSFET
t
Pmax = (Tamb – Tjmax ) / (Rthjc max + Rthcs max + Rths max + Rthsa max)
Where: Tamb = Ambient Temperature
Tjmax = Max. Junction Temperature
Rthjc max = Max. Thermal Resistance Junction to Case
Rthcs max = Max. Thermal Resistance Case to Heatsink
Rths max = Max. Thermal Resistance of Heatsink
Rthsa max = Max. Thermal Resistance Heatsink to Ambient www.irf.com
System Î Gate Drive Î MOSFET Î Design Example
RDS(ON) vs Qg
• There is tradeoff between Static Drain-to-Source On-
Resistance, RDS(ON) and Gate charge, Qg
Higher RDS(ON) ⇒ Lower Qg ⇒ Higher PCONDUCTION & Lower PSWITCHING
Lower RDS(ON) ⇒ Higher Qg ⇒ Higher PSWITCHING & Lower PCONDUCTION
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System Î Gate Drive Î MOSFET Î Design Example
Die Size vs Power Loss (1)
• Die size has a significant influence on MOSFET power
losses
Smaller Die ⇒ Higher PCONDUCTION & Lower PSWITCHING
Bigger Die ⇒ Higher PSWITCHING & Lower PCONDUCTION
Gen 7 100V MOSFET Platform – Power Losses @ 384kHz
Total Loss
Conduction
Loss Switching
Loss
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System Î Gate Drive Î MOSFET Î Design Example
Die Size vs Power Loss (2)
• Die size is directly related with RDS(ON) and RTHjc of the
MOSFET
Smaller Die ⇒ Higher RDS(ON) and Higher RTHjc
Bigger Die ⇒ Lower RDS(ON) and Lower RTHjc
55V Trench Technology MosFET 55V Trench Technology MosFET
Die Size vs. RDS(ON) Die Size vs. RTHjc
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System Î Gate Drive Î MOSFET Î Design Example
Choosing the Right MOSFET for Class D Applications (1)
• The criteria to select the right MOSFET for a Class D amplifier
application are:
– VBDSS should be selected according to amplifier operating voltage,
and it should be large enough to avoid avalanche condition during
operation
– Efficiency η is related to static drain-to-source on-resistance, RDS(ON).
smaller RDS(ON) improves efficiency η. RDS(ON) is recommended to be
smaller than 200mΩ for mid and high-end power, full-bandwidth
amplifiers
– Low gate charge, Qg, improves THD and efficiency η. Qg is
recommended to be smaller than 20nC for mid and high-end power,
full-bandwidth amplifiers
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System Î Gate Drive Î MOSFET Î Design Example
Choosing the Right MOSFET for Class D Application (2)
– Amplifier performance such as THD, EMI and efficiency η are also
related to MOSFET reverse recovery characteristics. Lower trr, Irr
and Qrr improves THD, EMI and efficiency η
– Rthjc should be small enough to dissipate MOSFET power losses
and keep Tj < limit
– Better reliability and lower cost are achieved with higher MOSFET
Tj max
– Finally, selection of device package determines the dimensions,
electrical isolation and mounting process. These factors should be
considered in package selection. Because cost, size and amplifier
performance depend on it.
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System Î Gate Drive Î MOSFET Î Design Example
Development of Class D Dedicated Devices
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System Î Gate Drive Î MOSFET Î Design Example
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System Î Gate Drive Î MOSFET Î Design Example
Influences of Stray Inductance
• Drain and source stray inductances reduces the gate voltage during
turn-on resulting in longer switching time.
• Also during turn-off, drain and source stray inductances generate a
large voltage drop due to dID/dt, producing drain to source over-
voltage transients.
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System Î Gate Drive Î MOSFET Î Design Example
DirectFET™ Packaging
Use a single multiple-finned heat sink
to dissipate heat from devices
passivated die DirectFET devices
copper ‘drain’ clip die attach material
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System Î Gate Drive Î MOSFET Î Design Example
Class D Amp Reference Design
• Specs
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System Î Gate Drive Î MOSFET Î Design Example
Class D Amp Reference Board: Block Diagram
Feed back
+V C C
Comparator
74HC04 IRFB23N15D
-V C C
-VCC
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System Î Gate Drive Î MOSFET Î Design Example
Circuit Diagram
1 2 3 4
D
R1
CH1 Feed Back Path
R3 +50V
D
47K 1K
C1
220pF, 100V
C8 Level Shift 1
2
3
0.1uF, 50V
R37
Q2 C25 47mOHM, 2W MKDS5/3-9.5
0.01uF R12
470 GNDP
GNDP
C17 MMBT5401
TP3 R28 -50V
1000pF, 100V PROTECT
R11 PAD 22K GNDP
R23 10K
TP
100 R26
1K
Input analog
C C18 C31 C38 C
2
MA2YD23
LPF
1
0.22uF, 100V
R21 R82 VDD_1
D6
470uF, 50V
J1 5K 1uF, 16V 10K Q5
0.22uF, 100V
U2 U4 U6
7
R10 C6 HO
3 GNDP Q1 2 7 2 7 9.1 R39 CH1 OUT
R4 C23 IRFB23N15D
10K U1 6 3 6 3 6 2 0.33uF, 25V 1
VB RLY1A
R8 10uF, 50V D1 D2 2 1K 4 5 4 5 MURS120 GNDP GNDP
L1
3
1N4148
1N4148
330K 6 4 J5
dummy
LT1220CS8 Lin VS
MMBT5401 TC7WH04FU TC7WH08FU 8 5
1
1 18uH
VCC 255-1054 (1) 2
4
R49 C51
GNDP 5 7 4.7 R61 MKDS5/2-9.5
1
0.47uF, 100V
C42 Hin COM MA2YD23 C49
GNDP Q9 10, 1W
0.1uF, 100V
R13 B MMBT3904 TP4 8 D7 Q6
LO
TP
3
MURS120DICT dummy
dummy
dummy
dummy GNDP
B B
-5V
R44 SD1 R47
4.7K 10 C44
1uF, 16V
Snubber
C19
dummy
R14 C32 C39
10K
0.22uF, 100V
470uF, 50V
-50_1
-50+VCC
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Sheet 2 of 4 Number: Revision:1.0
INTERNATIONAL RECTIFIER
Drawn by: Approved by: EL SEGUNDO, CALIFORNIA, USA
Modulator Protection
Analog Input
MOSFET
Gate Driver
(CH1) Speaker
HeatSink
(CH1) LPF
(CH1) (CH1)
Bus Capacitor
±5V
Regulator
Gate Driver
MOSFET
Modulator Speaker
LPF
Analog Input
(CH2) (CH2) (CH2)
(CH2)
+12V DC/DC
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Power Supply
System Î Gate Drive Î MOSFET Î Design Example
Performance
50W / 4Ω, 1KHz, THD+N=0.0078%
THD+N v.s. Output Power
10
9.35 HP8903B
CH1, f=1KHz, RL=4Ω
VCC=±50.0V
1
fPWM=426KHz
THD 0.1
0.01
342W / 4Ω, 1KHz, THD+N=10%
−3
7.5×101 .10 3
3
0.1 1 10 100 1 .10
0.16 Output_Power 342.3
fPWM=364KHz
THD 0.1
0.01
−3
7.1×101 .10 3
3 4 5
10 100 1 .10 1 .10 1 .10
20 Frequency 4
LPF
2×10
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Conclusion
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