library IEEE;

use IEEE.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.std_logic_unsigned.all;

entity my_example is
port (led : out std_logic;
CLK: in std_logic);
end my_example;
-- architecture
architecture my_soln_exam of my_example is
signal AB: std_logic_vector(1 downto 0);
signal NK: std_logic:='0';
signal A : std_logic:='0';
signal B : std_logic:='0';
signal pulso : std_logic :='0';
signal contador: integer range 0 to 99999999:=0;
signal contwo : integer range 0 to 5:=0;

begin

AB <= A & B; -- group signals for case statement

my_proc: process (CLK)
begin
if(rising_edge(CLK)) then
if (contador=400000) then
pulso <= NOT(pulso);
contador <= 0;
else
contador <= contador+1;
end if;
end if;
NK <= pulso;
if (contwo =3) then
contwo <= 0;
elsif (rising_edge(NK)) then
contwo <= contwo + 1;
end if;

-- ABC <= std_logic_vector(contwo);

--ABC <= std_logic_vector((contwo, ABC'length));
-- AB <= std_logic_vector(to_unsigned(contwo, ABC'length));
AB<=conv_std_logic_vector(contwo,2);
--AB <= (contwo, ABC'length);
case (AB) is
when "00" => led <= '1';
when "01" => led <= '1';
when "10" => led <= '1';
when others => led <= '0';
end case;
end process my_proc;
end my_soln_exam;