entity div_freq is

Port ( clk : in STD_LOGIC;

reset : in STD_LOGIC;
eout : out STD_LOGIC);
end div_freq;

architecture Behavioral of div_freq is

signal cp,cs : std_logic_vector ( 26 downto 0) ; --1011111010111100001000000
begin

com : process ( cp)

begin

if (cp = "1011111010111100001000000") then

eout <= '1';
cs <= (others=> '0');
else
eout <= '0';
cs <= cp+1;
end if;
end process com;

sec: process (clk,reset)

begin
if (reset ='1') then
cp <= (others => '0');
elsif (clk'event and clk = '1') then
cp <= cs;
end if;
end process sec;

end Behavioral;