library IEEE;

use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity PWM_SERVO50 is
port (
clk : in std_logic;
PWM1: out std_logic;
reset: in std_logic);

end PWM_SERVO50;

architecture Behavioral of PWM_SERVO50 is

signal HN, HP : std_logic;

signal contador : integer range 1 to 1000000;

begin

COMBINACIONAL: PROCESS(HP,CONTADOR, CLK)

constant pos1: integer := 70000; --representa a 1.50ms = 0�

constant pos2: integer := 54000; --representa a 1.75ms = 45�

BEGIN
if rising_edge(clk)then
contador <= contador + 1;
end if;

if (HP= '0') then

if (contador <= pos2 )then
PWM1 <= '1';
HN<=HP;
else
PWM1 <= '0';
HN<='1';
end if;

ELSE
if (contador <= pos1 )then
PWM1 <= '1';
HN<=HP;
else
PWM1 <= '0';
HN<='0';
end if;

END IF;

END PROCESS COMBINACIONAL;

SECUENCIAL: PROCESS (CLK, RESET)

BEGIN

IF (RESET = '0') THEN

 HP<='0';

ELSIF (CLK'EVENT AND CLK='1') THEN

HP<=HN;

END IF;

END PROCESS SECUENCIAL;

end Behavioral;
////////////////////////////////////////////////////
# PlanAhead Generated physical constraints

NET "clk" LOC = B8;

NET "PWM1" LOC = A9;
NET "reset" LOC = P11;