Faster Multi-Scenario ECO

Fixing in PrimeTime

Troy Epperly
PrimeTime CAE

© Synopsys 2011 1
 Agenda

• Overview of PrimeTime ECO

• New „Cheetah‟ Technology

• Doing More with PrimeTime ECO

– Design Rule Fixing
– PBA and Multi-Scenario Usage
– ICC, UPF Flows and Useful Tips

• Summary

© Synopsys 2011 2
 Timing Based ECO Solutions

ECO feature in Customized ECO

implementation tools tool/scripts

ECO Guidance in
PrimeTime

Manual ECO netlist editing Layout editing

© Synopsys 2011 3
 PrimeTime ECO
Faster Timing Convergence

• Automated fixing flow

– Supports full chip STA, SI IC Compiler StarRC
Extraction
and SSTA flows

ECO Guidance change list

Netlist &
– Fixes across all scenarios Constraints

– Setup, Hold & DRC fixing PrimeTime

Coupled
STA/SI SBPF/SPEF
• Minimizes iterations with
No
IC Compiler physical Violations
? Signoff
implementation flow Yes

ECO

• Flexibility of cell-sizing
and/or buffer insertion PrimeTime ECO Flow With
IC Compiler

© Synopsys 2011 4
 PrimeTime ECO Enables Faster
Timing Convergence

Provides Considers
• Addresses designs Guidance to Fix Single &
Setup /Hold / Multiple
with many scenarios DRC Violations Scenario Runs

PrimeTime
• When blocks are ECO
integrated at chip
level Enabled in Supports UPF
PrimeTime, & Multi-
PrimeTime SI, Voltage aware
PrimeTime VX fixing

© Synopsys 2011 5
 ECO Fixing in PrimeTime 2010.12

Setup Timing Hold Timing

fix_eco_timing
DRC Fixing
fix_eco_timing
fix_eco_drc
–type setup –type hold

• Resizes the timing • Uses buffer insertion • Supports

bottleneck cells to address hold max_transition,
violations max_capacitance, &
• Utilizes all available • Honors setup slack max_fanout
library cells in & DRC
link_path • Flexibility of cell-
• Supports path- sizing and/or buffer
• User control of cell based analysis insertion
sizing & selection mode

• Limits area increase

with ECO sizing
variable

© Synopsys 2011 6
 Interface to IC Compiler
fix_eco_timing
• Produces ECO changes made in the
and/or session
fix_eco_drc • Optimized SNPS tcl output

current_instance
size_cell {U11} {slow/BUFX8}
size_cell {U15} {slow/BUFX8}
write_changes – insert_buffer [get_pins {FF12/Q}] \
format icctcl –out slow/BUFX1 -new_net_names {net1}\
pteco.tcl -new_cell_names {U1}

• ICC to run incremental placement & routing

open_mw_cel top
source pteco.tcl
...
IC Compiler
legalize_placement –incremental –eco
route_zrt_eco –modified_nets_first_then_others \
-utilize_dangling_wires true

© Synopsys 2011 7
 Reasons for Timing ECO‟s After P&R
Inputs to P&R and Signoff Tools Often Different

• Different tool settings

• Different timing constraints
• Additional scenarios
• Reduced signoff SI pessimism
• PBA, VX, advanced analysis with CCS
• Signoff extraction
• Flat full chip timing
Timing deltas between P&R and
signoff can be reduced, not eliminated

© Synopsys 2011 8
 fix_eco_timing Options:
Path Selection options for –type setup/hold

[-slack_lesser_than slack_limit float]

[-slack_greater_than slack_limit float]
[-group group]
[-from from_list]
[-to to_list]

• By default all setup/hold violating paths selected

• Common path selection options are supported to control
fixing scope
–group supports lists and wildcards
-slack_greater_than can be used to avoid spending time
on large failures caused by misconstrained paths

© Synopsys 2011 9
 fix_eco_timing –type hold
Additional Options for hold fixing
[-buffer_list list]
• Buffer list to be used for hold buffer insertion

[-pba_mode effort]
• Specifies Path-Based analysis mode for hold fixing

[-hold_margin float]

• Specifies how much additional hold fixing margin should be applied

[-setup_margin float]
• Specifies how much setup slack should be preserved during hold-fixing
• Positive values will preserve that amount of setup slack
• Negative values will sacrifice that amount of setup slack

© Synopsys 2011 10
 Agenda

• Overview of PrimeTime ECO

• New „Cheetah‟ Technology

• Doing More with PrimeTime ECO

– Design Rule Fixing
– PBA and Multi-Scenario Usage
– ICC, UPF Flows and Useful Tips

• Summary

© Synopsys 2011 11
Limitations of Current ECO Techniques
• Most commercial ECO techniques are based on the concept of
analyzing PATH COLLECTIONS regardless of number of
violations
• Challenges
– QoR : Do not see global picture. Optimized in local environment
– Long runtime – Potentially very long runtime

Circuit netlist Collecting paths Bottleneck analysis

© Synopsys 2011 12
Current Techniques Are Not Scalable

• Paths to analyze  Number of scenarios

M scenarios

Total paths = N paths X M scenarios  Multiplicative growth

© Synopsys 2011 13
 What is „Cheetah‟ ECO Technology?

• A Synopsys project to improve the Galaxy ECO

process

• Next generation ECO guidance technology:

– New ECO timing engine architecture to address
increasing # of scenarios
– New algorithms to provide fastest turnaround, high
capacity with excellent, predictable results
– Limited Customer Availability (LCA) capability in PT
2010.12 release

© Synopsys 2011 14
 3rd Gen ECO Guidance Technology
Internal code name: „Cheetah‟
Overnight ECO Cycle 5-10x Faster Guidance
8
Runtimes (in hr)

2 Light weight
infrastructure
0
A B C D E Master
PT+ICC runs
Customer Designs

Scenario Runtime Scalability Scenario Memory Scalability

300
Runtimes (in mins)

3
250 Previous Gen
10.06 Previous
10.06 Gen Master
Master

Memory in GB
Cheetah 2.5 Cheetah Master
200
2 Slave Peak
150 1.5
100 1
50 0.5
0 0
0 2 4 6 8 10 0 2 4 6 8 10
Number of scenarios Number of scenarios

Source: Synopsys, results on customer designs

© Synopsys 2011 15
New Technology Addresses ECO Challenges
„Cheetah‟ ECO Core Technology – Patent Pending

New concept for ECO fixing

• Composite graph view created from Global timing view of each scenario
• ECO algorithms reference the composite graph view

Scenario 1
Scenario 2
Scenario 3
Composite graph view
Scenario 4
of scenarios

With „Cheetah‟ no iterative bottleneck analysis is required

© Synopsys 2011 16
 Improved Calibrated Estimation
„Cheetah‟ ECO Core Technology – Patent Granted

• Improved technique to quickly analyze best ‘fit’ without

requiring complete timing analysis of all possible
solutions

New Size Options

© Synopsys 2011 17
 „Cheetah‟ ECO – Setup Fixing
Setup Runtime Improvements in 2010.12
Single Scenario Multi-Scenario
Elapsed Time (in Hrs) Elapsed Time (in Hrs)
20 14
48 30
18 Hrs Hrs 12
16
10
14
12 8
10 6
8
4
6
4 2
2 0
0 4 10 2 16
1.71 1.38 1.33 1.32 1.26 1 2 3 4
# Scenarios
Customer Designs
Customer Designs (in Milion Instances) Customer Designs

PrimeTime Setup ECO Fixing is 5-10X faster

© Synopsys 2011 18
„Cheetah‟ ECO – Multi-Scenario
Hold Fixing Runtime Improvements in 2010.12

Elapsed Time (in Mins) 2100

mins
200
180
2010.06 ECO
160
140 New Cheetah ECO
120
100
80
60
40
20
0
9 9 4 6
# of Scenarios

Multi-scenario Hold ECO Fixing is 2-5X faster

© Synopsys 2011 19
 „Cheetah‟ ECO – Setup Fixing
Setup Runtime Improvements in 2010.12
Full ECO Loop
Elapsed Time (in Hrs)

10
2010.06 ECO
8 New Cheetah ECO

0
A B C D E
Customer Designs
Full ECO flow „IC Compiler + StarRC + PrimeTime‟ is ~1.5X faster

© Synopsys 2011 20
 Full ECO Loop Case Study
35
• Customer Design with 16
Scenarios 30
5.2X
• New technology in „Cheetah‟

Runtime (Hours)
25
coupled with new releases of StarRC
ICC and StarRC delivered a
20
5.2X performance ICC
improvement for the full ECO
loop 15
PTSI+
ECO
• „Cheetah‟ also delivered a 10

much better guidance for

fixes 5

– 2010.12 „Cheetah‟
• 84% fix rate 0
StarRC: 2009.06-SP3-3 StarRC: 2010.12-SP1
– 2010.06-SP2 ICC: 2009.06-SP5 ICC: 2010.12-SP2
• 39% fix rate PT: 2010.06-SP2 PT: 2010.12

© Synopsys 2011 21
„Cheetah‟ ECO Guidance
Provides fixes for 1000‟s of violations
Setup Fixing Rate After Hold Fixing Rate After
Implementation in IC Compiler Implementation in IC Compiler
100% 100%
90% 90%
80% 80%
70% 70%
60% 60%
50% 50%
40% 70% 40% 95%
30% 30%
20%
fixing rate 20%
fixing rate
10% 10%
0% 0%
Customer Designs Customer Designs

Design A B C D E F G
# of setup
21,446 525 464 166 46,261 3,972 10,572
violations fixed
# of hold
1,370 5,249 4,280 1,786 853 1,190 14,266
violations fixed
Note: Results based on fixes implemented in IC Compiler, Source Synopsys, Inc
Stress-test designs created with low-effort IC Compiler optimization to establish a quick baseline

© Synopsys 2011 22
„Cheetah‟ ECO Guidance Predictability

100%

IC Compiler StarRC 80%

Extraction
60%
Netlist & 40%
Constraints
20%
ECO Guidance change list

PrimeTime
0%

Coupled
Setup fixing guidance success rate: ~90%
STA/SI SBPF/SPEF
100%
80%
Yes
Meeting
Timing Signoff 60%

No 40%

ECO 20%
0%
Customer Designs

Cheetah ECO Flow With IC Compiler Hold fixing guidance success rate: ~95%

Guidance success rate = % of violations fixed by Cheetah remained

fixed after eco implementation in IC Compiler
Source: Synopsys, results on customer designs

© Synopsys 2011 23
 „Cheetah‟ ECO Technology
Usage

• Enable „Cheetah‟ Technology:

set_eco_options -enable_project_cheetah

- „Cheetah‟ is available in 2010.12 release

- „Cheetah‟ is a Limited Customer Availability (LCA) feature
- Consult your local AC for access to this technology

© Synopsys 2011 24
 „Cheetah‟ ECO Technology
New Options

New options with „Cheetah‟ fix_eco_timing

-methods <insert_buffer size_cell>

• If fixing method includes insert_buffer, the list of library

cells using -buffer_list should be specified

-current_library

• Improves performance by eliminating unnecessary

searching if there are many libraries in the link path

© Synopsys 2011 25
 „Cheetah‟ ECO Technology
Additional support in Setup Fixing

Setup and hold margins are honored with „Cheetah‟

setup fixing as well
[-setup_margin float]

• Specifies how much additional setup fixing margin should be

applied during setup fixing

[-hold_margin float]

• Specifies how much hold slack should be preserved during setup fixing

© Synopsys 2011 26
 „Cheetah‟ ECO Technology
Other Improvements
• PBA for setup fixing
– „Cheetah‟ supports PBA for both setup and hold fixing
– Non-„Cheetah‟ only supports PBA with only the hold fixing

• Distributed Multicore supported for setup fixing

– „Cheetah‟ supports Distributed Multicore for setup and hold
– Non-„Cheetah‟ supports Distributed Multicore only for hold

• library dont_use attribute support

– No need to use user defined attribute pt_dont_use to
avoid use of those cells during ECO fixing

© Synopsys 2011 27
Summary : „Cheetah‟ ECO Technology
• New infrastructure and algorithms
• Utilizes global timing view for optimizations
• 5-10X performance improvement, scalable Multi-Scenario memory
• Limited Customer Availability (LCA) in PrimeTime SI 2010.12

2010.06 Technology: Multi-scenario ECO New Cheetah ECO Engine: Multi-scenario ECO based on ECO
based on path group of each scenario timing graph with visibility into other scenarios

Heavy Light
communication communication

Master Master

© Synopsys 2011 28
 LSI :
Results with „Cheetah‟
• Tested on 3 real tape-out designs

• Compared results* vs.

LSI solution using PT
2010.06

• Speedup ranged from

7X to 23X

• Comparable fix rates

* Setup Fixing

© Synopsys 2011 29
Cisco:
Multi-Scenario Results with „Cheetah‟
• 6 Scenario Setup and Hold fixing
• Higher fix rates with 2010.12 „Cheetah‟ and
significantly faster runtime with reduction in Master
Memory usage

Please attend San Jose SNUG 2011 User Paper Session (TB3) on
Tuesday, March 29 at 1PM:
“Accelerated Timing Closure using PrimeTime DMSA based
Auto-ECO flow”
Venkataraman Srinivasagam, Cisco Systems, Inc.

© Synopsys 2011 30
 Agenda

• Overview of PrimeTime ECO

• New „Cheetah‟ Technology

• Doing More with PrimeTime ECO

– Design Rule Fixing
– PBA and Multi-Scenario Usage
– ICC, UPF Flows and Useful Tips

• Summary

© Synopsys 2011 31
 ECO DRC Fixing
fix_eco_drc Options
-type <max_transition|max_capacitance|max_fanout>

• Specify any one of the fixing type to be addressed

-methods <insert_buffer size_cell>

• If fixing method includes insert_buffer, the list of library cells using -

buffer_list should be specified

-buffer_list list

• Specifies buffer cells to be used for insertion

-verbose

• Verbose output to display unfixable violations with the reasons

© Synopsys 2011 32
 ECO DRC max_transition
Fixing Results
DESIGNS
METRICS T1 T2 T3 T4 T5

Number of High
Pre-ECO 9795 10345 6971 7197 2205 fixing rates
Violations
Post-ECO 16 2091 24 958 65

Fixing Rate(%) 99.84 79.79 99.66 86.69 97.05

Runtime
(in min) fix_eco_drc 22 23 9 11 18

• fix_eco_drc fixes large amounts of violations very quickly

• Details on unfixable violations are provided for further examination

© Synopsys 2011 33
 ECO DRC Fixing
Unfixable reasons
• Unfixable violations with the reason code are displayed
for the violations that cannot be fixed
– Displayed only when fix_eco_drc is run in verbose mode
– Unfixable reasons will guide the user to take the next steps

pt_shell> fix_eco_drc -type max_transition -method size_cell -verbose

Unfixable violations:
A - There are available lib cells outside area limit
C - The violation is in clock network
I - Buffer insertion with given lib cells cannot fix the violation
P - Driver cell of the violation is a port
Q - Driver cell of the violation is a sequential cell
S - Cell sizing with alternative lib cells cannot fix the violation
T - Timing margin is too tight to fix the violation
V - Driver cell of the violation is dont_touched

Violation Reasons
---------------------------------------------------------------------
U1/I C
U6/I V

© Synopsys 2011 34
Addressing Remaining DRC Violations

• If any DRC violations are unfixed after fix_eco_drc

– Re-execute the ECO DRC fixing process to see if the fixing rate
can be improved

– Analyze the unfixable reasons reported by –verbose option of

fix_eco_drc (Details in man page)

– Re-execute the fixing process based on analysis. For example:

Add insert_buffer method if previously only size_cell
method was used

pt_shell> fix_eco_drc -type max_transition \

-methods {size_cell insert_buffer} -buffer_list {buf4 buf6 buf8}

© Synopsys 2011 35
 ECO Multicore Support
• PrimeTime supports two different Multicore approaches
– Distributed and Multithreading

• In the 2010.12 release both Multicore approaches are

supported for ECO fixing
• ECO flow can utilize same Multicore approach that is done
in Signoff

© Synopsys 2011 36
 PBA based ECO fixing
• fix_eco_timing supports PBA and fixes violations
based upon the PBA timing graph

pt_shell> fix_eco_timing -type <setup/hold> \

-pba_mode <path/exhaustive>

• PBA paths are collected internally based upon the options

supplied to fix_eco_timing
• PBA based ECO is geared to correct smaller numbers of
final violations which are still present in PBA timing

© Synopsys 2011 37
 Support for ECO Fixing
dont_touch
• Cells with dont_touch will not be resized

• Buffers will not be inserted on dont_touch nets

• Clock nets, cells and clock nets used as data are considered
dont_touch

• For DMSA fixing, dont_touch on a net or cell in any scenario

implies dont_touch in all scenarios

• dont_touch on any hierarchical cell is honored

– ECO will consider all nets and cells inside hierarchy as dont_touch
– Different true or false dont_touch applied deeper in the hierarchy takes
precedence over any higher-level dont_touch.

© Synopsys 2011 38
 Support for ECO Fixing
dont_use
• Library cells with dont_use attribute set to true will not be
used during fixing process

• Ignored if -buffer_list has cell with dont_use

• fix_eco_timing (Non-Cheetah) doesn‟t honor library

dont_use
– Use user attribute, pt_dont_use instead (Details in
fix_eco_timing man page)
– pt_dont_use is honored by Cheetah and DRC fixing as well

© Synopsys 2011 39
 Area Ratio Control During Sizing

• Area increase during sizing controlled by variable

eco_alternative_area_ratio_threshold
– “0” allows unlimited upsizing (default)

– “1.4” allows resizing up to 1.4X area of original cell

– “1” allows resizing up to area of original cell

• Same or less area reduces disturbance in layout
• But it may reduce fixing rate and/or increase runtime

© Synopsys 2011 40
 Restricting Sizing within a Group
of Cells
• Sizing within a group of cells is controlled by
eco_alternative_cell_attribute_restrictions
– Powerful feature to enable sizing based on attribute value
– When set, same attribute value cells are used for sizing

set eco_alternative_cell_attribute_restrictions { grp }

INV20x_t1 INVX20_t2 ..t1 ..t1

grp = BUFX4 grp = NAND3X8 ….

grp = INVX20
..t2 ..t3
..t2 ..t3
INVX20_t3

© Synopsys 2011 41
 Example of ECO Fixing with Sizing
within Same Group of Cells
set_eco_options -enable_project_cheetah
define_user_attribute -classes lib_cell -type string grp
set_user_attribute [get_lib_cell lib/INVX20_t1] grp INVX20
set_user_attribute [get_lib_cell lib/INVX20_t2] grp INVX20
set_user_attribute [get_lib_cell lib/INVX20_t3] grp INVX20
set_user_attribute [get_lib_cell lib/BUFX4_t1] grp BUFX4
...
...
set eco_alternative_cell_attribute_restrictions { grp }
fix_eco_timing -type setup

© Synopsys 2011 42
 ECO Fixing Tips for DMSA (1)

• Cheetah should be enabled in master process

set_eco_options -enable_project_cheetah

• Following variables and commands should be used in slaves

remote_execute {
set eco_alternative_area_ratio_threshold 2
define_user_attribute -classes lib_cell -type string grp
set eco_alternative_cell_attribute_restrictions { grp }
set_dont_touch [get_lib_cell */CLKBUF*] }

© Synopsys 2011 43
 ECO Fixing Tips for DMSA (2)

• write_changes should be used in slaves

remote_execute {write_changes –format icctcl –out pteco.tcl}

- Writes out change list file inside scenario directory

- Changes are common in all files, any file can be used
in IC Compiler

• -buffer_list should include only the base names of

the library buffers (Not lib_name/base_name)
– Otherwise it cannot be resolved in multiple Scenarios

© Synopsys 2011 44
Order of DRC, Setup, and Hold Fixing

• Dependent on design status and ECO fixing goals of specific design

• Recommended order of ECO fixing:

DRC Setup Fixing Hold Fixing

Fixing (preserves DRC) (preserves DRC and setup)

Notes:
• Hold can be fixed before setup if setup degradation is allowed (using large
negative -setup_margin)
• For large number of changes
- First fix the type of violation which causes more changes
- Implement the changes in IC Compiler before doing next PT ECO

© Synopsys 2011 45
 Hierarchical ICC and Full Chip ECO
• ICC sees only Top level logic and block interface
• PT will see entire flat netlist
TOP(ICC)
BLOCK1 Model BLOCK2 Model
ICC doesn‟t
X
U3

X
U1 U2
FF1 FF2 see entire
netlist

TOP(PT)

BLOCK1 BLOCK2
U1 U2 U3 PT sees full
FF1 FF2 flat design

© Synopsys 2011 46
 ECO with Full Chip Netlist
TOP
BLOCK1 BLOCK2
U1 U2 U3
FF1 FF2

U1, U2 and U3
Resized by PT ECO

TCL files to be sourced in ICC

TCL file(eco_flat.tcl) written by PT eco_top.tcl
size_cell U2 BUFX4 Source in ICC Top Level run
size_cell U2 BUFX4 …
current_instance BLOCK2
size_cell U3 BUFX5 Parse
eco_BLOCK2.tcl
… Source in ICC BLOCK2 run
size_cell U3 BUFX5
…

eco_BLOCK1.tcl
size_cell U1 BUFX5 Source in ICC BLOCK1 run
…

© Synopsys 2011 47
 Implementing ECO Changes in ICC
Blocks and TOP

open_mw_cel BLOCK2 ICC BLOCK2 run script

BLOCK2
source eco_BLOCK2.tcl
U3
..
FF2
legalize_placement –incremental –eco
route_zrt_eco …

open_mw_cel TOP ICC TOP level run script

source eco_top.tcl
..
legalize_placement –incremental –eco
route_zrt_eco …

© Synopsys 2011 48
Splitting ECO Change files for ICC
TCL procedure Available on Solvnet : Article 032431

Flat ECO file : eco_flat.tcl

size_cell U2 BUFX4
current_instance BLOCK2 split_eco_file –instance_names “Block1 Block2” \
…… –out_file_names “B1 B2” –in_file_name eco_flat.tcl

top_out.tcl B1.tcl B2.tcl

size_cell U2 BUFX4 size_cell U1 BUFX4 size_cell U3 BUFX4
…… …… ……

ICC
Implementation BLOCK1 BLOCK2
Level

Solvnet Article
https://solvnet.synopsys.com/retrieve/032421.html
© Synopsys 2011 49
 UPF and Multi-Voltage Support
for ECO(1)
• PrimeTime ECO supports UPF and Multi-
Voltage designs
• Setup, Hold and DRC fixing
• Scalar, Multicore and DMSA flows

• Supports Multi-Voltage flow with :

• Library scaling group
• Link Path Per Instance (LPPI)
• Operating Condition (OPC), and
• UPF

© Synopsys 2011 50
 UPF and Multi-Voltage Support
for ECO(2)
• Understands UPF and its attributes
– Special cells with following attributes will not be changed
• always_on, is_retention, is_level_shifter,
is_isolation
– Any sizing will match PG pin count and vnom (nominal
voltage)
– Any buffer insertion will match voltage region of the
block/hierarchy
• Automatically handles UPF PG pin connections
– Sizing is done with cell of compatible PG pin
– Buffer insertion inherits PG pin connection from its
connected driver or load cell

© Synopsys 2011 51
Hold Fixing Example in Multi-Voltage Design
Library Scaling Group
set_link_path “* ccs_lib_0.8v.db”
read_verilog design.v
current_design top
define_scaling_lib_group {ccs_lib_0.8v.db ccs_lib_1.0v.db}
set_voltage 0.8 –obj {VDDA}
set_voltage 1.0 –obj {VDDB}

<top>
VDDA VDDB
BLKA BLKB
PDA 0.8 V PDB 1.0 V
Uses timing from Uses timing from
0.8v library 1.0v library

fix_eco_timing –buffer_list {BUF1 BUF2 BUF3} –type hold

• Buffer names are common in both libraries

• Flow works automatically
• Inserted buffers will use correct voltage scaling based on power domain

© Synopsys 2011 52
 Implementing ECO Changes in ICC
UPF and Multi-Voltage Designs
• In IC Compiler, use following command before
doing the ECO route
– derive_pg_connection –reconnect
– This will reconnect the power/ground pins in ICC

open_mw_cel Design1
check_mv_design
Violation checking source eco_pt.tcl
Violation
can be performed
checking can be ..
performed with
with legalize_placement …
check_mv_design derive_pg_connection –reconnect
route_zrt_eco …
check_mv_design

© Synopsys 2011 53
 PrimeTime Multi-Scenario ECO
Review of what we Covered Today

• Provided details on
PrimeTime Multi- Agenda
Scenario ECO and • Overview of PrimeTime ECO
the new technologies
• New „Cheetah‟ Technology
delivered in the
2010.12 release • Doing More with PrimeTime ECO
– Design Rule Fixing
– PBA and Multi-Scenario Usage
– ICC, UPF Flows and Useful Tips

• Covered PrimeTime • Summary

ECO Tips and Flow
support © Synopsys 2011 2

© Synopsys 2011 54
 Summary
• „Cheetah‟ new underlying engine for
setup/hold analysis released in 2010.12
(Faster, less memory, better QOR)

• Fast turnaround time improves PrimeTime

and IC Compiler productivity

• PrimeTime ECO Guidance also supports

DRC fixing and Multi-Voltage and UPF
designs

© Synopsys 2011 55
 Appendix

© Synopsys 2011 56
 Hold Fixing Example in MV Design
link_path_per_instance
set link_path_per_instance \
{{BLKA {* libA.db}} {BLKB {* libB.db}}}

<top>
BLKA BLKB

fix_eco_timing –buffer_list {BUFA1 BUFA2 BUFB1 BUFB2} –type hold

• -buffer_list for hold fixing can have different library buffers

corresponding to different blocks
• Hold fixing will automatically use correct buffers for the blocks
• DRC fixing will insert buffers in same way

© Synopsys 2011 57