Chapter 2: The Microprocessor and Its Architecture Chapter 2: The Microprocessor and Its Architecture

6/17/2011
Chapter 2: The Microprocessor and its Architecture Chapter 2: The Microprocessor and its Architecture
Introduction
• This chapter presents the microprocessor as a
programmable device by first looking at its
internal programming model and then how
its memory space is addressed.
• The architecture of Intel microprocessors is
presented, as are the ways that the family
members address the memory system.
• Addressing modes for this powerful family of
microprocessors are described for the real,
protected, and flat modes of operation.
Chapter 2: The Microprocessor and its Architecture The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,
Pentium Pro Processor, Pentium II, Pentium, 4, and Core2 with 64-bit Extensions Copyright ©2009 by Pearson Education, Inc.
Architecture, Programming, and Interfacing, Eighth Edition 4 Upper Saddle River, New Jersey 07458 • All rights reserved.
Barry B. Brey
Chapter Objectives Chapter Objectives (cont.)

Upon completion of this chapter, you will be able to: Upon completion of this chapter, you will be able to:
• Describe function and purpose of each • Describe how memory is accessed using
program-visible register in the 8086-Core2 protected mode memory-addressing
microprocessors, including 64-bit extensions. techniques.
• Detail the flag register and the purpose of • Describe how memory is accessed using the
each flag bit. 64-bit flat memory model.
• Describe how memory is accessed using real • Describe program-invisible registers found in
mode memory-addressing techniques. the 80286 through Core2 microprocessors.
• Detail the operation of the memory-paging
mechanism.
The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium, The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,
Pentium Pro Processor, Pentium II, Pentium, 4, and Core2 with 64 -bit Extensions Copyright ©2009 by Pearson Education, Inc. Pentium Pro Processor, Pentium II, Pentium, 4, and Core2 with 64-bit Extensions Copyright ©2009 by Pearson Education, Inc.
Architecture, Programming, and Interfacing, Eighth Edition 5 Upper Saddle River, New Jersey 07458 • All rights reserved. Architecture, Programming, and Interfacing, Eighth Edition 6 Upper Saddle River, New Jersey 07458 • All rights reserved.
Barry B. Brey Barry B. Brey
1
6/17/2011
2–1 INTERNAL MICROPROCESSOR The Programming Model

ARCHITECTURE • 8086 through Core2 considered program
• Before a program is written or instruction visible.
investigated, internal configuration of the – registers are used during programming and are
specified by the instructions
microprocessor must be known.
• Other registers considered to be program
• In a multiple core microprocessor, each core
invisible.
contains the same programming model.
– not addressable directly during applications
• Each core runs a separate task or thread programming
simultaneously.
Figure 2–1 The programming model of the 8086 through the Core2 microprocessor
• 80286 and above contain program-invisible including the 64-bit extensions.
registers to control and operate protected

memory.
– and other features of the microprocessor
• 80386 through Core2 microprocessors
contain full 32-bit internal architectures.
• 8086 through the 80286 are fully upward-
compatible to the 80386 through Core2.
• Figure 2–1 illustrates the programming model
8086 through Core2 microprocessor.
– including the 64-bit extensions
Multipurpose Registers • RBX, addressable as RBX, EBX, BX, BH, BL.

• RAX - a 64-bit register (RAX), a 32-bit register – BX register (base index) sometimes holds offset
address of a location in the memory system in all
(accumulator) (EAX), a 16-bit register (AX),
versions of the microprocessor
or as either of two 8-bit registers (AH and AL).
• RCX, as RCX, ECX, CX, CH, or CL.
• The accumulator is used for instructions such – a (count) general-purpose register that also holds
the count for various instructions
as multiplication, division, and some of the
adjustment instructions. • RDX, as RDX, EDX, DX, DH, or DL.
– a (data) general-purpose register
• Intel plans to expand the address bus to 52 – holds a part of the result from a multiplication
bits to address 4P (peta) bytes of memory. or part of dividend before a division
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• RBP, as RBP, EBP, or BP. • R8 - R15 found in the Pentium 4 and Core2 if
– points to a memory (base pointer) location 64-bit extensions are enabled.
for memory data transfers – data are addressed as 64-, 32-, 16-, or 8-bit
• RDI addressable as RDI, EDI, or DI. sizes and are of general purpose
– often addresses (destination index) string • Most applications will not use these registers
destination data for the string instructions until 64-bit processors are common.
• RSI used as RSI, ESI, or SI. – the 8-bit portion is the rightmost 8-bit only
– the (source index) register addresses source – bits 8 to 15 are not directly addressable as
string data for the string instructions a byte
– like RDI, RSI also functions as a general-
purpose register
Special-Purpose Registers • RFLAGS indicate the condition of the

• Include RIP, RSP, and RFLAGS microprocessor and control its operation.
– segment registers include CS, DS, ES, SS, FS, • Figure 2–2 shows the flag registers of all
and GS versions of the microprocessor.
• RIP addresses the next instruction in a section • Flags are upward-compatible from the
of memory. 8086/8088 through Core2 .
– defined as (instruction pointer) a code segment • The rightmost five and the overflow flag are
• RSP addresses an area of memory called changed by most arithmetic and logic
the stack. operations.
– the (stack pointer) stores data through this – although data transfers do not affect them
pointer
Figure 2–2 The EFLAG and FLAG register counts for the entire 8086 and Pentium
microprocessor family. • Flag bits, with a brief description of function.
• C (carry) holds the carry after addition or
borrow after subtraction.
– also indicates error conditions
• P (parity) is the count of ones in a number
expressed as even or odd. Logic 0 for odd
parity; logic 1 for even parity.
• Flags never change for any data transfer or
– if a number contains three binary one bits, it has
program control operation. odd parity
• Some of the flags are also used to control – if a number contains no one bits, it has even
features found in the microprocessor. parity
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List of Each Flag bit, with a brief • A (auxiliary carry) holds the carry (half-carry)
description of function. after addition or the borrow after subtraction
between bit positions 3 and 4 of the result.
• C (carry) holds the carry after addition or • Z (zero) shows that the result of an arithmetic
borrow after subtraction. or logic operation is zero.
– also indicates error conditions • S (sign) flag holds the arithmetic sign of the
• P (parity) is the count of ones in a number result after an arithmetic or logic instruction
expressed as even or odd. Logic 0 for odd executes.
parity; logic 1 for even parity. • T (trap) The trap flag enables trapping
– if a number contains three binary one bits, it has through an on-chip debugging feature.
odd parity; If a number contains no one bits, it
has even parity
• I (interrupt) controls operation of the INTR • IOPL used in protected mode operation
(interrupt request) input pin. to select the privilege level for I/O devices.
• D (direction) selects increment or decrement • NT (nested task) flag indicates the current
mode for the DI and/or SI registers. task is nested within another task in protected
• O (overflow) occurs when signed numbers mode operation.
are added or subtracted. • RF (resume) used with debugging to control
– an overflow indicates the result has exceeded resumption of execution after the next
the capacity of the machine instruction.
• VM (virtual mode) flag bit selects virtual
mode operation in a protected mode system.
• AC, (alignment check) flag bit activates if a • ID (identification) flag indicates that the
word or doubleword is addressed on a non- Pentium microprocessors support the CPUID
word or non-doubleword boundary. instruction.
• VIF is a copy of the interrupt flag bit available – CPUID instruction provides the system with
to the Pentium 4–(virtual interrupt) information about the Pentium microprocessor
• VIP (virtual) provides information about a
virtual mode interrupt for (interrupt pending)
Pentium.
– used in multitasking environments to provide
virtual interrupt flags
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Segment Registers • CS (code) segment holds code (programs

• Generate memory addresses when combined and procedures) used by the microprocessor.
with other registers in the microprocessor. • DS (data) contains most data used by a
• Four or six segment registers in various program.
versions of the microprocessor. – Data are accessed by an offset address or
contents of other registers that hold the offset
• A segment register functions differently in real address
mode than in protected mode. • ES (extra) an additional data segment used
• Following is a list of each segment register, by some instructions to hold destination data.
along with its function in the system.
• SS (stack) defines the area of memory used • FS and GS segments are supplemental
for the stack. segment registers available in 80386–Core2
– stack entry point is determined by the stack microprocessors.
segment and stack pointer registers – allow two additional memory segments for
– the BP register also addresses data within access by programs
the stack segment • Windows uses these segments for internal
operations, but no definition of their usage
is available.
2–2 REAL MODE MEMORY Segments and Offsets

ADDRESSING • All real mode memory addresses must consist
• 80286 and above operate in either the real or of a segment address plus an offset address.
protected mode. – segment address defines the beginning address
of any 64K-byte memory segment
• Real mode operation allows addressing of – offset address selects any location within the
only the first 1M byte of memory space—even 64K byte memory segment
in Pentium 4 or Core2 microprocessor.
• Figure 2–3 shows how the segment plus
– the first 1M byte of memory is called the real
offset addressing scheme selects a memory
memory, conventional memory, or DOS
memory system
location.
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Figure 2–3 The real mode memory-addressing scheme, using a segment address
plus an offset. • Once the beginning address is known, the
ending address is found by adding FFFFH.
– this shows a memory – because a real mode segment of memory is64K
segment beginning at in length
10000H, ending at
location 1FFFFH • The offset address is always added to the
• 64K bytes in length segment starting address to locate the data.
• Segment and offset address is sometimes
– also shows how an written as 1000:2000.
offset address, called a
– a segment address of 1000H; an offset of 2000H
displacement, of
F000H selects location
1F000H in the memory
Default Segment and Offset • Another of the default combinations is the

Registers stack.
– stack data are referenced through the stack
• The microprocessor has rules that apply to segment at the memory location addressed by
segments whenever memory is addressed. either the stack pointer (SP/ESP) or the pointer
– these define the segment and offset register (BP/EBP)
combination • Figure 2–4 shows a system that contains four
• The code segment register defines the start memory segments.
of the code segment. – a memory segment can touch or overlap if 64K
• The instruction pointer locates the next bytes of memory are not required for a segment
instruction within the code segment.
Figure 2–4 A memory system showing the placement of four memory segments. Figure 2–5 An application program containing a code, data, and stack segment
loaded into a DOS system memory.
– think of segments as – a program placed in

windows that can be memory by DOS is loaded
moved over any area in the TPA at the first
of memory to access available area of memory
data or code above drivers and other TPA
– a program can have programs
more than four or six – area is indicated by a free-
segments, pointer maintained by DOS
• but only access four or – program loading is handled
six segments at a time automatically by the
program loader within DOS
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Segment and Offset Addressing • Because memory is addressed within a

Scheme Allows Relocation segment by an offset address, the memory
segment can be moved to any place in the
• Segment plus offset addressing allows DOS memory system without changing any of the
programs to be relocated in memory. offset addresses.
• A relocatable program is one that can be • Only the contents of the segment register
placed into any area of memory and executed must be changed to address the program
without change. in the new area of memory.
• Relocatable data are data that can be placed • Windows programs are written assuming that
in any area of memory and used without any the first 2G of memory are available for code
change to the program. and data.
2–3 INTRO TO PROTECTED MODE Selectors and Descriptors

MEMORY ADDRESSING • The descriptor is located in the segment
• Allows access to data and programs located register & describes the location, length, and
within & above the first 1M byte of memory. access rights of the segment of memory.
– it selects one of 8192 descriptors from one
• Protected mode is where Windows operates. of two tables of descriptors
• In place of a segment address, the segment • In protected mode, this segment number can
register contains a selector that selects a address any memory location in the system
descriptor from a descriptor table. for the code segment.
• The descriptor describes the memory • Indirectly, the register still selects a memory
segment’s location, length, and access rights. segment, but not directly as in real mode.
Figure 2–6 The 80286 through Core2 64-bit descriptors.

• Global descriptors contain segment
definitions that apply to all programs.
• Local descriptors are usually unique to an
application.
– a global descriptor might be called a system
descriptor, and local descriptor an application
descriptor
• Figure 2–6 shows the format of a descriptor
for the 80286 through the Core2.
– each descriptor is 8 bytes in length
– global and local descriptor tables are a
maximum of 64K bytes in length
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• The base address of the descriptor indicates • Operating systems operate in a 16- or 32-bit
the starting location of the memory segment. environment.
– the paragraph boundary limitation is removed in • DOS uses a 16-bit environment.
protected mode
• Most Windows applications use a 32-bit
– segments may begin at any address
environment called WIN32.
• The G, or granularity bit allows a segment
• MSDOS/PCDOS & Windows 3.1 operating
length of 4K to 4G bytes in steps of 4K bytes.
systems require 16-bit instruction mode.
– 32-bit offset address allows segment lengths of
4G bytes • Instruction mode is accessible only in a
– 16-bit offset address allows segment lengths of
protected mode system such as Windows
64K bytes. Vista.
Figure 2–7 The access rights byte for the 80286 through Core2 descriptor.
• The access rights byte controls access to
the protected mode segment.
– describes segment function in the system and
allows complete control over the segment
– if the segment is a data segment, the direction of
growth is specified
• If the segment grows beyond its limit, the
operating system is interrupted, indicating
a general protection fault.
• You can specify whether a data segment
can be written or is write-protected.
Figure 2–8 The contents of a segment register during protected mode operation of
• Descriptors are chosen from the descriptor the 80286 through Core2 microprocessors.
table by the segment register.

– register contains a 13-bit selector field, a table
selector bit, and requested privilege level field
• The TI bit selects either the global or the local
descriptor table.
• Requested Privilege Level (RPL) requests
the access privilege level of a memory
segment.
– If privilege levels are violated, system normally
indicates an application or privilege level violation
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Figure 2–9 Using the DS register to select a description from the global descriptor
• Figure 2–9 shows how the segment register, table. In this example, the DS register accesses memory locations 00100000H–
001000FFH as a data segment.
containing a selector, chooses a descriptor
from the global descriptor table.
• The entry in the global descriptor table selects
a segment in the memory system.
• Descriptor zero is called the null descriptor,
must contain all zeros, and may not be used
for accessing memory.
Figure 2–10 The program-invisible register within the 80286–Core2 microprocessors.

Program-Invisible Registers
• Global and local descriptor tables are found
in the memory system.
• To access & specify the table addresses,
80286–Core2 contain program-invisible
registers.
– not directly addressed by software
• Each segment register contains a program-
invisible portion used in the protected mode.
– often called cache memory because cache is
any memory that stores information
• When a new segment number is placed in a • The GDTR (global descriptor table register)
segment register, the microprocessor and IDTR (interrupt descriptor table
accesses a descriptor table and loads the register) contain the base address of the
descriptor into the program-invisible portion of descriptor table and its limit.
the segment register. – when protected mode operation desired, address
– held there and used to access the memory of the global descriptor table and its limit are
segment until the segment number is changed loaded into the GDTR
• This allows the microprocessor to repeatedly • The location of the local descriptor table is
access a memory segment without referring selected from the global descriptor table.
to the descriptor table. – one of the global descriptors is set up to
– hence the term cache address the local descriptor table
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• To access the local descriptor table, the 2–4 MEMORY PAGING

LDTR (local descriptor table register) is
loaded with a selector. • The memory paging mechanism allows any
– selector accesses global descriptor table, & loads physical memory location to be assigned to
local descriptor table address, limit, & access any linear address.
rights into the cache portion of the LDTR • Iinear address is defined as the address
• The TR (task register) holds a selector, which generated by a program.
accesses a descriptor that defines a task. • Physical address is the actual memory
– a task is most often a procedure or application location accessed by a program.
• Allows multitasking systems to switch tasks • With memory paging, the linear address is
to another in a simple and orderly fashion. invisibly translated to any physical address.
Figure 2–11 The control register structure of the microprocessor.

Paging Registers
• The paging unit is controlled by the contents

of the microprocessor’s control registers.
• Beginning with Pentium, an additional control
register labeled CR4 controls extensions to
the basic architecture.
• See Figure 2–11 for the contents of control
registers CR0 through CR4.
Figure 2–12 The format for the linear address (a) and a page directory or page table
entry (b).
• The linear address, as generated by software, is

broken into three sections that are used to access
the page directory entry, page table entry, and
memory page offset address.
• Figure 2–12 shows the linear address and its
makeup for paging.
• When the program accesses a location between
00000000H and 00000FFFH, the microprocessor
physically addresses location 00100000H–
00100FFFH.
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• Intel has incorporated a special type of cache called The Page Directory and Page Table
TLB (translation look-aside buffer).
– because repaging a 4K-byte section of memory requires • Only one page directory in the system.
access to the page directory and a page table, both • The page directory contains 1024 doubleword
located in memory
addresses that locate up to 1024 page tables.
• The 80486 cache holds the 32 most recent page
translation addresses. • Page directory and each page table are 4K
– if the same area of memory is accessed, the address is bytes in length.
already present in the TLB • Figure 2–13 shows the page directory, a few
– This speeds program execution
page tables, and some memory pages.
• Pentium contains separate TLBs for each
of their instruction and data caches.
Figure 2–13 The paging mechanism in the 80386 through Core2 microprocessors.
• DOS and EMM386.EXE use page tables to
redefine memory between locations C8000H–
EFFFFH as upper memory blocks.
– done by repaging extended memory to backfill
conventional memory system to allow DOS access to
additional memory
• Each entry in the page directory corresponds to
4M bytes of physical memory.
• Each entry in the page table repages 4K bytes of
physical memory.
• Windows also repages the memory system.
Figure 2–14 The page directory, page table 0, and two memory pages. Note how the
address of page 000C8000–000C9000 has been moved to 00110000–00110FFF. 2–5 Flat Mode Memory
• A flat mode memory system is one in which
there is no segmentation.
– does not use a segment register to address a
location in the memory
• First byte address is at 00 0000 0000H; the
last location is at FF FFFF FFFFH.
– address is 40-bits
• The segment register still selects the privilege
level of the software.
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Figure 2–15 The 64-bit flat mode memory model.

• Real mode system is not available if the
processor operates in the 64-bit mode.
• Protection and paging are allowed in the 64-
bit mode.
• The CS register is still used in the protected
mode operation in the 64-bit mode.
• Most programs today are operated in the IA32
compatible mode.
– current software operates properly, but this will
change in a few years as memory becomes
larger and most people have 64-bit computers
SUMMARY SUMMARY (cont.)

• The programming model of the 8086 • 8-bit registers are AH, AL, BH, BL, CH, CL,
through 80286 contains 8- and 16-bit DH, and DL.
registers. • 16-bit registers are AX, BX, CX, DX, SP,
• The programming model of the 80386 and BP, DI, and SI.
above contains 8-, 16-, and 32-bit extended • The segment registers are CS, DS, ES, SS,
registers as well as two additional 16-bit FS, and GS.
segment registers: FS and GS. • 32-bit extended registers are EAX, EBX,
ECX, EDX, ESP, EBP, EDI, and ESI.
SUMMARY (cont.) SUMMARY (cont.)

• The 64-bit registers in a Pentium 4 with 64- • The starting location of a segment is
bit extensions are RAX, RBX, RCX, RDX, defined by the 16-bit number in the
RSP, RBP, RDI, RSI, and R8 through R15. segment register that is appended with a
• In addition, the microprocessor contains an hexadecimal zero at its rightmost end.
instruction pointer (IP/EIP/RIP) and flag • The offset address is a 16-bit number
register (FLAGS, EFLAGS, or RFLAGS). added to the 20-bit seg-ment address to
• All real mode memory addresses are a form the real mode memory address.
combination of a segment address plus an • All instructions (code) are accessed by the
offset address. combination of CS (segment ad-dress) plus
IP or EIP (offset address).
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• Data are normally referenced through a • Protected mode operation allows memory
combination of the DS (data segment) and above the first 1M byte to be accessed by
either an offset address or the contents of a the 80286 through the Core2
register that contains the offset address. microprocessors.
• The 8086-Core2 use BX, DI, and SI as • This extended memory system (XMS) is
default offset registers for data if 16-bit accessed via a segment address plus an
registers are selected. offset address, just as in the real mode.
• The 80386 and above can use the 32-bit • In the protected mode, the segment starting
registers EAX, EBX, ECX, EDX, EDI, and address is stored in a descriptor that is
ESI as default offset registers for data. selected by the segment register.

• A protected mode descriptor contains a • The 80286 microprocessor allows a
base address, limit, and access rights byte. memory segment to start at any of its 16M
• The base address locates the starting bytes of memory using a 24-bit base
address of the memory segment; the limit address.
defines the last location of the segment. • The 80386 and above allow a memory
• The access rights byte defines how the segment to begin at any of its 4G bytes of
memory segment is accessed via a memory using a 32-bit base address.
program. • This allows an 80286 memory segment limit
of 64K bytes, and an 80386 and above
mem-ory segment limit of either 1M bytes.

• The segment register contains three fields • Each segment register contains a cache
of information in the protected mode. portion that is used in protected mode to
• The leftmost 13 bits of the segment register hold the base address, limit, and access
address one of 8192 descriptors from a rights acquired from a descriptor.
descriptor table. • The cache allows the microprocessor to
• The program-invisible registers are used by access the memory segment without again
the 80286 and above to access the referring to the descriptor table until the
descriptor tables. segment register's contents are changed.
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• A memory page is 4K bytes in length. The • The page directory contains up to 1024
linear address, as generated by a program, page table addresses that are used to
can be mapped to any physical address access paging tables.
through the paging mechanism found within • The page table contains 1024 entries that
the 80386 through the Pentium 4. locate the physical address of a 4K-byte
• Memory paging is accomplished through memory page.
control registers CR0 and CR3. • The TLB (translation look-aside buffer)
• The PG bit of CR0 enables paging, and the caches the 32 most recent page table
contents of CR3 addresses the page translations.
directory.
SUMMARY
• The flat mode memory contains 1T byte of
memory using a 40-bit address.
• In the future, Intel plans to increase the
address width to 52 bits to access 4P bytes
of memory.
• The flat mode is only available in the
Pentium 4 and Core2 that have their 64-bit
extensions enabled.
The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,

Pentium Pro Processor, Pentium II, Pentium, 4, and Core2 with 64 -bit Extensions Copyright ©2009 by Pearson Education, Inc.
Architecture, Programming, and Interfacing, Eighth Edition 81 Upper Saddle River, New Jersey 07458 • All rights reserved.
Barry B. Brey
14

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6/17/2011

Chapter Objectives Chapter Objectives (cont.)

2–1 INTERNAL MICROPROCESSOR The Programming Model

registers to control and operate protected

Multipurpose Registers • RBX, addressable as RBX, EBX, BX, BH, BL.

Special-Purpose Registers • RFLAGS indicate the condition of the

Segment Registers • CS (code) segment holds code (programs

2–2 REAL MODE MEMORY Segments and Offsets

Default Segment and Offset • Another of the default combinations is the

– think of segments as – a program placed in

Segment and Offset Addressing • Because memory is addressed within a

2–3 INTRO TO PROTECTED MODE Selectors and Descriptors

Figure 2–6 The 80286 through Core2 64-bit descriptors.

table by the segment register.

Figure 2–10 The program-invisible register within the 80286–Core2 microprocessors.

• To access the local descriptor table, the 2–4 MEMORY PAGING

Figure 2–11 The control register structure of the microprocessor.

• The paging unit is controlled by the contents

• The linear address, as generated by software, is

Figure 2–15 The 64-bit flat mode memory model.

SUMMARY SUMMARY (cont.)

SUMMARY (cont.) SUMMARY (cont.)

SUMMARY (cont.) SUMMARY (cont.)

SUMMARY (cont.) SUMMARY (cont.)

SUMMARY (cont.) SUMMARY (cont.)

SUMMARY (cont.) SUMMARY (cont.)

The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,

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