Cid PDF

UNIVERSITATEA DIN CRAIOVA
)$&8/7$7($'($8720$7,& CALCULATOARE SI
ELECTRONICA
VINTIL FILIPESCU DAN GARAI MAN
CIRCUITE ELECTRONICE
DIGITALE
Îndrumar de laborator
5(352*5$),$81,9(56,7 ,,',1&5$,29$
1997
35()$
Îndrumarul de laborator "Circuitle elertronice digitale” VH DGUHVHD]
VWXGHQ LORUGLQDQLL ,,,DLIDFXOW LORUGH(OHFWURWHKQLFDúL(OHFWURPHFDQLF GDU poate

IL XWLO úL VWXGHQ LORU D F URU LQVWUXLUH VH GHVIDúRDU vQ FDGUXO VHF LLORU GH $XWRPDWLF
Calculatoare si (OHFWURQLF DOH)DFXOW LLGe A.C.E.

&HOH OXFU ri prezen WDWH vQFHDUF V DFRSHUH WHPDW ica cursului, fiind astfel
ordonate încât DERUGDUHD SUDFWLF D ILHF UHi OXFUDUL VH ED]HD] pe suportul teoretic
deja predat. Pentru studen Li care din diverse motive nu au audiat cursul, in Cadrul
ILHF UHL OXFUXUL D IRVW SU evazut un capitol de " Aspecte teoretice" care le permite
vQ HOHJHUHDSUREOHPDWLFLLSURSXVHúLGHVI úXUDUHDFX succes a lucrarii.
([SHULHQ D DFXPXODWD vQ W imp în cadrul disciplinei de "Circuite electronice
digitale", D I FXW SRVLELO Fererea unei platforme mulWLIXQF LRQDOH didactice, care
SHUPLWHVWXGLHUHD FRPRG D tuturor circuitelor propuse, cu un PLQLPGH DSDUDWXU
DGL LRQDO . /D SURLHFWDUHD úL UHDOL]DUea practica acesteia, o FRQWULEX LH LPSRWDQW D
avut-o studentul Mugurel Popescu de la facultatea de (OHFWURWHKQLF F UXLDL se cuvin

cele mai frumoase aprecieri
$GUHV P F OGXURDVH PXO XPLUL F olegilor úO . ing Sorin Nicola ú i conf dr ing.
Mircea Mihaiu pentru sugestiile utile úLUDEGDUHD cu care au recenzat manuscrisul.

0XO XPLGHDVHPHQHDvQWUHJXOXLFROHFWLY al Catedrei de ElectroniF úL
0 VXU ULúLvQVSHFLDO Doamnei prof. dr. ing. Elena Nicules FXúHID catedrei,
pentru FOLPDWXOGHHIHUYHVFHQ DSXEOLFLVWLF SHcare 1-au FUHDWúLFDre a constituit un

VWLPXOHQWSHQWUXILQDOL]DUHDDFHVWHLOXFU UL
AUTORII
4
CUPRINS
l . Prezentarea platformei de laborator..................................................................... .......................6

$QDOL]DúLVLQWH]DFLUFXLWHORUORJLFHFRPELQD LRQDOH ...................... ............. .....16
3.Detectorul de imparitate -paritate ........................................................................21
4.Circute de multiplexare ................................................................................................................27
5.Circuite de demultilplexare .......................................................................31
6.Comparatoare numerice................. ................................................................35
7. Sumatore......................................................................................................................................41
8. Convertoare de cod ....................................................................................... ......47
9. Circu ite de codificare ...............................................................................................................51
10. Circuite de decodificare ..............................................................................................................57
11. Poarta TTL standard. Analiza VWDWLF .............................................................64
12.CircuiteTTL cu colectorul în gol.............................................................. ....76
13.3R U L7 7 /F X stari... .........................................................................82
14. Poarta CMOS. Analiza statica ................................................................................................88
15.Regimul dinamic al SRU LOR U77/úL CMOS .............................................93
16. Circuie basculante bistabile...........................................................................................................100
17. Regisire ......................................................................................................................................118
$QH[
..............................................................................125
Bibliografie... ..........................................................................................................132
5
LUCRAREA NR.1
PREZENTAREA PLATFORMEI DE LABORATOR
O6FRSXOOXFU ULL
/XFUDUHDvúLSURSXQHSUH]HQWDUHDúLWHVWDUHD platformei de
laborator de circuite electronice digitale, materialul didactic de ba]
utilizat în dHVI úXUDUHDtXWXURUOXFU ULORUGHODERUDWRr cupinse în acest
îndrumar.
2. Aspecte teoretice
2.1 Descriere
Platfora de laboraor (PL), fig lOHVWHIRUPDW diQXUP WRDUHOH
blocuri fXQF LRQDOH:
2.1.1. Blocul de alimentare(BA), FRQ LQkQG ERUQHOH D WUHL surse
de WHQVLXQH VWDELOL]DWH úL DXWRSURWHMDWH (5VxlAt 15VxlA, 15VxlA)
fLHFDUH VXUV putând fi reglDW GH SH SODWIRUPD SULQ conectarea
convenabila a celor trei potentiometre (Pi GH /20. Sursele de
tensiuHVWDELOL]DW propriu-zise sunt montate în tabloul electric situat
între mesele de laborator.
2.1 .2. BORFXO FRQHFWRULORU %& IRUPDW GLQ GRL FRQHFWRUL PDP ,
$úL%cu câte 52 contacte fiecare, accesibile datorit a câteúLUXULde 8
pini dubli.
2.1.3. Blocul soclurilor de circuite integrate(BSCI): format din 8
socluri de CI FX FkWH FRQWDFWH ILHFDUH DFFHVLELOH GDWRULW D Fkte
GRX Viruri de 8 pini dubli.
2.1.4 Blocul de semnalizare a nivelurilor logice (BS). FRQ LQkQG

4x8 LED-uri incluse fiecare într-o VFKHP de tipul celei prezentate în
fig l.2. Cele 32 inversoare (6xCI - CDB 404, DQH[ ILJ $.2) si
UH]LVWHQ HOHDIHUHQWHVHDIO pe un cablaj imprimat situat sub zona BS
a platformei de laborator. IntU ULOH úL alimeQW ULOH BS sunt accesibile
GDWRULW DúLUXULGHFkWH 8+2 pini.
2.1.5. Blocul tastelor de FRPDQG %7Iormat din 6

taste accesibile fiecare prin intermediul a câte 2 pini.
6
)LJ8QDGLQFHOHVHF LXQLFRQVWLWXWLYHDOHOXL%6
3ODFKHWDPXOWLIXQF LRQDO 30ILJVHLQWURGXFHvQFRQH ctorXO%úL

FRQ LQHXUP WRDUHOHVXEE locuri:
a) Generatorul de tact automat (GTA), fig. 1.4 (CDB 413 -DQH[ ILJ$
b) Formatoarele de tact manual (FTM1 ,FTM2), fig. 1.5 (CDB 4121 -DQH[ ILJ
A. 1 4 );
7
Fig. 1.3. PlacheWDPXOWLIXQF LRQDO
Fig.1.4. Generatorul de tact automat
a) schema b) diagramele de semnal
Fie. 1.5. Formatorul de tact manual
8
F'LYL]RDUHOHGHIUHFYHQ ')1, DF2), fig. 1.6 (CDB 4193 -DQH[ ILJ$
)LJO'LYL]RUXOGHIUHFYHQ
d) Decodificatorul BCD - zecimal (DCD), fig. 1.7 (CDB 442 -DQH[ ILJ
A.6);
1.7. Decodificatorul BCD - zecimal
9
e) Formatorul de tact automat (FTA), fîg. 1.8 (CDB 4121 -DQH[ ILJ$
a) schema b) diagramele de semnal

Fig. 1.8. Formatorul de tact automat
$OLPHQWDUHDLQWU ULOHúLLHúLULOHVXEEORFXULORUSODFKHWHLPXOWLIXQF LRQDOHVXQW
accesibile prin intermediul pinilor conectorului B conform tab. 1.1. Mai mult, ele
sunt conectate prin intermedLXOXQXLFDEODMFRQYHQ LRQDO- invizibil din exteriorul
platformei -OD%6úL%7DVWIHOvQFkWSODFKHWDGHYLQHRSHUDWLY LPHGLDWGXS
cuplarea tensiunii de alimentare.
)XQF LRQDUH
&XSODFKHWDPXOWLIXQF LRQDO VFRDV GLQFRQHFWRUXO%VHLQWURGX ce cupla

SODWIRUPHLGHODERUDWRUvQSHUHFKHDVDVLWXDW SHSDUWHDODWHUDO DWDEORXOXLHOHFWULF
DOPHVHL3ULQDF LRQDUHDFRPXWDWRUXOXLVLWXDWSHWDEORXOHOHFWULFDPLQWLWVXQW
FXSODWHQXQXPDLFHOHVXUVHGHWHQVLXQHVWDELOL]DW DOHPHVHLGDUúLWHQVLXQL le
alternative la prize, în sectorul BA al platformei de laborator se vor observa
LQGLFD LLOHOXPLQRDVHDOHFHORU/('-XULFRUHVSXQ] WRDUHVXUVHORUGHWHQVLXQH
VWDELOL]DW GH999/LSVDLQGLFD LHLOXPLQRDVHDXQXL/('VHPQLILF ILH
VXUV GHIHFW ILHVFXUWFLUFXLWODERUQHOHGHLHúLUHDOHVXUVHLUHVSHFWLYH
ÎQFD]XOvQFDUHOXFUDUHDGHODERUDWRUDERUGDW QHFHVLW WHQVLXQLFRQWLQXH
UHJODELOHVHXWLOL]HD] 3333vQPRQWDMSRWHQ LRPHWULF
&RQHFWRULL$úL%FDUHHFKLSHD] SODWIRUPDGHODERUDWRUDXIRVWSUHY ]X L
vQXUP WRDUHOHVFRSXULFRQHFWRUXO$ - pentru eventuale extensii ale BSCI cu alte

tipuri de socluri si circuite integrate; conectorul B - pentru placheta
PXOWLIXQF LRQDO
10
2.2.3. ÎQIXQF LHGHOXFUDUHDGHODERUDWRUDERUGDW %6&,VHFRQHFWHD] FXDMXWRUXO
FRQH[LXQLORUODFHOHODOWHEORFXULDOHSODWIRUPHLúLODDSDUDWHOHGHP VXU
7DE'HVWLQD LDSLQLORUFRQHFWRUXOXL%
Nr. pin Bloc Nr. pin Bloc

conector 'HVWLQD LH IXQF LRQDO conector 'HVWLQD LH IXQF LRQDO
B B
B-l +Vcc PM B-23 Intr. FTA
B-2 -Vcc B-24 OHú
B-3 Intr. tact B-25 Intr. FTM,

B-4 OHú$0 B-26 OHú
B-5 OHú$1 B-27 Intr. FTM2

B-6 Ies. A2 B-28 Ies.
B-7 OHú$3 DF1 B-29 -
B-8 OHú$4 B-30 OHú GTA
B-9 OHú$5 B-31 Intr. A0
B-10 lHú$6 B-32 Intr. A,
B-ll OHú$7 B-33 Intr. A2
B-12 Reset-1 B-34 Intr. A3
B-13 Intr. tact B-35 OHú<0
B-14 OHú%0 B-36 OHú<1
B-15 OHú%1 B-37 OHú<2 DCD

B-16 Ies. B2 B-38 OHú<3
B-17 OHú%3 DF2 B-39 OHú<4
B-18 OHú
B4 B-40 OHú<5
B-19 OHú%5 B-41 OHú<6
B-20 OHú%6 B-42 OHú<7
B-21 OHú%7 B-43 OHú<8
B-22 Reset-2 B-44 OHú<9
2.2.4. Toate LED-XULOH%6WUHEXLHV ILe VWLQVHGDF LQWU ULOH$i. Bi. Ci ,Di, cu

i=0,l.... 7, sunt neconHFWDWH5H]LVWHQ D5ILJDVLJXU vQDFHVWFD]XQ2
ORJLFODLQWUDUHDLQYHUVRUXOXLGHFLOORJLFODLHúLUHDDFHVWXLDúLGLIHUHQ DGH
SRWHQ LDODSOLFDW JUXSXOXL5: - LED" este sub pragul de 1,6 V necesar

deschiderii LED-XOXL'DF XQDGLQLQWU ULOHAi. Bi. Ci ,Di,HVWHvQV
11
FRQHFWDW ,DOORJLFODLHúLUHDLQYHUVRUXOXLYRPDYHD2ORJLFúL/(' -ul se va
aprinde.
vQFD]XOvQFDUHSODFKHWDPXOWLIXQF LRQDODHVWHGHMDLQWURGXV vQFRQHFWRUXO%
LQWU ULOH$iúL%i
, ale lui BS, cu i=0.1 ... 7, sXQWFRQHFWDWHODLHúLULOH
FRUHVSXQ] WRDUHDOHGLYL]RDUHORUGHIUHFYHQ ')1úL')26W ULOHDFHVWRULHúLUL
ILLQGDEVROXWLPSUHYL]LELOHGXS FXSODUHDWHQVLXQLLGHDOLPHQWDUHHVWHILUHVFFDúL
VW ULOHSULPHORU[/(' XULDOH%6V ILHGHDVHPHQHDLPSUHYL]

- ibile.
Stingerea LED-XULORUVHIDFHSULQUHVHWDUHDQXP U WRDUHORUYSDUDJUDIXO
2.2.6.C).
7DVWHOHGHFRPDQG vQGHSOLQHVFXUP WRDUHOHIXQF LXQL
- TR1,2 UHDOL]HD] SXQHUHDSH]HURúWHUJHUHD5(6(7-area) divizoarelor de

IUHFYHQ ')1, DF2;
- TM1,2VXQWFRQHFWDWHODLQWU ULOH%-25,27 ale formatoarelor de tact manual

FTM1, FTM2,.
2.2.6. Prin conectarea pinilor B-OúL%-2 la bornele "+", respectiv "-" ale sursei de
9SODFKHWDPXOWLIXQF LRQDO 30-LQWURGXV DELDDFXPvQFRQHFWRUXO%- úL
blocul de semnalizare a nivelurilor logice (BS) vor primi tensiune de alimentare.

D3XQkQGGXS GRULQ FRPXWDWRUXO.1DO*7$SHSR]L LDOVDXYRPSXWHD
YL]XDOL]DFXDMXWRUXOXQXLRVFLORVFRSODLHúLUHD% -30 a GTA impulsuri

dreptunghiulare cu frecYHQ DGHN+]VDXN+]
E&RQHFWkQGVXFFHVLYLHúLULOH%-úL%-28 ale FTM1úL)702 la un aparat de
P VXU VDXODXQDGLQFHOHVHF LXQLQHXWLOL]DWHDOH%6&i , Di , cu i=0,l... 7), se
SRDWHREVHUYDDSDUL LDXQXLLPSXOVGHGXUDW IRDUW VFXUW vnPRPHQWXODF LRQ ULL
tastei TM1 (TM2),

F6HFRQHFWHD] ale FTM1úL)702 ODLQWU ULOHGLYL]RDUHORUGHIUHFYHQ ')1úL
DF2UHDOL]kQGSXQ LOH%-26, B-3), (B-28, B-úLVHUHVHWHD] GLYL]Rarele prin

DS VDUHDWDVWHORU751, TR2. 6HDF LRQHD] vQPRGUepetat TM1 (TM2úLVHREVHUYD
derularea nXP U ULLELQDUHSHVHF LXQLOH$i (Bi) ale BS.

G6HFRQHFWHD] LHúLULOH$Q, A,, A,, Aj a\e lui DFVvQUHJLPGHQXP U WRU
]HFLPDOUHDOY]kQGSXQ LOH%-4, B-3 1), (B-5 , B-32), (B-6, B-33), (B-7 , B-34).
,HúLULOH Y 0 (B-35), Y 1 (B-36),... , Y 9 (B-VHFRQHFWHD] OD%6&0. C1, .... C7,
D0. D1 - fig. 1.9.

3DUFXUJHUHDVXFFHVLY DSULPHORUFRPELQD LLELQDUHGHLQWUDUHDOH'&'YD
conduce la activarea în RUGLQHFUHVF WRDUHDEDUHORUGHLHúLUHDOH'&' Y 0 , Y 1 ,... ,

Y 9 6XSUDOLQLHUHDP ULPLORUGHLHúLUHVXJHUHD] IDSWXOF DFHVWHDVXQWDFWLYH
pe "O" logic (detalii în lucrarea nr. 10).
e) Se coQHFWHD] LHúLUHD%-30 a GTA (cu comutatorul K1SHSR]L LDOODLQWUDUHD
B-D)7$úLVHYL]XDOL]HD] LQWUDUHDúLLHúLUHD)7$FXFRPXWDWRUXO
12
K2SXVVXFFHVLYSHSR]L LLOHOVLXWLOL]kQGXQRVFLORVFRSFXGRX VSRWXUL
Rolul FTA este de a elabora imSXOVXULGHGXUDW VWDQGDUGQVHFUHVSHFWLY
QVHFQHFHVDUHVWXGLHULLUHJLPXULORUGLQDPLFHDOHSRU LORU77/úL&026
)LJ6FKHP SHQWUXWHVWDUHDGHFRGLILFDWRUXOXL%&' - zecimal
'HVI úXUDUHDOXFU ULL
&XSODFKHWDPXOWLIXQF LRQDO LQWURGXV vQFRQHFWRUXO%úLXUPkQGLQGLFD LLOH
GHODSXQFWXOVHDOLPHQWHD] SODWIRUPDGHODERUDWRUúLVHYHULILF H[LVWHQ D
tensiunilor continue de alimentare la cele trei perechi de borne ale BA.

6HGHFXSOHD] WHQVLXQHDGHDOLPHQWDUHúLVHYHULILF FXRKP-metrul
continuitatea "conector A (B) - pini conexiune".

6HYHULILF FXRKP-metrul sau vizual continuitatea "contacte soclu CI - pini
conexiune".
6HFXSOHD] WHQVLXQHDGHDOLPHQWDUHúLVHYHULILF H[LVWHQ DFHORU9SH
fiecare pereche de pini din stânga celor 4 grupuri de LED-XUL6HDSOLF OORJLF
VXFFHVLYFHORU[FLUFXLWHGHWLSXOFHOXLGLQILJGLQVWUXFWXUD%6úLVH
REVHUY DSULQGHUHDvQRUGLQHDFHORU/(' -uri.
13
6HGHFXSOHD] WHQVLXQHDGHDOLPHQWDUHúLVHYHULILF FXDMXWRUXORKP -
PHWUXOXLEXQDIXQF LRQDUHDFHORUWDVWHDOH%7
6HLQWURGXFHSODFKHWDPXOWLIXQF LRQDO vQFRQHFWRUXO%úLVHFXSOHD]
tensiunea de alimentare.
D8UPkQGLQGLFD LLOHGHODSXQFWXODúLFXSOkQGVRQGDXQXLRVFLORVFRS
vQWUHLHúLUHD% *7$úLPDV VHYL]XDOL]HD] LPSXOVXULOHGUHSWXQ

- ghiulare
GHIUHFYHQ N+].1SHSR]L LDVDXN+].1SHSR]L LD
6HP VRDU FkWPDLH[DFWIUHFYHQ HOHI1úLI2FXDMXWRUXORVFLORVFRSXOXLFXúLI U
generator de frecveQ VXSOLPHQWDU
E&RQIRUPLQGLFD LLORUGHODSXQFWXOEVHYL]XDOL]HD] L mpulsurile formate

GHF WUH)701úL)702 ;
F8UPkQGLQGLFD LLOHGHODSXQFWXOFVHYHULILF IXQF LRQDUHD')1úL')2 în
UHJLPGHQXP U WRUFRPDQGDWSULQ)70FRQIRUPWDE . l .2.
7DE7DEHOXOGHIXQF LRQDUHDGLYL]RUXOXLGHIUHFYHQ
Nr. ,HúLUL
imp.
intrare
A7(B7) A6(B6) A5(B5) A4(B4) A3(B3) A2(B2) A1(B1) A0(B0)
0 0 0 0 0 0 0 0 0
1 0 0 0 0 0 0 0 1
2 0 0 0 0 0 0 1 0
3 0 0 0 0 0 0 1 1
. . . . . . . . .
. . . . . . . . .
. . . . . . . . .
254 1 1 1 1 1 1 1 0
255 1 1 1 1 1 1 1 1
&RQHFWkQGLHúLUHD B-30 a GTA la intrarea B-3 a DF1úLXWLOL]kQGXQRVFLORVFRSFX

GRX VSRWXULVHYL]XDOL]HD] -S VWUkQGFDED] LPSXOVXULOHGHLQWUDUH- formele
GHXQG GHODLHúLULOH$0, A1.... ,A7.
G8UPkQGLQGLFD LLOHGHODSXQFWXOGVHYHULILF IXQF LRQDUHD'&'FRQIRUP
tab. 1.3.
H8WLOL]kQGLQGLFD LLOHGHODSXQFWXOFVHYL]XDOL]HD] úLVHP VRDU
impulsurile din fig. l .8b.

1RW (VWHLQGLFDW SDUFXUJHUHDvQWU RSULP ID] DSXQFWHORUúLFDUH
-
QXQHFHVLW FXSODUHDWHQVLXQLLGHDOLPHQWDUHXUPkQGFDGXS HSXL]DUHDDFHVWRUD
V VHFXSOH]HWHQVLXQHDGHDOLPHQWDUHúLV VHSDUFXUJ UHVWXOSXQFWHORU
14
7DE7DEHOXOGHIXQF LRQDUHDGHFRGLILFDWRUXOXL
Y0 Y1 Y 2 Y3 Y 4 Y5 Y 6 Y7 Y8 Y9
A3 A2 A1 A0
0 0 0 0 0 1 i 1 i 1 i 1 1 1
0 0 0 1 1 0 i 1 i 1 i 1 1 1
0 0 1 0 1 1 0 1 i 1 i 1 1 1
0 0 1 1 1 1 1 0 i 1 i 1 1 1
0 1 0 0 1 1 1 1 0 1 i 1 1 1
0 1 0 1 1 1 1 1 1 0 i 1 1 1
0 1 1 0 1 1 1 1 1 1 0 1 1 1
0 1 1 1 1 1 1 1 1 1 1 0 1 1
1 0 0 0 1 1 1 1 1 1 1 1 0 1
1 0 0 1 1 1 1 1 1 1 1 1 1 0
1 0 1 0 1 1. 1 1 1 1 1 1 1 1
1 0 1 1 1 1 1 1 1 1 1 1 1 1
1 1 0 0 1 1 1 1 1 1 1 1 1 1
1 1 0 1 1 1 1 1 1 1 1 1 1 1
1 1 1 0 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 1 1 1
&RQ LQXWXOUHIHUDWXOXL
4.1. Schema GTA (fig. 1.4);

4.2. Diagramele semnalelRUGHODLHúLUHD*7$SHQWUXI1 si f2 in FRUHVSRQGHQ
WHPSRUDO
4.3. ValorLOHP VXUDWHDOHIUHFYHQ HORUI1úL f2. Descrierea si explicarea

RSHUD LXQLORUGHP VXUDUH
4.46FKHPD)70ILJDúLGLDJUDPHOHGHVHPQDOILJE

6FKHPD')ILJOúLWDE
'LDJUDPHOHGHVHPQDODOHLQWU ULLúLSULPLORUEL LGHLHúLUHDL')$0 , A1,

A2, A3vQFRUHVSRQGHQ WHPSRUDO
ÎQFRQVWUXF LDGLDJUDPHORUVHYD LQHVHDPDGHXUP WRDUHOH
- înainte de aplicarea primului impuls (tact), divizoarele sunt resetate;
-LPSXOVXULOHGHWDFWVXQWDFWLYHSHIURQWXOFUHVF WRU
6FKHPDGHWHVWDUHD'&'ILJúLWDEHOXOGHIXQF LRQDUHWDE
4.8. Schema FTA (fig. DúLGiagramele de semnal (fig. l.8b);

2EVHUYD LLSHUVRQDOHDOHVWXGHQWXOXL
15
LUCRAREA NR. 2
ANALIZA SI SINTEZA CIRCUITELOR LOGICE

COMBINATIONALE
/6FRSXOOXFU ULL
LucrDUHDvúLSURSXQHRSUH]HQWDUHDSUREOHPHORUOHJDWHGHDQDOL]DúLVLQWH]Dunui
ciUFXLWORJLFFRPELULD LRQDOVLPSOu.
*HQHUDOLW L
&LUFXLWHOHORJLFHFRPELQD LRQDOHFOFVXQWFLUFXLWHI U PHPRULHFDUDFWHUL]DWH
SULQIDSWXOF YDORULOHORJLFHDOHIXQF LLORUGHLHúLUHGHSLQGQXPDLGHYDORULOH
logiceDOHYDULDELOHORUGHLQWUDUHILLQGLQGHSHQGHQWHGHVW ULOHDQWHULRDUHDOH
circuitului.
6FKHPDEORFDXQXLFOFHVWHGDW vQILJIXQF LLOHGHLHúLUHSXWkQGILVFULVH
sub forma:
Yk = Yk(x1,x2,...;xn), (2.1)
cu k.= l, 2,... , m.
Fig. 2.1. Schema bloc a unui c.l.c.
2.2. Analiza c.l.c.
$QDOL]DFOFSRUQHúWHGHODVFKHPDORJLF FXQRVFXW DFLUFXLWXOXLúLXUP UHúWH
VWDELOLUHDPRGXOXLGHIXQF LRQDUHDDFHVWXLDI ie prin construirea
16
WDEHOXOXLGHIXQF LRQDUHILHSULQVFULHUHDIRUPHLDQDOLWLFHDIXQF LHLGHLHúLUH
Exemplul 2.1
3RUQLQGGHODVFKHPDORJLF DXQXLFOFVLPSOXILJGHGXFHPGLQDSURDSHvQ
DSURDSHXUP ULQGWUDQVIRUP ULOHVHPQDOHORUGHLQWUDUHH[SUHVLDDQDOLWLF D
IXQF LHLGHLHúLUH
Y=AB.+ AB (2.2)
)LJ6FKHPDORJLF DXQXL;25
Construirea tabelului de IXQF LRQDUHWDEelului . 2.1, este acum extrem de

VLPSO
7DE7DEHOXOGHIXQF LRQDUHDOFOFGLQILJ
B A B A AB AB Y = AB +AB
0 0 1 1 0 0 0
0 1 1 0 0 1 1
1 0 0 1 1 0 1
1 1 0 0 0 0 0
5HFXQRDúWHPIXQF LDGHLHúLUHúLWDEHOXOGHIXQF LRQDUHDOFLUFXLWXOXL
SAU-EXCLUSIV (XOR).
2.3. Sinteza c.l.c.
6LQWH]DFOFSRUQHúWHGHODIXQF LDSHFDUHWUHEXLHV RvQGHSOLQHDVF FLUFXLWXOúL
vúLSURSXQHRE LQHUHDXQHLYDULDQWHPLQLPDOHDVWUXFWXULLDFHVWXLD
Etapele VLQWH]HLVXQWGHILQLUHDIXQF LHLIXQF LLORUGHLHúLUHPLQLPL]DUHDúLvQ

final, desenarea schemei circuitului.
'XS PRGXOvQFDUHDIRVWVFULV IXQF LDLPSOHPHQWDUHDVHSRDWHIDFH
DFXFLUFXLWH6$825ùO$1'18127
EFXFLUFXLWHù,-NU (NAND);
c) cu circuite SAU-NU (NOR).
17
Exemplul 2.2
6HG IXQF LD
Y = A⊕ B (2.3)
si tabelul ei GHIXQF LRQDUHWDE
7DE7DEHOXOGHIXQF LRQDUHDOIXQF LHL;25
B A Y
0 0 0
0 1 1
1 0 1
1 1 0
2EVHUY PF WDEHOHOHúLVXQWLGHQWLFHLDUUHOD LLOHúLVXQW
echivalente.
1HSURSXQHPV UHDOL] PVLQWH]DFOFH[SULPDWSULQUHOD LDúLWDEvQ
mai multe variante.

Varianta (a)
3RUQLQGGHODWDEREVHUY PF IRUPDFDQRQLF GLVMXQFWLY )&'DIXQF LHL
HVWHFHDH[SULPDW GHUHOD LD)LLQGRIRUP GHMDPLQLPDO LPSOHPHQWDUHDHL
conduce la circuitul din fig. 2.2.

3URFHGkQGVLPLODUGDUXWLOL]kQGIRUPDFDQRQLF FRQMXQFWLY )&&RE LQHP
Y= (A + B)(A + B) (2.4)
,PSOHPHQWDUHDUHOD LHLFRQGXFHODFLUFX itul din fig. 2.3.
)LJ2DOW YDULDQW GHLPSOHPHQWDUHD;25 -uIui
Varianta (b)
$SOLFkQG'H0RUJDQDVXSUD)&'RE LQHP
Y = AB + A B = ( AB )( AB ) (2.5)
,PSOHPHQWDUHDUHOD LHLSRDWHILI FXW QXPDLFX1$1' XULúLFRQGXFHOD

-
circuitul din fie. 2.4.
18
Varianta (c)
$SOLFkQG'H0RUJDQDVXSUD)&&RE LQHP
Y = ( A + B)( A + B) = ( A + B)( A + B ) (2.6)
Fig. 2.4. Implementarea XOR-ului numai cu NAND-uri
,PSOHPHQWDUHDUHOD LHLSRDWHILI FXW QXPDLFX125 XULúLFRQGXFHOD

-
circuitul din fig. 2.5.
A
Fig. 2.5. Implementarea XOR-ului numai cu NOR-uri
Ne propunem implementarea c.l.c. din fig. 2.4.

vQDFHVWVFRSYRPXWLOL]DSODWIRUPDGHODERUDWRUSUH]HQWDWDvQOXFUDUHDQUOúL
circuitul integrat CDB 400. fig. A. l -DQH[

3.1. Se coPSOHWHD] ILJFXQXPHUHOHSLQLORUILHF UHLSRU L1$1'LQFOXVLY
pinii de alimentare ai CI.

6HLPSOHPHQWHD] FOFGLQILJSH]RQDFXVRFOXULGH&,DSODWIRUPHLY
fig. 1.1).
19
6HFRQHFWHD] ODLQWU ULOH$%DOHFOFLHúLULOH$0 (B-úL$1 (B-5) ale DF1
SXVvQUHJLPGHQXP U WRUFRPDQGDWSULQ)701YOXFUDUHDQU,HúLUHDFOFVH
FRQHFWHD] OD%6VHF LXQHD&0 .

6HDOLPHQWHD] SODWIRUPDúLFLUFXLWXOGLQILJODWHQVLXQHDGH9
6HYHULILF WDEFXDMXWRUXOtactului manual
O6FKHPDGLQILJFRPSOHWDW FXQXP UXOSLQLORUUHVSHFWLYL
4.2. Tabelul 2.2;

20
LUCRAREA NR. 3
DETECTORUL DE IMPARITATE – PARITATE
1. Scopul OXFU ULL
/XFUDUHDvúLSURSXQHVLQWHWL]DUHDXQXLGHWHFWRUGHLPSDULWDWH -paritate cu 4
variabile de intrare.
*HQHUDOLW L
'HWHFWRUXOGHLPSDULWDWHSDULWDWHHVWHXQFLUFXLWORJLFFRPELQD LRQDOODLHúLUHD
F UXLDWUHEXLHV VHRE LQ OORJLFGDF QXP UXOYDULDELOHORUGHLQWUDUHHJDOHFX
"l " este impar (par).

(ODUHODED] SRDUWD6$8 (;&/86,9;25FXGRX LQWU ULILJúL
-
Fig. 3.1. Simbolul circuitului XOR
WDEHOXOGHDGHY U WDE/DLHúLUHD;25
- -ului se ob LQHOFkQGLQWU ULOHVXQW
diferite (01 sau 10 -GHFLQXP ULPSDUGHOúL2FkQGLQWU ULOHFRLQFLGVDX
11 -GHFLQXP USDUGHO
7DE7DEHOXOGHDGHY UDOIXQF LHL;25
A B Y=A(+)B
0 0 0
0 1 1
1 0 1
1 1 0
21
3UH]HQW PvQFRQWLQXDUHFkWHYDSURSULHW LDOHIXQF LHLORJLFH;25FDUHXUPHD]
a fi folosite la sinteza detectorului de imparitate-paritate.
3URSULHWDWHDQUODVRFLDWLYLWDWHDIXQF LHL;25
Y = ( A ⊕ B) ⊕ C = A ⊕ ( B ⊕ C ) (3.1)
'HPRQVWUD LH
Y = ( A ⊕ B) ⊕ C = ( AB + AB) ⊕ C = ( AB + AB)C + ( AB + AB)C = ... =

ABC + ABC + ABC + ABC = A( BC + BC ) + A( BC + BC ) =
A( B ⊕ C ) + A( B ⊕ C ) = A ⊕ ( B ⊕ C )
ProprLHWDWHDQURULFDUHDUILQXP UXOGHLQWU ULDOXQHLSRU L;25
LHúLUHD< OGDF XQQXP ULPSDUSDUGHYDULDELOHGHLQWUDUHHVWHHJDOFX
1 ⊕1⊕
.....
⊕1 ⊕ 0 ⊕0⊕

....
⊕0 = 0 ; ( 3 . 2 )
NR . par . de " 1 " NR . oarecare . de " 0 "
1 ⊕1⊕
.....
⊕1 ⊕ 0 ⊕0⊕

....
⊕0 = 1 ; ( 3 . 3 )
NR . impar . de " 1 " NR . oarecare . de " 0 "
'HPRQVWUD LDVHED]HD] SHWDEHOXOGHDGHY UDOIXQF LHL;25 , tab. 3.1.
Proprietatea, nr. 3 (utilizarea XOR-ului ca circuit inversor/neinversor

comandat):
A ⊕ 1 = A ; (3 .4 )
A ⊕ 0 = A ; (3 .5 )
&XPXOkQGFHOHGRX UH]XOWDWHUHOD LLOHúLRE LQ em circuitul
inversor/neinversor comandat din fig. 3.2.
Fig. 3.2. Circuitul inversor/neinversor comandat
2.2. Detectorul de impuritate cu 4 variabile ele intrare
3RUQLQGGH,DWDEHOXOGHDGHY UWDEvQFDUHYDORULOHORJLFHGLQFRORDQHOH<
aXIRVWRE LQXWH LQkQGVHDPDGHSURSULHW LOHúLDOH;25 -ului rezulta

SHQWUXFLUFXLWGRX YDULDQWHGHLPSOHPHQWDUH
9DULDQWDSUH]HQWDW vQILJSUH]LQW DYDQWDMXOXQRUW pd (timpi de întârziere la

propagare) egali pentru toate variabilele de intrare.
22
7DE7DEHOXOGHDGHY UDOGHWHFWRUXOXLGHLPSDULWDWH
Var. intrare Y=[(A ⊕ B) ⊕ C] ⊕ D Y=(A ⊕ B) ⊕ (C ⊕ D)

YAB= YABC = Y= YAB= YCD= Y=
D C B A
A ⊕ B YAB ⊕ C YABC ⊕ D A ⊕ B C ⊕ D YAB ⊕ YCD
0 0 0 0 0 0 0 0 0 0
0 0 0 1 1 1 1 1 0 1
0 0 1 0 1 1 1 1 0 1
0 0 1 1 0 0 0 0 0 0
0 1 0 0 0 1 1 0 1 1
0 1 0 1 1 0 0 1 1 0
0 1 1 0 1 0 0 1 1 0
0 1 1 1 0 1 1 0 1 1
1 0 0 0 0 0 1 0 1 1
1 0 0 1 1 1 0 1 1 0
1 0 1 0 1 1 0 1 1 0
1 0 1 1 0 0 1 0 1 1
1 1 0 0 0 1 0 0 0 0
1 1 0 1 1 0 1 1 0 1
1 1 1 0 1 0 1 1 0 1
1 1 1 1 0 1 0 0 0 0
Fig. 3.3. Schema detectorului de Fig. 3.4. Schema detectorului de

imparitate varianta l imparitate varianta 2
2.3. Detectorul de imparitate-paritate comandat
În sintezDGHWHFWRUXOXLHVWHQHFHVDUV VH LQ VHDPDGHXUP WRDUHOHFRQGL LL

1) Transformarea detectorului de imparitate (fig. 3.4) în detector de
23
SDULWDWHWUHEXLHUHDOL]DW SULQVFKLPEDUHDYDORULLORJLFHDXQHLVLQJXUHEDUHGH
FRPDQG
2) Indiferent dHUHJLPXOGHLPSDULWDWHVDXSDULWDWHvQFDUHOXFUHD]
GHWHFWRUXOLHúLUHDDFHVWXLDWUHEXLHV ILHOORJLFvQPRPHQWXOGHWHF LHL5H]XOW
F SHQWUXUHJLPXOGHLPSDULWDWHLHúLUHD<
Y , iar pentru regimul de "paritate",
Y’=Y (vWDE(VWHGHFLQHFHVDU XWLOL]DUHDSURSULHW LLGHPDQLHUDGLQILJ
3.5.
Fig. 3.5. Schema detectorului de imparitate-paritate comandat
Într-DGHY U
Y , dacaP ="0" (det ector.de.imparitate)

Y ‘= Y ⊕ P = 
Y , dacaP ="1" (det ector.de. paritate)
3.'HVI úXUDUHDOXFU ULL
3HQWUXLPSOHPHQWDUHDGHWHFWRDUHORUGHODSXQFWHOHúLVHYDIRORVL
SODWIRUPDGHODERUDWRUúLFLUFXLWXOLQWHJUDW&'%[;25FXFkWHLQWU UL
SUH]HQWDWvQDQH[ fi g. A. 13.
3.1. Studiul detectorului de imparitate
6HFRPSOHWHD] ILJFXQXPHUHOHSLQLORUILHF UXL;25LQFOXVLYSLQLLGH
DOLPHQWDUHDL&,SUHOXD LGLQILJ$ DQH[

-
6HLPSOHPHQWHD] GHWHFWRUXOGLQILJSH]RQDFXVRFOXUL de CI a
platformei.
6HFRQHFWHD] ODLQWU ULOH$%&'DOHGHWHFWRUXOXLLHúLULOH$0
(B-4), A1 (B-
5), A2, (B-6), A3 (B-7) DOHGLYL]RUXOXLGHIUHFYHQ ')1 în regim de num U WRU
comandat cu ajutorul FTM1YOXFUDUHDQUO,HúLUHDGHWHFWRUXOXLVe coQHFWHD]
OD%6VHF LXQHD&0.
O6HDOLPHQWHD] SODWIRUPDGHODERUDWRUúLGHWHFWRUXOODVXUVDGH9
24
3.1.5. 6HYHULILF WDEFXDMXWRUXOWDFWXOXLPDQXDO
6HUHSHW RSHUD LLOH - 3.1.5. pentru detectorul din fig.3.4.
Tab. 3.3. Tabelul de aGHY UDOGHWHFWRUXOXL

de imparitate - paritate comandat
D C B A F P Y‘
0 0 0 0 0 0 0
0 0 0 1 1 0 1
0 0 1 0 1 0 1
0 0 1 1 0 0 0
0 1 0 0 1 0 1
0 1 0 1 0 0 0
0 1 1 0 0 0 0
0 1 1 1 1 0 1
1 0 0 0 1 0 1
1 0 0 1 0 0 0
1 0 1 0 0 0 0
1 0 1 1 1 0 1
1 1 0 0 0 0 0
1 1 0 1 1 0 1
1 1 1 0 1 0 1
1 1 1 1 0 0 0
0 0 0 0 0 1 1
0 0 0 1 1 1 0
0 0 1 0 1 1 0
0 0 1 1 0 1 1
0 1 0 0 1 1 0
0 1 0 1 0 1 1
0 l 1 0 0 1 1
0 1 1 1 1 1 0
1 0 0 0 1 1 0
1 0 0 1 0 1 1
1 0 1 0 0 1 1
1 0 1 1 1 1 0
1 1 0 0 0 1 1
1 1 0 1 1 1 0
1 1 1 0 1 1 0
1 1 1 1 0 1 1
25
3.2. Studiul detectorului de imparitate-paritate comandat
6HFRPSOHWHD] ILJFXQXPHUHOHSLQLORUILHF UXL;25LQFOXVLYSLQLLGH
DOLPHQWDUHDL&,SUHOXD LGLQILJXUD$ DQH[

-
6HLPSOHPHQWHD] Getectorul din fig. 3.5 pe zona cu socluri de CI a
platformei.
6HFRQHFWHD] ODLQWU ULOH$%&'DOHGHWHFWRUXOXLLHúLULOH$0
(B-4), A1
(B-5), A2 (B-6), A3 (B-DOHGLYL]RUXOXLGHIUHFYHQ ')1 în regim de num U WRU
comandat cu ajutorai FTM1 (v.OXFUDUHDQU,QWUDUHD3VHODV vQDHU3 O
SHQWUXVWXGLXOGHWHFWRUXOXLGHSDULWDWHVDXVHFRQHFWHD] ODPDV 3 SHQWUX
VWXGLXOGHWHFWRUXOXLGHLPSDULWDWH,HúLUHDGHWHFWRUXOXLVHFRQHFWHD] OD%6
VHF LXQHD&0 .
3.2.4. Se alimenteaz SODWIRUPDGHODERUDWRUúLGHWHFWRUXOODVXUVDGH9
6HYHULILF IXQF LRQDUHDGHWHFWRUXOXLFXDMXWRUXOWDE
6FKHPHOHGLQILJúLFRPSOHWDWHFXQXP UXOSLQLORUUHVSHFWLYL
7DEHOHOHúL
3.3;
26
LUCRAREA NR. 4
CIRCUITE DE MULTIPLEXARE
1. 6FRSXOOXFU ULL
/XFUDUHDvúLSURSXQHVLQWHWL]DUHDXQXLFLUFXLWGHPXOWLSOH[DUHFXLQWU UL
*HQHUDOLW L
Circuitele de multiplexare (MUX-urile) sunt c.l.c. care permit trecerea datelor de

ODXQDGLQFHOHQLQWU ULVSUHLHúLUHDXQLF 6HOHF LDLQWU ULLFDUHXQQHD] DDYHD
DFFHVODLHúLUHVHIDFHSULQWU XQFXYkQWGHFRGDGUHV DYkQG

- p EL LILJ
Fig.4. O6FKHPDEORFJHQHUDO DXQXLPXOWLSOH[RU
p
6HREVHUY F Q DGLF QXP UXOGHLQWU ULHVWHHJDOFXQXP UXOFRPELQD LLORU
GHFRGDOHEDUHORUGHDGUHV
1.2. &LUFXLWXOGHPXOWLSOH[DUHFXLQWU UL
În cazul MUX-ului cu n LQWU UL,0

, I1, I2,. I3QXP UXOEDUHORUGHDGUHV HVWH
p=2(A0, A1).
27
2EVHUYD LH6FKHPDHVWHSUHY ]XW úLFXRLQWUDUHGHDXWRUL]DUH E DFWLY vQVWDUHD
"L".
3RUQLQGGHODWDEHOXOGHDGHY UDOXQXLFLUFXLWGHPXOWLSOH[DUHFXLQWU ULWDE
VFULHP)&'UHOD LDDF UHLLPSOHPHQWDUHHVWHSUH]HQWDW vQILJ
7DEO7DEHOXOGHDGHY UDOXQXL08;FXLQWU UL
E A1 A0 I0 I1 I2 I3 Y
1 x x x x x x 0
0 0 0 Io x x x I0
0 0 1 x I1 x x I3
0 1 0 x x I2 x I2
0 1 1 x x x I3 I3
(4.1)
Fig2VFKHP PLQLPDO D08; XOXLFXLQWU UL

-
LQkQGVHDPDGHGLVSRQLELOXOGHFLUFXLWHLQWHJUDWH&'%
LQYHUVRDUFILJ$&'%[ù,FXFkWHLQWU ULILJ$&'%
28
RSHUDWRUùL -SAU-18FX[LQWU ULILJ$úLXWLOL]kQGSURSULHWDWHDGH
DVRFLDWLYLWDWHDIXQF LHLù,
x1x2x3x4=(x1x2)(x3x4), (4.2)
VFKHPDGLQILJSRDWHILWUDQVIRUPDW GHPDQLHUDGLQILJ
)LJ2VFKHP FRQYHQDELO D08; XOXLFXLQWU UL

-
MUX-XULOHSRWILXWLOL]DWHODLPSOHPHQWDUHDFOFFXRVLQJXU LHúLUHODFRQYHUVLD
paralel-VHULHDGDWHORUSUHFXPúLODUHDOL]DUHDGHVLVWHPHGHWUDQVPLVLHDGDWHORU
pe un singur canal, cu asigurarHDVLQFURQL] ULL
29
3HQWUXLPSOHPHQWDUHDXQXLFLUFXLWGHPXOWLSOH[DUHFXLQWU ULVHYDIRORVL
SODWIRUPDGHODERUDWRUúLFLUFXLWHOHLQWHJUDWH&'%&'%úL&'%
SUH]HQWDWHvQILJ$$úL$ DQH[
-
3.1. Se completeD] ILJFXQXPHUHOHSLQLORUILHF UXLFLUFXLWLQWHJUDWLQFOXVLY
pinii de alimentare.
6HLPSOHPHQWHD] FLUFXLWXOGHPXOWLSOH[DUHFXLQWU ULSH]RQDFX
socluri de CI a platformei.
6HFRQHFWHD] LQWU ULOH,0, I1, I2, I3úL$0, A1 ale circuitului de multiplexare la
LHúLULOH$0 (B-4), A1 (B-5), A2 (B-6), A3 (B-7), respectiv B0 (B-14), B1 (B-15)
ale DF1úL')2SXVHvQUHJLPGHQXP U WRUFRPDQGDWSULQ)70,HúLUHDFLUFXLWXOXL
GHPXOWLSOH[DUHVHFRQHFWHD] OD%6ELWXO&0.
3.4. Se alimenteaz FLUFXLWHOHSODWIRUPHLGHODVXUVDGH9

6HYHULILF WDESHQWUXWRDWHFRPELQD LLOHLQWU ULORUGHDGUHV $0, A1úL
LQWU ULORUGHGDWH,0, Ib I2,13.
6FKHPDGLQILJFRPSOHWDW FXQXP UXOSLQLORUUHVSHFWLYL
4.2. Tabelul 4.1;

30
LUCRAREA NR. 5
CIRCUITE DE DEMULTIPLEXARE
1. 6FRSXOOXFU ULL
/XFUDUHDvúLSURSXQHVLQWHWL]DUHDXQXLFLUFXLWGHGHPXOWLSOH[DUHFXLHúLUL
2.1. GeneraliW L
Circuitele de demultiplexare (DEMUX-urile) sunt c.l.c. care permit transmiterea

GDWHORUGHODRLQWUDUHXQLF ODXQDGLQFHOHPLHúLULVHOHFWDWHSULQWU-un cuvânt de
FRGDGUHV
p
6FKHPDXQXL'(08;FXPLHúLULúLSEDUHGHDGUHV P ) este prezentaW vQ
fig. 5.1.
)LJ6FKHPDEORFJHQHUDO DXQXL demultiplexor
2.2. &LUFXLWXOGHGHPXOWLSOH[DUHFXLHúLUL
&LUFXLWXOGHGHPXOWLSOH[DUHFXP LHúLUL Y0,Y1, Y2, Y3DUHS EDUHGHDGUHV
(A0.A1).
31
3RUQLQGGHODWDEHOXOGHDGHY UD l unui astfel de circuit, tab. 5.1,
7DE7DEHOXOGHDGHY UDOXQXL'(08;FXLHúLUL
A1 A0 I YO Y1 Y2 Y3
0 0 0/1 0/1 0 0 0
0 1 0/1 0 0/1 0 0
1 0 0/1 0 0 0/1 0
1 1 0/1 0 0 0 0/1
VHVFULXIXQF LLOHGHLHúLUH
Y 0 = I A1 A 0 ,
Y 1 = I A1 A 0
(5.1)
Y 2 = IA 1 A 0
Y 3 = IA 1 A 0
úLVHRE LQHYDULDQWDGHLPSOHPHQWDUHGLQILJ
Fig2VFKHP PLQLPDO D'(08; XOXLFXLHúLUL

-
LQkQGVHDPDGHGLVSRQLELOXOGHFLUFXLWHLQWHJUDWH&'%[ù,FXFkWH
LQWU ULILJ$úL&'%LQYHUVRDUHILJ$úLXWLOL]kQGSURSULHWDWHDGH
DVRFLDWLYLWDWHDIXQF LHLù,
32
x1x2x3 = x1(x2x3), (5.2)
SRU LOHORJLFHù,FXLQWU ULVHSRWVLQWHWL]DGLQSRU LORJLFHùOFXLQWU ULDúD
cum este ilustrat în fig. 5.3.
)LJ6LQWHWL]DUHDSRU LLúLFXLQWU UL
ÎQDFHVWHFRQGL LLFLUFXLWXOGLQILJVHWUDQVIRUP GHPDQLHUDGLQ
fig. 5.4.
)LJ2VFKHP FRQYHQDELO D'(08; XOXLFXLHúLUL

-
2. 'HVI úXUDUHDOXFU ULL
3HQWUXLPSOHPHQWDUHDXQXLFLUFXLWGHGHPXOWLSOH[DUFFXLHúLULVHYDIRORVL
SODWIRUPDGHODERUDWRUúLFLUF uitele integrate CDB 404 (6 inversoare) si CDB 408

[ùOFXLQWU ULSUH]HQWDWHvQILJ$úL$-DQH[
6HFRPSOHWHD] ILJFXQXPHUHOHSLQLORUILHF UXLFLUFXLWLQWHJUDWLQFOXVLY
SLQLLGHDOLPHQWDUHDL&,SUHOXD LGLQILJ$úL$
33
6HLPSOHPHQWHD] FLUFXLWXOGHGHPXOWLSOH[DUFFXLHúLULSH]RQDFX
socluri de CI a platformei.
6HFRQHFWHD] LQWU ULOH$0úL$1DOHFLUFXLWXOXLGHGHPXOWLSOH[DUHODLHúLULOH
A0 (B-úL$1 (B-5) ale DF1 pus în regim de num U WRUFRPDQGDWFXDMXWRUXO

FTM1YOXFUDUHDQU,QWUDUHD,VHFRQHFWHD] DOWHUQDWLYODOVDXOD2ORJLF
IeúLULOHFLUFXLWXOXLGHGHPXOWLSOH[DUHVHFRQHFWHD] OD%6EL LL&0, C1, C2 úL&3.
6HDOLPHQWHD] FLUFXLWHOHSODWIRUPHLGHODVXUVDGH9
6HYHULILF WDESHQWUXWRDWHFRPELQD LLOHLQWU ULORUGHDGUHV $0, A1úL

de date (I).
&RQ LQXWXO referatului
4.2. Tabelul 5.1;

34
LUCRAREA NR..6
COMPARATOARE NUMERICE
1. 6FRSXOOXFU ULL
/XFUDUHDvúLSURSXQHVLQWHWL]DUHDXQRUFRPSDUDWRDUHQXPHULFHGHOELWúLGHEL L
SUHFXPúLVWXGLXOFRPSDUDWRUXOXLLQWHJUDW61
*HQHUDOLW L
Comparatoarele numerice sunt c.l.c. care permit determinarea valorii relative a

GRX QXPHUHH[SULPDWHvQFRGELQDr.
6FKHPDEORFDXQXLFRPSDUDWRUGHQEL LHVWHSUH]HQWDW vQILJ
)LJO6FKHPDEORFDXQXLFRPSDUDWRUGHQEL L
2.2. Comparatorul numeric de un bit
&RPSDUDWRUXOQXPHULFGHXQELWSUH]LQW VFKHPDEORFGLQILJ
35
fik (Ak inferior lui Bk)
fek (Ak egal cu Bk)
fsk(Ak superior lui Bk)
Fig, 6.2. Schema bloc a comparatorului de l bit
CompaUDUHDQXPHULF DFHORUGRX QXPHUHGHFkWHXQELWDUHODED]
 A K B K = 1 − pentruA k < B

XUP WRDUHOHREVHUYD LL  A k ⊕ B K = 1 − pentruA k = B

 A K B K = 1 − pentruA k > B
3RUQLQGGHODWDEHOXOGHDGHY UWDEvQFDUHFRORDQHOHVLUHSUH]LQW
LHúLULOHFRPSDUDWRUXOXLGHOELWSHQWUXFHOHVLWXD LLSRVLELOHUH]XOWDWHvQXUPD
FRPSDU ULLVHRE LQHYDULDQWDGHLPSOHPHQWDUHGLQILJ
7DE7DEHOXOGHDGHY UDOFRPSDUDWRUXOXLGHOELW
fik fek fsk

AK BK A K BK A K ⊕ BK AK B K
0 0 0 1 0
0 1 1 0 0
1 0 0 0 1
1 1 0 1 0
AK <BK AK =BK AK >BK
fik
)LJ6FKHPDORJLF D
comparatorului de l bit
fek
fsk
36
2.&RPSDUDWRUXOQXPHULFGHSDWUXEL L
6HSRDWHRE LQHSULQLQWHUFRQHFWDUHDDSDWUXFRPSDUDWRDUHGHXQELW&HOHGRX
QXPHUHGHEL LVHSRWVFULH
A = 23A3+22A2+21A1+20A0;
B = 23B3+22B2+21B1+20B0.
3URFHVXOFRPSDU ULLvQFHSHFXEL LLFHLPDLVHPQLILFDWLYL$VWIHOSHQWUXDDYHD
A<B este necesar ca:

sau A3 < B3,
sau A3 = B3úL$2 < B2,
sau A3 = B3úL$2 = B2úL$1 < B1 ,
sau A3 = B3úL$2 = B2úL$1 = B1úL$0 < B0.
5H]XOW IXQF LD
Fi = fi3 +fe3fi2+fe3fe2fi1+fe3fe2fe1fi0. (6. l)

Pentru A = B ete necesar ca:
A3 = B3úL$2 = B2úL$1 = B1úL$0 = B0.
5H]XOW IXQF LD
Fe = fe3fe2fe,fe0. (6.2)
Pentru A > B este necesar ca:
sau A3 > B3,
sau A3 = B3úi A2 > B2,
sau A3 = B3úL$2 = B2úL$1 > B1,
sau A3 = B3úL$2 = B2úLA1 = B1 úL$0 > B0.
5H]XOW IXQF LD
Fs = fs3+fe3fs2+fe3fe2fs1+fe3fe2fe1fs0. (6.3)
ÎQWUXFkWUHOD LLOHúLQXSRWILDGHY UDWHVLPXOWDQVHSRDWHVFULHF
RULFDUHGLQFHOHUHOD LLHVWHDGHY UDW GDF FHOHODOWHGRX VXQWIDOVH
Fi = FeFs ; (6.4)
Fe = Fi Fs ; (6.5)
Fs = Fi Fe . (6.6)
Prin XUPDUHWHRUHWLFHVWHVXILFLHQW RE LQHUHDDGRX GLQUHOD LLOH
úLDWUHLDUH]XOWkQGFXQXPDLGRX LQYHVRDUHúLRSRDUW ù,GLQWU -

XQDGLQUHOD LLOHVDX3UDFWLFVHLPSOHPHQWHD] WRDWHFHOH
UHOD LLSHQWUXDQXDS UHDGLIHUHQ HGHWLPSLGHSURSDJDUH
6HSUH]LQW - spre exemplificare -LPSOHPHQWDUHDIXQF LLORU)LILJDúL)H

ILJEFXREVHUYD LDF FLUFXLWXOFRUHVSXQ] WRUOXL)VSRDWHILUHDOL]DWGH
PDQLHUDGLQILJDHYLGHQWFXDOWHP ULPLGHLQWUDU e) sau de maniera din fig.

FYUHOD LD
37
c)
a)
)LJ6FKHPHOHORJLFHVLPSOLILFDWHDOHIXQF LLORU
GHLHúLUHDOHFRPSDUDWRUXOXLGHEL L
)L
)H
úL)V
VXQWLQWU ULGHH[WHQVLHODFDUHVHFRQHFWHD] LHúLULOHFRPSDUDWRUXOXL
GHEL LGHUDQJLQIHULRU
ÎQWUXFkWLPSOHPHQWDUHDvQODERUDWRUDFRPSDUDWRUXOXLGHEL LSUH]HQWDWvQILJ
HVWHGLILFLO GDWRULW FRPSOH[LW LLFLUFXLWXOXLQHSURSXQHPvQFRQWLQXDUHVWXGLXO
comparatorului nuPHULFLQWHJUDWGHEL L61ILJDQH[ $
A0 A1 A2 A3 B0 B1 B2 B3
Fe1
Fi1
Fs1
)LJ6FKHPDGHFRQH[LXQLDXQXLFRPSDUDWRULQWHJUDWGHEL L
2.4 Comparatorul numeULFGHEL

&RQHFWkQGvQFDVFDG GRX FRPSDUDWRDUH61RE LQHPXQ
FRPSDUDWRUQXPHULFGHEL LILJ
38
Fig. 6.6. Schema de conexiuni aXQXLFRPSDUDWRUGHEL LVLQWHWL]DWFX[61
7485
3HQWUXLPSOHPHQWDUHDFRPSDUDWRDUHORUSUH]HQWDWHODSXQFWHOHúLVHYD
IRORVLSODWIRUPDGHODERUDWRUúLFLUFXLWHOHLQWHJUDWH&'%&'%&'%
úL61 - anex ILJ$$$úL$
3.1. Implementarea comparatorului de l bit
6HFRPSOHWHD] FLUFXLWXOGLQILJFXQXPHUHOHSLQLORUFLUFXLWHORU
LQWHJUDWHXWLOL]DWHILJ$$úL$LQFOXVLYSLQLLGHDOLPHQWDUH
6HLPSOHPHQWHD] comparatorul din fig. 6.3 pe zona cu socluri de CI a

platformei.
6HFRQHFWHD] LQWU ULOH$k
, BkDOHFRPSDUDWRUXOXLODLHúLULOH$0 (B-4), B0
(B-14) aOHGLYL]RDUHORUGHIUHFYHQ ')1 DF2SXVHvQUHJLPGHQXP U WRU
FRPDQGDWSULQ)70,HúLULOHFRPSDUDWRUXOXLVHFRQHFWHD] OD%6EL LL&0, C1, C2
6HYHULILF WDESHQWUXWRDWHFRPELQD LLOHLQWU ULORU$k , Bk.
6WXGLXOFRPSDUDWRUXOXLGHEL L
6HUHDOL]HD] FRQH[LXQLOHGLQILJSH]RQDFXVRFOXULGH&,DSODWIRUPHL
6HFRQHFWHD] LQWU ULOH$0

, A1, A2, A3úL%0, B1, B2, B3 ale
FRPSDUDWRUXOXLODLHúLULOH$0
(B-4), A1 (B-5), A2 (B-.6), A3 (B-úL%0 (B-14), B1
(B-15), B2 (B-16), B3 (B-17) aOHGLYL]RDUHORUGHIUHFYHQ ')1, DF2 : puse în
UHJLPGHQXP U WRUFRPDQGDWSULQ)70,HúLULOHFRPSDUDWRUXOXLVHFRQHFWHD] OD
%6EL LL&0 . C1,C2.

6HDOLPHQWHD] FLUFXLWHOHSODWIRUPHLGHODVXUVD de 5V.
39
6HYHULIWF IXQF LRQDUHDFRPSDUDWRUXOXLGHEL LSHQWUXWRDWHFRPELQD LLOH
SRVLELOHDOHLQWU ULORU
6WXGLXOFRPSDUDWRUXOXLGHEL L
6HUHDOL]HD] FLUFXLWXOILJSH]RQDFXVRFOXULGH&,DSODWIRUPHL
3.3.2. Se coQHFWHD] LQWU ULOH$0

, A1, ..., A7úL%0, B1, ..., B7, ale
FRPSDUDWRUXOXLODLHúLULOH$0 (B-4), A1 (B-5), ..., A7 (B-OúL%0 (B-14), B1 (B-
15) , ..., B7 (B-21) aOHGLYL]RDUHORUGHIUHFYHQ ')1, DF2 puse în regim de

QXP U WRUFRPDQGDWSULQ)70,HúLULOHFRPSDUDWRUXOXLVHFRQHFWHD] OD%6EL LL
C0. C1,C2.
6HYHULILF IXQF LRQDUHDFRPSDUDWRUXOXLGHEL LSHQWUXWRDWHFRPELQD LLOH
SRVLELOHDOHLQWU ULORU
&RQ LQXWXOUHIHUDW ului
4.2. Tabelul 6.1;

4.3. Schema din fig. 6.5;
7DEHOXOGHIXQF LRQDUHDFRPSDUDWRUXOXLGHEL LGLQILJFRQ LQkQG
FRPELQD LLOHORJLFHUHOHYDQWHDOHFHORU[LQWU ULúLYDORULOHORJLFHDOHLHúLULORU

40
LUCRAREA NR. 7
SUMATOARE
1. 6FRSXOOXFU ULL
/XFUDUHDvúLSURSXQHVLQWHWL]DUHDXQXLVHPLVXPDWRUúLVXPDWRUFRPSOHWGHXQELW
SUHFXPúLVWXGLXOXQXLVXPDWRUGHEL LLQWHJUDW
*HQHUDOLW L
6XPDWRUXOHVWHVXEVLVWHPXOORJLFFRPELQD LRQDOFDUHDVLJXU - direct sau indirect -

HIHFWXDUHDWXWXURURSHUD LLORUDULWPHWLFHGLQWU -un sistem de calcul.
Schema bloc a unui sumator de 2QXPHUHELQDUHDFkWHQEL LHVWHSUH]HQWDW vQ
fig. 7.1, unde s-au notat cu Si , i=0,l, ..., n-EL LLFRUHVSXQ] WRULVXPHLLDUFX
Ci WUDQVSRUWXOF WUHUDQJXOXUP WRU
A0
S0
A1
S1
An-1
B0
B1 Sn-1
Cn-1
Bn-1
)LJO6FKHPDEORFJHQHUDO DXQXLVXPDWRU
2.2. Semisumatorul
Semisumatorul UHDOL]HD] VXPDDGRX QXPHUHELQDUHGHFkWHOELWI U D LQH
seDPDGHWUDQVSRUWXOGHODELWXOLPHGLDWLQIHULRUFDVHPQLILFD LH
41
3RUQLQGGHODWDEHOXOGHDGHY UDOXQXLVHPLVXPDWRUGHOELWWDE
7DE7DEHOXOGHDGHY UDOVHPLVXPDWRUXOXLGHOELW
A1 Bt Rezultatul Suma Transport

DGXQ rii (S1) (C1)
0 0 00 0 0
0 1 01 1 0
1 0 01 1 0
1 1 10 0 1
se RE LQUHOD LLOHGHFDOFXOúLDF URULPSOHPHQWDUHFRQGXFHODVFKHPD
GLQILJDVDXODQLYHOGHVFKHP EORFILJE
(7 .1)
S i = Ai ⊕ Bi
 (7.2)
C i = Ai Bi
DVFKHPDORJLF b) Schema bloc
Fig. 7.2. Semisumatorul de l bit
2.3. Sumatorul complet de l bit
6SUHGHRVHELUHGHVHPLVXPDWRUVXPDWRUXOFRPSOHWGHOELWLDvQFRQVLGHUD LHúL
transportul Ci-1 de la bitul imediat inferior, conform schemei bloc din fig. 7.3.
7DEHOXOGHIXQF LRQDUHDOVXPDWRUXOXLFRPSOHWGHOELWHVWHWDE
&DúLvQFD]XOVHPLVXPDWRUXOXLLHúLUHD6iHVWHVXPDPRGXORDFHORULQWU UL
S i = Ai ⊕ Bi ⊕ C i = A i B i C i −1 + A i Bi C i −1 + Ai B i C i −1 + Ai Bi C i −1 (7.3)
UHOD LHFDUHVHSRDWHRE LQHúLGLUHFWGLQWDE . 7.2.
42
Ai Bi Ci-1
Ci Si
Fig. 7.3. Schema bloc a sumatorului complet de l bit
7DE7DEHOXOGHIXQF LRQDUHDOVXPDWRUXLXLFRPSOHWGHOELW
,QWU UL Suma ,HúLUL
Ai Bi Ci-1 Si Ci
0 0 0 00 0 0
0 0 1 01 1 0
0 1 0 01 1 0
0 1 1 10 0 1
1 0 0 01 1 0
1 0 1 10 0 1
1 1 0 10 0 1
1 1 1 11 1 1
'LQDFHODúLWDEHOVHSRDWHGHGXFHúL& i:
Ci = A i Bi C i −1 + Ai B i C i −1 + Ai Bi C i −1 + Ai Bi Ci −1 (7.4)
Grupând succesiv fiecare din pULPLLWUHLWHUPHQLDLUHOD LHLFXXOWLPXOVH
RE LQH
Ci=BiCi-1 + AiCi-1 + AiBi (7.5)

úLGXS RSHUD LLOHGHULJRDUH
Ci = A i Bi + A i C i −1 + B i C i −1 (7.6)
Notând primii trei termeni din S, cu D,:
Di = A i B i C i −1 + A i Bi C i −1 + Ai B i C i −1 (7.7)
REVHUY PF DFHúWLDVHSRWRE LQHGLQSURGXVXOORJLFDOOXL&;cu (A. + B. + C;.,):
Di = ( Ai + Bi + Ci −1 )C i −1 (7.8)
într-DGHY ULQWURGXFkQG C i GLQUHOD LDvQúLHIHFWXkQGRSHUD LLOHVH
RE LQHH[SUHVLD
5H]XOW F 6i se poate scrie:
43
S i = Di + Ai Bi Ci −1 = Ai C i + Bi C i + Ci −1 C i + Ai Bi C i −1 (7.9)
,PSOHPHQWDUHDUHOD LLORUúLFRQGXFHODVLQWH]DVFKHPHL
sumatorului complet de l bit, fig. 7.4.

Ai Bi Ci-1 C i +Vcc
)LJ6FKHPDORJLF DVXPDWRUXOXLFRPSOHWGHOELW
6XPDWRUXOFRPSOHWGHEL L
6HRE LQHSULQLQWHUFRQHFWDUHDDVXPDWRDUHFRPSOHWHGH 1ELWDúDFXPHVWH

ilustrat în fig. 7.5. întrucât implementarea unui astfel de sumator cu ajutorul
FLUFXLWHORUORJLFHHOHPHQWDUHHVWHGHRVHELWGHODERULRDV YRPXWLOL]DSHQWUX
LOXVWUDUHVXPDWRUXOFRPSOHWGHEL LLQWHJUDW&'%DF UXLVFKHP EORFHVWH
LGHQWLF FXFHDSUH]HQWDW vQILJDQH[ ILJ$
3'HVI úXUDUHDOXFU ULL
3HQWUXVWXGLXOFLUFXLWHORUSUH]HQWDWHODSXQFWHOHúLVHYDXWLOL]D
SODWIRUPDGHODERUDWRUúLFLUFXLWHOHLQWHJUDWH&'%$&'%$
&'%$&'%;úL&'%$
44
+Vcc A3 B 3 A2 B2 A 1 B1 A0 B0
C-1
S3 S2 S1 S0
Fig. 7.5. Schema bloc a sumatorului cRPSOHWGHEL L
3.1. Studiul semisumatorului
6HFRPSOHWHD] ILJDFXQXPHUHOHSLQLORU&,XWLOL]DWH&'%úL
CDB 486), inclusiv pinii de alimentare.

6HLPSOHPHQWHD] VHPLVXPDWRUXOGLQILJDSH]RQDFXVRFOXULGH&,D
platformei.
3.6HFRQHFWHD] LQWU ULOH$iúL%iDOHVHPLVXPDWRUXOXLODLHúLULOH$0 (B-úL
B0 (B-DOHGLYL]RDUHORUGHIUHFYHQ ')1 DF2SXVHvQUHJLPGHQXP U WRr
FRPDQGDWSULQ)70,HúLULOH6iúL&iVHFRQHFWHD] OD%6EL LL&0úL
C1.
3.1.4. Se alimenteaz FLUFXLWHOHSODWIRUPHLGHODVXUVDGH9
6HYHULILF WDESHQWUXWRDWHFRPELQD LLOHORJLFHSRVLELOHDOHLQWU ULORU
Ai, Bi.
3.2. Studiul sumatorului complet de l bit
6HPRGLILF VFKHPDGLQILJvQORFXLQGX VHSRDUWDù,FXLQWU ULFX

-
GRX SRU Lù,FXFkWHLQWU ULYILJ
6HFRPSOHWHD] VFKHPDRE LQXW ODSXQFWXOFXQXPHUHOHSLQLORU&,
XWLOL]DWH&'%&'%úL&'%LQFOXVLYSLQLLGHDOLPHQWDUH
6HLPSOHPHQWHD] VXPDWRUXOGHODSXQFWXO .2. pe zona cu socluri de CI a

platformei.
6HFRQHFWHD] LQWU ULOH$iúL%iDOHVHPLVXPDWRUXOXLODLHúLULOH$0 (B-úL
B0 (B-14) aOHGLYL]RDUHORUGHIUHFYHQ ')1 , DF2SXVHvQUHJLPGHQXP U WRU
45
comandat prin FTM. Intrarea de transport Ci-1., se cRQHFWHD] GXS FD]OD2 "
VDXOORJLFLDULHúLULOH6iúL&iVHFRQHFWHD] OD%6EL LL&0úL&1
.
6HYHULILF WDESHQWUXWRDWHFRPELQD LLOHORJLFHSRVLELOHDOH
LQWU ULORU
AI, Bi;.
6WXGLXOVXPDWRUXOXLFRPSOHWGHEL L
6HXWLOL]HD] FLUFXLWXOLQWHJUDW&'%ILJ
3.3.2. Se introduce CI CDB 483 din fig. 7.5 într-un soclu din zona
FRUHVSXQ] WRDUHDSODWIRUPHL
6HFRQHFWHD] LQWU ULOH$0 , A1, A2, A3úi B0, B1, B2, B3 ale sumatorului la
LHúLULOH$0 (B-4), A1 (B-5), A2 (B-6), A3 (B-úL%0 (B-14), B1 (B-15), B2 (B-16),
B3 (B-17) aOHGLYL]RDUHORUGHIUHFYHQ ')1, DF2SXVHvQUHJLPGHQXP U WRU

comandat prin FTM. Intrarea de transport C-1, se conHFWHD] ODPDV LDULHúLULOH
S0, S1, S2, S3úL&3VHFRQHFWHD] OD%6EL LL'0, D1 D2 D3úL D4.
6HYHULILF IXQF LRQDUHDVXPDWRUXOXLFRPSOHWGHEL LLQWHJUDW&'%
SHQWUXDGXQ ULGHQXPHUHDF URUVXP HVWHPDLPLF GH (1111), caz în care

transportul C3=0, respectiv mai mare de 15.
O6FKHPDGLQILJDFRPSOHWDW FXQXP UXOSLQLORUUHVSHFWLYL
4.2. Tabelul 7.1;

6FKHPDGLQILJPRGLILFDW úLFRPSOHWDW FXQXP UXOSLQLORUUHVSHFWLYL
4.4. Tabelul 7.2;

([HPSOHFRQFUHWHGHRSHUD LLGHDGXQDUHDGRX QXPHUHGHFkWHEL LD
F URUVXP HVWHPDLPLF GHUHVSHFWLYPDLPDUHGH
2EVHUYD LLSHUVRQDOHDOHVW udentului.
46
LUCRAREA NR. 8
CONVERTOARE DE COD
/6FRSXOOXFU ULL
/XFUDUHDvúLSURSXQHVLQWHWL]DUHDXQXLFRQYHUWRUGHFRGGLQFRGELQDUQDWXUDOvQ
FRGELQDUUHIOHFWDW*UD\úLDXQXLFRQYHUWRUGHFRGGLQFRGELQDUUHIOHFWDW*UD\
în cod binar natural.
*HQHUDOLW L
Convertorul de cod este un c.l.c. care permite transformarea unui cod binar în
altul.
6FKHPDEORFDXQXLFRQYHUWRUGHQPEL LHVWHSUH]HQWDW vQILJ
)LJ6FKHPDEORFJHQHUDO DXQXLFR nvertor de cod 2.2.
2.2. Convertorul de cod din cod binar natural în cod (Gray)
6FKHPDEORFDXQXLFRQYHUWRUSHEL LGLQFRGELQDUQDWXUDOvQFRG*UD\VHRE LQH
GLQILJOSHQWUXQ P úLHVWHSUH]HQWDW vQILJ
'XS FXPUH]XOW úLGLQWDEHOXOGHDGHY UWDEFRGXOELQDUUHIOHFWDW*UD\VH
RE LQHGLQFRGXOELQDUQDWXUDODVWIHO
G0 -UHSHW SULPHOHORFD LLDOHOXL%0GXS FDUHVHUHIOHFW GLQvQORFD LL
G1 - repHW SULPHOHORFD LLDOHOXL%1GXS FDUHVHUHIOHFW GLQvQORFD L i;
47
G2 -UHSHW SULPHOHORFD LLDOHOXL%2GXS FDUHVHUHIOHFW GLQvQ
ORFD LL
G3 -UHSHW %3 .
Fig. 8.2. Schema bloc a convertorului de cod "binar natural - Gray"
7DE7DEHOXOGHDGHY UDOFRQYHUWRUXOXLGHFRGELQDUQDWXUDO - Gray"
Binar natural Gray

B3 B2 B1 B0 G3 G2 G1 G0
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 1
0 0 1 1 0 0 1 0
0 1 0 0 0 1 1 0
0 1 0 1 0 1 1 1
0 1 1 0 0 1 0 1
0 1 1 1 0 1 0 0
1 0 0 0 1 1 0 0
1 0 0 1 1 1 0 1
1 0 1 0 1 1 1 1
1 0 1 1 1 1 1 0
1 1 0 0 1 0 1 0
1 1 0 1 1 0 1 1
1 1 1 0 1 0 0 1
1 1 1 1 1 0 0 0
Pornind de la tab. 8.1, DOF WXLPGLDJUDPHOH9.SHQWUX*3 . G2, G1, si G0. fig. 8.3.
'XS PLQLPL]DUHRE LQHPXUP WRDUHOHH[SUHVLL
G3 = B 3,
G2 = B2 ⊕ B3,
G1 = B1 ⊕ B2 (8.1.)
G0 = B0 ⊕ B1
48
DF URULPSOHPHQWDUHFRQGXFHODVFKHPDGLQILJ
B1B0 00 01 11 10 B1B0 00 01 11 10
B3B2 B3B2
00 00
01 01 1 1 1 1
11 1 1 1 1 11
10 1 1 1 1 10 1 1 1 1
G2 = B 2 B3 + B2 B 3
G3=B3
= B2 ⊕ B3
a) b)
B1B0 00 01 11 10 B1B0 00 01 11 10
B3B2 B3B2
00 1 1 00 1 1
01 1 1 01 1 1
11 1 1 11 1 1
10 1 1 10 1 1
1
G1 = B 1 B2 + B1 B 2 G0 = B 1 B0 + B1 B 0
= B1 ⊕ B2 = B0 ⊕ B1
c) d)
)LJ'LDJUDPHOH9.FRUHVSXQ] WRDUHIXQF LLORUGHLHúLUHDOHFRQYHUWRUXOXL
)LJ6FKHPDORJLF PLQLPDO DFRQYHUWRUXOXLGHFRGELQDUQDWXUDO - Gray"
49
2.3. Convertor de cod "Gray - binar natural"
SchePDEORFDXQXLFRQYHUWRUGLQFRG*UD\vQFRGELQDUQDWXUDOHVWHSUH]HQWDW vQ
ILJLDUWDEHOXOGHDGHY UvQWDE
Cod binar
natural
Cod binar
reflectant.
Fig. 8.5. Schema bloc a convertorului de cod "Gray - binar natural"
Tab. 8.2. 7DEHOXOGHDGHY UDOFRQYHUWRUXOXLGHFRG*UD\ - binar natural"
Gray Binar natural

G3 G2 G1 G0 B3 B2 B2 B1
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 1
0 0 1 1 0 0 1 0
0 1 0 0 0 1 1 1
0 1 0 1 0 1 1 0
0 1 1 0 0 1 0 0
0 1 1 1 0 1 0 1
1 0 0 0 1 1 1 1
1 0 0 1 1 1 1 0
1 0 1 0 1 1 0 0
1 0 1 1 1 1 0 1
1 1 0 0 1 0 0 0
1 1 0 1 1 0 0 1
1 1 l 0 1 0 1 1
1 1 1 1 1 0 1 0
Întrucât aplicarea procedului de la punctul 2.2 HVWHGHVWXOGHODERULRDV apeO POD

XUP WRUXODUWILFLXFXQRVFXWIXQGIDSWXOF $ ⊕ A ⊕ % %FDOFXO Pcu ajutorul
UHOD LLORUXUP WRDUHOHVXPHPRGXOH2:
G2 ⊕ G3 , G1 ⊕ G2 ⊕ G3 siG0 ⊕ G1 ⊕ G2 ⊕ G3 (8.2.)
50
2E LQHP*3 =B3; =>B3=G3;
G 2 ⊕ G 3 = B2 ⊕ B3 ⊕ B3 =>B1=G2 ⊕ G3;

0
G 1 ⊕ G 2 ⊕ G3 = B1 ⊕ B2 ⊕ B2 ⊕ B3 ⊕ B3 => B1 = G1 ⊕ G2 ⊕ G3 (8.3)

0 0
G 0 ⊕ G 1 ⊕ G 2 ⊕ G3 = B0 ⊕ B1 ⊕ B1 ⊕ B2 ⊕ B2 ⊕ B3 ⊕ B3

0 0 0
=> B0 = G0 ⊕ G1 ⊕ G 2 ⊕ G3 .
,PSOHPHQWDUHDUHOD LLORUFRQGXFHODFLUFXLWXOGLQILJ
+Vcc
Fig. 8.6. SchHPDORJLF DFRQYHUWRUXOXLGHFRG*UD\

- binar natural"
Pentru implementarea convertoarelor prezentate la punctele 2.2 úLVHYDIRORVL

SODWIRQQDGHODERUDWRUúLFLUFXLWXOLQWHJUDW&'%SUH]HQWDWvQILJ$-
DQH[
3.1. Studiul convertorului de cod "binar natural" - "Gray"
6HFRPSOHWHD] ILJFXQXPHUHOHSLQLORUFLUFXLWXOXLLQWHJUDW&'%
fig. A. 13 -DQH[ LQFOXVLYSLQLLGHDOLPHQWDUHDL&,
6HLPSOHPHQWHD] FRQYHUWRUXOGLQILJSH]RQDFXVR cluri de CI a

platformei.
36HFRQHFWHD] LQWU ULOH%3,. B2, B1, B0 aOHFRQYHUWRUXOXLODLHúLULOH$3 (B-7),
A2 (B-6). A1 (B-5), A0 (B-4) ale DF1SXVvQUHJLPGHQXP U WRUFRPDQGDWGH
)70YOXFUDUHDQUO,HúLULOHFRQYHUWRUXOXL*3, G2, G1, G0 se coQHFWHD] OD%6
EL LL&3. C2, C1úL&0.
51
6HYHULILF WDESHQWUXWRDWHFRPELQD LLOHFRGXOXLELQDUQDWXUDO
3.2. Studiul convertorului de cod "Gray - binar natural"
3.2.1. Se compleWHD] ILJFXQXPHUHOHSLQLORUFLUFXLWXOXLLQWHJUDW&'%

fig. A. 13, inclusiv pinii de alimentare ai CI.
6HLPSOHPHQWHD] FRQYHUWRUXOGLQILJSH]RQDFXVRFOXULGH&,D
platformei.
6HFRQHFWHD] LQWU ULOH*3 , G2, G1; G0 ale conYHUWRUXOXLODLHúLULOH$3 (B-7),
A2 (B-6), A1 (B-5), A0 (B-4) ale DF1SXVvQUHJLPGHQXP U WRUFRPDQGDWGH
)70YOXFUDUHDQU,HúLULOHFRQYHUWRUXOXL%3, B2, B1, B0VHFRQHFWHD] OD%6
EL LL&3, C2, C1úL&0.
6HDOLPHQWHD] FLUFXLWHOHSODWIRUPei de la sursa de 5V.
6HYHULILF WDESHQWUXWRDWHFRPELQD LLOHFRGXOXL*UD\
4.2. Tabelul 8.1;

6FKHPDGLQILJFRPSOHWDW FXQXP UXOSLQLOR r respectivi;
4.4. Tabelul 8.2;
52
LUCRAREA NR. 9
CIRCUITE DE CODIFICARE
1. 6FRSXOOXFU ULL
/XFUDUHDvúLSURSXQHVLQWHWL]DUHDXQXLFRGLILFDWRUGHDGUHV VLPSOX
2.1. GenerDOLW L
&RGLILFDWRUXOHVWHXQFOFFXQLQWU ULúLPLHúLULGHDGUHV 6FKHPDEORFDXQXL
FRGLILFDWRUHVWHSUH]HQWDW vQILJO
)LJ6FKHPDEORFJHQHUDO DXQXLFRGLILFDWRU
2.2. &RGLILFDWRUXOGHDGUHV VLPSOX
Codificatorul de adrHV VLPSOXIXUQL]HD] ODLHúLUHXQFXYkQWELQDUGHPEL L
DWXQFLFkQGQXPDLXQDGLQFHOHQLQWU ULDOHVDOHHVWHDFWLYDW
m
'HFLQXP UXOFXYLQWHORUIXUQL]DWHHVWHQHJDOFXQXP UXOGHLQWU ULFXQ -l.
Codificatoarele constituie de fapt subsisteme ale unor circuite integrate M.S.I. sau
L.S.I. cum ar fi: convertoarele de cod, circuitele ROM, PLA, etc.
ÎQOXFUDUHVHYDVLQWHWL]DXQFRGLILFDWRUGHDGUHV FXLQWU ULGHFLFXYkQWXOGH
DGUHV YDILIRUPDWGLQEL LQ P
3RUQLQGGHODWDEHOXOGHDGHY UWDEVHGHGXFH[SUHVLLOHIXQF LLORUGHLHúLUHúL
VHRE LQHYDULDQWDGHLPSOHPHQWDUHGLQILH
53
7DE7DEHOXOGHDGHY UDOFRGLILFDWRUXOXLGHDGUHV
,175 5, ADRESE
I1 I2 I3 I4 I5 I6 I7 A2, A1 A0
1 0 0 0 0 0 0 0 0 1
0 1 0 0 0 0 0 0 1 0
0 0 1 0 0 0 0 0 1 1
0 0 0 1 0 0 0 1 0 0
0 0 0 0 1 0 0 1 0 1
0 0 0 0 0 1 0 1 1 0
0 0 0 0 0 0 1 1 1 1
A0 = I1 + I3 + I5 + I7 (9.1)
A1 = I2 + I3 + I6 + I7 (9.2)
A0 = I4 + I5 + I6 + I7 (9.3)
)LJ6FKHPDORJLF DFRGLILFDWRUXOXLGHDGUHV
2EVHUYD LHHVWHLQWHU]LV DFWLYDUHDVLPXOWDQ DPDLPXOWRUOLQLLGHLQWUDUH
deoarece se pot crea confuzii. De exemplu, aFWLYDUHDVLPXOWDQ DOLQLLORU,1úLI2

JHQHUHD] FXYkQWXOGHFRG$2=0, A1=l, A0=l (011) care corespunde de fapt, într-o
IXQF LRQDUHQRUPDO DFWLY ULLOXL,3.
ÎQFD]XOvQFDUHQXVHSRDWHHYLWDDFWLYDUHDVLPXOWDQ DPDLPXOWRULQWU ULVH

folosesc circuite de codificare (codare) prioritare.
2DOW YDULDQW GHLPSOHPHQWDUHD&'FXLQWU ULúLLHúLULGHDGUHV VHSRDWH
RE LQHDSOLFkQGUHOD LLORUúLSULQFLSLXOGXEOHLQHJD LLúLXQDGLQ
54
UHOD LLOHOXL'H0RUJD
(9.1)
A0 = I1 + I 3 + I 5 + I 7 = I 1 I 3 I 5 I 7
(9.2)
A1 = I 2 + I 3 + I 6 + I 7 = I 2 I 3 I 6 I 7 (9.3)
A2 = I 4 + I 5 + I 6 + I 7 = I 4 I 5 I 6 I 7
6HRE LQHVFKHPD
)LJ2DOW YDULDQW GHLPSOHPHQWDUHDFRGLILFDWRUXOXLGHDGUHV
Pentru implementarea codificatorului prezentat în fig. 9.3 se va folosi platforma

de laERUDWRUúLFLUFXLWXOLQWHJUDW&'%-DQH[ $
6HFRPSOHWHD] VFKHPDGLQILJFXQXPHUHOHSLQLORUFLUFXLWHORULQWHJUDWH
utilizate (3 x CDB 413).

6HLPSOHPHQWHD] FRGLILFDWRUXOSH]RQDFXVRFOXULGH&,D
platformei.
3.6HFRQHFWHD] LQWU ULOH I 1 , I 2 ,....., I 7 DOHFRGLILFDWRUXOXLODLHúLULOH Y 0 (B-37),
Y 1 (B-38), ..., Y 6 (B-43) ale decodificatorului de pe placheta-
PXOWLIXQF LRQDO YILJ 1.8, lucrarea nr.YL]XDOL]DUHDLQWU ULORU
I1 , I 2 ,....., I 7 HVWHUHDOL]DW GHF WUH%6&0, C1 ..., C6,HúLULOH$0, A1úL$2 ale
55
FRGLILFDWRUXOXLVHFRQHFWHD] OD%6'0 , D1úL').
6HDOLPHQWHD] FLUFXLWHOHSODWIRUPHLGHODERUDWRUGHODVXU sa de 5V.
6HYHULILF WDE LQkQGVHDPDGHIDSWXOF WRDWHYDORULOHORJLFHGLQ
UXEULFLOHFHFRUHVSXQGLQWU ULORUVXQWLQYHUVDWH
4. l. Schema din fig 9.3 completata cu numarul pinilor respectivi.

4.2. Tabelul 9.l modificat pentru schema din fig.9.3.
scnema bloc de testare a codificatorulu , obtinuta prin modificarea fig. 1.8
(lucrarea nr. 1) îQFRQFRUGDQW FXREVHUYDWLOH de la punctul 3.3;
2EVHUYD Lpersonale ale studentului.
56
LUCRAREA NR. 10
CIRCUITE DE DECODIFICARE
1. 6FRSXOOXFU ULL
/XFUDUHDvúLSURSXQHVLQWHWL]DUHDXQXLGHFRGLILFDWRUGHDGUHV úLVWXGLHUHD
decodificatoarelor integrate BCD -]HFLPDO&'%úL%&'- 7 segmente

(CDB 447).
*HQHUDOLW L
DecodLILFDWRUXOHVWHXQFOFFXQLQWU ULúLPLHúLULUHDOL]DWvQWHKQRORJLH06,
FDUHDFWLYHD] XQDVDXPDLPXOWHLHúLULvQIXQF LHGHFXYkQWXOGHFRGDSOLFDWOD
intrare (m=2n).
6FKHPDEORFDXQXLGHFRGLILFDWRUHVWHSUH]HQWDW vQILJO
Fig.6FKHPDEORFJHQHUDO DXQXLGHFRGLILFDWRU
2.2. 'HFRGLILFDWRUXOGHDGUHV
'HFRGLILFDWRUXOGHDGUHV DFWLYHD] OLQLDGHLHúLUHDF UHLDGUHV FRGLILFDW ELQDU
HVWHDSOLFDW ODLQWU UL
Exemplu: n = LQWU ULP 2 = LHúLUL

Schema bloc a unui decoGLILFDWRUGHDGUHV FXLQWU ULVLLHúLULHVWHSUH]HQWDW
în fig. 10.2.
'LQWDEHOXOGHDGHY UWDEVHRE LQH[SUHVLLOHIXQF LLORUGHLHúLUHúL
57
varianta de implementare din fig. 10.3.
)LJ6FKHPDEORFDXQXL'&'FXLQWU ULúLLHúLUL
7DEO7DEHOXOGHDGHY UDO'&' XOXLFXLQWU ULVLLHúLUL

-
A1 A0 Y0 Y1 Y2 Y3
0 0 1 0 0 0
0 1 0 1 0 0
1 0 0 0 1 0
1 1 0 0 0 1
Y0 = A1 A 0 ; Y1 = A1 A0 ; Y2 = A1 A 0 ; Y3 = A1 A0 (10.1)
)LJ6FKHPDORJLF D'&' XOXLFXLQWU ULúLLHúLUL

-
2.3. Decodificatorul BCD-zecimal
3UHVFXUWDUHD%&'VHPQLILF ]HFLPDOFRGDWELQDU
Schema bloc a unui decodificator BCD-]HFLPDOHVWHSUH]HQWDW vQILJ

Spre deosebire de codXOELQDUQDWXUDO%&'QXLQFOXGHFRPELQD LLOHELQDUH
58
1011, 1100, 1101, 1110. 11 11FRPELQD LLFHFRUHVSXQGQXPHUHORU
]HFLPDOHúL5.
Fig. 10.4. schema bloc a DCD-ului BCD – zecimal
Aparitia orcareia din cele 6 combinatii de intrare excluse, duce toate iesirile nin
starea „1”.
Se spune ca decodificatorul rejecteza datele false.
)XQFWLRQDUHDGHFRGLILFDWRUXOXLGLQILJLQYDULDQW integrata – CDB 442) este
descrisa de tab 10.2 (identic cu tab.1.3, lucrarea nr.1).
TaE7DEHOXOGHDGHY UDO'&' -ului BCD - zecimal
A3 A2 A1 A0 Y0 Y1 Y 2 Y3 Y4 Y5 Y6 Y7 Y8 Y9
0 0 0 0 0 1 l 1 1 1 1 l 1 1
0 0 0 1 1 0 1 1 1 1 1 1 1 1
0 0 1 0 1 1 0 1 1 1 1 1 1 1
0 0 1 1 1 1 1 0 1 1 1 1 1 1
0 1 0 0 1 1 1 1 0 1 1 1 1 1
0 1 0 1 1 1 1 1 1 0 1 1 1 1
0 1 1 0 1 1 1 1 1 1 0 1 1 1
0 1 1 1 1 1 1 1 1 1 1 0 1 1
1 0 0 0 1 1 1 1 1 1 1 1 0 1
1 0 0 1 1 1 l 1 1 1 1 1 1 0
1 0 1 0 l 1 1 1 1 1 1 1 1 1
1 0 1 1 1 1 1 1 1 1 1 1 1 1
1 1 0 0 1 1 1 1 1 1 1 1 1 1
1 1 0 1 1 1 1 1 1 1 1 1 1 1
1 1 1 0 1 1 1 1 l 1 1 1 1 1
1 1 1 1 l 1 1 1 1 1 1 1 1 1
2.4. Decodificatorul BCD - 7 segmente
Dccodificatorul BCD - 7 segmente integrat (CDB 447) preziQW VFKHPDEORFGLQ
ILJDFFHSW XQFRGGHLQWUDUH%&'úLSURGXFHLHúLULOHDGHFYDWHSHQWUX
59
selectarea segmentelor unui digit cu 7 segmente utilizat pentru
reprezentarea numerelor zecimale 0, 1,..,9.
Fig. 10.5. schema bloc a unui DCD BCD – 7 segmente
Cele 7 iesiri ( a, b, c, d , e, f , g ) ale decodificatorului, active in stare „jos” ,

selecteza elementele corespunzatoare ale display-ului cu 7 segmente reprezntat in
fig. 10.6a.
a) modul de notare al segmentelor b) modul de conectare a LED-urilor
Fig. 10.6. Display-ul cu 7 segmente cu anod comun
Display-ul este format din 7 LED-XULDúH]DWHvQVSDWHOHIDQWHORUFDUHUHSUH]LQW
VHJPHQWHOHúLFRQHFWDWHHOHFWULFGHPDQLHUDGLQILJE
Modul de formare al numerelor zecimale 0, 1, ..., 9 cu ajutorul celor 7 segmente

este prezentat în fig. 10.7.
10.7. Formarea cifrelor zecimale cu ajutorul celor 7 segmente
60
6FREVHUY F VHJPHQWHOHDFWLYDWHvQFD]XOFRPELQD LLORUORJLFHGHLQWUDUH
interzise în BCD (ce corespund numerelor zecimale 10, 11, ..., 15), nu au practic
QLFLRVHPQLILFD LH
Tabelul de aGHY UDOGHFRGLIOFDWRUXOXL%&' - 7 segmente integrat CDB 447 este

tab. 10.3.
7DE7DEHOXOGHDGHY UDO'&'%&' -7 segmente CDB 447

ZECIMAL ,175 5, ,(ù,5,
SAU
)81& ,$
LT RBI A3 A2 A1 A0 BI / RBO(b) a b c d e f g
0 1 l 0 0 0 0 1 0 0 0 0 0 0 1
1 1 x 0 0 0 1 1 1 0 0 1 1 1 1
2 1 x 0 0 1 0 1 0 0 1 0 0 1 0
3 1 x 0 0 1 1 1 0 0 0 0 1 1 0
4 1 x 0 1 0 0 1 1 0 0 1 1 0 0
5 1 x 0 1 0 1 1 0 1 0 0 1 0 0
6 1 x 0 1 1 0 1 1 1 0 0 0 0 0
7 1 x 0 1 1 1 1 0 0 0 1 1 1 1
8 1 x 1 0 0 0 1 0 0 0 0 0 0 0
9 1 x 1 0 0 1 1 0 0 0 1 1 0 0
10 1 x 1 0 1 0 1 1 1 1 0 0 1 0
11 1 x 1 0 1 1 1 1 1 0 0 1 1 0
12 1 x 1 1 0 0 1 1 0 1 1 1 0 0
13 1 x 1 1 0 1 1 0 1 1 0 1 0 0
14 1 x 1 1 1 0 1 1 1 1 0 0 0 0
15 1 x 1 1 1 1 1 1 1 1 1 1 1 1
BI (b) x x x x x x 0 1 1 1 1 1 1 1
RBI (b) 1 0 0 0 0 0 0 1 1 1 1 1 1 1
LT (b) 0 x x x x x 1 0 0 0 0 0 0 0
Nota (b):
BI / RBO (Blanking Input / Ripple Blanking Output);
BI -vQDHUVDXODOGDF GRULPIXQF LLOHGHLHúLUH-^-15;
RBI -vQDHUVDXODOGDF DILúDUHDOXL2QXHVWHGRULW
LT (Lamp Test Input).
61
Pentru implementarea decodiflcatorului de DGUHV úLVWXGLHUHDGHFRGLILFDWRDUHORU
integrate BCD-]HFLPDOúL%&'-VHJPHQWHSXQFWHOHúLVHYDIRORVL
SODWIRUPDGHODERUDWRUúLFLUFXLWHOHLQWHJUDWH&'%
&'%&'%úL&%' DQH[ ILJ$$$úL$

-
3.1. ImplemenWDUHDGHFRGLIOFDWRUXOXLGHDGUHV
6HFRPSOHWHD] FLUFXLWXOGLQILJFXQXPHUHOHSLQLORU
circuitelor integrate utilizate (A.2, A.3), inclusiv pinii de alimentare.

6HLPSOHPHQWHD] GHFRGLILFDWRUXOGLQILJSH]RQDFXVRF luri de CI a
platformei.
6HFRQHFWHD] LQWU ULOH$0 , A1 ale decodiflcatorulXLODLHúLULOHVLPLODUHDOH
DF1SXVvQUHJLPGHQXP U WRUFRPDQGDWFX)70,HúLULOHGHFRGLIOFDWRUXOXLVH
FRQHFWHD] OD%6EL LL&0, C1, C2úL&3.
O6HDOLPHQWHD] FLUFXLWHOHSODWIRUPHLGHODVXUVDGH96HYHULILF
tab. 10.1.
3.2. Studiul decodiflcatorului BCD – zecimal
6HUHDOL]HD] PRQWDMXOGLQILJOXFUDUHDQU
6HYHULILF WDE
3.3. Studiul decodiflcatorului BCD - 7 segmente
6HFRQHFWHD] LHúLULOH$0 (B-4), A1 (B-5), A2 (B-úL$3 (B-7) ale DF1 pus
vQUHJLPGHQXP U WRUFRPDQGDWSULQ)70ODLQWU ULOH$0 (7), A1 (1), A2úL$3
DOH&'%,HúLULOH a (13), b (12), c (ll), d (10), e (9), f úL g (14)
DOHFLUFXLWXOXLLQWHJUDW&'%VHFRQHFWHD] ODWHUPLQDOHOHFRUHVSXQ] WRDUH
ale digitului cu 7VHJPHQWHúLDQRGFRPXQ

6HFRQHFWHD] FLUFXLWXOLQWHJUDWúLGLVSOD\ -ul cu 7 segemente la bornele de
alimentare ale sursei de 5V.
6HYHULILF IXQF LRQDUHDGHFRGLIOFDWRUXOXLXUP ULQGWDEúLILJ
4. &RQ LQXWXOUHIHUDWXOXL
O6FKHPDGLQILJFRPSOHWDW FXQXP UXOSLQLORUUHVSHFWLYL
4.2. Tabelul 10.1;

4.4. Tabelul 10.2;
6FKHPDGHFRQH[LXQLSHQWUXYHULILFDUHDIXQF LRQ ULLGHFRGL flcatorului BCD -
VHJHPHQWHUHDOL]DW vQWU RPDQLHU DVHP Q WRDUHVFKHPHLGLQILJO
-
62
)LJXULOHúL
4.7. Tabelul 10.3;

63
LUCRAREA NR. 11
POARTA TTL67$1'$5'$1$/,=$67$7,&
/6FRSXOOXFU ULL
/XFUDUHDvúLSURSXQHVWXGLHUHDGLQSXQFWGHYHGHUHVWDWLFDSRU LL77/
standard: poarta NAND (1/4 CBD400, fig. A. l -DQH[ SULYLW FDLQYHUVRU
2.Aspecte teoretice
*HQHUDOLW L
Poarta NAND-TTL pre]LQW VFKHPDGLQILJO a, simbolul logic din fig. 11.1b

úLWDEHOXOGHDGHY U- tab. 11.1.
+Vcc(5V)
b) simbol
a) schema
Fia. 11.1. Poarta NAND - TTL

Diodele D1úL'2SURWHMHD] WUDQ]LVWRUXOmultiemiter T1 împotriva
64
HYHQWXDOHORUWHQVLXQLQHJDWLYHFHSRWDS UHDSHLQWU ULvQWLPSXOUHJLPXULORU
tranzitorii. ÎQUHJLPVWD LRQDUHOHQXDXQLFLXQIHOGHLPSRUWDQ PRWLYSHQWUX
care vor fi ignorate în continuare.
Tab. L11O7DEHOXOGHDGHY UDOSRU LL1$1'
B A Y
0 0 1
0 1 1
1 0 1
1 1 0
Tranzistorul multiemiter T1DVLJXU FXUHQWXOGHED] QHFHVDUWUDQ]LVWRUXOXL

defazor T2FDUHFRPDQG HWDMXOILQDOGHWLSWRWHPSROHvQFRQWUDWLPSUHDOL]DW
cu tranzistoarele T3úL74. Acest tip de etaj final permiteRE LQHUHDXQRUWLPSLGH
SURSDJDUHUHGXúLRFUHVWUeHDLPXQLW LLODSHUWXUED LLDSRU LLúLRVF GHUHD
rezisWHQ HLGHLHúLUHDDFHVWHLD vQVWDUH/úL în stare "H").
)XQF LRQDUH
ÎQORFXLQGMRQF LXQLle tranzistorului multiemiter T1 cu diode, schema din fig. 11. l

DVHWUDQVIRUP GHPDQLHUDGLQILJ.2.
+Vcc(5V)
1.2. 2VFKHP PDLLQWXLWLYDDSRU LL1

$1' – TTL
65
6HREVHUY XúRUF circuitul din fig. 11.2. este format dintr-XQùO-pasiv
(realizat de diodele DBE11, DBE12úLUH]LVWHQ DR1, urmat de un inversor (realizat cu
tranzistoarele T2, T3úL74).
Într-DGHY UH[FHSWkQG'BC1FDUHDUHUROGHGHSODVDUHGHQLYHOYIDPLOLD'7/úL
rHDPLQWLQGIDSWXOF VHPQDOXOGLQFROHFWRUXOXQXLWUDQ]LVWRUHYROXHD] vQDQWLID]
ID GHFHOGLQED] úLHPLWHUREVHUY PF RFUHúWHUHDQLYHOXOXLVHPQDOXOXLGLQ
B2YDDQWUHQDRVF GHUHDQLYHOXOXLvQ%4úL- implicit -vQ<VLPXOWDQFXRFUHúWHUH

a nivelului în B3úLRVF GHUHDDFHVWXLDvQ<&RQFOX]LRQkQGFUHúWHUHDQLYHOXOXL
în B2FRQGXFHODRVF GHUH-SHGRX F L- a nivelului în Y, inversarea semnalului
ILLQGHYLGHQW
)XQF LDù, 181$1'DFLUFXLWXOXLILLQGGHPRQVWUDW WDEHOXOGHDGHY U

-
este verificat.
ÎQFHOHFHXUPHD] QHSURSXQHPWUDQVIRUPDUHDFLUFXLWXOXL1$1'vQWU-un
inversor (prin conectarea la +VCCDERUQHLGHLQWUDUH%úLH[SOLFDUHDIXQF LRQ ULL
inversorului în paralel cu ridicarea caracteristicii de transfer a acestuia, fig. 11.3.
(3 ) (4)
V1[V]
0 0,5 1,1 1,7
Fig. 11.3. Caracteristica de transfer a inversorului TTL
Starile tranzistoarelor in fiecare din zonele (1) .... (4), fig. 11.3. le vom centraliza
in tabelul 11.2.
7DE&HQWUDOL]DWRUDOVW ULORUWUDQ]LVWRDUHORUvQWLPSXOFRPXWD LHL
Zona \ Trz. TI 72 T3 T4
(D Sat. Bl. Bl. Sat.
(2) Sat. RAN Bl. RAN
(3) Sat. RAN RAN RAN
(4) RAI Sat. Sat. Bl.
66
ÎQH[SOLFDUHDIXQF LRQ ULLVFKHPHLGLQPRWL ve de simplificare a expunerii, vom
OXDvQFRQVLGHUD LHXUP WRDUHOHYDORUL
VBEon = 0,6V - pentru un tranzistor în RAN;

VBEsat = 0.7V -SHQWUXXQWUDQ]LVWRUvQVDWXUD LH
VCEsat = 0,1 V -SHQWUXXQWUDQ]LVWRUvQVDWXUD LH
VD = 0,7V -SHQWUXRGLRG vQFRQGXF LH
([SOLFDUHDIXQF LRQ ULLLQYHUVRUXOXLQHFHVLW OXDUHDvQFRQVLGHUD LHDXUP WRDUHORU
zone:
Zona.(l): 0<V1<0,5. (11.1)
DBE11HVWHSRODUL]DW GLUHFWSULQ51GHF WUHGLIHUHQ DGHSRWHQ LDO9CC-V1 întrucât
DBE11 cRQGXFHSRWHQ LDOXOSXQFWXOXL%1 va fi:
' VB1=VI + VBE11 sat = V1 + 0,7. (11.2)
LQkQGVHDPDGHUHOD LLOHúLORE LQHP
0,7 <VBC <1,2 (11.3)

úLvQWUXFkW
VB1 - VBC1 + VBE2 + R2IE2, (11.4)

SXWHPVFULHF
0,7<VBC1+VBE2 + R2IE2<1,2. (11.5)

5H]XOW F MRQF LXQLOH%&1úL%(2YRUILVXSXVHILHFDUHFkWHXQHLGLIHUHQ HGH
SRWHQ LDO9BC1 = VBE2 < 0,6, iar tranzistorul T1VHYDDIODvQVLWXD LD

prezentat vQILJ
)LJ([SOLFDWLY SHQWUXVWDUHDWUDQ]LVWRUXOXL71
úLDQXPH
VCE1 = VBE11 - VBC1 (11.6)

deci:
0,1 <VCE1<0.35, (11.7)
úL71 este saturat.
Tranzistorul T2 este blocat deoarece VBE2 < 0,6V.

Tranzistorul T3 este blocat deoarece VBE3 = R2I2: = 0.
Tensiunea V0 (1)SRDWHILHYDOXDW GLQILJRE LQXW GLQILJ2 prin
eliminarea tranzistoarelor T1 (neinteUHVDQWúL72. T3 (blocate).
Putem scrie:
V0 (1) = VCC-R3IB4-VBE4-VD. (11.8)
67
Neglijând termenul R3IB4 (IB4~RE LQHP
V0(1) = VCC- VBE4-VD = 5 - 0,7 - 0,7 = 3,6V. (11.9)
Având VBE4 9úLOXFUkQGvQUHJLPGHUHSHWRU74 - saturat.
)LJ([SOLFDWLY SHQWUX]RQD
Zona (2): 0,5 < V1 < 1,1. (11.10)

'LQUHOD LDORE LQem:
1,2<VB1<1,8. (11.11)
3RWHQ LDOXOSXQFWXOXL%1HVWHVXILFLHQWSHQWUXDGHVFKLGHMRQF LXQLOH%&1
úL%(2GDULQVXILFLHQWSHQWUXDGHVFKLGHúLMRQF LXQHD%(35H]XOW F 73 este

blocat în continuare.
T1DUHDPEHOHMRQF LXQLGLUHFWSRODUL]DWHGHFLHVWHVDWXUDW
T2DUHMRQF LXQHD%(2GLUHFWúLVXILFLHQWSRODUL]DW
VB2 = VBI-VBC1=VB1-0,6, (11.12)
úL LQkQGVHDPDGHUHOD LLOHOúLOSXWHPGHGuce:
VB2=V1+0,7-0,6= V1+0,1 (11.13)

deci
0,6<VB,< 1,2. (11.14)
Eliminând din schema din fig. 11.2 tranzistoarele T1QHLQWHUHVDQWúL73 (blocat),
(2)
RE LQHPVFKHPDGLQILJXUDFXDMXWRUXOF UHLDvOSXWHPFDOFXODSH V0
V0(2)= Vcc – R3IC2 - VBE4 - VD. (11.15)

IC2 § N2; IE2 = N2(VB2-VBE2)/R2 (11.16)
(2)
V0 = VCC - N2(VB2-VBE2)/R3 /R2- VBE4 – VD. (11.17)
VDXGDWRULW UHOD LHL
V0(2) = VCC - N2(V1+ O, l - VBE2)R3/R2 – VBE4 - VD. (11.18)

Al GRLOHDWHUPHQGLQPHPEUXOGUHSWDOUHOD LHLUHSUH]LQW F GHrea de
WHQVLXQHSHUH]LVWHQ D53:
68
VR3 = N2(V1 + 0,1 - VBE2)R3/R2. (11.19)
)LJ([SOLFDWLY SHQWUX]RQD
Starea tranzistorului T2GHSLQGHGHGLIHUHQ DGHSRWHQ LDO

VBC2=VB2-VB4=VB2-(VCC-VR3) (11.20)
DF UHLYDORDUHPD[LP VHGHWHUPLQ DVWIHO
VBC2max = VB2max (Vcc-VR3max)= l,2 - (5-l) < 0. (11.21)

în calculul lui VR3max, rel (11.19), am considerat N2 §91 = 1,1 V si VBE2 =
0.6V.
5H]XOW F 72VHDIO în.RAN.
Procedând similar pentru T4:

VBC4 = VB4-VCC = VCC-VR3-VCC<0, (11.22)
deci T4VHDIO -în RAN.
&DOFXO P90 cu rel. (11.18) Ia limita din stânga a intervalului 11.3, când V1 =
0,5V, VBE2 = 0,6V, VBE4 = VD 9úLRE LQHP

V0(2B) = 5 - N2(0,5 + 0,1 - 0,6)R3/R2 - 0,7 - 0,7 = 3,6V, (11.23)
FHHDFHFRQILUP UH]XOWDWXORE LQXWDQWHULRUUHOD LD
Pentru limita din dreapta a intervalului (2), în UHOD LDOVHYDORULOH
V1 = l, l V VBE2 = 0,6V, VBE4 = 0,6V, rezultând:
V0(2C) = 5-1,6(1,1+0,1- 0,6) - 0,6 - 0,7 = 2,7V. (11.24)
$úDFXPVHREVHUY GHIDSWúLGLQUHOD LDvQWUHSXQFWHOH]RQD
FDUDFWHULVWLFDGHWUDQVIHUHVWHOLQLDU úLDUHSDQWD
m2 = - N2 R3/R2 (11.25)
Zona (3): 1,1 < V1 < 1,1 + V , (11.26)
unde V HVWHRWHQVLXQHLQILQLWPLF 5H]XOW
1,8<VB1< 1,8+V . (11.27)
Imediat ce V1GHS úHúWHOO99B2GHS úHúWH9YUHO13), úLVH deschide
69
MRQF LXQHD%(3 a tranzistorului T3. Astfel, în paralel cu R2DSDUHUH]LVWHQ DGH
intrare a lui T3UHOD LDGHYHQLQG
R3
V0 = Vcc − α N 2 (V1 + −0,1 − V BE 2 ) − V BE 4 − V D
( 3)
(11.28)
R2 RinT 3
Panta caracteristicii de transfer în zona (3) este:
m3 = - N2R3/(R2||RinT3), (11.29)
úL LQkQGVHDPDGHIDSWXOF 5lnT3 ≈ 1K ,
m3 ≈ 2m2. (11.30)
Întrucât V0QXSRDWHV VFDG VXEYDORDUHD9CE3sat = O, l V, se poate calcula din
(3D)
UHOD LDOYDORDUHDOXL91 pentru care V0 = VBE3sal5H]XOW 91 = 1,6V.
6W ULOHWUDQ]LVWRDUHORUODvQFHSXWXOLQWHUYDOXOXL, deci pentru 1.1 < V1 < 1,1 +
V VXQW71FDúLvQB]RQDSUHFHGHQW VDWXUDWLDU72úL73DYkQGMRQF LXQLOH%(

vQVHULDWHúLVXSXVHXQHLGLIHUHQ HGHSRWHQ LDO9B2 ≈ 1,2 + V , sunt suficient
SRODUL]DWHSHQWUXDFRQGXFHGDUvQF LQVXILFLHQWSRODUL]DWHSHQWUXDVHVDWXUD
5H]XOW F 72úL T3 se afl vQ5$1
În ceeace-SULYHúWHSH74DFHVWDDUHMRQF LXQHD%(GLUHFWúLVXILFLHQWSRODUL]DW
SRWHQ LDOXl colectorului VC4 ≈ 9PLQLPXP9vQVDUFLQ LDUSRWHQ LDOXO
bazei: VB4 ≈ 95H]XOW F MRQF LXQHD%&DWUDQ]LVWRUXOXL74 este invers

SRODUL]DW úL74OXFUHD] vD5$1
Zona.(4): Luând pentru V1 o valoare cDUHV VHDIOHFXFHUWLWXGLQHvQ]RQD

spre exemplu V1!O9FRQVWDW PF vQWUXFkW9B1QXSRDWHGHS úLYDORDUHD
FRUHVSXQ] WRDUHVDWXUD LHLFHORUMRQF LXQL%&1, BE2, BE3,
VB1max = 3 x O,7V = 2,l V, (11.31)

MRQF LXQHD%(11 a tranzistorului T1YDILLQYHUVSRODUL]DW vQWLPSFHMRQF LXQHD
BC, va fi diUHFWúLVXILFLHQWSRODUL]DW 71 va lucra, prin urmare, în RAI (regiunea

DFWLY LQYHUV
T2úL73 sunt saturate deoarece VBE2 = VBE3 = 0,7V.

Starea lui T4VHHYDOXHD] DVWIHO
VB3=0,7 V (11.32)
VB4=VB3 + VCE2sat = 0,7 +0,1 = 0,8 V (11.33)
V0 = VCE3sat ≈ 0,lV (11.34)
VB4-V0 = 0,8 - 0,1 = 0,7V (11.35)
'LIHUHQ DGHSRWHQ LDO9B4 - V0VHDSOLF MRQF LXQLL%(DWUDQ]LVWRUXOXL74 úLGLRGHL
'ILLQGLQVXILFLHQW SHQWUXDOHGHVFKLGH5H]XOW F 74HVWHEORFDW6HREVHUY F
rolul diodei D este tocmai acela de a asigura blocarea lui T4FkQGLHúLUHDSRU LLVH
DIO vQVWDUHD "L".
70
2.3. Caracteristici statice
2.3.1..Caracteristica de transfer
&DUDFWHULVWLFDGHWUDQVIHUUHSUH]LQW GHSHQGHQ D90 = f(V1úLDUHDVSHFWXOGLQILJ
11.3.
5LGLFDUHDH[SHULPHQWDO DFDUDFWHULVWLFLLGHWUDQVIHULPSXQHFXQRDúWHUHDúL
respectarea nivelurilor logice prezentate în fig. 11.7.
)LJ1LYHOXULOHORJLFHDOHSRU LL77/VWDQGDUG
Astfel,WHQVLXQHDGHLHúLUHDSRU LL31FDUHFRPDQG SRDWHILFHOPXOWVoLmax =

0,4V SHQWUX2ORJLFúLFHOSX LQ9OHmin = 2,4V pentru "l" logic.
Poarta P2FRPDQGDW UHFXQRDúWHGUHSW2ORJLFRULFHWHQVLXQHGHLQWUDUHVLWXDW
sub VILmax 9úLGUHSWOORJLFRULFHWHQVLXQHGHLQWUDUHFDUHGHS úHúWH91Hmin
= 2V.
0DUMHOHGHUHFXQRDúWHUHGHF WUH32 a niveluriloUORJLFHGHODLHúLUHDSRU ii P1 sunt
MH = ML 9úLVHQXPHVFPDUJLQLGH]JRPRW
2.3.2. Caracteristica de intrare
PrezHQW PvQILJGHSHQGHQ D,1 = f(V1).
&RQYHQ LRQDOFXUHQWXOFDUHLQWU vQSRDUW HVWHFRQVLGHUDWSR]LWLYLDUFXUHQWXO
care iese - negativ.

Sensul curentulXLGHLQWUDUHvQIXQF LHGHYDORDUHDDOXL91 este prezentat în fig.
11.9.
Scriind KIISHFLUFXLWXOPDUFDWvQILJDRE LQHP
V − V BE1 − V1L
− I II = CC ≈ 1mA (11.38)
RI
71
Fig. 11.8. Caracteristica de intrare a inversorului
a) cu intrarea în stare "L" b) cu intrarea în stare "H"

)LJ([SOLFDWLY ODFDUDFWHULVWLFDGHLQWUDUHDLQYHUVRUXOXL
/HJkQGvPSUHXQ WRDWHLQWU ULOHOXL71 pentru V1L = 0,4V, valoarea lui I1L nu se

PRGLILF QHSXWkQGV GHS úHDVF vQFHOPDLGHIDYRUDELOFD]_IIL| < l,6mA (v. fig.
11.8).
Pentru V1 9OORJLFYDORDUHDFXUHQWXOXLFDUHVHVWDELOHúWHSULQ73 creúWH
FXQXP UXOLQWU ULORUOXL71FDUHVHOHDJ vPSUHXQ
2EVHUYD LL
1. Valorile negative ale lui V1 sunt limitate la (0,7 ÷ 9GHF WUHGLRGHOH'1,D2

YILJ'HS úLUHD- în regim static - a valoni maxime admise de catalog (-
1,8 V) poate conduce la distrugerea acestor diode;

2. Pentru V1!9DSDUHULVFXOGLVWUXJHULLMRQF LXQLL%(DWUDQ]LVWRUXOXL
PXOWLHPLWHUSULQGHS úLUHDSUDJXOXLGHSRODUL]DUHLQYHUV GH9PDLDOHVvQ
72
FD]XOvQFDUHXQDGLQLQWU ULHVWHFRQHFWDW OD2ORJLF3HQWUXHYLWDUHDXQHL
DVWIHOGHVLWXD LLFRQHFWDUHDXQHLLQWU ULOD9CC se face prin intermediul unei

UH]LVWHQ HPDLPDULGH. .
&DUDFWHULVWLFDGHLHúLUH
ÎQILJHVWHSUH]HQWDWFLUFXLWXOúLFDUDFWHULVWLFDGHLHúLUHSHQWUX90 în starea
"L", iar în fig. 11.11 - pentru V0 în starea "H".
“B1”
a; circuitul b) caracteristica propriu-]LV
)LJ&DUDFWHULVWLFDGHLHúLUHDSRU LL77/VWDQGDUGFXLHúLUHDvQVWDUH/
a) circuitul b) caracteristica propriu-]LV

)LJ&DUDFWHULVWLFDGHLHúLUHDSRU LL77/VWDQGDUGFXLHúLUHDvQVWDUH+
73
3.'HVI úXUDUHDOXFU ULL
Pentru ULGLFDUHDFDUDFWHULVWLFLORUVWDWLFHDOHSRU LL77/VWDQGDUGVHYDXWLOL]D

platformaGHODERUDWRUúLFLUFXLWXOLQWHJUDW&'%ILJ$O-DQH[
3.1. Caracteristica de transfer
6HULGLF SULQSXQFWHFDUDFWHULVWLFDGHWUDQVIHU90 = f(V1ILJDSRU LL

NAND din CI -&'%vQGRX VLWXD LL
-FXLHúLUHDvQJRO
-FXLHúLUHDFRQHFWDW ODVDUFLQL77/
Valorile lui V1VHUHJOHD] vQLQWHUYDOXO>299@FRQIRUPWDEHOXOXL
Tab. 11.3. Tabel pentru ridicarea caracteristicii de transfer
V 1[V] 0 0,2 0,4 0,6 0,8 1 1,2 1,4 1,6 1,8 2 3 4 5

V2IV]
Montajul utilizat este cel prezentat în fig 11.12.
Fig. 11.12. Montaj experimental pentru ridicarea caracteristicii de transfer 3.2.
2.3. Caracteristica de intrare
6HULGLF SULQSXQ cte caracteristica de intrare I1 = f(V1ILJDSRU LL1$1'

din CI -&%'FXFHDODOW LQWDUHODOORJLFvQDHU
Valorile lui V1VHUHJOHD] vQLQWHUYDOXO>295V] conform tab. 1 1.4.
Montajul utilizat este cel prezentat în fig. 11.13.
74
Tab. 11.4. Tabel pentru ridicarea caracteristicii de intrare
V 1[V] 0 0,1 0,2 0,4 0,6 0,8 1,2 1,4 1,6 2 3 4 5

V1[mV]
Fig.11.13.
3.3. &DUDFWHULVWLFLOHGHLHúLUH
3.3.1. Caracteristica VOL= f(IOL)

6HULGLF SULQSXQFWHFDUDFWHULVWLFDGHLHúLUH9OL = f(IOL), fig. 11.10EDSRU LL
NAND din CI - CDB 400, utili]kQGPRQWDMXOGLQILJvQFDUHDPEHOHLQWU UL
DOHSRU LLVXQWODOORJLFvQDHULDULHúLUHDHVWHFRQHFWDW OD2 ÷ 10 sarcini
TTL.
Fig. 11.14. Montaj experimentai pentru ridicarea caracteristicii VOL = f (IOL)
6HFRPSOHWHD] WDEHOXO
75
Tab. 11.5. Tabel pentru ridicarea caracteristicii VOL = f(IOL)
Nr. sarcini
0 2 4 6 8 10
TTL
IOL[mA]
VOL[V]
3.3.2. Caracteristica VOH = f(IOH)

6HULGLF SULQSXQFWHRSDUWHGLQFDUDFWHULVWLFDGHLHúLUH9OH
= f(IOH), fig. 11.11 b,
DSRU LL1$1'GLQ&,- CDB 400, utilizând montajul din fig. 11.15 în care
DPEHOHLQWU ULDOHSRU LLVXQWOD2ORJLFFRQHFWDWHODPDV LDULHúLUHDHVWH
FRQHFWDW OD2 ÷ 10 sarcini TTL.
Fig. 11.15. Montaj pentru ridicarea caracteristicii VOH =f(IOH)

Se completeaza tabelul 11.6.
Tab. 11.6. Tabel pentru ridicarea caracteristicii VOH = f(IOH)
Nr. sarcini TTL 0 2 4 6 8 10

-IOL[mA]
VOL[V]
4.1. Montajul pentru ridicarea caracteristicii de transfer (fig. 11.12).

rezultatele experimentale (tab. 11.3 - completat) si caracteristica de transfer
RE LQXW SHED]DGDWHORUGLQWDEHO
4.2. Montajul pentru ridicarea caracteristicii de intrare (fig. 11.13).
76
rezultatele experimentale (tab. 11.4 -FRPSOHWDWúLFDUDFWHULVWLFDGHLQWUDUH
RE LQXW SHED]DGDWHORUGLQWDEHO
0RQWDMHOHSHQWUXULGLFDUHDFDUDFWHULVWLFLORUGHLHúLUHILJVL
UH]XOWDWHOHH[SHULPHQWDOHWDEú i 11.6 - completate) si

FDUDFWHULVWLFLOHGHLHúLUHRE LQXWHSHED]DGDWHORUGLQWDEHOH
77
LUCRAREA NR. 12
CIRCUITE TTL CU COLECTORUL IN GOL
6FRSXOOXFU ULL
LucraUHDvúLSURSXQHVWXGLHUHDSRU LL77/FXFROHFWRUXOvQJRO&,- CDB 405,

DQH[ -ILJ$FDHOHPHQWGHED] vQUHDOL]DUHDIXQF LHLùO-cablat".
*HQHUDOLW L
(WDMXOILQDODOSRU LL77/VWDQGDUGDVLJXU FDUDFWHULVWLFLIXQF LRnale deosebite

DFHVWHLIDPLOLLFDUDFWHULVWLFLFDUHVHUHIHU ODWLPSLLGHFRPXWD LHODLPSHGDQ HOH
GHLHúLUHPLFLvQDPEHOHVW ULORJLFHSUHFXPúLODIDQ -out. Singurul dezavantaj al

DFHVWXLHWDMILQDOFRQVW vQDFHHDF QXSHUPLWHUHDOL]DUHDIXQF LHLù, prin
FDEODUHDGLF SULQFRQHFWDUHDvQSDUDOHODLHúLULORUPDLPXOWRUSRU LORJLFHvQWU-
DGHY UFXSODUHDvQSDUDOHODLHúLULORUDGRX SRU L77/VWDQGDUGILJWUHEXLH
V LQ VHDPDGHFHOHGRX VLWXD LLSRVLELOHúLDQXPH
78
Fig. ([SOLFDWLY ODFXSODUHDvQSDUDOHODLHúLULORUDGRX SRU L77/VWDQGDUG
-1LYHOXULOHORJLFHDOHLHúLULORUFHORUGRX SRU LFRincid, caz în care nu apar nic
un fel de probleme;
-1LYHOXULOHORJLFHUHVSHFWLYHGLIHU YILJFD]vQFDUHVHVWDELOHúWHXQ
curent I pe traseul +VCC -> R'4 -> T'4 -> D' -> T3 -> PDV FXUHQWFHDUHH[SUHVLD
V − V ‘CE 4 −V ‘D −VCE 3
I = CC ≈ 30mA (12.1)
R‘4
=
LQkQGVHDPDGHFDUDFWHULVWLFLOHFRQVWUXFWLYHDOHWUDQ]LVWRDUHORU73úL7
4 (IC3max
=
16mA, IC4max 0,8mA), pericolul distrugerii lor este evident. Oricum, consumul
GHFXUHQWGLQVXUVDGHDOLPHQWDUHDUFUHúWHLDUSRWHQ LDOXOGHLHúLUHDOSRU LORU
interconectate nu ar mai fi nici 0,4V, nici 2,4V, alterându-se deci nivelurile

logice.
Toate aceste neajunsuri sunt eliminate în FD]XOSRU LL77/FXFROHFWRUXOvQJRO
FDUHVHRE LQHGLQSRDUWD77/VWDQGDUGSULQVXSULPDUHDJUXSXOXL54, T4, D - fig.
12.2 -úLvQORFXLUHDDFHVWXLDFXRUH]LVWHQ GHVDUFLQ 5LH[WHULRDU FLUFXLWXOXL

integrat.
Fig. 12.2. Poarta (inversoml) TTL cu colectorul în gol
&XSODUHDSHDFHHDúLVDUFLQ 5LDGRX LQYHUVRDUHFXFROHFWRUXOvQJROGHWLSXO
FHOXLGLQILJYILJFRQGXFHODVFKHPDGLQILJDF UHL
IXQF LRQDUHHVWHSUH]HQWDW vQWDEHOXO
2.2. Calculul valorii lui RL
Calculul valorii lui RLWUHEXLHV LQ VHDPDGHQXP UXOPGHSRU LORJLFHDOH
F URULHúLULVHFXSOHD] vQSDUDOHOGHQXP UXOQGHVDUFLQL77/VWDQGDUGSHFDUH
DFHVWHDWUHEXLHV GHELWH]HúLQXvQXOWLPXOUkQGGHFHOHGRX QLYHOXULORJLFHFH
79
potDS UHDODLHúLUHDFRPXQ DFHORUm SRU L
)LJ&XSODUHDSHRVDUFLQ )LJ5HDOL]DUHDIXQF LHLù,FDEODW
FRPXQ DLHúLULORUDGRX SRU L
logice cu colectorul în gol
7DE([SOLFDWLYODUHDOL]DUHDIXQF LHLù, cablat
B A T’3 T3 Y
0 0 Bl. Bl. i
0 1 Bl. Sat. 0
1 0 Sat. Bl. 0
1 1 Sat. Sat. 0
$VWIHODúDFXPUH]XOW GLQILJúLvQFDUHFXUHQ LLDXYDORULOH
80
)LJ([SOLFDWLY SHQWUXFDOFXOXOYDORULLOXL51 la VOHmax
+Vcc
)LJ([SOLFDWLY SHQWUXFDOFXOXOYDORULLOXL5L la VOlmax
I0Hmax = 250uA, I1Hmax = 40uA, respectiv IOLmax = 16mA, I1Lmax = l,6mA, se

FDOFXOHD] GRX YDORULOLPLW SHQWUX5L:
Vcc − V0 H min
R L max = (12.2)
m ⋅ I OH max + n ⋅ I IH max
Vcc − V0 L min
R L min = (12.3)
m ⋅ I OL max − n ⋅ I IL max
Se alege RL astfel incat:
RL ∈ ( R L min , R L max ) (12.4)
3HQWUXUHDOL]DUHDIXQF LHLùO FDEODWúLYHULILFDUHDIXQF LRQ UL

- i acesteia, vom
XWLOL]DSODWIRUPDGHODERUDWRUúLFLUFXLWXOLQWHJUDW&'%&'%ILJ$ -
DQH[
6WXGLXOIXQF LHLùO -cablat"
3HQWUXVWXGLXOIXQF LHLùO FDEODWRE LQXWHSULQLQWHUFRQHFWDUHDLHúLULORUDSRU L

-
TTL cu colector în gol pe o VDUFLQ FRQVWLWXLW GLQDOWHSRU LVHYRUSDUFXUJH
XUP WRDUHOHHWDSH
6HFDOFXOHD] 5Lmax , RLmin si se alege RLXWLOL]kQGUHOD LLOHúL

(12.4).
3.1.2. Utilizând CI -&'%&'%DQH[ ILJ$VH
completeaz VFKHPDGLQILJFXQXPHUHOHFRUHVSXQ] WRDUHSLQLORU&,
LQFOXVLYFHLDIHUHQ LERUQHORUGHDOLPHQWDUHVLVHLPSOHPHQWHD] PRQWDMXOSH
81
zona cu socluri de CI a platformei de laborator.
6HFRQHFWHD] ODLQWU ULOH$0 , A1, A:2, A3 ale montajului din fig. 12.7 LHúLULOH
FRUHVSXQ] WRDUHDOH')1 (fig. 1.6, pinii B-4, B-5, B-úL%-7) în regim de
QXP U WRUFRPDQGDWSULQ)701,HúLUHD<DPRQWDMXOXLVHFXSOHD] ODXQ
voltmetru sau la BS, bitul C0.

Vcc
)LJ0RQWDMH[SHULPHQWDOSHQWUXYHULILFDUHDIXQF LHL
ù, FDEODWúLDQLYHOXULORUORJLFHGHLHúLUH
-
6HYHULILF IXQF LRQDUHDFLUFXLWXOXLGLQILJúLVHFRPSOHWHD] WD b. 12.2.
7DE7DEHOGHIXQF LRQDUHDOFLUFXLWXOXLGLQILJ
A3 A2 A1 A0 Y
0 0 0 0
0 0 0 1
0 0 1 0
. . . .
. . . .
1 1 1 0
1 1 1 1
6WXGLXOLQIOXHQ HLYDORULLOXL5LDVXSUDQLYHOXULORUORJLFHGHLHúLUH
Se utilizHD] PRQWDMXOGLQILJSHQWUXYDORULGLVWLQFWHDOHOXL5LúLVH
FRPSOHWHD] WDEHOXOvQFHUFXLQGX VHYDORULOHGHLHúLUHFDUHQXVH

-
82
ÎQFDGUHD] vQOLPLWHOHFXQRVFXWHDOHQLYHOXULORUORJLFH
7DE,QIOXHQ DYDORULLOXL5L asupra nLYHOXOXLORJLFDOLHúLULLFLUFXLWXOXLGLQ

fig. 12.7
A3 A2 A1 A0 V0[V]
RL <RLmin RLmin<RL<RLmax RL>RLmax
0 0 0 0
0 0 0 1
0 0 1 1
0 1 1 1
1 1 1 1

7DEHOHOHúL;
83
LUCRAREA NR. 13
325 ,77/&867 5,
/6FRSXOOXFU ULL
/XFUDUHDvúLSURSXQHVWXGLHUHDSRU LL77/FXVW UL61DQH[ ILJ$
19).
*HQHUDOLW i
)DPLOLD76/7KUHH6WDWH/RJLFSHUPLWHFXSODUHDvQSDUDOHODLHúLULORUPDLPXOWRU
SRU LORJLFHI U GH]DYDQWDMHOHSHFDUHOHLPSOLF XWLOL]DUHDUH]LVWHQ HLH[WHUQH5L
vQFD]XOSRU LORUORJLFHFXFROHFWRUXOvQJRO
)DPLOLD76/RIHU LPSHGDQ HGHLHúLUHPLFLvQVW ULOH2úLOORJLFDFHOHDúLFD
ODSRDUWD77/VWDQGDUGLDUvQFHDGHDWUHLDVWDUHVWDUHDGHvQDOWDLPSHGDQ
+=SUH]LQW DYDQWDMXOGHDQXvQF UFDFLUFXLWHOHFXFDUHHVWHFXSODW
6FKHPDXQHLSRU L1$1' 76/VHRE LQHGLQFHDDSRU LL

- TTL standard, prin
LQWURGXFHUHDXQXLLQYHUVRU,úLDXQHLGLRGH'2DúDFXPHVWHLOXVWUDWvQILJ
6LPEROXOSRU LL1$1' -TSL este prezentat în fig. 13.2.
)XQF LRQDUH
)XQF LRQDUHDSRU LL1$1' 76/HVWHSUH]HQWDW FRPSULPDWvQWDEHOXOGH

-
IXQF ionare - tab. 13.1.
$VWIHOGDF LQWUDUHDGHDXWRUL]DUH E ( ENABLE ) este activata E ODLHúLUHD
inversomlui I vom avea "l" logic ceeace face inoperant cel de-al treilea emiter al
Iui T1 în acHODúLWLPS'2YDILEORFDW LDUVFKHPDGLQILJYDIXQF LRQDFDXQ
NAND-TTL standard (fig. 11.1).
ÎnFRQGL LLOHvQFDUH E OODLHúLUHDLQYHUVRPOXL,YRPDYHD "O" logic, fapt care
LPSOLF 73 - blocat (v. lucrarea nr. 11). în plus, dioda D2 va conduce, blocându-1
pe T4,HúLUHD<YDILSULQXUPDUHSUDFWLFL]RODW ID DGHFHOHGRX
84
ERUQHDOHVXUVHLGHDOLPHQWDUHRIHULQGFLUFXLWHORUFXFDUHHVWHLQWHUFRQHFWDW R
vQDOW LPSHGDQ +=
+Vcc
)LJ6LPEROXOSRU LL76/
)LJ6FKHPDSRU LL1$1' – TSL
7DE7DEHOXOGHIXQF LRQDUHDOSRU LL76/
E B A Y
0 0 0 1
0 0 1 1
0 1 0 1
0 1 1 0
1 X X HZ
&XSODUHDSHRPDJLVWUDO GHGDWHDLHúLULORUDGRX SRU L76/VHUHDOL]HD] VLPSOX
ILJXQLFDFRQGL LHFDUHVHLPSXQHILLQGDFHHDDYDOLG ULLQHVLPXOWDQHDFHORU
E1 ≠ E 2 .
GRX VDXPDLPXOWHSRU L
Adoptând un sistem de autorizare de tipul celui din fig. 13.4. cu

E = E 1 = E2 (13.1)
RE LQHP
Y = A1 B1 E + A2 B2 E (13.2)
deci:
 A B , pentru E = 0
Y = 1 1 , (13.3)
 A2 B 2 , pentru E = 1
85
Fig. 13.3. Cuplarea ieúLULORUDGRX SRU L76/ Fig. 13.4. Sistem de autorizare
vQFRQWUDWLPSDIXQF LRQ ULL
SRU LORU76/GLQILJ
Pentru studiul inversorului TSL vom utiliza platforma de laborator, trei circuite
LQWHJUDWH61DQH[ ILJ$úLXQDSDUDWGHP VXU GHWLS
MAVO.
6HFRPSOHWHD] VFKHPDGLQILJFXQXP UXOSLQLORU CI utilizate,
inclusiv pinii de alimentare.
+Vcc
)LJ0RQWDMH[SHULPHQWDOSHQWUXYHULILFDUHDIXQF LRQ ULLSRU LORU76/FX
LHúLULOHFXSODWHSHRPDJLVWUDO
3.26HLPSOHPHQWHD] VFKHPDGLQILJSH]RQDFXVRFOXULGH&,D
86
platformei de laborator.
6HFRQHFWHD] LQWU ULOHGHDXWRUL]DUH E − 1, E − 2, E − 3 ILJODLHúLULOH
A0, A1, A2 ale DF1úLLQWU ULOH$%&ODLHúLULOH$0, A2, A2 ale DF2, cu DF1úL')2
SXVHvQUHJLPGHQXP U WRDUHFRPDQGDWHGHWDFWXOPDQXDO
6HDOLPHQWHD] SODWIRUPDGHODERUDWRUúLVFKHPDGLQILJ
6HYHULILF IXQF LRQDUHDFLUFXLWXOXLúLVHFRPSOHWHD] WDE
Tab. 13.2. Explicativ pentru montajul din fig. 13.5
E − 3 E − 2 E −1 C B A V01[V] V02[V] Y
1 1 1 x x x
1 1 0 0 0 0
1 1 0 0 0 1
1 0 1 0 0 0
1 0 1 0 1 0
0 1 1 0 0 0
0 1 1 1 0 0
2EVHUYD LL
'DF V01 = V02 = 0 9LHúLUHD<VHDIO vQVWDUHDGHvQDOW LPSHGDQ +=
'DF YDORDUHDOXL901HVWHVF ]XW LDUDOXL902 -ULGLFDW <HVWH2ORJLF

'DF YDORDUHDOXL901HVWHULGLFDW LDUDOXL902 -VF ]XW <HVWHvQOORJLF
&RQ LQXWXOUH feratului
4.2. Tabelul 13.2. completat;

87
LUCRAREA N.R. 14
32$57$&026$1$/,=$67$7,&
1. 6FRSXOOXFU ULL
/XFUDUHDvúLSURSXQHVWXGLHUHDGLQSXQFWGHYHGHUHVWDWLFDSRU LL&026
MMC 4049, fig. A.16 -DQH[
2.1. *HQHUDOLW L
FamiliDORJLF &026&RPSOHPHQWDU\026XWLOL]HD] -DúDFXPUH]XOW úL din

denumire - tranzistoare MOSFRPSOHPHQWDUHúLHVWHIDPilia cu parametrii cei mai
DSURSLD LGHFHLDLXQHLIDPLOLLLGHDOHSXWHUHGLVLSDW IRDUWHPLF vQUHJLPVWDWLF
(10 n\9SRDUW WLPSGHSURSDJDUHPLFQVHFGHSHQGHQWGHWHQVLXQHD

de alimentare, imunitate la zogomot -GLQGLIHUHQ DWHQVLXQLlor
FRUHVSXQ] WRDUHFHORUGRX QLYHOXULORJLFHIURQWXULFRQWURODELOHHWF
2.2. )XQF LRQDUHDLQYHUVRUXOLLL&026
,QYHUVRUXO&026ILJODHVWHIRUPDWGLQGRX WUDQ]LVWRDUH
a) VFKHP b) caracteristica de c) caracteristica de

transfer a lui Tn transfer a lui Tp
Fig. 14.1. Inversorul CMOS
88
complementare cu canal indus de tip n (Tn), respectiv p (Tp), ambele realizate pe
DFHODúLVXEVWUDWGHED] &DUDFWHULVWLFLOHGHWUDQVIHUDOHFHORUGRX WUDQ]LVWRare
sunt prezentate în fig. 14.1EúLFXQGHV-au notat VpnúL9pp tensiunile de

prag.
3HILJXUDODSRWILVFULVHFXXúXULQ UHOD LLOH
VGSn= V1, (14.1)

VGSp = V1 - VDD , (14.2)
DF URULQWHUSUHWDUHFRUHODW FXGLDJUDPHOHGLQILJOEúLFH[SOLF FX
VXILFLHQW FODULWDWHIXQF LRQDUHDLQYHUVRUXOXL&026
Astfel, pentru V1 < Vpn (spre exemplu, V1 = O, deci A = "O" logic), Tn va fi

blocat iar Tp va conduce în regiunea ohPLF 9GSp - VDDUHO3RWHQ LDOXO
+VDDYDILWUDQVIHUDWODLHúLUHDLQYHUVRUXOXLSULQFRQGXFWDQ DGUHQ -VXUV DOXL7P
úLLHúLUHDYDIL< OORJLF
Similar, pentru Vt > Vpn (spre exemplu V1 = VDD, deci A = "l" logic), Tn va
conduce în regiunea ohPLF 9GSn = VDD, rel. 14.1), iar Tp va fi blocat (VGSp = O,
UHO3RWHQ LDOXOPDVHLYDILWUDQVIHUDWODLHúLUHDLQYHUVRUXOXLSULQ
FRQGXFWDQ DGUHQ -VXUV DOXL7núLLHúLUHDYDIL2ORJLF
)XQF LRQDUHDFDLQYHUVRUDFLUFXLWXOXLHVWHGHPRQVWUDW
ODQDOL] PDLGHWDOLDW SRDWHILI FXW FXDMXWRUXOGLDJUDPHORUGLQILJDúLE
úLDWDEHOXOXLH[SOLFDWLY
([SOLFDWLY SHQWUXIXQF LRQDUHDLQYHUVRUXOXL&026
a) caracteristicile de transfer ale tranzistoarelor TnúL7p

b) caracteristica de transfer a inversorului
89
7DE([SOLFDWLYSHQWUXIXQF LRQDUHDLQYHUVRQLOXL&026
ZONA
Trz. I II III IV V
Tn Bl. Sat. ID Sat. ID R. lin. R. lin
TP R. lin R. lin SatID SatID Bl.
$úDFXPUH]XOW úLGLQFDUDFWHULVWLFDGHWUDQVIHUG in fig. 14.2b, consumul de

SXWHUHvQUHJLPVWDWLF]RQHOH,úL9HVWHQHJOLMDELOILLQGGDWGHUHOD LD
Ps = IoVDD, (14.3)
unde I0 = inA este curentul rezidual al tranzistorului blocat (fie Tn, fie Tp).
Pentru un VDD ∈ >99@UH]XOW XQFRQVXPVWDWLFGHSXWHUHvQWU-DGHY U
neglijabil:
Ps ∈ [5nW, 15nW], (14.4)
în regim dinDPLFGHFLvQWLPSXOWUDQ]L LHLGLQWU-RVWDUHvQDOWD]RQHOH,,,,,úL,9
GDUvQVSHFLDO]RQD,,,FRQVXPXOVHYDGDWRUDFLUFXOD LHLXQXLFXUHQW,D (fig.
14.2a) între +VDDúLPDV $FHVWFRQVXPGHSXWHUHVXSOLPHQWDUHVWHGDWGHUHOD LD

PD = CLVDD2f, (14.5)
în care CLUHSUH]LQW FDSDFLWDWHDHFKLYDOHQW GHODLHúLUHDLQYHUVRUXOXLIRUPDW
GLQFDSDFLW LOHSRU LORUFRPDQGDWHúLFHOHSDUD]LWHLDUI-IUHFYHQ DGHFRPXWD LH
2EVHUYD LL:
1) Fan-out-XOLQYHUVRUXOXLDUHYDORDUHDWLSLF UH]XOWDW QXGLQQHFHVLWDWHD

PHQ LQHULLQLYHOXULORUGHWHQVLXQHvQUHJLPVWDWLFFLGLQFRQVLGHUHQWHOHJDWHGH
limitarea lui PDDF UXLYDORDUHFUHúWHGLUHFWSURSRU LRQDOFX&LGHFLFXQXP UXO
GHSRU LFRQHFWDWHFDVDUFLQ
$WkWvQF UFDUHDFkWúLGHVF UFDUHDFDSDFLW LORUGLQFRPSRQHQ DOXL&L , are loc

FXRFRQVWDQW GHWLPSUHGXV GDWRULW YDORULLPLFLDUH]LVWHQ HLGUHQ
-VXUV D
WUDQ]LVWRUXOXLFDUHFRQGXFH6HRE LQDVWIHOWLPSLGHFRPXW
are rezonabili (în jur de
60nsec), ameliorându-se unul din principalele dezavantaje ale circuitelor
logice PMOS si NMOS,
2.3. Caracteristici statice
2.3,1. Caracteristica de transfer
&DUDFWHULVWLFDGHWUDQVIHUUHSUH]LQW GHSHQGHQ D90 = f(V1) si are aspectul din fig.

EFXREVHUYD LDF 9DDSRDWHOXDYDORULFXSULQWFvQWUHúL9
5LGLFDUHDH[SHULPHQWDO DFDUDFWHULVWLFLLGHWUDQVIHULPSXQHFXQRDúWHUHD
90
úLUHVSHFWDUHDQLYHOXULORUORJLFH$VWIHOSHQWUX9DD = 5 V, nivelurile logice sunt
prezentate în fig. 14.3.
Fig. 14.3. Nivelurile logice ale familiei CMOS
'LQPRWLYHGHVLPLOLWXGLQHúLHFRQRPLHGHVSD LXVXJHU PVWXGHQ LORUV UHYDG
paragraful 2.3.l de la lucrarea nr. 11.
2.5.2. Caracteristica de intrare
Studiul caracterLVWLFLLGHLQWUDUHHVWHQHLQWHUHVDQWGDWRULW UH]LVWHQ HLGHLQWUDUH

foarte mari (> 1012 ) a tranzistoarelor MOSúLLPSOLFLWDFXUHQWXOXLGHLQWUDUH
practic nul.
&DUDFWHULVWLFDGHLHúLUH
6WXGLXOFDUDFWHULVWLFLLGHLHúLUHDIQYHUVRUXOXLHVWHGHDsemenea neinteresant
GDWRULW UH]LVWHQ HLGHLQWUDUHIRDUWHPDULDSRU LORUFRPDQGDWHúLLPSOLFLWDIDQ -
out-XOXLH[WUHPGHULGLFDWDOLQYHUVRUXOXLvQUHJLPVWDWLFYREVHUYD LDQUOGHOD
paragraful 2.2).
Pentru ridicarea expeULPHQWDO DFDUDFWHULVWLFLLGHWUDQVIHUVHYDXWLOL]DSODWIRUPD
GHODERUDWRUúLFLUFXLWXOLQWHJUDW00&ILJ$ DQH[
-
6HUHDOL]HD] PRQWDMXOGLQILJGXS FRPSOHWDUHDILJXULLFXQXP UXO
pinilor CI. inclusiv cei de alimentare.
91
3.2. 6HFRPSOHWHD] WDESHQWUXGRX YDORULGLVWLQFWHDOHWHQVLXQLLGH
alimentare: VDD 9úL9DD = 15V.
Fig. 14.4. Montaj experimental pentru ridicarea caracteristicii de transfer a

inversorului CMOS
Tab. 14.2. Tabel pentru ridicarea caracteristicii de transfer
V1[V] 0 1 . . . . . . . . . . . . I/DD
V0[V]

4.2. Tabelul 14.2 (pentru VDD 9úL9DD = 15V);
4.3. Caracteristicile de transfer pentru VDD 9úL9DD = 15V;
92
LUCRAREA NR. 15
5(*,08/',1$0,&$/325 ,/2577/6,&026
/6FRSXOOXFU ULL
/XFUDUHDvúLSURSXQHVWXGLHUHDUHJLPXOXLGLQDPLFDOSRU LORU77/VWDQGDUGúL
&026&'%&'%ILJ$úL$ - DQH[ UHVSHFWLY00&ILJ
A. 16 -DQH[
2.1. *HQHUDOLW L
3ULQFLSDOXOSDUDPHWUXSULQLQWHUPHGLXOF UXLDVHHYDOXHD] IXQF LRQDUHDvQUHJLP
GLQDPLFDXQHLSRU LORJLFHHVWHWLPSXOGHvQWkU]LHUHODSURSDJDUHSURSDJDWLRQ
delay time - tpd(OH[SULP YLWH]DGHU VSXQVDFLUFXLWXOXLORJLFVDXPDL
H[SOLFLWvQWkU]LHUHDFXFDUHUHDF LRQHD] LHúLUHDFLUFXLWXOXLODXQVWLPXODSOLFDWOD
intrare.
2.2. 5HJLPXOGLQDPLFDOSRU LL77/VWDQGDUG
6XUVDSULQFLSDO DvQWkU]LHULORUvQSU opagarea semnalelor prin circuitele logice

UHDOL]DWHvQWHKQLF ELSRODU RFRQVWLWXLHWLPSXOQHFHVDULHúLULLGLQVDWXUD LHD
WUDQ]LVWRDUHORU(VWHFXQRVFXWIDSWXOF ODVDWXUD LHFHOHGRX MRQF LXQLDOH
tranzistorului sunt direct polarizate, având loc o GXEO LQMHF LHGHSXUW WRUL
PDMRULWDULSURYHQL LGLQ]RQHOHHPLWHUXOXLúLFROHFWRUXOXL - în zona bazei.

(YDFXDUHDVDUFLQLORUVWRFDWHvQED] vQFRQGL LLOHvQFDUHWUDQ]LVWRUXODSULPLW
FRPDQGDGHLHúLUHGLQVDWXUD LHQXVHSURGXFHLQVWDQWDQHXFLGXS XQ anumit

LQWHUYDOGHWLPSQXPLWWLPSGHVWRFDUH5H]XOW F Wpd XOSRU LL77/VWDQGDUG
-
GHSLQGHGHQXP UXOWUDQ]LVWRDUHORUFDUHS U VHVFVWDUHDGHVDWXUD LH$SDUHQW
SULYLQGILJúLWDEFRQVWDW PF WUDQ]L LD+ —> L (trecerea din zona (l),

fig.vQ]RQDLPSOLF LHúLUHDGLQVDWXUD LHDWUDQ]LVWRDUHORU71úL74, iar
WUDQ]L LD/—> H -LHúLUHDGLQVDWXUD LHDWUDQ]LVWRDUHORU72úL73.
93
&RQFOX]LDILUHDVF DUILDFHHDF WUDQ]L LLOHvQDPEHOHVHQVXULDXORFvQLQWHUYDOH
de timp egale.
ÎQUHDOLWDWHGLPHQVLXQHDUHGXV DOXL71FRQGXFHODFDSDFLW LSDUD]LWHUHGXVHúL
ODRYLWH] GHFRPXWD LHDDFHVWXLDIRDUWHPDUH
5H]XOW QHFHVLWDWHDGHILQLULLDGRLWLPSLGHvQWkU]LHUHODSURSDJDUHWpdHL , pentru

FRPXWDUHDLHúLULLGLQVWDUHDVXVvQVWUDUHDMRVúLWpdLHSHQWUXFRPXWDUHDLHúLULL
GLQVWDUHDMRVvQVWDUHDVXVFXREVHUYD LDF WpdLH > tpdlHL.

$PELLSDUDPHWULLVXQWP VXUD LvQFRQGL LLOHXQXLIDQ-RXW úLVXQWLOXVWUD LvQ
diagramele din fig. 15.1.
Fig. 15.1. ExpliFDWLY SHQWUXWLPSLLGHvQWkU]LHUHODSURSDJDUH
DIRUPDGHXQG DWHQVLXQLLGHLQWUDUH
EIRUPDGHXQG DWHQVLXQLLGHLHúLUH
7LPSXOGHvQWkU]LHUHODSURSDJDUHDOSRU LL77/VWDQGDUGVHRE LQHHIHFWXkQG
PHGLDDULPHWLF DFHORUGRL :
t pdHL + t pdLH
t pd = = 10ns (15.1)
2
'DWRULW GLIHUHQ HLGLQWUHWpdHLúLWpdLHSRDWHDS UHDRPRGLILFDUHDGXUDWHL
LPSXOVXOXLFHVHSURSDJ SULQWU XQODQ GHSRU L77/VWDQGDUG

-
$VWIHOvQFD]XOXQXLQXP USDUGHSRU L$1'ILJDGLDJU amele de semnal
vor avea aspectul din fig. 15.2b.
'LQILJEREVHUY PF
T*=T – 2 (tpdLH -TpdHL) (15.2)

VDXJHQHUDOL]kQGSHQWUXQSRU L
T* = T –n (tpdLH -TpdHL) (15.3)
94
6HREVHUY F GXUDWDLPSXOVXOXLVHUHGXFHFXFkWH
tpdLH-tpdHL=12 - 8 = 4ns (15.4)

ODWUHFHUHDSULQILHFDUHSRDUW 77/VWDQGDUGSkQ ODGLVSDUL LDWRWDO D
impulsului.
a) schema
b)diagramele de semnal
Fig. 15.20RGLILFDUHDGXUDWHLLPSXOVXOXLFHVHSURSDJ SULQWU-XQODQ GHSRU L

AND
ÎQFD]XOXQXLODQ IRUPDWGLQWU-XQQXP USDUGHSRU L1$1'ILJDVHRE LQ
diagramele din fig. 15.3b.
a) schema
b) diagramele de semnal
Fig. 15.3. Conservarea duratei impulsului la trecerea printr-XQQXP USDUGHSRU L
NAND
95
'LQILJEREVHUY PF
T* = T + (tpdLH - tpdHL.) - (tpdLH - tpdHL)= T (15-5)

GHFLGXUDWDLPSXOVXOXLVHUHIDFHGXS XQQXP USDUGHLQYHUV UL
5HJLPXOGLQDPLFDOSRU LL&026
ÎQFD]XOSRU LL&026VXUVDSULQFLSDO DvQWkU]LHULORUvQSURSDJDUHDVHPQDOHORUR
FRQVWLWXLHFDSDFLW LOHSDUD]LWH
Astfel, aplicând la intrarea unui inversor CMOS un semnal dreptunghiular ideal

FXDPSOLWXGLQHDYDULLQGvQWUHQLYHOXULOH2úL9DD, putem calcula timpii de
vQF UFDUHGHVF UFDUHDLFDSDFLW LLGHVDUFLQ &L a inversorului (prin tranzistorul
MOS cu canal p, respectiv n).

Timpul de propagare prin inversor este:
o,9 ⋅ C L  1  1
t pd =   + (15.6)
V DD ⋅ K n  (1 − V pn / V DD )  K p / K n (1 − V pp / V DD ) 2
2
úLGHSLQGHGHUDSRUWXO&L / VDDDúDFXPHVWHLOXVWUDWvQILJ
ÎQWLPSXOFRPXWD LHLFDSDFLWDWHDGHLQWUDUHD7(&026-ului (§S)FUHúWHGH-
RULGDWRULW HIHFWXOXL0,LLERFDX]DWSHFDSDFLWDWHDGHUHDF LHJULO -dren
(CgdúLWUDQVFRQGXFWDQ DJm), fig. 15.5.
)LJ'HSHQGHQ DWpd = f(CL,VDD) )LJ'HSHQGHQ D&iN = f ( V)
În proiectare se poate utiliza o valoare a fan-out-ului mai mare de 50 (v.

REVHUYD LDQUOGHODSDUDJUDIXOOXFUDUHDQU&UHúWHUHDIDQ-out-ului
P UHúWHvQV FDSDFLWDWHDWRWDO GHVDUFLQ ODYDORDUHD
CL = 5x + C0 [PF], (15.7)
XQGH[HVWHQXP UXOGHVDUFLQLDGL LRQDOHLDU&0YDULD] vQIXQF LH de VDD astfel:
VDD= 5V , C0 = 40pF:
96
VDD=10V , C0 = 20 pF;
VDD=15V , C0=10 PF.
&UHúWHUHDOXL&L FRQGXFHODFUHúWHUHDOXL3DUHOúLOLPLWHD] FUHúWHUHDIDQ
-
out-ului.
3HQWUXVWXGLHUHDUHJLPXOXLGLQDPLFDOSRU LORU77/úL&026VHYDXWLOL]D
platfonna de laborator, circuitele integrate CDB 404, CDB 408, MMC 4049 - fig.
$$úL$-DQH[ -úLXQRVFLORVFRSFXGRX VSRWXUL
6WXGLXOUHJLPXOXLGLQDPLFDOSRU LL77/VWDQGDUG
6HUHDOL]HD] PRQWDMXOGLQILJGXS FRPSOHWDUHDVFKHPHLFX
)LJ0RQWDMH[SHULPHQWDOSHQWUXVWXGLHUHDUHJLPXOXLGLQDPLFDOSRU LL$1' -
TTL
QXPHUHOHSLQLORUFRUHVSXQ] WRUL&,&'%LQFOXVLYSLQLL de alimentare.

Comutatoarele K1úL.2GHSHSODFKHWDPXOWLIXQF LRQDO VXQWDPEHOHSHSR]L LD
3.1.2. Vizualizând cu ajutorul osciloscopului semnalele din punctele A, B, .. , E
VWXGLHPXUP WRDUHOHDVSHFWH
D6F GHUHDSURJUHVLY GHOD$OD(DGXUDWHLLPSXOVXULORUSkQ ODDQXODUHDORU
(v. fig. 15.2b);

b) Durata fronturilor anterioare - trúLSRVWHULRDUH-tf (v. fig. 15. la);
c) Timpii de întârziere la propagare tpdHLúLWpdLH.
6HUHDOL]HD] PRQWDMXOGLQILJGXS FRPSOHWDUHDVFKHPHLFX
QXPHUHOHSLQLORUFRUHVSXQ] WRUL&,&'%LQFOXVLYSLQLL de alimentare.

Comutatoarele K1úL.2GHSHSODFKHWDPXOWLIXQF LRQDO VXQWDPEHOHSHSR]L LD
3.1.4. Vizualizând cu ajutorul osciloscopului semnale! din punctele A, B.
97
..., E, VWXGLHPXUP WRDUHOHDVSHFWH
D5HIDFHUHDGXUDWHLLPSXOVXULORUGXS FkWHGRX LQYHUV ULVXFFHVLYH
b) Duratele fronturilor anterioare - trúLSRVWHULRDUH- tf (v. fig. 15.la);

c) Timpii de întârziere la propagare tpdHLúLWpdLH.
Fig. 15.7. Montaj experimental pentru studierea inversomlui TTL
3.2. Studiul regimului dinamic al pRU LL&026
6HUHDOL]HD] PRQWDMXOGLQILJGXS FRPSOHWDUHDVFKHPHLFXQXPHUHOH
SLQLORUFRUHVSXQ] WRUL&,00&LQFOXVLYSLQ ii de alimentare. Comutatorul

K1DO*7$VHDIO SHSR]L LDO.+=LDUFRPXWDWRUXO.2 al FTA -SHSR]L LD
(T2 § 300nsec).
+Vcc
Fig. 15.8. Montaj experimental pentru studierea inversorului CMOS '
3.2.2. Se refac experimentele de la punctul 3. l .4.
4.1. 6FKHPDGLQILJFRPSOHWDW FXQXP UXOSLQLORUUHVSHFWLYL
'LDJUDPHOHGHVHPQDOYL]XDOL]DWHvQSXQFWHOH$%(FXHYLGHQ LHUHD
duratei impulsurilor si a timpilor de întârziere la propagare (v. fig. 15.2b);

'LDJUDPDGHVHPQDOYL]XDOL]DW vQSXQFWXO%ILJFXHYLGHQ LHUHD
fronturilor (tr, tf-úLDWLPSLORUGHvQWkU]LHUHODSURSDJDUHYILJ

4.5. Diagramele de semnal vizualizate în puncctele A, B,.... E, cuHYLGHQ LHUHD

GXUDWHLLPSXOVXULORUúLDWLPSLORUGHvQWkU]LHUHODSURSDJDUHYILJE
98
4.7. Diagramele de semnal vizualizate în punctele A. B, ..., E, fig. 15.8, cu

HYLGHQ LHUHDGXUDWHLLPSXOVXULORUúLDWLPSLORUGHvQWkU]LHUHODSURSDJDUHYILJ
15.3b);
'LDJUDPDGHVHPQDOYL]XDOL]DW vQSXQFWXO%ILJFXHYLGHQ LHUHD
GXUDWHLIURQWXULORUúLDWLPSLORUGHvQWkU]LHUHODSURSDJDUHYILJ
2EVHUYD LLSHUVRQDOH ale studentului.
99
LUCRAREA NR. 16
CIRCUITE BASCULANTE BISTABILE
6FRSXOOXFU ULL
/XFUDUHDvúLSURSXQHVWXGLHUHDGLIHULWHORUWLSXULGHFLUFXLWHEDVFXODQWHELVWDELOH
&%%XWLOL]DWHvQFLUFXLWHOHúLVLVWHPHOHGLJLWDOH
*HQHUDOLW L
Circuitele basculante bistabile (CBB) fac parte din marea familie a circuitelor
ORJLFHVHFYHQ LDOHFOVFXQRVFXWHvQOLWHUDWXU úLVXEGHQXPLUHDGHVLVWHPHGH
ordin > 1. Trecerea de la sistemele de ordin zero (c.l.c.) la cele de ordin superior
VHIDFHSULQLQWURGXFHUHDXQRUUHDF LLFDUH-LFRQIHU VLVWHPXOXLSURSULHWDWHDGH
PHPRULH$VWIHOLHúLULOHFLUFXLWXOXLVHFYHQ LDOVXQWSDU LDOLQGHSHQGHQWHGH
semnalele de intrare din acel moment, depinzând -WRWSDU Lal -GHVW ULOHDQWHULRDUH
ale circuitului.
2.2. Circuitul basculant bistabîl RS
CBB-56VHRE LQHSULQLQWURGXFHUHDXQHLUHDF LLvQWU-un sistem elementar de ordin

]HUR6LVWHPXODVWIHORE LQXWHVWHGHRUGLQ
CBB-RS poate fi realizat în varianta asincron VLQFURQ VDX0DVWHU-Slave"

VW SkQ-sclav)
2.2.1. CBB-RS asincron

CBB-RS asincron, cunoscut -GDWRULW SURSULHW LORUVDOHGHDPHPRUD-úLVXE
GHQXPLUHDGHODWFK] YRUSRDWHILUHDOL]DWFX125-uri sau cu NAND-uri,
vQYDULDQWD125ILJIXQF LRQDUHDFLUFXLWXOXLHVWHLOXVWUDW GHWDEHOXOGH
WUDQ]L LHWDEvQFDUHV -a notat cu indice "n" -YDORDUHDORJLF SUH]HQW úLFX
"n+1" -YDORDUHDORJLF YLLWRDUH
Q Q
D6FKHP ORJLF E6FKHP EORF
Fig. 16.1. CBB-RS asincron, varianta NOR
100
7DE7DEHOGHWUDQ]L LHDO Fig. 16.2 . Diagrama VK pentru
CBB-RS asincron, varianta NOR CBB-RS asincron, varianta NOR
Rn SN Qn+1 RnSn 00 01 11 10
Qn
0 0 Qn
0 l i 0 0 1 X 0
1 0 0
1 1 x 1 1 1 X 0
R n Qn Sn
Astfel, pentru RnSn = 00 (prima linie a tabHOXOXLGHWUDQ]L LHSRU LOH31úL32 sunt
YDOLGDWHúLYDORDUHDORJLF DOXL4n ( Q GHODLHúLUHDSRU LL31 (P2) ajunge la
n
LHúLUHDSRU LL32
(P1) sub forma Q n (Qn2EVHUY PF YDORULOHORJLFHDOHLHúirilor
U PkQQHVFKLPEDWHGHFL4n+] = Qn.
Pentru RnSn=01 (Rn=0, Sn OLHúLUHDSRU LLYDIL

Qn= Q + S = Q n +1 = 1 =0, (16.1)
n n
GHFLODLQWUDUHDSRU LL31VHDSOLF 5n úL Qn (YLGHQWODLHúLUHDSRU LL31 vom

avea:
Qn +1 = Rn + Q n = 0 + 0 = 0 = 1 (16.2)
Prin urmare atunci ckQGLQWUDUHD6HVWHDFWLYDW 6n OVHUHDOL]HD]
vQVFULHUHDXQXLOORJLFvQPHPRULH'HQXPLUHD6DLQWU ULLHVWHRSUHVFXUWDUH
DFXYkQWXOXL6(7GLQOLPEDHQJOH] FDUHvQVHDPQ vQVFULHUH
Pentru RnSn=10 (Rn=l, Sn=0), se poate demonstra - urmând o cale

VLPLODU FHOHLGHPDLVXV-F VHRE LQH4n+1=0.
5H]XOW F DFWLYDUHDLQWU ULL55n OFRQGXFHODúWHUJHUHDLQIRUPD LHL
GLQPHPRULHHFKLYDOHQWFXSXQHUHDSH2DPHPRULHL'HQXPLUHD5DLQWU ULL
este RSUHVFXUWDUHDFXYkQWXOXL5(6(7GLQOLPEDHQJOH] FDUHvQVHDPQ
úWHUJHUH
Pentru RnSn OOLHúLULOHFHORUGRX SRU LVXQWIRU DWHVLPXOWDQvQ2ORJLFGHFLV -

DUDMXQJHODVLWXD LDLQDGPLVLELO vQFDUH
Qn +1 = Q n +1 = 0 (16.3)
Din acest motiv cRPELQD LDGHLQWUDUHHVWHLQWHU]LV GHRELFHLSULQ
ORJLF VXSOLPHQWDU LDUvQORFD LDFRUHVSXQ] WRDUHGLQWDEVHSXQHVHPQXO
[VSHFLILFORFD LLORUvQFDUHIXQF LDHVWHQHGHILQLW
3HQWUXDRE LQHRIRUP PLQLPDO DIXQF LHLGHLHúLUHFRQVWUXL m diagrama Veitch
101
-.DPDXJK9.DFLUFXLWXOXLILJúLGXS JUXS ULFRQYHQDELOHRE LQHP
Qn+1 =Sn+ R n Qn (16.4)

5HOD LDVHYHULILF QXPDLSHQWUXSULPHOHWUHLOLQLLDOHWDE
Varianta NAND a CBB-RS asincron esteSUH]HQWDW vQILJ
Q Q
DVFKHPDORJLF b) schema bloc
Fig. 16.3. CBB-RS asincron, varianta NAND

IXQF LRQDUHDFLUFXLWXOXLHVWHLOXVWUDW vQWDEHOXOGHWUDQ]L LHWDELU
PLQLPL]DUHDIXQF LHLGHLHúLUHHVWHUHDOL]DW FXDMXWRUXOGLDJUDPHL9.ILJ
7DE7DEHOGHWUDQ]L LHDO
CBB-RS asincron, varianta NAND

Rn S n 00 01 11 10
Rn Sn Qn+1
0 0 Qn
Qn
0 l 1
1 0 0 0 X 0 0 1
1 1 x
1 X 0 1 1 Sn
RNQn
Fig. 16.4. Diagrama VK pentru CBB-RS asincron, varianta NAND
104
2EVHUY PF vQXUPDPLQLPL] ULLVHRE LQHDFHHDúLH[SUHVLHSHQWUX4n+1 .
CBB-56DVLQFURQLQGLIHUHQWGHYDULDQWDGHLPSOHPHQWDUHDGRSWDW SUH]LQW
XUP WRDUHOHGHILFLHQ H
-DFHOHDúLVHPQDOHFDUHLQGLF PRGXO&80vQFDUHWUHEXLHV VHIDF comutarea,

GLFWHD] úLPRPHQWXO&Æ1'WUHEXLHV DLE ORFDFHDVWD
-SHQWUXDQXPLWHWUDQ]L LLDOHLQWU ULORUFLUFXLWXOXLVWDUHDLHúLULORUHVWH
LPSUHYL]LELO
([HPSOX7UDQ]L LD -> DLQWU ULORUSRDWHDGXFHLHúLULOH4

Q ale CBB din
ILJvQRULFDUHGLQFHOHGRX VW ULSRVLELOH$VWIHOSHQWUX5nSn=1l, vom avea
102
Q= Q úLSRU LOH31P2 vor fi validate. Pentru RnSn = 00, aGPL kQGF SRDUWD31
HVWHPDLUDSLG VHYDRE LQHXQOORJLFODLHúLUHD4, ceea cHIRU HD] - prin
UHDF LH- un "O" logic la Q (YLGHQWGDF DSOLF PDFHHDúLVXSR]L LHSHQWUXSRDUWD
P2YDORULOHORJLFHDOHLHúLULORUVHLQYHUVHD]
2.2.2. CBB-RS.sincron
CBB-56VLQFURQVHRE LQHGLQ&%%-56DVLQFURQSULQDG XJDUHDDGRX SRU LúL
YDOLGDELOHGHXQLPSXOVGHWDFWILJúL
Q Q
Fig. 16.5. CBB-RS sincron, varianta NOR
)XQF LRQDUHDFHORUGRX &%% 56VLQFURQHILLQGVLPLODU QHYRPOLPLWDOD

-
H[SOLFDUHDIXQF LRQ ULLFLUFXLWXOXLGLQILJD
103
Fig. 16.6. CBB-RS sincron, varianta NAND
2EVHUY PF SHQWUX CLK SRU LOHúLVXQWLQKLEDWHúLRULFHPRGLILFDUHDOXL

R, S nu va afecta CBB-XO65DVLQFURQIRUPDWGLQSRU LOHOúLvQWU-DGHY U
LQWU rile acestuia pentru CLK OYRUILúLFRQIRUPSULPHLOLQLLGLQWDE
LHúLULOHYRUU PkQHQHVFKLPEDWH
Când CLK 2SRU LOHVLVXQWYDOLGDWHúLLQWU ULOH R S , transformate în RS,

vor avea acces la CBB-RS asinFURQDF LRQkQGFRQIRUPWDE
3HQWUXRIXQF LRQDUHVLQFURQ DFLUFXLWXOXLHVWHQHFHVDUFDLPSXOVXOGH CLK care
GLFWHD] &Æ1'V VHH[HFXWHFRPHQ]LOH R S V DSDU QXPDLGXS FHDFHVWHDV-au
stabilizat. Modificarea lui R S vQLQWHUYDOXOGHWLPSvQFDUHSRU LOHGHLQWUDUH

VXQWGHVFKLVHFRQGXFHODRIXQF LRQDUHDVLQFURQ DFLUFXLWXOXL'LQDFHVWPRWLY
VXQWQHFHVDUHFRQGL LLUHVWULFWLYHSHQWUXUHOD LDGHWLPSGLQWUH CLK úL R S .

&LUFXLWXOGLQILJIXQF LRQHD] VLPLODULPSXOVXOGHWDFWILLQGGHDFHDVW GDW
activ pe palierul "l" logic.
2.2.3. CBB-RS - "Master-Slave"

'XS FXPUHLHVHGLQILJ&%% -RS-06UHSUH]LQW RH[WHQVLHVHULHD
bistabilului RS sincron implementat cu NAND-XULYILJ6FKHPDORJLF
HVWHSUH]HQWDW vQILJDLDUGLDJUDPHOH&/.úL CLK -vQILJEúLF
104
Fig. 16.7. CBB-RS-MS - Schema bloc
a) schema b), c) diaeramc
Fig. 16.8. CBB-RS-MS
105
În intervalul (l) - SRU LOHGHLQWUDUH00úLGHWUDQVIHU66VXQW
blocate iar MASTER-XOHVWHL]RODWDWkWGHLQWU ULFkWúLGH6/$9(
în intervalul (2) - SRU LOH00VXQWYDOLGDWHúLLQIRUPD LDVHvQVFULHvQ
0$ù7(5SRU LOH66ILLQGEORFDWH CLK = O), SLAVE este în continuare
L]RODWID GH0$6TER.
În intervalul (3)-VHUHSHW VLWXD LDGLQ intervalul (l)-(2) când MASTER-ul era
L]RODWDWkWGHLQWU ULFkWúLGH6/$9(
ÎQVIkUúLWGXS PRPHQWXOSRU LOH00VXQWEORFDWH0$67(5 -ul izolat

ID GHLQWU ULLDUSRU LOH66VXQWYDOLGDWHúLLQIRUPD LDGLQ0$ù7(5VH
WUDQVIHU vQ6/$9(
CoQFOX]LRQkQGvQVFULHUHDLQIRUPD LHLvQ0$ù7(5DUHORFvQDLQWHGHPRPHQWXO
SRVLELOFKLDUSHIURQWXOGHVFUHVF WRUDO&/.LDUWUDQVIHUXOHLvQ6/$9(úL
GHFLODLHúLUHDUHORFGXS PRPHQWXOGHFLSHDFHODúLIURQWGHVFUHVF WRUDO
CLK).
Prin urmare,SHQWUXvQVFULHUHDI U HURULDLQIRUPD LHLvQ&%% -RS-MS, este
QHFHVDUFDDFHDVWDV U PkQ VWDELO ODLQWUDUHXQLQWHUYDOGHWLPSQMXUXO
intervalului (3)-(4).
CBB-RS-06QXHOLPLQ SRVLELOLWDWHDWUDQ]L LLORUQHGHWHUPLQDWHYWDEVL
16.2).
Evident, se pot construi CBB-RS-06FDUHV FRPXWHSHWUDQ]L LDSR]LWLY D
impulsului de tact.
2.3. Circuitul basculant bistabil de tip D
2.3.1. CBB de tip D asincron

&%%GHWLS'DVLQFURQILJVHRE LQHGLQWU -un CBB-RS asincron (fig. 16.1,
tab. 16.1 sau fLJWDESULQDWDúDUHDXQXLLQYHUVRUvQVFRSXOHOLPLQ ULL
VW ULORUQHGHWHUPLQDWH
7DE7DEHOGHWUDQ]L LHDO&%%GHWLS'
Dn = S n = R n Qn Qn + 1
1 x 1
0 X 0
Fig. 16.9. CBB de tip D
'DWRULW LQYHUVRUXOXLGLQWDEU PkQQXPDLOLQLLOHSHQWUXFDUH
106
Dn = Sn = R n deci liniile 2 si 3.
'HRDUHFHUHSHW SUDFWLFLQVWDQWDQHXODLHúLUHFHHDFHLVHDSOLF ODLQW rare (v. tab.
FLUFXLWXOQXSUH]LQW LQWHUHVSUDFWLF
2.3.2. CBB de tip D sincron

&%%GHWLS'VLQFURQILJúLVHRE LQHGLQWU -un CBB-RS sincron
ILJúLWRWSULQDWDúDUHDXQXLLQYHUVRU
DPRGXOGHRE LQHUH b) schema bloc DPRGXOGHRE LQHUHEVFKHPDEORF
Fig. 16.10. CBB de tip D Fig. 16.11. CBB de tip D sincron

sincron pe palier inferior pe palier superior
&DúLv n cazul CBB-RS sincron, pentru a comuta sincronizat de CLK este necesar
FDLQIRUPD LDGHODLQWUDUHD'V VHPRGLILFHvQDIDUDSDOLHUXOXLDFWLYDOLPSXOVXOXL
CLK ( CLK SHQWUXILJúL&/. SHQWUXILJvQWLPSXOSDOLHUXOX i

UHVSHFWLYHDU PkQkQGVWDELO $SDUL LDSDOLHUXOXLDFWLYDOLPSXOVXOXLGH&/.
WUDQVIHU ODLHúLUHLQIRUPD LDGHODLQWUDUHDELVWDELOXOXL6SXQHPF VHUHDOL]HD] R
WHPSRUL]DUHFRPDQGDW SULQ&/.'HIDSWGHQXPLUHDGHELVWDELOGHWLS'
provine din englezescul DELAY=întârziere.

vQILJDPUHSUH]HQWDWVFKHPDORJLF DXQXLDGLQFHOHGRX ODWFK -uri de câte
EL LGHWLS'FRQ LQXWHvQFLUFXLWXOLQWHJUDW&'%.70ILJ$ -
DQH[ LDUvQWDE IXQF LRQDUHDODWFK
- -ului respectiv.
BistaELOXOGHWLS'VLQFURQDUHQXPHURDVHDSOLFD LLSUDFWLFHGLQWUHFDUHDPLQWLP
latch-ul adresabil, memoria RAM, etc.
107
)LJ6FKHPDORJLF DODWFK -ului de tip D din structura CI - CDB 475
7DE([SOLFDWLYSHQWUXIXQF LRQDUH a latch-ului de tip D
,QWU UL ,HúLUL
Mod
operare En Dn Qn+1 Q n +1
Autorizare 1 0 0 1
date 1 1 1 0
Blocare date 0 x Qn Qn
2.3,3, CBB de tip D Master-Slave

CBB-D-06VHGHRVHEHúWHGH&%%-D sincron prin faptul F DúDFXPDPY ]XWúL
în cazul CBB-RS-MS, comutarea se produce pe frontul (anterior sau posterior) al
impulsului de CLK.
Circuitul integrat cel mai reprezentativ este CDB 474, fig. A. l O -DQH[ FDUH
FRQ LQHGRX ELVWDELOHGHWLS'VLQFURQHFXFRPXWDUHSHIURQW)XQF LRQDUHD
DFHVWRUDHVWHFHDGHVFULV vQWDE5HPDUF PIDSWXOF LQWU ULOH R si S sunt

active în "O" logic si sunt independente de tact. Astfel, pentru S 2VHRE LQH
Q=l, iar pentru R = 0=>Q = 0.
'LQWUHFHOHPDLIUHFYHQWHDSOLFD LLDOH&%%-D-06HQXPHU PUHJLVWUXOGH
deplasare serie, paralel, serie-paralel, universal, etc.

&LUFXLWHOHEDVFXODQWHELVWDELOHGHWLS56úL'IDFSDUWHGLQVLVWHPHOHGHRUGLQXO,
1HRFXS PvQFRQWLQXDUHGHDOWHGRX WLSXULGHELVWDELOH7úL-.FDUH
SUH]HQWkQGFkWHRUHDF LHVXSOLPHQWDU VXQWFRQVLGHUDWHVLVWHPHGHRUGLQXO,,
108
2.4. Circuitul basculant bistabil de tip T
%LVWDELOXOGHWLS7VHRE LQHGLQWU XQELVWDELO'SULQLQWURGXFHUHDXQHLUHDF

- ii
VXSOLPHQWDUHLHúLUH LQWUDUHDSOLFDW SULQLQWHUPHGLXOXQXLFOFHOHPHQWDUILJ
-
16.13).
DPRGXOGHRE LQHUH b) schema bloc
Fig. 16.13. CBB de tip T sincron Tab.
7DEHOXOGHWUDQ]L LHDO&% B–T
Tn Qn+1
0 Qn
1 Qn
'LQWDEHOXOGHWUDQ]L LHWDEVHSRDWHGHGXFHH[SUHVLDIXQF LHLGHLHúLUH
Qn+1=Qn Tn + Q + Tn = Qn ⊕ T. (16.1)
%LVWDELOXO7GLQILJQXvQGHSOLQHúWHIXQF LDGHPHPRULHSURSLX ]LV FXP
-
HVWHFD]XOELVWDELOHORU56úL'DYkQGXQFRPSRUWDPHQWGHILQLWDWkWGHLQWUDUHFkW
úLGHVWDUHDvQFDUHVHDIO (OHVWHFHOPDLVLPSOXVLVWHPDXWRPDWúLHVWHXW ilizat,

VSUHH[HPSOXODFRQVWUXLUHDQXP U WRDUHORUDVLQFURQH
2.5. Circuitul basculant bistabil de tip JK
5HDPLQWLPIDSWXOF ELVWDELOXO'DDS UXWFDXUPDUHDQHFHVLW LLGHDvQO WXUD
WUDQ]L LLOHQHGHWHUPLQDWHDOHELVWDELOHORU56$FHODúLHIHFWGHHOLminare a
WUDQ]L LLORUQHGHWHQQLQDWHVHSRDWHRE LQHSULQLQWURGXFHUHDGHUHDF LLVXSOLPHQWDUH
în structurile RS.
109
2.5.1. CBB-JK asincron
%LVWDELOXO-.DVLQFURQILJSRDWHILRE LQXWGLQELVWDELOXO56DVLQFURQSULQ
LQWURGXFHUHDXQHLUHDF LL
Fig. 16.14. Schema CBB-JK asincron
'LQILJVHSRDWHGHGXFHVXFFHVLYIXQF LDGHLHúLUHDFLUFXLWXOXL
Sn=Jn Qn ; (16.2)
Rn = KnQn (16.3)
( ) ( )(
Qn +1 = K n Q n + J n Qn + Qn = K n Qn J n Q n + Qn = )
(K n )( )
+ Q n J n Qn + Qn = K n J n Qn + K n + Q n J n Qn ; (16.4)
Qn +1 = J n Q n + K n Qn
LQkQGVHDPDGHWDEHOXOGHWUDQ]L LHDO&%% -RS asincron, tab. 16.1, putem
DOF WXLWDE
7DE7DEHOXOGHWUDQ]L LHDO&%% -JK asincron
Jn Kn Rn Sn Qn+1
0 0 0 0 Qn
1 0 0 Qn 1
0 1 Qn 0 0
1 1 Qn Qn Qn
6HREVHUY F SHQWUX-n =Kn=1LHúLULOHRVFLOHD]
110
2.12. CBB-JK sincron
Schema CBB--.VLQFURQILJVHRE LQHGLQFHDSUHFHGHQW SULQ
LQWURGXFHUHDXQHLERUQHVXSOLPHQWDUHSHQWUXWDFWLDUWDEHOXOGHWUDQ]L LHHVWHWDE
16.7.
Fig. 16.15. Schema CBB-JK sincron Tab.
7DEHOXOGHWUDQ]L LHDO&%% -JK sincron
Jn Kn CLK Qn+1
0 0 0->1 Qn
1 0 0->1 1
0 1 0->1 0
)XQF LRQDUH
1 1 0->1 Q
n Sincron
x x 0 Qn Circuit blocat
0->1 0 1 1 )XQF LRQDUH-
0 0->1 1 0 DVLQFURQ
6HREVHUY F SULQOHJDUHDvPSUHXQ DLQWU ULORU-úL.VHRE LQHXQELVWDELOGHWLS
7FDUHEDVFXOHD] GLQWU -o stare în alta pentru Jn=Kn=Tn OvQSUH]HQ DLPSXOVXOXL
de CLK.
2.5.3. CBB--.0DúWHU6ODYH
Bistabilul JK-06VHRE LQHSULQFRQHFWDUHDvQFDVFDG DGRX &%%-JK sincrone.
Circuitul integrat cel mai reprezentativ este CDB 472, fig. A.9 -DQH[ SUHY ]XW
cuRSHUDWRUL$1'FXFkWHLQWU ULSHQWUXLQWURGXFHUHDLQIRUPD LHLvQ
VHF LXQHDPDúWHUSUHFXPúLFXLQWU ULGHvQVFULHUH S úLúWHUJHUH R )
LQGHSHQGHQWHGHWDFWúLDFWLYHvQVWDUH-267UDQVIHUXOLQIRUPD LHLvQVHF LXQHD
111
VODYHVHSURGXFHSHIURQWXOGHVFUHVF WRUDOLPSXOVXOXLGH&/.7DEHOXOGH
WUDQ]L LHHVWHWDE
7DE([SOLFDWLYSHQWUXIXQF LRQDUHD&%% -JK-MS
Jn Kn Qn+1
0 0 Qn
0 1 0
1 0 1
1 1 Qn
2.6. Conversia cLUFXLWHORUELVWDELOH56'7úL-.
vQQXPHURDVHDSOLFD LLHVWHQHFHVDU XWLOL]DUHDXQXLDQXPLWWLSGH&%%SUDFWLF
ILLQGGLVSRQLELOXQDOWXOvQDFHVWHFRQGL LLGHPDUHDMXWRUVXQWHFXD LLOHORJLFHGH
OHJ WXU GLQWUHGLIHULWHWLSXULGHELVWDELOOHUHOD LLFHVHSRWRE LQHSHED]DWDEHOXOXL
comparativ, tab. 16.9.
Tab. 16.9. Tabel comparativ a! diferitelor tipuri de CBB

Tip CBB
RS D T JK
RnSN Qn+1 Qn Qn+1 Tn Qn+1 Jn Kn Qn+1
Tabelul de 00 Qn 00 Qn
0 0 0 Qn
01 l 01 0
DGHY U 10 0 10 1
11 ? 1 1 1 Qn 11 Qn
(FXD LLOH Qn+1 S n + R n Qn D T n Q n + Tn Q n J n Q n + K n Q n
logice
Qn +1 R n + S n Q n D T n Q n + T n Q n J n Q n + K n Qn
2.6.1. Conversia în T
Pentru realizarea conversiei JK ->T sau D -> T WUHEXLHJ VLW UHOD LDGLQWUH
LQWUDUHD7DELVWDELOXOXLVLPXODWúLLQWU ULOH-.VDX'DOHELVWDELOXOXLGLVSRQLELO -
fig. 16.16.
Pentru aFHDVWDVHFRQVWUXLHúWHWDEHOXODMXW WRUDVWIHOvQSULPHOHGRX
FRORDQHVHWUHFWRDWHFRPELQD LLOHORJLFHSRVLELOHDOHLQWU ULL7núLVW ULL
112
(QnELVWDELOXOXLVLPXODWvQXUP WRDUHOHGRX FRORDQH- valorile logice ale
LQWU ULORU-nKnúL'n, complHWDWHQXPDLGXS WUHFHUHDvQXOWLPDFRORDQ DYDORULORU
ORJLFHDOHLHúLULL4n+1 a bistabilului simulat.
Fig. 16.16. Conversia în T: punerea problemei
Tab. 16.10. Explicativ pentru realizarea conversiilor în T
Tn Qn Jn Kn Dn Qn+1
0 0 Ox 0 0
0 1 xO 1 1
1 0 1x 1 1
1 1 xl 0 0
&RPSOHWDUHDFXYDORULOHORJLFHFRUHVSXQ] WRDUHDFRORDQHORU-n.ÄúL'n se face

SRUQLQGGHODYDORULOHORJLFHDOHVW ULLSUH]HQWHúLYLLWRDUH4núL4n+1GXS R
VWXGLHUHDWHQW DWDE
$VWIHOVLWXD LD4n=0, Q„+,=0, sHRE LQHDWXQFLFkQG-nKn=00 sau 01, deci

JnKn 2[XQGHSULQ[vQ HOHJHPLQGLIHUHQW4r OúL4n+1 OVHRE LQHFkQG JnKn
=00 sau 10, deci JnKn [2úDPG
6LPLODUVHSURFHGHD] FXFRORDQDOXL'n.
2GDW FRPSOHWDWWDEVHSRDWHWUHFHODVLQWH] construind diagramele VK

SHQWUXIXQF LLOHGHLHúLUH-n , KnúL'n - fig. 16.17.
a) Jn=Tn b) Kn=Tn c) Dn=TnQn+TnQn=Tn ⊕ Qn
)LJ6LQWH]DIXQF LLORUGHLHúLUHDHEOR cului X din fig. 16.16

&XDFHVWHUH]XOWDWHVFKHPDJHQHUDO GLQILJFDS W DVSHFWHOHconcrete din
fig. 16.18.
113
a) JK ->T b) D-> T
Fig. 16.18. Conversia în T
2.6.2. Conversia în RS
3URFHGkQGVLPLODURE LQHPWDEFDUHSHUPLWHLPSOHPHQWDUHD
circuitelor de conversie JK— >56úL'— >RS.
Tab. 16.11. Explicativ pentru realizarea conversiilor în RS
RNSN Qn Jn Kn Dn Qn+1
00 0 Ox 0 0
00 1 xO 1 1
01 0 1x 1 1
01 1 xO 1 1
10 0 Ox 0 0
10 1 xl 0 0
11 0 xx x 0/0
11 1 xx x 1/0
3HQWUXLPSOHPHQWDUHDúLVWXGLHUHDFLUFXLWHORUEDVFXODQWHELVWDELOHSUH]HQWDWHvQ
SDUDJUDIXODQWHULRUVHYDXWLOL]DSODWIRUPDGHODERUDWRUúLFLUFXLWHOHLQWHJUDWH
&'%&'%&'%&'%úL&'%SUH]HQWDWHvQILJ$O$
$$úL$ DQH[
-
3.1. Studiul circuitului basculant bistabil – RS
3.1.1. Studiul CBB-RS asincron

6HFRPSOHWHD] FLUFXLWXOGLQILJ
DFXQXPHUHOHSLQL lor circuitului
integrat folosit (CDB 400, fig. A. l), inclusiv pinii do alimentare.
6HLPSOHPHQWHD] &%%-RS asincron din fig. 16.3 pe zona cu socluri de
CI a platformei.
6HFRQHFWHD] LQWU ULOH R úL S DOH&%%ODLHúLULOH$1 (B-úL$0
114
(B-4) ale DF1SXVvQUHJLPGHQXP U WRUFRPDQGDWGH)70YOXFUDUHDQU
,HúLULOH&%%-56DVLQFURQVHFRQHFWHD] OD%6EL LL&0úL&1.
3.1.1.5.6HYHULILF FRUHFWDIXQF LRQDUHD&%%-RS asincron cu ajutorul tab. 16.2.

3.1.2. Studiul CBB-RS sincron
6HFRPSOHWHD] FLUFXLWXOGLQILJDFXQXPHUHOHSLQLORUFLUFXLWXOXL
integrat utilizat (CDB 400. fig. A.l), inclusiv pinii de alimentare.

6HLPSOHPHQWHD] &%%-RS sincron din fig. 16.6a pe zona cu socluri de
CI a platformei.
6HFRQHFWHD] LQWU ULOH5úL6DOH&%%ODLHúLULOH$1 (B-úL$0 (B-4) ale
DF1úLLQWUDUHD&/.D&%%ODLHúLUHD%0 (B-14) a DF2 (DF1úL')2 în regim de

QXP U WRDUHFRPDQGDWHGH)70,QWU ULOHDVLQFURQH R úL S VHFRQHFWHD] OD%6
EL LL&0úi C1LDULHúLULOH&%%-RS sincron -OD%6EL LL'0úL'1.
6HDOLPHQWHD] FLUFXLWHOHSODWIRUPHLGHODVXUVDGe 5V.
6HYHULILF FRUHFWDIXQF LRQDUHD&%%-56VLQFURQFXDMXWRUXOWDEúL
tab. 16.2, observându-se rolul palierului superior al impulsului de CLK.

6HYHULILF IXQF LRQDUHDLQFRUHFW DVLQFURQ D&%%-RS sincron cu
DMXWRUXODFHORUDúLWDEHOHúLSHQWUX&/. vQLQWHUYDOXOGHWLPSvQFDUH
VHPRGLILF GDWHOHODLQWU ULOH5úL6
3.2. Studiul circuitului basculant bistabil –D
3.2.1, Studiul CBB-D sincron

6HXWLOL]HD] FLUFXLWXOLQWHJUDW&%'.70ILJ$OO DQH[
-
36HFRQHFWHD] LQWU ULOH'0úL(0-1ILJODLHúLULOH$0 (B-úL%0 (B-
14) ale DF1úL')2vQUHJLPGHQXP U WRDUHFRPDQGDWHGH)70,HúLULOH40úL Q 0
VHFRQHFWHD] OD%6EL LL&0úL&1.
6HDOLPHQWHD] FLUFXLWHle platformei de la susa de 5V.
6HYHULILF FRUHFWDIXQF LRQDUHDODWFK-ului de tip D conform tab. 16.4.
3.2.2. Studiul CBB-D Master-Slave

6HXWLOL]HD] FLUFXLWXOLQWHJUDW&'%ILJ$O2-DQH[
6HFRQHFWHD] LQWU ULOHO'úL7ODLHúLULOH$0 (B-úL%0 (B-14) ale DF1
úL')2vQUHJLPGHQXP U WRDUHFRPDQGDWHGH)70,HúLULOH40úL Q se
0
FRQHFWHD] OD%6EL LL&0úL&1.
6HLQL LDOL]HD] bistabilul punând pinul IR ODPDV úLVHYHULILF
IXQF LRQDUHDFDFLUFXLWGHWHPSRUL]DUHFRPDQGDWGHIURQWXOLPSXOVXOXLGHWDFW
3.3. Studiul circuitului basculant bistabil - T
6HLPSOHPHQWHD] VFKHPDGH&%% -T din fig. 16.18, utilizând circuitele

LQWHJUDWH&'%úL&'%ILJ$úL$-DQH[ GXS FRPSOHWDUHDFX
115
QXP UXOSLQLORUFLUFXLWHORULQWHJUDWHLQFOXVLYERUQHOHGHDOLPHQWDUH
6HFRQHFWHD] LQWU ULOH7úL&/.ILJODLHúLULOH$0

(B-úL B0 (B-
14) ale DF1úL')2vQUHJLPGHQXP U WRDUHFRPDQGDWHGH)70,HúLULOH4úL Q se
FRQHFWHD] OD%6EL LL&0úL&1.
6HYHULILF FRUHFWDIXQF LRQDUHD&%% -T conform tabelului 16.5 completat

cu coloana CLK.
2.4. Studiul circuitului basculant bistabil - JKMaster-Slave
6HXWLOL]HD] FLUFXLWXOLQWHJUDW&'%ILJ$ DQH[

-
6HFRQHFWHD] LQWU ULOH-1 K1 (cu J2, J3, K2, K3 -QHFRQHFWDWHODLHúLULOH$1
(B-5)úL$0 (B-4) ale DF1úLLQWUDUHDGHWDFW7ODLHúLUHD%0 (B-14) DF2 (DF1úL')2
vQUHJLPGHQXP U WRDUHFRPDQGDWHGH)70,HúLULOH4úL Q VHFRQHFWHD] OD
%6EL LL&0úL&1.
6HDOLPHQWHD] FLUFXLWHOHSODWIRUPHLGHODVXUVDGH 5V.
6HLQL LDOL]HD] ELVWDELOXOFRQHFWkQGWHPSRUDUSLQXO R ODPDV úLVHYHULILF
IXQF LRQDUHDFRQIRUPWDE
3.4.4. Cu Jn=Kn OVHFRQHFWHD] ODLQWUDUHD T D&%%LHúLUHD%-30 a GTA. Cele

GRX LQWU ULDOHRVFLORVFRSXOXLFXGRX VSRWXULFXOHJVHPQDOHGHODLQWUDUHD T
UHVSHFWLYLHúLUHD4DELVWDELOXOXL-.FRQIRUPVFKHPHLGLQILJ
Fig. 16.19. Montaj experimental pentru studiul regimului dinamic al CBB-JK-MS
6HREVHUY GLYL]DUHDGHIUHFYHQ UHDOL]DW GHFHOXODGHPHPRULHSUHFXPúL
FRPDQGDSHIURQWGHVFUHVF WRUDELVWDELOXOXL
116
4.1. Montajul experimental pentru studiul CBB-56DVLQFURQúLWDEHOXOGH

IXQF LRQDUH
4.2. Montajul experimenta] pentru studiul CBB-56VLQFURQúLWDEHOXOGH

IXQF LRQDUH
4.3. Montajul experimental pentru studiul CBB-D sincron si tabelul de

IXQF LRQDUH
4.4. Montajul experimental pentru studiul CBB-D Master-Slave si tabelul de

IXQF LRQDUH
4.5. Montajul experimental pentru studiul CBB-7úLWDEHOXOGH

IXQF LRQDUH
4.6. Montajul experimental pentru studiul CBB-JK Master-6ODYHUHJLPVWDWLFúL

GLQDPLFúLWDEHOXOGHIXQF LRQDUH
117
LUCRAREA NR. 17
REGISTRE
1.6FRSXOOXFU ULL
/XFUDUHDvúLSURSXQHVWXGLHUHDWXWXURUUHJLPXULORUGHOXFUXDOHUHJLVWUXOXL
XQLYHUVDOELGLUHF LRQDOGHEL L61ILJ$ DQH[

-
*HQHUDOLW L
Registrele sunt cirFXLWHHOHFWURQLFHFDUHSHUPLWVWRFDUHDúLVDXGHSODVDUHDXQRU

cuvinte de cod binar.
3RUQLQGGHODDFHDVW GHILQL LHUHJLVWUHOHVHSRWFODVLILFDvQUHJLVWUHSDUDOHOGH
stocare), registre de deplasare serie, registre combinate (serie-paralel sau paralel-

sHULHúLUHJLVWUHXQLYHUVDOH
2.2. Registrul paralel
Registrul paralel (de stocare, tampon), fig. 17.1, este format din n bistabili de tip
'DF LRQD LVLQFURQGHXQWDFWFRPXQ
Fig. 17. l. Schema JHQHUDO DXQXLUHJLVWUXSDUDOHO
În momentXODSOLF ULLWDFWXOXLFXYkQWXOELQDUGHQEL LSUH]HQWODLQWU ULOH
118
I0,11(..., In.1HVWHvQVFULVvQFHOHQFHOXOHGHPHPRULHúLSRDWHILFLWLWODLHúLULOH40,
Q1,.......Qn+1.
)XQF LDSULQFLSDO DXQXLDVWIHOGHUHJLVWUXHVWHDFHHDGHDVWRFDWHPSRUDUanumite
FRQILJXUD LLELQDUHvQVFRSXOXQXLDFFHVXúRUODHOHvQYHGHUHDSUHOXFU ULL
5HJLVWUXOSDUDOHOHVWHPHPRULD]RQHORUGHYLWH] PD[LP GLQWU -un sistem digital

de prelucrare a datelor.
2.3. Registrul de deplasare
Registrul de deplasare serie, fig. 17.2, este format din 4 bistabili de tip D Master-
Slave.
)LJ6FKHPDJHQHUDO DXQXLUHJLVWUXGHGHSODVDUHVHULH
vQWLPSXOIXQF LRQ ULLODWFK XULOHGHWLSPDúWHUVXQWGHVFKLVHVLPXOWDQSHQWUX

-
CLK=0, cele de tip "slave" fiind închise, în tLPSXOWUDQ]L LHLGLQ2vQOD
semnalului de CLK, latch-XULOHPDúWHUVHEORFKHD] LDUFHOHVODYHVHGHVFKLG
úLSULPHVFLQIRUPD LDGLQPDúWHU6HUHPDUF IDSWXOF vQQLFLXQPRPHQWQX
H[LVW RFDOHGHVFKLV vQWUHLQWUDUHDúLLHúLUHDUHJLVWUXOXL
Pe ED]DVFKHPHLGLQILJSXWHPVFULHXUP WRDUHOHUHOD LL

D0uTn=Q3n=D3n-1=Q2n-1=D2n-2=Q1n-2=D1n-3=Q0n-3=D0n-4=DINn-4 (17.1.)
6HREVHUY F LQIRUPD LD'ADMXQJHODLHúLUHDUHJLVWUXOXLGXS LPSXOVXULGHWDFW
Registrele de deplasare pRWILFRQVWUXLWHDWkWvQYDULDQWHVWDWLFHFkWúLGLQDPLFHvQ

FD]XOVWUXFWXULORUGLQDPLFHYDWUHEXLLPSXV RIUHFYHQ PLQLP DVHPQDOXOXLGH
FHDVSHQWUXFDGDWHOHvQVFULVHvQFHOXOHOHGHPHPRUDUHV VHSRDW UHJHQHUDVLJXU
SULQWUDQVIHUXOvQFHOXOHOHXUPtoare
Registrele de deplasare serie pot fi utilizate ca memorii cu acces serie (SAR -
6HULDO$FFHV0HPRU\5HJLVWHU(OHVXQWFRQVWUXLWHSHQWUXXQQXP UIRDUWHPDUH
GHEL LFUHúWHUHDQXP UXOXLGHFHOXOHGHPHPRUDUHQHDYkQGQLFLXQIHOGH
LPSOLFD LLDVXSUDQXP UXOXLGHFRQH[LXQLH[WHUQHDOHLQWHJUDWXOXL
119
2.4. Registre combinate
&HOHGRX WLSXULGHUHJLVWUHWUDWDWHPDLVXVVXQWXWLOL]DWHvQDSOLFD LLvQFDUH
transferul datelor se face fie numai paralel, fie numai serie.

Registrele combinate permit trecerHDGHODWUDQVIHUXOSDUDOHOODFHOVHULHúLLQYHUV
vQILJSUH]HQW PXQUHJLVWUXFRPELQDWSDUDOHO-serie sau serie-paralel) de 4
EL L
)LJ6FKHPDJHQHUDO DXQXLUHJLVWUXSDUDOHO -serie sau serie-paralel
Pentru S/P = O, suQWGHVFKLVHSRU LOHúLGDWHOHGHLQWUDUH,0, Il I2, I3 au acces la

LQWU ULOHFHORUELVWDELOHvQF UFDUHDSDUDOHODUHORFvQPRPHQWXODSOLF ULL
impulsului de CLK.
3HQWUX63 OUHJLVWUXOUHDOL]HD] RGHSODVDUHVHULHDGDWHORUGHODVWkQJDOD
dreapta, cu câte un bit pentru fiecare impuls de CLK.

5HJLVWUXOIXQF LRQHD] FDXQFRQYHUWRUSDUDOHO-serie, datele fiind introduse paralel
ODLQWU ULOHI0, Il I2, I3 úLILLQGH[WUDVHVHULHODLHúLUHD626HULDO2XWSXWD
circuitului.
În regim de convertor serie-pDUDOHOGDWHOHVHLQWURGXFGHRPDQLHU VHULDO OD
LQWUDUHD6,6HULDO,QSXWúLVXQWH[WUDVHSDUDOHOODLHúLULOHQ0,Q1, Q2 Q3.
120
5HJLVWUXOXQLYHUVDOELGLUHF LRQDOGHEL L
5HJLVWUXOXQLYHUVDOELGLUHF LRQDOGHEL L61ILJDFRSHU SU actic

toate variantele de registre prezentate anterior.
&DUDFWHULVWLFLOHIXQF LRQDOHDOHDFHVWXLWLSGHUHJLVWUXVXQWSUH]HQWDWHvQWDEHOXOGH
IXQF LRQDUH- tab. 17.1.
)LJ5HJLVWUXOXQLYHUVDOELGLUHF LRQDOGHEL L61 94)
&LUFXLWXOLQWHJUDW61SUH]LQW FRPHQ]LORJLFHVSHFLDOHFDUH -i sporesc

GRPHQLXOGHDSOLFDELOLWDWH)XQF LRQDUHDVLQFURQ DFLUFXLWXOXLHVWHGHWHUPLQDW GH
FHOHGRX LQWU ULGHVHOHF LHDPRGXOXLGHOXFUX60úL61'XS FXPUH]XOW úLGLQ
tabeluOGHIXQF LRQDUHGDWHOHSRWILLQWURGXVHúLGHSODVDWHGHODVWkQJDODGUHDSWD
GHODGUHDSWDODVWkQJDVDXLQWURGXVHSDUDOHOvQF UFkQGVLPXOWDQvQUHJLVWUXWR L
FHLEL L'DF DPEHOHLQWU ULGHVHOHF LH60úL61 sunt în stare "jos", datele

existente îQUHJLVWUXVXQWS VWUDWH7HUPLQDOHL5 5LJKW,QSXWúL/,/HIW,QSXW
I
VXQWLQWU ULVHULDOHSHQWUXGHSODVDUHDODGUHDSWDUHVSHFWLYODVWkQJDDGDWHORUúLQX
LQWHUIHUHD] vQQLFLXQIHOFXRSHUD LXQHDGHvQF UFDUHSDUDOHODGDWHORU
121
,QWU ULOHGHVHOHF LHúLGHGDWHWUHEXLHV VHVWDELOL]H]HFXXQDQXPLWLQWHUYDOGH
WLPSvQDLQWHDDSDUL LHLIURQWXOXLSR]LWLYDO&/.HOHGHYHQLQGDFWLYHQXPDLGXS
acest moment.
7DE7DEHOXOGHIXQF LRQDUHDOUHJLVWUXOXLXQLYHUVDO61
Mod de ,QWU UL IeúLUL

operare CLK CL S1 S0 RI LI In Qo Q1 Q2 Q3
ùWHUJHUH X L X X X X X L L L L
Hold X H l(b) l(b) X X X q0 q1 q 2 q3
Deplasare H h l(b) X l X q1 q2 q 3 L
la stânga TJ h l(b) X h X q1 q2 q 3 H
Deplasare H Kb) h 1 X X L q0 q1 q2
la dreapta H l(b) h h X X H q0 q1 q2
vQF UFDUH
paralel H h h X X in i1 i2 i3 i4
H = nivel de tensiune ridicat;

K LGHPVWDELOLWDQWHULRUWUDQ]L LHL/ —>H a CLK;
L = nivel de tensiune coborât;
l LGHPVWDELOLWDQWHULRUWUDQ]L LHL/—>H a CLK;
in(qn VW ULOHLQWU ULORUVDXLHúLULORUVWDELOLWHDQWHULRUWUDQ]L LHL/->H a CLK;
X = indiferent;
WUDQ]L LH/->H a CLK.
1RW E7UDQ]L LD+-!/DLQWU ULORU60úL61WUHEXLHV VHSURGXF QXPDLvQWLPS
FH&/.HVWH+SHQWUXRSHUD LLFRQYHQ LRQDOH
3. Desf úXUDUHDOXFU ULL
Pentru studierea registrelor prezentate în cadrul paragrafului 2, se va utiliza

SODWIRUPDGHODERUDWRUúLFLUFXLWXOLQWHJUDW61ILJ$-DQH[
&RQH[LXQLOHQHFHVDUHSHQWUXEXQDGHVI úXUDUHDOXFU ULLVXQW
-,HúLULOHGLYL]RUXOXLGHIUHFYHQ ')1vQUHJLPGHQXP U WRUFRPDQGDWSULQ

FTM1FXLQWU ULOHGHGDWHDOH61DVWIHO
A0(B-4)-I0(3); A1 (B-5) –I1 (4); A2 (B-6) –I2 (5); A3 (B-7) –I3 (6);
-,HúLULOHGLYL]RUXOXLGHIUHFYHQ ')2vQUHJLPGHQXP U WRUFRPDQGDWSULQ
FTM2FXLQWU ULOHGHVHOHF LHDOH61DVWIHO
B0(B-14)-S0(9); B1(B-15)-S1 (10);
-&HOHGRX WDVWHGHUH]HUY GLQEORFXO%7DLSODWIRUPHLSULPDFRQHFWDW OD+ iar
122
cea de-DGRXDODPDV FXWHUPLQDOHleGH&/.úL&/DOH&,61
- Circuitele de semnalizare C0, C1, C2úL&3GLQEORFXO%6DOSODWIRUPHLFXLHúLULOH
Q0 (15), Q1 (14), Q2úL43 (12) ale SN 74194;
-%RUQHOHVXUVHLGHDOLPHQWDUHGH9FXSLQLLGHDOLPHQWDUHúLDL61
3.1. Studiul registrului paralel
3.1.1. Se cuplHD] WHQVLXQHDGHDOLPHQWDUHúLVHUHVHWHD] GLYL]RDUHOHGH
IUHFYHQ úLFHLELVWDELOLGLQUHJLVWUX
$F LRQkQGUHSHWDWWDVWD702VHIL[HD] LQWU ULOHGHVHOHF LH61 S0 = 11,

WUHFkQGUHJLVWUXOvQPRGXOGHRSHUDUHvQF UFDUHSDUDOHO
$F LRQk nd TM1VHVWDELOHúWHRDQXPLW FRQILJXUD LHORJLF DFHORUEL LGH
intrare (I3I2I1I0).
$F LRQkQGWDVWDGH&/.REVHUY PWUDQVIHUXOGDWHORUGHODLQWU ULOH,3 I2I1I0
ODLHúLULOH43 Q2Q1Q0 ale registrului.
6HUHSHW RSHUD LLOHGHVFULVHODSFWúLSHQWUXGLYHUVHFRPELQD LL
de intrare.
3.2. Studiul registrului de deplasare serie
6HUHVHWHD] GLYL]RDUHOHGHIUHFYHQ úLFHLELVWDELOLGLQUHJLVWUX
$F LRQkQGUHSHWDWWDVWD702VHIL[HD] LQWU ULOHVHVHOHF LH61 S0 = 01,

trecând registrul în modul de lucru "deplasare la dreapta".
6HFRQHFWHD] LQWUDUHDVHULDO SHQWUXGHSODVDUHDODGUHDSWD5,ODOORJLF
$F LRQkQGvQPRGUHSHWDWWDVWD&/.VHXUP UHúWHPRGXOvQFDUHHYROXHD]
LHúLULOH40 Q1Q2Q3 (OOOO->1000->1100->1110->1111).

÷ 3.2.4 pentru S1S0 úL/,FRQHFWDWODOORJLF
6HUHSHW SXQFWHOH
úLVHREVHUY IXQF LRQDUHDUHJLVWUXOXLvQUHJLPGHGHSODVDUHGHODGUHDSWDODVWkQJD
(0000->0001 ->0011 ->0111 ->1111).
3.3. Studiul registrului (convertorului) paralel-serie
8UPkQGSDúLLGHVFULúLODSXQFWXOVHvQVHQHvQUHJLVWUXRFRPELQD LH
ELQDU GHH[HPSOX
3.3.2. Punând S1S0 REVHUY PLHúLUHDVHULDO DGDWHORUODSLQXO52VXE
DF LXQHDLPSXOVXOXLGH tact.
3.3.3. Punând S1 S0 REVHUY PLHúLUHDVHULDO DGDWHORUODSLQXO/2VXE
DF LXQHDLPSXOVXOXLGHWDFW
123
3.4. Studiul registrului (convertorului) serie-paralel
6HGHFRQHFWHD] LHúLULOH')1GHODLQWU ULOH,0 ,I1, I2,13DOHUHJLVWUXOXLúL se

FRQHFWHD] LHúLUHD$0 (B-4) a DF1ODLQWUDUHDVHULDO 5,DUHJLVWUXOXL
$F LRQkQGUHSHWDWWDVWD702VHIL[HD] LQWU ULOHGHVHOHF LH61 S0=01.

6HUHVHWHD] ELVWDELOLLUHJLVWUXOXL
$F LRQkQGVXFFHVLY701úL&/.VHYDvQVFULHVHU
ial, de la stânga la dreapta,
RVXFFHVLXQHGH2úLODVWIHO->1000->0100->1010->0101.
3RVLELOLWDWHDFLWLULLSDUDOHODDFHVWHLFRPELQD LLORJLFHHVWHHYLGHQW
3.4.5. Experimentul poate fi repetat pentru verificarea înscrierii seriale de la

dreapta laVWkQJDSULQFRQHFWDUHDLHúLULL$0 (B-4) a lui DF1 la intrarea LI (7) a
UHJLVWUXOXLúLIL[DUHDFRPELQD LHL61S0=10.
6FKHPDUHJLVWUXOXLXQLYHUVDOELGLUHF LRQDOGHEL L - SN 74194 (fig. 17.4);

7DEHOXOGHIXQF LRQDUH
(tab. 17.1);
4.3. Schemele bloc necesare pentru realizarea experimentelor, completate cu
QXP UXOSLQLORUUHVSHFWLYL
124
$1(;
125
126
127
128
129
130
131
BIBLIOGRAFIE
1. Filipescu, V. F. Curs de "Circuite electronice digitale", în cuUVGHDSDUL LHOD

5HSURJUDILD8QLYHUVLW LLGLQ&UDLRYD
2. Maican, S. „Sisteme numerice cu circuite integrate - culegere de probleme,

(GLWXUD7HKQLF %XFXUHúWL
3. Millman, J., Grabel, A., Microelectronique, Mc GRAW-HILL, 1991;
4. Sztojanov, I, De la poarta TTL la microprocesor, vol,(GLWXUD7HKQLF
%XFXUHúWL
5. ùWHIDQ*KúD Circuite integrate digitale. (GLWXUD'LGDFWLF úL
3HGDJRJLF %XFXUHúWL
6. * * *, Catalog "Circuite integrate digitale", ,356% QHDVD
7. * * *, Catalog "Digital Integrated Circuits". Signetics, 1988.
132

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UNIVERSITATEA DIN CRAIOVA

VINTIL FILIPESCU DAN GARAI MAN

Îndrumarul de laborator "Circuitle elertronice digitale” VH DGUHVHD]

VWXGHQ LORUGLQDQLL ,,,DLIDFXOW LORUGH(OHFWURWHKQLFDúL(OHFWURPHFDQLF GDU poate

Calculatoare si (OHFWURQLF DOH)DFXOW LLGe A.C.E.

([SHULHQ D DFXPXODWD vQ W imp în cadrul disciplinei de "Circuite electronice

avut-o studentul Mugurel Popescu de la facultatea de (OHFWURWHKQLF F UXLDL se cuvin

Mircea Mihaiu pentru sugestiile utile úLUDEGDUHD cu care au recenzat manuscrisul.

pentru FOLPDWXOGHHIHUYHVFHQ DSXEOLFLVWLF SHcare 1-au FUHDWúLFDre a constituit un

l . Prezentarea platformei de laborator..................................................................... .......................6

2.1.4 Blocul de semnalizare a nivelurilor logice (BS). FRQ LQkQG

2.1.5. Blocul tastelor de FRPDQG %7 Iormat din 6

3ODFKHWDPXOWLIXQF LRQDO 30 ILJVHLQWURGXFHvQFRQH ctorXO%úL

Fig.1.4. Generatorul de tact automat

a) schema b) diagramele de semnal

Fie. 1.5. Formatorul de tact manual

1.7. Decodificatorul BCD - zecimal

a) schema b) diagramele de semnal

&XSODFKHWDPXOWLIXQF LRQDO VFRDV GLQFRQHFWRUXO%VHLQWURGX ce cupla

VWDELOL]DW GH999/LSVDLQGLFD LHLOXPLQRDVHDXQXL/('VHPQLILF ILH

VXUV GHIHFW ILHVFXUWFLUFXLWODERUQHOHGHLHúLUHDOHVXUVHLUHVSHFWLYH

ÎQFD]XOvQFDUHOXFUDUHDGHODERUDWRUDERUGDW QHFHVLW WHQVLXQLFRQWLQXH

UHJODELOHVHXWLOL]HD] 3333vQPRQWDMSRWHQ LRPHWULF

vQXUP WRDUHOHVFRSXULFRQHFWRUXO$ - pentru eventuale extensii ale BSCI cu alte

Nr. pin Bloc Nr. pin Bloc

B-3 Intr. tact B-25 Intr. FTM,

B-5 OHú$1 B-27 Intr. FTM2

B-14 OHú%0 B-36 OHú<1

B-15 OHú%1 B-37 OHú<2 DCD

B-17 OHú%3 DF2 B-39 OHú<4

B-19 OHú%5 B-41 OHú<6

B-20 OHú%6 B-42 OHú<7

B-21 OHú%7 B-43 OHú<8

B-22 Reset-2 B-44 OHú<9

2.2.4. Toate LED-XULOH%6WUHEXLHV ILe VWLQVHGDF LQWU ULOH$i. Bi. Ci ,Di, cu

SRWHQ LDODSOLFDW JUXSXOXL5: - LED" este sub pragul de 1,6 V necesar

VW ULOHSULPHORU[/(' XULDOH%6V ILHGHDVHPHQHDLPSUHYL]

- TR1,2 UHDOL]HD] SXQHUHDSH]HUR úWHUJHUHD5(6(7-area) divizoarelor de

- TM1,2VXQWFRQHFWDWHODLQWU ULOH%-25,27 ale formatoarelor de tact manual

blocul de semnalizare a nivelurilor logice (BS) vor primi tensiune de alimentare.

YL]XDOL]DFXDMXWRUXOXQXLRVFLORVFRSODLHúLUHD% -30 a GTA impulsuri

P VXU VDXODXQDGLQFHOHVHF LXQLQHXWLOL]DWHDOH%6 &i , Di , cu i=0,l... 7), se

SRDWHREVHUYDDSDUL LDXQXLLPSXOVGHGXUDW IRDUW VFXUW vnPRPHQWXODF LRQ ULL

tastei TM1 (TM2),

DF2UHDOL]kQGSXQ LOH %-26, B-3), (B-28, B- úLVHUHVHWHD] GLYL]Rarele prin

derularea nXP U ULLELQDUHSHVHF LXQLOH$i (Bi) ale BS.

,HúLULOH Y 0 (B-35), Y 1 (B-36),... , Y 9 (B- VHFRQHFWHD] OD%6&0. C1, .... C7,

D0. D1 - fig. 1.9.

conduce la activarea în RUGLQHFUHVF WRDUHDEDUHORUGHLHúLUHDOH'&' Y 0 , Y 1 ,... ,

)LJ6FKHP SHQWUXWHVWDUHDGHFRGLILFDWRUXOXL%&' - zecimal

'HVI úXUDUHDOXFU ULL

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