library ieee;

use ieee.std_logic_1164.all;

entity bcd is
port (
b: in std_logic_vector(3 downto 0);
s: out std_logic_vector(1 to 7)
);
end bcd;

architecture simple of bcd is

begin
process(b)
begin
case b is
when "0000"=>
s<="0000001";
when "0001"=>
s<="1001111";
when "0010"=>
s<="0010010";
when "0011"=>
s<="0000110";
when "0100"=>
s<="1001100";
when "0101"=>
s<="0100100";
when "0110"=>
s<="0100000";
when "0111"=>
s<="0001111";
when "1000"=>
s<="0000000";
when others=>
s<="0000100";
end case;
end process;

end architecture simple;